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iwlwifi/iwl3945 : unify apm stop operation
[linux-2.6/libata-dev.git] / drivers / net / wireless / iwlwifi / iwl-4965.c
blobdd10c426ecc45122a9711f9b737e4b76fa712487
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * Intel Linux Wireless <ilw@linux.intel.com>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 *****************************************************************************/
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/pci.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/delay.h>
33 #include <linux/skbuff.h>
34 #include <linux/netdevice.h>
35 #include <linux/wireless.h>
36 #include <net/mac80211.h>
37 #include <linux/etherdevice.h>
38 #include <asm/unaligned.h>
39
40 #include "iwl-eeprom.h"
41 #include "iwl-dev.h"
42 #include "iwl-core.h"
43 #include "iwl-io.h"
44 #include "iwl-helpers.h"
45 #include "iwl-calib.h"
46 #include "iwl-sta.h"
47 #include "iwl-agn-led.h"
48
49 static int iwl4965_send_tx_power(struct iwl_priv *priv);
50 static int iwl4965_hw_get_temperature(struct iwl_priv *priv);
51
52 /* Highest firmware API version supported */
53 #define IWL4965_UCODE_API_MAX 2
54
55 /* Lowest firmware API version supported */
56 #define IWL4965_UCODE_API_MIN 2
57
58 #define IWL4965_FW_PRE "iwlwifi-4965-"
59 #define _IWL4965_MODULE_FIRMWARE(api) IWL4965_FW_PRE #api ".ucode"
60 #define IWL4965_MODULE_FIRMWARE(api) _IWL4965_MODULE_FIRMWARE(api)
61
62
63 /* module parameters */
64 static struct iwl_mod_params iwl4965_mod_params = {
65 .num_of_queues = IWL49_NUM_QUEUES,
66 .num_of_ampdu_queues = IWL49_NUM_AMPDU_QUEUES,
67 .amsdu_size_8K = 1,
68 .restart_fw = 1,
69 /* the rest are 0 by default */
70 };
71
72 /* check contents of special bootstrap uCode SRAM */
73 static int iwl4965_verify_bsm(struct iwl_priv *priv)
74 {
75 __le32 *image = priv->ucode_boot.v_addr;
76 u32 len = priv->ucode_boot.len;
77 u32 reg;
78 u32 val;
79
80 IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
81
82 /* verify BSM SRAM contents */
83 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
84 for (reg = BSM_SRAM_LOWER_BOUND;
85 reg < BSM_SRAM_LOWER_BOUND + len;
86 reg += sizeof(u32), image++) {
87 val = iwl_read_prph(priv, reg);
88 if (val != le32_to_cpu(*image)) {
89 IWL_ERR(priv, "BSM uCode verification failed at "
90 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
91 BSM_SRAM_LOWER_BOUND,
92 reg - BSM_SRAM_LOWER_BOUND, len,
93 val, le32_to_cpu(*image));
94 return -EIO;
95 }
96 }
97
98 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
99
100 return 0;
101 }
102
103 /**
104 * iwl4965_load_bsm - Load bootstrap instructions
105 *
106 * BSM operation:
107 *
108 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
109 * in special SRAM that does not power down during RFKILL. When powering back
110 * up after power-saving sleeps (or during initial uCode load), the BSM loads
111 * the bootstrap program into the on-board processor, and starts it.
112 *
113 * The bootstrap program loads (via DMA) instructions and data for a new
114 * program from host DRAM locations indicated by the host driver in the
115 * BSM_DRAM_* registers. Once the new program is loaded, it starts
116 * automatically.
117 *
118 * When initializing the NIC, the host driver points the BSM to the
119 * "initialize" uCode image. This uCode sets up some internal data, then
120 * notifies host via "initialize alive" that it is complete.
121 *
122 * The host then replaces the BSM_DRAM_* pointer values to point to the
123 * normal runtime uCode instructions and a backup uCode data cache buffer
124 * (filled initially with starting data values for the on-board processor),
125 * then triggers the "initialize" uCode to load and launch the runtime uCode,
126 * which begins normal operation.
127 *
128 * When doing a power-save shutdown, runtime uCode saves data SRAM into
129 * the backup data cache in DRAM before SRAM is powered down.
130 *
131 * When powering back up, the BSM loads the bootstrap program. This reloads
132 * the runtime uCode instructions and the backup data cache into SRAM,
133 * and re-launches the runtime uCode from where it left off.
134 */
135 static int iwl4965_load_bsm(struct iwl_priv *priv)
136 {
137 __le32 *image = priv->ucode_boot.v_addr;
138 u32 len = priv->ucode_boot.len;
139 dma_addr_t pinst;
140 dma_addr_t pdata;
141 u32 inst_len;
142 u32 data_len;
143 int i;
144 u32 done;
145 u32 reg_offset;
146 int ret;
147
148 IWL_DEBUG_INFO(priv, "Begin load bsm\n");
149
150 priv->ucode_type = UCODE_RT;
151
152 /* make sure bootstrap program is no larger than BSM's SRAM size */
153 if (len > IWL49_MAX_BSM_SIZE)
154 return -EINVAL;
155
156 /* Tell bootstrap uCode where to find the "Initialize" uCode
157 * in host DRAM ... host DRAM physical address bits 35:4 for 4965.
158 * NOTE: iwl_init_alive_start() will replace these values,
159 * after the "initialize" uCode has run, to point to
160 * runtime/protocol instructions and backup data cache.
161 */
162 pinst = priv->ucode_init.p_addr >> 4;
163 pdata = priv->ucode_init_data.p_addr >> 4;
164 inst_len = priv->ucode_init.len;
165 data_len = priv->ucode_init_data.len;
166
167 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
168 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
169 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
170 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
171
172 /* Fill BSM memory with bootstrap instructions */
173 for (reg_offset = BSM_SRAM_LOWER_BOUND;
174 reg_offset < BSM_SRAM_LOWER_BOUND + len;
175 reg_offset += sizeof(u32), image++)
176 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
177
178 ret = iwl4965_verify_bsm(priv);
179 if (ret)
180 return ret;
181
182 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
183 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
184 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, IWL49_RTC_INST_LOWER_BOUND);
185 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
186
187 /* Load bootstrap code into instruction SRAM now,
188 * to prepare to load "initialize" uCode */
189 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
190
191 /* Wait for load of bootstrap uCode to finish */
192 for (i = 0; i < 100; i++) {
193 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
194 if (!(done & BSM_WR_CTRL_REG_BIT_START))
195 break;
196 udelay(10);
197 }
198 if (i < 100)
199 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
200 else {
201 IWL_ERR(priv, "BSM write did not complete!\n");
202 return -EIO;
203 }
204
205 /* Enable future boot loads whenever power management unit triggers it
206 * (e.g. when powering back up after power-save shutdown) */
207 iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
208
209
210 return 0;
211 }
212
213 /**
214 * iwl4965_set_ucode_ptrs - Set uCode address location
215 *
216 * Tell initialization uCode where to find runtime uCode.
217 *
218 * BSM registers initially contain pointers to initialization uCode.
219 * We need to replace them to load runtime uCode inst and data,
220 * and to save runtime data when powering down.
221 */
222 static int iwl4965_set_ucode_ptrs(struct iwl_priv *priv)
223 {
224 dma_addr_t pinst;
225 dma_addr_t pdata;
226 int ret = 0;
227
228 /* bits 35:4 for 4965 */
229 pinst = priv->ucode_code.p_addr >> 4;
230 pdata = priv->ucode_data_backup.p_addr >> 4;
231
232 /* Tell bootstrap uCode where to find image to load */
233 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
234 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
235 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
236 priv->ucode_data.len);
237
238 /* Inst byte count must be last to set up, bit 31 signals uCode
239 * that all new ptr/size info is in place */
240 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
241 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
242 IWL_DEBUG_INFO(priv, "Runtime uCode pointers are set.\n");
243
244 return ret;
245 }
246
247 /**
248 * iwl4965_init_alive_start - Called after REPLY_ALIVE notification received
249 *
250 * Called after REPLY_ALIVE notification received from "initialize" uCode.
251 *
252 * The 4965 "initialize" ALIVE reply contains calibration data for:
253 * Voltage, temperature, and MIMO tx gain correction, now stored in priv
254 * (3945 does not contain this data).
255 *
256 * Tell "initialize" uCode to go ahead and load the runtime uCode.
257 */
258 static void iwl4965_init_alive_start(struct iwl_priv *priv)
259 {
260 /* Check alive response for "valid" sign from uCode */
261 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
262 /* We had an error bringing up the hardware, so take it
263 * all the way back down so we can try again */
264 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
265 goto restart;
266 }
267
268 /* Bootstrap uCode has loaded initialize uCode ... verify inst image.
269 * This is a paranoid check, because we would not have gotten the
270 * "initialize" alive if code weren't properly loaded. */
271 if (iwl_verify_ucode(priv)) {
272 /* Runtime instruction load was bad;
273 * take it all the way back down so we can try again */
274 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
275 goto restart;
276 }
277
278 /* Calculate temperature */
279 priv->temperature = iwl4965_hw_get_temperature(priv);
280
281 /* Send pointers to protocol/runtime uCode image ... init code will
282 * load and launch runtime uCode, which will send us another "Alive"
283 * notification. */
284 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
285 if (iwl4965_set_ucode_ptrs(priv)) {
286 /* Runtime instruction load won't happen;
287 * take it all the way back down so we can try again */
288 IWL_DEBUG_INFO(priv, "Couldn't set up uCode pointers.\n");
289 goto restart;
290 }
291 return;
292
293 restart:
294 queue_work(priv->workqueue, &priv->restart);
295 }
296
297 static bool is_ht40_channel(__le32 rxon_flags)
298 {
299 int chan_mod = le32_to_cpu(rxon_flags & RXON_FLG_CHANNEL_MODE_MSK)
300 >> RXON_FLG_CHANNEL_MODE_POS;
301 return ((chan_mod == CHANNEL_MODE_PURE_40) ||
302 (chan_mod == CHANNEL_MODE_MIXED));
303 }
304
305 /*
306 * EEPROM handlers
307 */
308 static u16 iwl4965_eeprom_calib_version(struct iwl_priv *priv)
309 {
310 return iwl_eeprom_query16(priv, EEPROM_4965_CALIB_VERSION_OFFSET);
311 }
312
313 /*
314 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
315 * must be called under priv->lock and mac access
316 */
317 static void iwl4965_txq_set_sched(struct iwl_priv *priv, u32 mask)
318 {
319 iwl_write_prph(priv, IWL49_SCD_TXFACT, mask);
320 }
321
322 static int iwl4965_apm_init(struct iwl_priv *priv)
323 {
324 int ret = 0;
325
326 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
327 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
328
329 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
330 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
331 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
332
333 /* set "initialization complete" bit to move adapter
334 * D0U* --> D0A* state */
335 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
336
337 /* wait for clock stabilization */
338 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
339 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
340 if (ret < 0) {
341 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
342 goto out;
343 }
344
345 /* enable DMA */
346 iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
347 APMG_CLK_VAL_BSM_CLK_RQT);
348
349 udelay(20);
350
351 /* disable L1-Active */
352 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
353 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
354
355 out:
356 return ret;
357 }
358
359
360 static void iwl4965_nic_config(struct iwl_priv *priv)
361 {
362 unsigned long flags;
363 u16 radio_cfg;
364 u16 lctl;
365
366 spin_lock_irqsave(&priv->lock, flags);
367
368 lctl = iwl_pcie_link_ctl(priv);
369
370 /* HW bug W/A - negligible power consumption */
371 /* L1-ASPM is enabled by BIOS */
372 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
373 /* L1-ASPM enabled: disable L0S */
374 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
375 else
376 /* L1-ASPM disabled: enable L0S */
377 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
378
379 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
380
381 /* write radio config values to register */
382 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) == EEPROM_4965_RF_CFG_TYPE_MAX)
383 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
384 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
385 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
386 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
387
388 /* set CSR_HW_CONFIG_REG for uCode use */
389 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
390 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
391 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
392
393 priv->calib_info = (struct iwl_eeprom_calib_info *)
394 iwl_eeprom_query_addr(priv, EEPROM_4965_CALIB_TXPOWER_OFFSET);
395
396 spin_unlock_irqrestore(&priv->lock, flags);
397 }
398
399 static int iwl4965_apm_reset(struct iwl_priv *priv)
400 {
401 int ret = 0;
402
403 iwl_apm_stop_master(priv);
404
405
406 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
407
408 udelay(10);
409
410 /* FIXME: put here L1A -L0S w/a */
411
412 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
413
414 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
415 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
416 if (ret < 0)
417 goto out;
418
419 udelay(10);
420
421 /* Enable DMA and BSM Clock */
422 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT |
423 APMG_CLK_VAL_BSM_CLK_RQT);
424
425 udelay(10);
426
427 /* disable L1A */
428 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
429 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
430
431 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
432 wake_up_interruptible(&priv->wait_command_queue);
433
434 out:
435 return ret;
436 }
437
438 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
439 * Called after every association, but this runs only once!
440 * ... once chain noise is calibrated the first time, it's good forever. */
441 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
442 {
443 struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
444
445 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
446 struct iwl_calib_diff_gain_cmd cmd;
447
448 memset(&cmd, 0, sizeof(cmd));
449 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
450 cmd.diff_gain_a = 0;
451 cmd.diff_gain_b = 0;
452 cmd.diff_gain_c = 0;
453 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
454 sizeof(cmd), &cmd))
455 IWL_ERR(priv,
456 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
457 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
458 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
459 }
460 }
461
462 static void iwl4965_gain_computation(struct iwl_priv *priv,
463 u32 *average_noise,
464 u16 min_average_noise_antenna_i,
465 u32 min_average_noise,
466 u8 default_chain)
467 {
468 int i, ret;
469 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
470
471 data->delta_gain_code[min_average_noise_antenna_i] = 0;
472
473 for (i = default_chain; i < NUM_RX_CHAINS; i++) {
474 s32 delta_g = 0;
475
476 if (!(data->disconn_array[i]) &&
477 (data->delta_gain_code[i] ==
478 CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
479 delta_g = average_noise[i] - min_average_noise;
480 data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
481 data->delta_gain_code[i] =
482 min(data->delta_gain_code[i],
483 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
484
485 data->delta_gain_code[i] =
486 (data->delta_gain_code[i] | (1 << 2));
487 } else {
488 data->delta_gain_code[i] = 0;
489 }
490 }
491 IWL_DEBUG_CALIB(priv, "delta_gain_codes: a %d b %d c %d\n",
492 data->delta_gain_code[0],
493 data->delta_gain_code[1],
494 data->delta_gain_code[2]);
495
496 /* Differential gain gets sent to uCode only once */
497 if (!data->radio_write) {
498 struct iwl_calib_diff_gain_cmd cmd;
499 data->radio_write = 1;
500
501 memset(&cmd, 0, sizeof(cmd));
502 cmd.hdr.op_code = IWL_PHY_CALIBRATE_DIFF_GAIN_CMD;
503 cmd.diff_gain_a = data->delta_gain_code[0];
504 cmd.diff_gain_b = data->delta_gain_code[1];
505 cmd.diff_gain_c = data->delta_gain_code[2];
506 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
507 sizeof(cmd), &cmd);
508 if (ret)
509 IWL_DEBUG_CALIB(priv, "fail sending cmd "
510 "REPLY_PHY_CALIBRATION_CMD \n");
511
512 /* TODO we might want recalculate
513 * rx_chain in rxon cmd */
514
515 /* Mark so we run this algo only once! */
516 data->state = IWL_CHAIN_NOISE_CALIBRATED;
517 }
518 data->chain_noise_a = 0;
519 data->chain_noise_b = 0;
520 data->chain_noise_c = 0;
521 data->chain_signal_a = 0;
522 data->chain_signal_b = 0;
523 data->chain_signal_c = 0;
524 data->beacon_count = 0;
525 }
526
527 static void iwl4965_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
528 __le32 *tx_flags)
529 {
530 if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
531 *tx_flags |= TX_CMD_FLG_RTS_MSK;
532 *tx_flags &= ~TX_CMD_FLG_CTS_MSK;
533 } else if (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
534 *tx_flags &= ~TX_CMD_FLG_RTS_MSK;
535 *tx_flags |= TX_CMD_FLG_CTS_MSK;
536 }
537 }
538
539 static void iwl4965_bg_txpower_work(struct work_struct *work)
540 {
541 struct iwl_priv *priv = container_of(work, struct iwl_priv,
542 txpower_work);
543
544 /* If a scan happened to start before we got here
545 * then just return; the statistics notification will
546 * kick off another scheduled work to compensate for
547 * any temperature delta we missed here. */
548 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
549 test_bit(STATUS_SCANNING, &priv->status))
550 return;
551
552 mutex_lock(&priv->mutex);
553
554 /* Regardless of if we are associated, we must reconfigure the
555 * TX power since frames can be sent on non-radar channels while
556 * not associated */
557 iwl4965_send_tx_power(priv);
558
559 /* Update last_temperature to keep is_calib_needed from running
560 * when it isn't needed... */
561 priv->last_temperature = priv->temperature;
562
563 mutex_unlock(&priv->mutex);
564 }
565
566 /*
567 * Acquire priv->lock before calling this function !
568 */
569 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
570 {
571 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
572 (index & 0xff) | (txq_id << 8));
573 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
574 }
575
576 /**
577 * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
578 * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
579 * @scd_retry: (1) Indicates queue will be used in aggregation mode
580 *
581 * NOTE: Acquire priv->lock before calling this function !
582 */
583 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
584 struct iwl_tx_queue *txq,
585 int tx_fifo_id, int scd_retry)
586 {
587 int txq_id = txq->q.id;
588
589 /* Find out whether to activate Tx queue */
590 int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
591
592 /* Set up and activate */
593 iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
594 (active << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
595 (tx_fifo_id << IWL49_SCD_QUEUE_STTS_REG_POS_TXF) |
596 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_WSL) |
597 (scd_retry << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
598 IWL49_SCD_QUEUE_STTS_REG_MSK);
599
600 txq->sched_retry = scd_retry;
601
602 IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
603 active ? "Activate" : "Deactivate",
604 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
605 }
606
607 static const u16 default_queue_to_tx_fifo[] = {
608 IWL_TX_FIFO_AC3,
609 IWL_TX_FIFO_AC2,
610 IWL_TX_FIFO_AC1,
611 IWL_TX_FIFO_AC0,
612 IWL49_CMD_FIFO_NUM,
613 IWL_TX_FIFO_HCCA_1,
614 IWL_TX_FIFO_HCCA_2
615 };
616
617 static int iwl4965_alive_notify(struct iwl_priv *priv)
618 {
619 u32 a;
620 unsigned long flags;
621 int i, chan;
622 u32 reg_val;
623
624 spin_lock_irqsave(&priv->lock, flags);
625
626 /* Clear 4965's internal Tx Scheduler data base */
627 priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
628 a = priv->scd_base_addr + IWL49_SCD_CONTEXT_DATA_OFFSET;
629 for (; a < priv->scd_base_addr + IWL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4)
630 iwl_write_targ_mem(priv, a, 0);
631 for (; a < priv->scd_base_addr + IWL49_SCD_TRANSLATE_TBL_OFFSET; a += 4)
632 iwl_write_targ_mem(priv, a, 0);
633 for (; a < priv->scd_base_addr +
634 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
635 iwl_write_targ_mem(priv, a, 0);
636
637 /* Tel 4965 where to find Tx byte count tables */
638 iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
639 priv->scd_bc_tbls.dma >> 10);
640
641 /* Enable DMA channel */
642 for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++)
643 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
644 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
645 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
646
647 /* Update FH chicken bits */
648 reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
649 iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
650 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
651
652 /* Disable chain mode for all queues */
653 iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
654
655 /* Initialize each Tx queue (including the command queue) */
656 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
657
658 /* TFD circular buffer read/write indexes */
659 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
660 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
661
662 /* Max Tx Window size for Scheduler-ACK mode */
663 iwl_write_targ_mem(priv, priv->scd_base_addr +
664 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i),
665 (SCD_WIN_SIZE <<
666 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
667 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
668
669 /* Frame limit */
670 iwl_write_targ_mem(priv, priv->scd_base_addr +
671 IWL49_SCD_CONTEXT_QUEUE_OFFSET(i) +
672 sizeof(u32),
673 (SCD_FRAME_LIMIT <<
674 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
675 IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
676
677 }
678 iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
679 (1 << priv->hw_params.max_txq_num) - 1);
680
681 /* Activate all Tx DMA/FIFO channels */
682 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 6));
683
684 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
685
686 /* Map each Tx/cmd queue to its corresponding fifo */
687 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
688 int ac = default_queue_to_tx_fifo[i];
689 iwl_txq_ctx_activate(priv, i);
690 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
691 }
692
693 spin_unlock_irqrestore(&priv->lock, flags);
694
695 return 0;
696 }
697
698 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
699 .min_nrg_cck = 97,
700 .max_nrg_cck = 0, /* not used, set to 0 */
701
702 .auto_corr_min_ofdm = 85,
703 .auto_corr_min_ofdm_mrc = 170,
704 .auto_corr_min_ofdm_x1 = 105,
705 .auto_corr_min_ofdm_mrc_x1 = 220,
706
707 .auto_corr_max_ofdm = 120,
708 .auto_corr_max_ofdm_mrc = 210,
709 .auto_corr_max_ofdm_x1 = 140,
710 .auto_corr_max_ofdm_mrc_x1 = 270,
711
712 .auto_corr_min_cck = 125,
713 .auto_corr_max_cck = 200,
714 .auto_corr_min_cck_mrc = 200,
715 .auto_corr_max_cck_mrc = 400,
716
717 .nrg_th_cck = 100,
718 .nrg_th_ofdm = 100,
719 };
720
721 static void iwl4965_set_ct_threshold(struct iwl_priv *priv)
722 {
723 /* want Kelvin */
724 priv->hw_params.ct_kill_threshold =
725 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY);
726 }
727
728 /**
729 * iwl4965_hw_set_hw_params
730 *
731 * Called when initializing driver
732 */
733 static int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
734 {
735
736 if ((priv->cfg->mod_params->num_of_queues > IWL49_NUM_QUEUES) ||
737 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
738 IWL_ERR(priv,
739 "invalid queues_num, should be between %d and %d\n",
740 IWL_MIN_NUM_QUEUES, IWL49_NUM_QUEUES);
741 return -EINVAL;
742 }
743
744 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
745 priv->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM;
746 priv->hw_params.scd_bc_tbls_size =
747 IWL49_NUM_QUEUES * sizeof(struct iwl4965_scd_bc_tbl);
748 priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
749 priv->hw_params.max_stations = IWL4965_STATION_COUNT;
750 priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
751 priv->hw_params.max_data_size = IWL49_RTC_DATA_SIZE;
752 priv->hw_params.max_inst_size = IWL49_RTC_INST_SIZE;
753 priv->hw_params.max_bsm_size = BSM_SRAM_SIZE;
754 priv->hw_params.ht40_channel = BIT(IEEE80211_BAND_5GHZ);
755
756 priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
757
758 priv->hw_params.tx_chains_num = 2;
759 priv->hw_params.rx_chains_num = 2;
760 priv->hw_params.valid_tx_ant = ANT_A | ANT_B;
761 priv->hw_params.valid_rx_ant = ANT_A | ANT_B;
762 if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
763 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
764
765 priv->hw_params.sens = &iwl4965_sensitivity;
766
767 return 0;
768 }
769
770 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
771 {
772 s32 sign = 1;
773
774 if (num < 0) {
775 sign = -sign;
776 num = -num;
777 }
778 if (denom < 0) {
779 sign = -sign;
780 denom = -denom;
781 }
782 *res = 1;
783 *res = ((num * 2 + denom) / (denom * 2)) * sign;
784
785 return 1;
786 }
787
788 /**
789 * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
790 *
791 * Determines power supply voltage compensation for txpower calculations.
792 * Returns number of 1/2-dB steps to subtract from gain table index,
793 * to compensate for difference between power supply voltage during
794 * factory measurements, vs. current power supply voltage.
795 *
796 * Voltage indication is higher for lower voltage.
797 * Lower voltage requires more gain (lower gain table index).
798 */
799 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
800 s32 current_voltage)
801 {
802 s32 comp = 0;
803
804 if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
805 (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
806 return 0;
807
808 iwl4965_math_div_round(current_voltage - eeprom_voltage,
809 TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
810
811 if (current_voltage > eeprom_voltage)
812 comp *= 2;
813 if ((comp < -2) || (comp > 2))
814 comp = 0;
815
816 return comp;
817 }
818
819 static s32 iwl4965_get_tx_atten_grp(u16 channel)
820 {
821 if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
822 channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
823 return CALIB_CH_GROUP_5;
824
825 if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
826 channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
827 return CALIB_CH_GROUP_1;
828
829 if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
830 channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
831 return CALIB_CH_GROUP_2;
832
833 if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
834 channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
835 return CALIB_CH_GROUP_3;
836
837 if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
838 channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
839 return CALIB_CH_GROUP_4;
840
841 return -1;
842 }
843
844 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
845 {
846 s32 b = -1;
847
848 for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
849 if (priv->calib_info->band_info[b].ch_from == 0)
850 continue;
851
852 if ((channel >= priv->calib_info->band_info[b].ch_from)
853 && (channel <= priv->calib_info->band_info[b].ch_to))
854 break;
855 }
856
857 return b;
858 }
859
860 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
861 {
862 s32 val;
863
864 if (x2 == x1)
865 return y1;
866 else {
867 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
868 return val + y2;
869 }
870 }
871
872 /**
873 * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
874 *
875 * Interpolates factory measurements from the two sample channels within a
876 * sub-band, to apply to channel of interest. Interpolation is proportional to
877 * differences in channel frequencies, which is proportional to differences
878 * in channel number.
879 */
880 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
881 struct iwl_eeprom_calib_ch_info *chan_info)
882 {
883 s32 s = -1;
884 u32 c;
885 u32 m;
886 const struct iwl_eeprom_calib_measure *m1;
887 const struct iwl_eeprom_calib_measure *m2;
888 struct iwl_eeprom_calib_measure *omeas;
889 u32 ch_i1;
890 u32 ch_i2;
891
892 s = iwl4965_get_sub_band(priv, channel);
893 if (s >= EEPROM_TX_POWER_BANDS) {
894 IWL_ERR(priv, "Tx Power can not find channel %d\n", channel);
895 return -1;
896 }
897
898 ch_i1 = priv->calib_info->band_info[s].ch1.ch_num;
899 ch_i2 = priv->calib_info->band_info[s].ch2.ch_num;
900 chan_info->ch_num = (u8) channel;
901
902 IWL_DEBUG_TXPOWER(priv, "channel %d subband %d factory cal ch %d & %d\n",
903 channel, s, ch_i1, ch_i2);
904
905 for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
906 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
907 m1 = &(priv->calib_info->band_info[s].ch1.
908 measurements[c][m]);
909 m2 = &(priv->calib_info->band_info[s].ch2.
910 measurements[c][m]);
911 omeas = &(chan_info->measurements[c][m]);
912
913 omeas->actual_pow =
914 (u8) iwl4965_interpolate_value(channel, ch_i1,
915 m1->actual_pow,
916 ch_i2,
917 m2->actual_pow);
918 omeas->gain_idx =
919 (u8) iwl4965_interpolate_value(channel, ch_i1,
920 m1->gain_idx, ch_i2,
921 m2->gain_idx);
922 omeas->temperature =
923 (u8) iwl4965_interpolate_value(channel, ch_i1,
924 m1->temperature,
925 ch_i2,
926 m2->temperature);
927 omeas->pa_det =
928 (s8) iwl4965_interpolate_value(channel, ch_i1,
929 m1->pa_det, ch_i2,
930 m2->pa_det);
931
932 IWL_DEBUG_TXPOWER(priv,
933 "chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
934 m1->actual_pow, m2->actual_pow, omeas->actual_pow);
935 IWL_DEBUG_TXPOWER(priv,
936 "chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
937 m1->gain_idx, m2->gain_idx, omeas->gain_idx);
938 IWL_DEBUG_TXPOWER(priv,
939 "chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
940 m1->pa_det, m2->pa_det, omeas->pa_det);
941 IWL_DEBUG_TXPOWER(priv,
942 "chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
943 m1->temperature, m2->temperature,
944 omeas->temperature);
945 }
946 }
947
948 return 0;
949 }
950
951 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
952 * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
953 static s32 back_off_table[] = {
954 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
955 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
956 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
957 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
958 10 /* CCK */
959 };
960
961 /* Thermal compensation values for txpower for various frequency ranges ...
962 * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
963 static struct iwl4965_txpower_comp_entry {
964 s32 degrees_per_05db_a;
965 s32 degrees_per_05db_a_denom;
966 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
967 {9, 2}, /* group 0 5.2, ch 34-43 */
968 {4, 1}, /* group 1 5.2, ch 44-70 */
969 {4, 1}, /* group 2 5.2, ch 71-124 */
970 {4, 1}, /* group 3 5.2, ch 125-200 */
971 {3, 1} /* group 4 2.4, ch all */
972 };
973
974 static s32 get_min_power_index(s32 rate_power_index, u32 band)
975 {
976 if (!band) {
977 if ((rate_power_index & 7) <= 4)
978 return MIN_TX_GAIN_INDEX_52GHZ_EXT;
979 }
980 return MIN_TX_GAIN_INDEX;
981 }
982
983 struct gain_entry {
984 u8 dsp;
985 u8 radio;
986 };
987
988 static const struct gain_entry gain_table[2][108] = {
989 /* 5.2GHz power gain index table */
990 {
991 {123, 0x3F}, /* highest txpower */
992 {117, 0x3F},
993 {110, 0x3F},
994 {104, 0x3F},
995 {98, 0x3F},
996 {110, 0x3E},
997 {104, 0x3E},
998 {98, 0x3E},
999 {110, 0x3D},
1000 {104, 0x3D},
1001 {98, 0x3D},
1002 {110, 0x3C},
1003 {104, 0x3C},
1004 {98, 0x3C},
1005 {110, 0x3B},
1006 {104, 0x3B},
1007 {98, 0x3B},
1008 {110, 0x3A},
1009 {104, 0x3A},
1010 {98, 0x3A},
1011 {110, 0x39},
1012 {104, 0x39},
1013 {98, 0x39},
1014 {110, 0x38},
1015 {104, 0x38},
1016 {98, 0x38},
1017 {110, 0x37},
1018 {104, 0x37},
1019 {98, 0x37},
1020 {110, 0x36},
1021 {104, 0x36},
1022 {98, 0x36},
1023 {110, 0x35},
1024 {104, 0x35},
1025 {98, 0x35},
1026 {110, 0x34},
1027 {104, 0x34},
1028 {98, 0x34},
1029 {110, 0x33},
1030 {104, 0x33},
1031 {98, 0x33},
1032 {110, 0x32},
1033 {104, 0x32},
1034 {98, 0x32},
1035 {110, 0x31},
1036 {104, 0x31},
1037 {98, 0x31},
1038 {110, 0x30},
1039 {104, 0x30},
1040 {98, 0x30},
1041 {110, 0x25},
1042 {104, 0x25},
1043 {98, 0x25},
1044 {110, 0x24},
1045 {104, 0x24},
1046 {98, 0x24},
1047 {110, 0x23},
1048 {104, 0x23},
1049 {98, 0x23},
1050 {110, 0x22},
1051 {104, 0x18},
1052 {98, 0x18},
1053 {110, 0x17},
1054 {104, 0x17},
1055 {98, 0x17},
1056 {110, 0x16},
1057 {104, 0x16},
1058 {98, 0x16},
1059 {110, 0x15},
1060 {104, 0x15},
1061 {98, 0x15},
1062 {110, 0x14},
1063 {104, 0x14},
1064 {98, 0x14},
1065 {110, 0x13},
1066 {104, 0x13},
1067 {98, 0x13},
1068 {110, 0x12},
1069 {104, 0x08},
1070 {98, 0x08},
1071 {110, 0x07},
1072 {104, 0x07},
1073 {98, 0x07},
1074 {110, 0x06},
1075 {104, 0x06},
1076 {98, 0x06},
1077 {110, 0x05},
1078 {104, 0x05},
1079 {98, 0x05},
1080 {110, 0x04},
1081 {104, 0x04},
1082 {98, 0x04},
1083 {110, 0x03},
1084 {104, 0x03},
1085 {98, 0x03},
1086 {110, 0x02},
1087 {104, 0x02},
1088 {98, 0x02},
1089 {110, 0x01},
1090 {104, 0x01},
1091 {98, 0x01},
1092 {110, 0x00},
1093 {104, 0x00},
1094 {98, 0x00},
1095 {93, 0x00},
1096 {88, 0x00},
1097 {83, 0x00},
1098 {78, 0x00},
1099 },
1100 /* 2.4GHz power gain index table */
1101 {
1102 {110, 0x3f}, /* highest txpower */
1103 {104, 0x3f},
1104 {98, 0x3f},
1105 {110, 0x3e},
1106 {104, 0x3e},
1107 {98, 0x3e},
1108 {110, 0x3d},
1109 {104, 0x3d},
1110 {98, 0x3d},
1111 {110, 0x3c},
1112 {104, 0x3c},
1113 {98, 0x3c},
1114 {110, 0x3b},
1115 {104, 0x3b},
1116 {98, 0x3b},
1117 {110, 0x3a},
1118 {104, 0x3a},
1119 {98, 0x3a},
1120 {110, 0x39},
1121 {104, 0x39},
1122 {98, 0x39},
1123 {110, 0x38},
1124 {104, 0x38},
1125 {98, 0x38},
1126 {110, 0x37},
1127 {104, 0x37},
1128 {98, 0x37},
1129 {110, 0x36},
1130 {104, 0x36},
1131 {98, 0x36},
1132 {110, 0x35},
1133 {104, 0x35},
1134 {98, 0x35},
1135 {110, 0x34},
1136 {104, 0x34},
1137 {98, 0x34},
1138 {110, 0x33},
1139 {104, 0x33},
1140 {98, 0x33},
1141 {110, 0x32},
1142 {104, 0x32},
1143 {98, 0x32},
1144 {110, 0x31},
1145 {104, 0x31},
1146 {98, 0x31},
1147 {110, 0x30},
1148 {104, 0x30},
1149 {98, 0x30},
1150 {110, 0x6},
1151 {104, 0x6},
1152 {98, 0x6},
1153 {110, 0x5},
1154 {104, 0x5},
1155 {98, 0x5},
1156 {110, 0x4},
1157 {104, 0x4},
1158 {98, 0x4},
1159 {110, 0x3},
1160 {104, 0x3},
1161 {98, 0x3},
1162 {110, 0x2},
1163 {104, 0x2},
1164 {98, 0x2},
1165 {110, 0x1},
1166 {104, 0x1},
1167 {98, 0x1},
1168 {110, 0x0},
1169 {104, 0x0},
1170 {98, 0x0},
1171 {97, 0},
1172 {96, 0},
1173 {95, 0},
1174 {94, 0},
1175 {93, 0},
1176 {92, 0},
1177 {91, 0},
1178 {90, 0},
1179 {89, 0},
1180 {88, 0},
1181 {87, 0},
1182 {86, 0},
1183 {85, 0},
1184 {84, 0},
1185 {83, 0},
1186 {82, 0},
1187 {81, 0},
1188 {80, 0},
1189 {79, 0},
1190 {78, 0},
1191 {77, 0},
1192 {76, 0},
1193 {75, 0},
1194 {74, 0},
1195 {73, 0},
1196 {72, 0},
1197 {71, 0},
1198 {70, 0},
1199 {69, 0},
1200 {68, 0},
1201 {67, 0},
1202 {66, 0},
1203 {65, 0},
1204 {64, 0},
1205 {63, 0},
1206 {62, 0},
1207 {61, 0},
1208 {60, 0},
1209 {59, 0},
1210 }
1211 };
1212
1213 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1214 u8 is_ht40, u8 ctrl_chan_high,
1215 struct iwl4965_tx_power_db *tx_power_tbl)
1216 {
1217 u8 saturation_power;
1218 s32 target_power;
1219 s32 user_target_power;
1220 s32 power_limit;
1221 s32 current_temp;
1222 s32 reg_limit;
1223 s32 current_regulatory;
1224 s32 txatten_grp = CALIB_CH_GROUP_MAX;
1225 int i;
1226 int c;
1227 const struct iwl_channel_info *ch_info = NULL;
1228 struct iwl_eeprom_calib_ch_info ch_eeprom_info;
1229 const struct iwl_eeprom_calib_measure *measurement;
1230 s16 voltage;
1231 s32 init_voltage;
1232 s32 voltage_compensation;
1233 s32 degrees_per_05db_num;
1234 s32 degrees_per_05db_denom;
1235 s32 factory_temp;
1236 s32 temperature_comp[2];
1237 s32 factory_gain_index[2];
1238 s32 factory_actual_pwr[2];
1239 s32 power_index;
1240
1241 /* tx_power_user_lmt is in dBm, convert to half-dBm (half-dB units
1242 * are used for indexing into txpower table) */
1243 user_target_power = 2 * priv->tx_power_user_lmt;
1244
1245 /* Get current (RXON) channel, band, width */
1246 IWL_DEBUG_TXPOWER(priv, "chan %d band %d is_ht40 %d\n", channel, band,
1247 is_ht40);
1248
1249 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1250
1251 if (!is_channel_valid(ch_info))
1252 return -EINVAL;
1253
1254 /* get txatten group, used to select 1) thermal txpower adjustment
1255 * and 2) mimo txpower balance between Tx chains. */
1256 txatten_grp = iwl4965_get_tx_atten_grp(channel);
1257 if (txatten_grp < 0) {
1258 IWL_ERR(priv, "Can't find txatten group for channel %d.\n",
1259 channel);
1260 return -EINVAL;
1261 }
1262
1263 IWL_DEBUG_TXPOWER(priv, "channel %d belongs to txatten group %d\n",
1264 channel, txatten_grp);
1265
1266 if (is_ht40) {
1267 if (ctrl_chan_high)
1268 channel -= 2;
1269 else
1270 channel += 2;
1271 }
1272
1273 /* hardware txpower limits ...
1274 * saturation (clipping distortion) txpowers are in half-dBm */
1275 if (band)
1276 saturation_power = priv->calib_info->saturation_power24;
1277 else
1278 saturation_power = priv->calib_info->saturation_power52;
1279
1280 if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
1281 saturation_power > IWL_TX_POWER_SATURATION_MAX) {
1282 if (band)
1283 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
1284 else
1285 saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
1286 }
1287
1288 /* regulatory txpower limits ... reg_limit values are in half-dBm,
1289 * max_power_avg values are in dBm, convert * 2 */
1290 if (is_ht40)
1291 reg_limit = ch_info->ht40_max_power_avg * 2;
1292 else
1293 reg_limit = ch_info->max_power_avg * 2;
1294
1295 if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
1296 (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
1297 if (band)
1298 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
1299 else
1300 reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
1301 }
1302
1303 /* Interpolate txpower calibration values for this channel,
1304 * based on factory calibration tests on spaced channels. */
1305 iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
1306
1307 /* calculate tx gain adjustment based on power supply voltage */
1308 voltage = priv->calib_info->voltage;
1309 init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
1310 voltage_compensation =
1311 iwl4965_get_voltage_compensation(voltage, init_voltage);
1312
1313 IWL_DEBUG_TXPOWER(priv, "curr volt %d eeprom volt %d volt comp %d\n",
1314 init_voltage,
1315 voltage, voltage_compensation);
1316
1317 /* get current temperature (Celsius) */
1318 current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
1319 current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
1320 current_temp = KELVIN_TO_CELSIUS(current_temp);
1321
1322 /* select thermal txpower adjustment params, based on channel group
1323 * (same frequency group used for mimo txatten adjustment) */
1324 degrees_per_05db_num =
1325 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
1326 degrees_per_05db_denom =
1327 tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
1328
1329 /* get per-chain txpower values from factory measurements */
1330 for (c = 0; c < 2; c++) {
1331 measurement = &ch_eeprom_info.measurements[c][1];
1332
1333 /* txgain adjustment (in half-dB steps) based on difference
1334 * between factory and current temperature */
1335 factory_temp = measurement->temperature;
1336 iwl4965_math_div_round((current_temp - factory_temp) *
1337 degrees_per_05db_denom,
1338 degrees_per_05db_num,
1339 &temperature_comp[c]);
1340
1341 factory_gain_index[c] = measurement->gain_idx;
1342 factory_actual_pwr[c] = measurement->actual_pow;
1343
1344 IWL_DEBUG_TXPOWER(priv, "chain = %d\n", c);
1345 IWL_DEBUG_TXPOWER(priv, "fctry tmp %d, "
1346 "curr tmp %d, comp %d steps\n",
1347 factory_temp, current_temp,
1348 temperature_comp[c]);
1349
1350 IWL_DEBUG_TXPOWER(priv, "fctry idx %d, fctry pwr %d\n",
1351 factory_gain_index[c],
1352 factory_actual_pwr[c]);
1353 }
1354
1355 /* for each of 33 bit-rates (including 1 for CCK) */
1356 for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
1357 u8 is_mimo_rate;
1358 union iwl4965_tx_power_dual_stream tx_power;
1359
1360 /* for mimo, reduce each chain's txpower by half
1361 * (3dB, 6 steps), so total output power is regulatory
1362 * compliant. */
1363 if (i & 0x8) {
1364 current_regulatory = reg_limit -
1365 IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
1366 is_mimo_rate = 1;
1367 } else {
1368 current_regulatory = reg_limit;
1369 is_mimo_rate = 0;
1370 }
1371
1372 /* find txpower limit, either hardware or regulatory */
1373 power_limit = saturation_power - back_off_table[i];
1374 if (power_limit > current_regulatory)
1375 power_limit = current_regulatory;
1376
1377 /* reduce user's txpower request if necessary
1378 * for this rate on this channel */
1379 target_power = user_target_power;
1380 if (target_power > power_limit)
1381 target_power = power_limit;
1382
1383 IWL_DEBUG_TXPOWER(priv, "rate %d sat %d reg %d usr %d tgt %d\n",
1384 i, saturation_power - back_off_table[i],
1385 current_regulatory, user_target_power,
1386 target_power);
1387
1388 /* for each of 2 Tx chains (radio transmitters) */
1389 for (c = 0; c < 2; c++) {
1390 s32 atten_value;
1391
1392 if (is_mimo_rate)
1393 atten_value =
1394 (s32)le32_to_cpu(priv->card_alive_init.
1395 tx_atten[txatten_grp][c]);
1396 else
1397 atten_value = 0;
1398
1399 /* calculate index; higher index means lower txpower */
1400 power_index = (u8) (factory_gain_index[c] -
1401 (target_power -
1402 factory_actual_pwr[c]) -
1403 temperature_comp[c] -
1404 voltage_compensation +
1405 atten_value);
1406
1407 /* IWL_DEBUG_TXPOWER(priv, "calculated txpower index %d\n",
1408 power_index); */
1409
1410 if (power_index < get_min_power_index(i, band))
1411 power_index = get_min_power_index(i, band);
1412
1413 /* adjust 5 GHz index to support negative indexes */
1414 if (!band)
1415 power_index += 9;
1416
1417 /* CCK, rate 32, reduce txpower for CCK */
1418 if (i == POWER_TABLE_CCK_ENTRY)
1419 power_index +=
1420 IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
1421
1422 /* stay within the table! */
1423 if (power_index > 107) {
1424 IWL_WARN(priv, "txpower index %d > 107\n",
1425 power_index);
1426 power_index = 107;
1427 }
1428 if (power_index < 0) {
1429 IWL_WARN(priv, "txpower index %d < 0\n",
1430 power_index);
1431 power_index = 0;
1432 }
1433
1434 /* fill txpower command for this rate/chain */
1435 tx_power.s.radio_tx_gain[c] =
1436 gain_table[band][power_index].radio;
1437 tx_power.s.dsp_predis_atten[c] =
1438 gain_table[band][power_index].dsp;
1439
1440 IWL_DEBUG_TXPOWER(priv, "chain %d mimo %d index %d "
1441 "gain 0x%02x dsp %d\n",
1442 c, atten_value, power_index,
1443 tx_power.s.radio_tx_gain[c],
1444 tx_power.s.dsp_predis_atten[c]);
1445 } /* for each chain */
1446
1447 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
1448
1449 } /* for each rate */
1450
1451 return 0;
1452 }
1453
1454 /**
1455 * iwl4965_send_tx_power - Configure the TXPOWER level user limit
1456 *
1457 * Uses the active RXON for channel, band, and characteristics (ht40, high)
1458 * The power limit is taken from priv->tx_power_user_lmt.
1459 */
1460 static int iwl4965_send_tx_power(struct iwl_priv *priv)
1461 {
1462 struct iwl4965_txpowertable_cmd cmd = { 0 };
1463 int ret;
1464 u8 band = 0;
1465 bool is_ht40 = false;
1466 u8 ctrl_chan_high = 0;
1467
1468 if (test_bit(STATUS_SCANNING, &priv->status)) {
1469 /* If this gets hit a lot, switch it to a BUG() and catch
1470 * the stack trace to find out who is calling this during
1471 * a scan. */
1472 IWL_WARN(priv, "TX Power requested while scanning!\n");
1473 return -EAGAIN;
1474 }
1475
1476 band = priv->band == IEEE80211_BAND_2GHZ;
1477
1478 is_ht40 = is_ht40_channel(priv->active_rxon.flags);
1479
1480 if (is_ht40 &&
1481 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1482 ctrl_chan_high = 1;
1483
1484 cmd.band = band;
1485 cmd.channel = priv->active_rxon.channel;
1486
1487 ret = iwl4965_fill_txpower_tbl(priv, band,
1488 le16_to_cpu(priv->active_rxon.channel),
1489 is_ht40, ctrl_chan_high, &cmd.tx_power);
1490 if (ret)
1491 goto out;
1492
1493 ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
1494
1495 out:
1496 return ret;
1497 }
1498
1499 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
1500 {
1501 int ret = 0;
1502 struct iwl4965_rxon_assoc_cmd rxon_assoc;
1503 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1504 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1505
1506 if ((rxon1->flags == rxon2->flags) &&
1507 (rxon1->filter_flags == rxon2->filter_flags) &&
1508 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1509 (rxon1->ofdm_ht_single_stream_basic_rates ==
1510 rxon2->ofdm_ht_single_stream_basic_rates) &&
1511 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1512 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1513 (rxon1->rx_chain == rxon2->rx_chain) &&
1514 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1515 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n");
1516 return 0;
1517 }
1518
1519 rxon_assoc.flags = priv->staging_rxon.flags;
1520 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1521 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1522 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1523 rxon_assoc.reserved = 0;
1524 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1525 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1526 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1527 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1528 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1529
1530 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1531 sizeof(rxon_assoc), &rxon_assoc, NULL);
1532 if (ret)
1533 return ret;
1534
1535 return ret;
1536 }
1537
1538 #ifdef IEEE80211_CONF_CHANNEL_SWITCH
1539 static int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1540 {
1541 int rc;
1542 u8 band = 0;
1543 bool is_ht40 = false;
1544 u8 ctrl_chan_high = 0;
1545 struct iwl4965_channel_switch_cmd cmd = { 0 };
1546 const struct iwl_channel_info *ch_info;
1547
1548 band = priv->band == IEEE80211_BAND_2GHZ;
1549
1550 ch_info = iwl_get_channel_info(priv, priv->band, channel);
1551
1552 is_ht40 = is_ht40_channel(priv->staging_rxon.flags);
1553
1554 if (is_ht40 &&
1555 (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
1556 ctrl_chan_high = 1;
1557
1558 cmd.band = band;
1559 cmd.expect_beacon = 0;
1560 cmd.channel = cpu_to_le16(channel);
1561 cmd.rxon_flags = priv->active_rxon.flags;
1562 cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
1563 cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1564 if (ch_info)
1565 cmd.expect_beacon = is_channel_radar(ch_info);
1566 else
1567 cmd.expect_beacon = 1;
1568
1569 rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_ht40,
1570 ctrl_chan_high, &cmd.tx_power);
1571 if (rc) {
1572 IWL_DEBUG_11H(priv, "error:%d fill txpower_tbl\n", rc);
1573 return rc;
1574 }
1575
1576 rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
1577 return rc;
1578 }
1579 #endif
1580
1581 /**
1582 * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
1583 */
1584 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
1585 struct iwl_tx_queue *txq,
1586 u16 byte_cnt)
1587 {
1588 struct iwl4965_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
1589 int txq_id = txq->q.id;
1590 int write_ptr = txq->q.write_ptr;
1591 int len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
1592 __le16 bc_ent;
1593
1594 WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
1595
1596 bc_ent = cpu_to_le16(len & 0xFFF);
1597 /* Set up byte count within first 256 entries */
1598 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
1599
1600 /* If within first 64 entries, duplicate at end */
1601 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
1602 scd_bc_tbl[txq_id].
1603 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
1604 }
1605
1606 /**
1607 * sign_extend - Sign extend a value using specified bit as sign-bit
1608 *
1609 * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
1610 * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
1611 *
1612 * @param oper value to sign extend
1613 * @param index 0 based bit index (0<=index<32) to sign bit
1614 */
1615 static s32 sign_extend(u32 oper, int index)
1616 {
1617 u8 shift = 31 - index;
1618
1619 return (s32)(oper << shift) >> shift;
1620 }
1621
1622 /**
1623 * iwl4965_hw_get_temperature - return the calibrated temperature (in Kelvin)
1624 * @statistics: Provides the temperature reading from the uCode
1625 *
1626 * A return of <0 indicates bogus data in the statistics
1627 */
1628 static int iwl4965_hw_get_temperature(struct iwl_priv *priv)
1629 {
1630 s32 temperature;
1631 s32 vt;
1632 s32 R1, R2, R3;
1633 u32 R4;
1634
1635 if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
1636 (priv->statistics.flag & STATISTICS_REPLY_FLG_HT40_MODE_MSK)) {
1637 IWL_DEBUG_TEMP(priv, "Running HT40 temperature calibration\n");
1638 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1639 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1640 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1641 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
1642 } else {
1643 IWL_DEBUG_TEMP(priv, "Running temperature calibration\n");
1644 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1645 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1646 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1647 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
1648 }
1649
1650 /*
1651 * Temperature is only 23 bits, so sign extend out to 32.
1652 *
1653 * NOTE If we haven't received a statistics notification yet
1654 * with an updated temperature, use R4 provided to us in the
1655 * "initialize" ALIVE response.
1656 */
1657 if (!test_bit(STATUS_TEMPERATURE, &priv->status))
1658 vt = sign_extend(R4, 23);
1659 else
1660 vt = sign_extend(
1661 le32_to_cpu(priv->statistics.general.temperature), 23);
1662
1663 IWL_DEBUG_TEMP(priv, "Calib values R[1-3]: %d %d %d R4: %d\n", R1, R2, R3, vt);
1664
1665 if (R3 == R1) {
1666 IWL_ERR(priv, "Calibration conflict R1 == R3\n");
1667 return -1;
1668 }
1669
1670 /* Calculate temperature in degrees Kelvin, adjust by 97%.
1671 * Add offset to center the adjustment around 0 degrees Centigrade. */
1672 temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
1673 temperature /= (R3 - R1);
1674 temperature = (temperature * 97) / 100 + TEMPERATURE_CALIB_KELVIN_OFFSET;
1675
1676 IWL_DEBUG_TEMP(priv, "Calibrated temperature: %dK, %dC\n",
1677 temperature, KELVIN_TO_CELSIUS(temperature));
1678
1679 return temperature;
1680 }
1681
1682 /* Adjust Txpower only if temperature variance is greater than threshold. */
1683 #define IWL_TEMPERATURE_THRESHOLD 3
1684
1685 /**
1686 * iwl4965_is_temp_calib_needed - determines if new calibration is needed
1687 *
1688 * If the temperature changed has changed sufficiently, then a recalibration
1689 * is needed.
1690 *
1691 * Assumes caller will replace priv->last_temperature once calibration
1692 * executed.
1693 */
1694 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
1695 {
1696 int temp_diff;
1697
1698 if (!test_bit(STATUS_STATISTICS, &priv->status)) {
1699 IWL_DEBUG_TEMP(priv, "Temperature not updated -- no statistics.\n");
1700 return 0;
1701 }
1702
1703 temp_diff = priv->temperature - priv->last_temperature;
1704
1705 /* get absolute value */
1706 if (temp_diff < 0) {
1707 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d, \n", temp_diff);
1708 temp_diff = -temp_diff;
1709 } else if (temp_diff == 0)
1710 IWL_DEBUG_POWER(priv, "Same temp, \n");
1711 else
1712 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d, \n", temp_diff);
1713
1714 if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
1715 IWL_DEBUG_POWER(priv, "Thermal txpower calib not needed\n");
1716 return 0;
1717 }
1718
1719 IWL_DEBUG_POWER(priv, "Thermal txpower calib needed\n");
1720
1721 return 1;
1722 }
1723
1724 static void iwl4965_temperature_calib(struct iwl_priv *priv)
1725 {
1726 s32 temp;
1727
1728 temp = iwl4965_hw_get_temperature(priv);
1729 if (temp < 0)
1730 return;
1731
1732 if (priv->temperature != temp) {
1733 if (priv->temperature)
1734 IWL_DEBUG_TEMP(priv, "Temperature changed "
1735 "from %dC to %dC\n",
1736 KELVIN_TO_CELSIUS(priv->temperature),
1737 KELVIN_TO_CELSIUS(temp));
1738 else
1739 IWL_DEBUG_TEMP(priv, "Temperature "
1740 "initialized to %dC\n",
1741 KELVIN_TO_CELSIUS(temp));
1742 }
1743
1744 priv->temperature = temp;
1745 iwl_tt_handler(priv);
1746 set_bit(STATUS_TEMPERATURE, &priv->status);
1747
1748 if (!priv->disable_tx_power_cal &&
1749 unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
1750 iwl4965_is_temp_calib_needed(priv))
1751 queue_work(priv->workqueue, &priv->txpower_work);
1752 }
1753
1754 /**
1755 * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
1756 */
1757 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
1758 u16 txq_id)
1759 {
1760 /* Simply stop the queue, but don't change any configuration;
1761 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1762 iwl_write_prph(priv,
1763 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1764 (0 << IWL49_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1765 (1 << IWL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1766 }
1767
1768 /**
1769 * txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE
1770 * priv->lock must be held by the caller
1771 */
1772 static int iwl4965_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1773 u16 ssn_idx, u8 tx_fifo)
1774 {
1775 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1776 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1777 IWL_WARN(priv,
1778 "queue number out of range: %d, must be %d to %d\n",
1779 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1780 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1781 return -EINVAL;
1782 }
1783
1784 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1785
1786 iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1787
1788 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1789 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1790 /* supposes that ssn_idx is valid (!= 0xFFF) */
1791 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1792
1793 iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1794 iwl_txq_ctx_deactivate(priv, txq_id);
1795 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1796
1797 return 0;
1798 }
1799
1800 /**
1801 * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
1802 */
1803 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1804 u16 txq_id)
1805 {
1806 u32 tbl_dw_addr;
1807 u32 tbl_dw;
1808 u16 scd_q2ratid;
1809
1810 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1811
1812 tbl_dw_addr = priv->scd_base_addr +
1813 IWL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1814
1815 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1816
1817 if (txq_id & 0x1)
1818 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1819 else
1820 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1821
1822 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1823
1824 return 0;
1825 }
1826
1827
1828 /**
1829 * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
1830 *
1831 * NOTE: txq_id must be greater than IWL49_FIRST_AMPDU_QUEUE,
1832 * i.e. it must be one of the higher queues used for aggregation
1833 */
1834 static int iwl4965_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1835 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1836 {
1837 unsigned long flags;
1838 u16 ra_tid;
1839
1840 if ((IWL49_FIRST_AMPDU_QUEUE > txq_id) ||
1841 (IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES <= txq_id)) {
1842 IWL_WARN(priv,
1843 "queue number out of range: %d, must be %d to %d\n",
1844 txq_id, IWL49_FIRST_AMPDU_QUEUE,
1845 IWL49_FIRST_AMPDU_QUEUE + IWL49_NUM_AMPDU_QUEUES - 1);
1846 return -EINVAL;
1847 }
1848
1849 ra_tid = BUILD_RAxTID(sta_id, tid);
1850
1851 /* Modify device's station table to Tx this TID */
1852 iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1853
1854 spin_lock_irqsave(&priv->lock, flags);
1855
1856 /* Stop this Tx queue before configuring it */
1857 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
1858
1859 /* Map receiver-address / traffic-ID to this queue */
1860 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1861
1862 /* Set this queue as a chain-building queue */
1863 iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
1864
1865 /* Place first TFD at index corresponding to start sequence number.
1866 * Assumes that ssn_idx is valid (!= 0xFFF) */
1867 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1868 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1869 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
1870
1871 /* Set up Tx window size and frame limit for this queue */
1872 iwl_write_targ_mem(priv,
1873 priv->scd_base_addr + IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id),
1874 (SCD_WIN_SIZE << IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1875 IWL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1876
1877 iwl_write_targ_mem(priv, priv->scd_base_addr +
1878 IWL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1879 (SCD_FRAME_LIMIT << IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
1880 & IWL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1881
1882 iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
1883
1884 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1885 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1886
1887 spin_unlock_irqrestore(&priv->lock, flags);
1888
1889 return 0;
1890 }
1891
1892
1893 static u16 iwl4965_get_hcmd_size(u8 cmd_id, u16 len)
1894 {
1895 switch (cmd_id) {
1896 case REPLY_RXON:
1897 return (u16) sizeof(struct iwl4965_rxon_cmd);
1898 default:
1899 return len;
1900 }
1901 }
1902
1903 static u16 iwl4965_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1904 {
1905 struct iwl4965_addsta_cmd *addsta = (struct iwl4965_addsta_cmd *)data;
1906 addsta->mode = cmd->mode;
1907 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
1908 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
1909 addsta->station_flags = cmd->station_flags;
1910 addsta->station_flags_msk = cmd->station_flags_msk;
1911 addsta->tid_disable_tx = cmd->tid_disable_tx;
1912 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
1913 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
1914 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
1915 addsta->reserved1 = cpu_to_le16(0);
1916 addsta->reserved2 = cpu_to_le32(0);
1917
1918 return (u16)sizeof(struct iwl4965_addsta_cmd);
1919 }
1920
1921 static inline u32 iwl4965_get_scd_ssn(struct iwl4965_tx_resp *tx_resp)
1922 {
1923 return le32_to_cpup(&tx_resp->u.status + tx_resp->frame_count) & MAX_SN;
1924 }
1925
1926 /**
1927 * iwl4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue
1928 */
1929 static int iwl4965_tx_status_reply_tx(struct iwl_priv *priv,
1930 struct iwl_ht_agg *agg,
1931 struct iwl4965_tx_resp *tx_resp,
1932 int txq_id, u16 start_idx)
1933 {
1934 u16 status;
1935 struct agg_tx_status *frame_status = tx_resp->u.agg_status;
1936 struct ieee80211_tx_info *info = NULL;
1937 struct ieee80211_hdr *hdr = NULL;
1938 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1939 int i, sh, idx;
1940 u16 seq;
1941 if (agg->wait_for_ba)
1942 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1943
1944 agg->frame_count = tx_resp->frame_count;
1945 agg->start_idx = start_idx;
1946 agg->rate_n_flags = rate_n_flags;
1947 agg->bitmap = 0;
1948
1949 /* num frames attempted by Tx command */
1950 if (agg->frame_count == 1) {
1951 /* Only one frame was attempted; no block-ack will arrive */
1952 status = le16_to_cpu(frame_status[0].status);
1953 idx = start_idx;
1954
1955 /* FIXME: code repetition */
1956 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1957 agg->frame_count, agg->start_idx, idx);
1958
1959 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1960 info->status.rates[0].count = tx_resp->failure_frame + 1;
1961 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1962 info->flags |= iwl_is_tx_success(status) ?
1963 IEEE80211_TX_STAT_ACK : 0;
1964 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1965 /* FIXME: code repetition end */
1966
1967 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1968 status & 0xff, tx_resp->failure_frame);
1969 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1970
1971 agg->wait_for_ba = 0;
1972 } else {
1973 /* Two or more frames were attempted; expect block-ack */
1974 u64 bitmap = 0;
1975 int start = agg->start_idx;
1976
1977 /* Construct bit-map of pending frames within Tx window */
1978 for (i = 0; i < agg->frame_count; i++) {
1979 u16 sc;
1980 status = le16_to_cpu(frame_status[i].status);
1981 seq = le16_to_cpu(frame_status[i].sequence);
1982 idx = SEQ_TO_INDEX(seq);
1983 txq_id = SEQ_TO_QUEUE(seq);
1984
1985 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1986 AGG_TX_STATE_ABORT_MSK))
1987 continue;
1988
1989 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1990 agg->frame_count, txq_id, idx);
1991
1992 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1993 if (!hdr) {
1994 IWL_ERR(priv,
1995 "BUG_ON idx doesn't point to valid skb"
1996 " idx=%d, txq_id=%d\n", idx, txq_id);
1997 return -1;
1998 }
1999
2000 sc = le16_to_cpu(hdr->seq_ctrl);
2001 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
2002 IWL_ERR(priv,
2003 "BUG_ON idx doesn't match seq control"
2004 " idx=%d, seq_idx=%d, seq=%d\n",
2005 idx, SEQ_TO_SN(sc), hdr->seq_ctrl);
2006 return -1;
2007 }
2008
2009 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
2010 i, idx, SEQ_TO_SN(sc));
2011
2012 sh = idx - start;
2013 if (sh > 64) {
2014 sh = (start - idx) + 0xff;
2015 bitmap = bitmap << sh;
2016 sh = 0;
2017 start = idx;
2018 } else if (sh < -64)
2019 sh = 0xff - (start - idx);
2020 else if (sh < 0) {
2021 sh = start - idx;
2022 start = idx;
2023 bitmap = bitmap << sh;
2024 sh = 0;
2025 }
2026 bitmap |= 1ULL << sh;
2027 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
2028 start, (unsigned long long)bitmap);
2029 }
2030
2031 agg->bitmap = bitmap;
2032 agg->start_idx = start;
2033 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
2034 agg->frame_count, agg->start_idx,
2035 (unsigned long long)agg->bitmap);
2036
2037 if (bitmap)
2038 agg->wait_for_ba = 1;
2039 }
2040 return 0;
2041 }
2042
2043 /**
2044 * iwl4965_rx_reply_tx - Handle standard (non-aggregation) Tx response
2045 */
2046 static void iwl4965_rx_reply_tx(struct iwl_priv *priv,
2047 struct iwl_rx_mem_buffer *rxb)
2048 {
2049 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
2050 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
2051 int txq_id = SEQ_TO_QUEUE(sequence);
2052 int index = SEQ_TO_INDEX(sequence);
2053 struct iwl_tx_queue *txq = &priv->txq[txq_id];
2054 struct ieee80211_hdr *hdr;
2055 struct ieee80211_tx_info *info;
2056 struct iwl4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
2057 u32 status = le32_to_cpu(tx_resp->u.status);
2058 int tid = MAX_TID_COUNT;
2059 int sta_id;
2060 int freed;
2061 u8 *qc = NULL;
2062
2063 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
2064 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
2065 "is out of range [0-%d] %d %d\n", txq_id,
2066 index, txq->q.n_bd, txq->q.write_ptr,
2067 txq->q.read_ptr);
2068 return;
2069 }
2070
2071 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
2072 memset(&info->status, 0, sizeof(info->status));
2073
2074 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
2075 if (ieee80211_is_data_qos(hdr->frame_control)) {
2076 qc = ieee80211_get_qos_ctl(hdr);
2077 tid = qc[0] & 0xf;
2078 }
2079
2080 sta_id = iwl_get_ra_sta_id(priv, hdr);
2081 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
2082 IWL_ERR(priv, "Station not known\n");
2083 return;
2084 }
2085
2086 if (txq->sched_retry) {
2087 const u32 scd_ssn = iwl4965_get_scd_ssn(tx_resp);
2088 struct iwl_ht_agg *agg = NULL;
2089
2090 WARN_ON(!qc);
2091
2092 agg = &priv->stations[sta_id].tid[tid].agg;
2093
2094 iwl4965_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
2095
2096 /* check if BAR is needed */
2097 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
2098 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
2099
2100 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
2101 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
2102 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim scd_ssn "
2103 "%d index %d\n", scd_ssn , index);
2104 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2105 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2106
2107 if (priv->mac80211_registered &&
2108 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
2109 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
2110 if (agg->state == IWL_AGG_OFF)
2111 iwl_wake_queue(priv, txq_id);
2112 else
2113 iwl_wake_queue(priv, txq->swq_id);
2114 }
2115 }
2116 } else {
2117 info->status.rates[0].count = tx_resp->failure_frame + 1;
2118 info->flags |= iwl_is_tx_success(status) ?
2119 IEEE80211_TX_STAT_ACK : 0;
2120 iwl_hwrate_to_tx_control(priv,
2121 le32_to_cpu(tx_resp->rate_n_flags),
2122 info);
2123
2124 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) "
2125 "rate_n_flags 0x%x retries %d\n",
2126 txq_id,
2127 iwl_get_tx_fail_reason(status), status,
2128 le32_to_cpu(tx_resp->rate_n_flags),
2129 tx_resp->failure_frame);
2130
2131 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
2132 if (qc && likely(sta_id != IWL_INVALID_STATION))
2133 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
2134
2135 if (priv->mac80211_registered &&
2136 (iwl_queue_space(&txq->q) > txq->q.low_mark))
2137 iwl_wake_queue(priv, txq_id);
2138 }
2139
2140 if (qc && likely(sta_id != IWL_INVALID_STATION))
2141 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
2142
2143 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
2144 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n");
2145 }
2146
2147 static int iwl4965_calc_rssi(struct iwl_priv *priv,
2148 struct iwl_rx_phy_res *rx_resp)
2149 {
2150 /* data from PHY/DSP regarding signal strength, etc.,
2151 * contents are always there, not configurable by host. */
2152 struct iwl4965_rx_non_cfg_phy *ncphy =
2153 (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
2154 u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL49_AGC_DB_MASK)
2155 >> IWL49_AGC_DB_POS;
2156
2157 u32 valid_antennae =
2158 (le16_to_cpu(rx_resp->phy_flags) & IWL49_RX_PHY_FLAGS_ANTENNAE_MASK)
2159 >> IWL49_RX_PHY_FLAGS_ANTENNAE_OFFSET;
2160 u8 max_rssi = 0;
2161 u32 i;
2162
2163 /* Find max rssi among 3 possible receivers.
2164 * These values are measured by the digital signal processor (DSP).
2165 * They should stay fairly constant even as the signal strength varies,
2166 * if the radio's automatic gain control (AGC) is working right.
2167 * AGC value (see below) will provide the "interesting" info. */
2168 for (i = 0; i < 3; i++)
2169 if (valid_antennae & (1 << i))
2170 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
2171
2172 IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
2173 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
2174 max_rssi, agc);
2175
2176 /* dBm = max_rssi dB - agc dB - constant.
2177 * Higher AGC (higher radio gain) means lower signal. */
2178 return max_rssi - agc - IWL49_RSSI_OFFSET;
2179 }
2180
2181
2182 /* Set up 4965-specific Rx frame reply handlers */
2183 static void iwl4965_rx_handler_setup(struct iwl_priv *priv)
2184 {
2185 /* Legacy Rx frames */
2186 priv->rx_handlers[REPLY_RX] = iwl_rx_reply_rx;
2187 /* Tx response */
2188 priv->rx_handlers[REPLY_TX] = iwl4965_rx_reply_tx;
2189 }
2190
2191 static void iwl4965_setup_deferred_work(struct iwl_priv *priv)
2192 {
2193 INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
2194 }
2195
2196 static void iwl4965_cancel_deferred_work(struct iwl_priv *priv)
2197 {
2198 cancel_work_sync(&priv->txpower_work);
2199 }
2200
2201 #define IWL4965_UCODE_GET(item) \
2202 static u32 iwl4965_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2203 u32 api_ver) \
2204 { \
2205 return le32_to_cpu(ucode->u.v1.item); \
2206 }
2207
2208 static u32 iwl4965_ucode_get_header_size(u32 api_ver)
2209 {
2210 return UCODE_HEADER_SIZE(1);
2211 }
2212 static u32 iwl4965_ucode_get_build(const struct iwl_ucode_header *ucode,
2213 u32 api_ver)
2214 {
2215 return 0;
2216 }
2217 static u8 *iwl4965_ucode_get_data(const struct iwl_ucode_header *ucode,
2218 u32 api_ver)
2219 {
2220 return (u8 *) ucode->u.v1.data;
2221 }
2222
2223 IWL4965_UCODE_GET(inst_size);
2224 IWL4965_UCODE_GET(data_size);
2225 IWL4965_UCODE_GET(init_size);
2226 IWL4965_UCODE_GET(init_data_size);
2227 IWL4965_UCODE_GET(boot_size);
2228
2229 static struct iwl_hcmd_ops iwl4965_hcmd = {
2230 .rxon_assoc = iwl4965_send_rxon_assoc,
2231 .commit_rxon = iwl_commit_rxon,
2232 .set_rxon_chain = iwl_set_rxon_chain,
2233 };
2234
2235 static struct iwl_ucode_ops iwl4965_ucode = {
2236 .get_header_size = iwl4965_ucode_get_header_size,
2237 .get_build = iwl4965_ucode_get_build,
2238 .get_inst_size = iwl4965_ucode_get_inst_size,
2239 .get_data_size = iwl4965_ucode_get_data_size,
2240 .get_init_size = iwl4965_ucode_get_init_size,
2241 .get_init_data_size = iwl4965_ucode_get_init_data_size,
2242 .get_boot_size = iwl4965_ucode_get_boot_size,
2243 .get_data = iwl4965_ucode_get_data,
2244 };
2245 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
2246 .get_hcmd_size = iwl4965_get_hcmd_size,
2247 .build_addsta_hcmd = iwl4965_build_addsta_hcmd,
2248 .chain_noise_reset = iwl4965_chain_noise_reset,
2249 .gain_computation = iwl4965_gain_computation,
2250 .rts_tx_cmd_flag = iwl4965_rts_tx_cmd_flag,
2251 .calc_rssi = iwl4965_calc_rssi,
2252 };
2253
2254 static struct iwl_lib_ops iwl4965_lib = {
2255 .set_hw_params = iwl4965_hw_set_hw_params,
2256 .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
2257 .txq_set_sched = iwl4965_txq_set_sched,
2258 .txq_agg_enable = iwl4965_txq_agg_enable,
2259 .txq_agg_disable = iwl4965_txq_agg_disable,
2260 .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
2261 .txq_free_tfd = iwl_hw_txq_free_tfd,
2262 .txq_init = iwl_hw_tx_queue_init,
2263 .rx_handler_setup = iwl4965_rx_handler_setup,
2264 .setup_deferred_work = iwl4965_setup_deferred_work,
2265 .cancel_deferred_work = iwl4965_cancel_deferred_work,
2266 .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
2267 .alive_notify = iwl4965_alive_notify,
2268 .init_alive_start = iwl4965_init_alive_start,
2269 .load_ucode = iwl4965_load_bsm,
2270 .dump_nic_event_log = iwl_dump_nic_event_log,
2271 .dump_nic_error_log = iwl_dump_nic_error_log,
2272 .apm_ops = {
2273 .init = iwl4965_apm_init,
2274 .reset = iwl4965_apm_reset,
2275 .stop = iwl_apm_stop,
2276 .config = iwl4965_nic_config,
2277 .set_pwr_src = iwl_set_pwr_src,
2278 },
2279 .eeprom_ops = {
2280 .regulatory_bands = {
2281 EEPROM_REGULATORY_BAND_1_CHANNELS,
2282 EEPROM_REGULATORY_BAND_2_CHANNELS,
2283 EEPROM_REGULATORY_BAND_3_CHANNELS,
2284 EEPROM_REGULATORY_BAND_4_CHANNELS,
2285 EEPROM_REGULATORY_BAND_5_CHANNELS,
2286 EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS,
2287 EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS
2288 },
2289 .verify_signature = iwlcore_eeprom_verify_signature,
2290 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
2291 .release_semaphore = iwlcore_eeprom_release_semaphore,
2292 .calib_version = iwl4965_eeprom_calib_version,
2293 .query_addr = iwlcore_eeprom_query_addr,
2294 },
2295 .send_tx_power = iwl4965_send_tx_power,
2296 .update_chain_flags = iwl_update_chain_flags,
2297 .post_associate = iwl_post_associate,
2298 .config_ap = iwl_config_ap,
2299 .isr = iwl_isr_legacy,
2300 .temp_ops = {
2301 .temperature = iwl4965_temperature_calib,
2302 .set_ct_kill = iwl4965_set_ct_threshold,
2303 },
2304 };
2305
2306 static struct iwl_ops iwl4965_ops = {
2307 .ucode = &iwl4965_ucode,
2308 .lib = &iwl4965_lib,
2309 .hcmd = &iwl4965_hcmd,
2310 .utils = &iwl4965_hcmd_utils,
2311 .led = &iwlagn_led_ops,
2312 };
2313
2314 struct iwl_cfg iwl4965_agn_cfg = {
2315 .name = "4965AGN",
2316 .fw_name_pre = IWL4965_FW_PRE,
2317 .ucode_api_max = IWL4965_UCODE_API_MAX,
2318 .ucode_api_min = IWL4965_UCODE_API_MIN,
2319 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
2320 .eeprom_size = IWL4965_EEPROM_IMG_SIZE,
2321 .eeprom_ver = EEPROM_4965_EEPROM_VERSION,
2322 .eeprom_calib_ver = EEPROM_4965_TX_POWER_VERSION,
2323 .ops = &iwl4965_ops,
2324 .mod_params = &iwl4965_mod_params,
2325 .use_isr_legacy = true,
2326 .ht_greenfield_support = false,
2327 .broken_powersave = true,
2328 .led_compensation = 61,
2329 .chain_noise_num_beacons = IWL4965_CAL_NUM_BEACONS,
2330 };
2331
2332 /* Module firmware */
2333 MODULE_FIRMWARE(IWL4965_MODULE_FIRMWARE(IWL4965_UCODE_API_MAX));
2334
2335 module_param_named(antenna, iwl4965_mod_params.antenna, int, S_IRUGO);
2336 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
2337 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, S_IRUGO);
2338 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
2339 module_param_named(
2340 disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, S_IRUGO);
2341 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
2342
2343 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, S_IRUGO);
2344 MODULE_PARM_DESC(queues_num, "number of hw queues.");
2345 /* 11n */
2346 module_param_named(11n_disable, iwl4965_mod_params.disable_11n, int, S_IRUGO);
2347 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
2348 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K,
2349 int, S_IRUGO);
2350 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
2351
2352 module_param_named(fw_restart4965, iwl4965_mod_params.restart_fw, int, S_IRUGO);
2353 MODULE_PARM_DESC(fw_restart4965, "restart firmware in case of error");
Linux 2.6 libata-dev (mirror)