drivers/video/exynos/exynos_dp_core.c

   1 /*
   2  * Samsung SoC DP (Display Port) interface driver.
   3  *
   4  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
   5  * Author: Jingoo Han <jg1.han@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/io.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/delay.h>
  21
  22 #include <video/exynos_dp.h>
  23
  24 #include "exynos_dp_core.h"
  25
  26 static int exynos_dp_init_dp(struct exynos_dp_device *dp)
  27 {
  28         exynos_dp_reset(dp);
  29
  30         exynos_dp_swreset(dp);
  31
  32         /* SW defined function Normal operation */
  33         exynos_dp_enable_sw_function(dp);
  34
  35         exynos_dp_config_interrupt(dp);
  36         exynos_dp_init_analog_func(dp);
  37
  38         exynos_dp_init_hpd(dp);
  39         exynos_dp_init_aux(dp);
  40
  41         return 0;
  42 }
  43
  44 static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
  45 {
  46         int timeout_loop = 0;
  47
  48         exynos_dp_init_hpd(dp);
  49
  50         usleep_range(200, 210);
  51
  52         while (exynos_dp_get_plug_in_status(dp) != 0) {
  53                 timeout_loop++;
  54                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
  55                         dev_err(dp->dev, "failed to get hpd plug status\n");
  56                         return -ETIMEDOUT;
  57                 }
  58                 usleep_range(10, 11);
  59         }
  60
  61         return 0;
  62 }
  63
  64 static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
  65 {
  66         int i;
  67         unsigned char sum = 0;
  68
  69         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  70                 sum = sum + edid_data[i];
  71
  72         return sum;
  73 }
  74
  75 static int exynos_dp_read_edid(struct exynos_dp_device *dp)
  76 {
  77         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  78         unsigned int extend_block = 0;
  79         unsigned char sum;
  80         unsigned char test_vector;
  81         int retval;
  82
  83         /*
  84          * EDID device address is 0x50.
  85          * However, if necessary, you must have set upper address
  86          * into E-EDID in I2C device, 0x30.
  87          */
  88
  89         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  90         exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
  91                                 EDID_EXTENSION_FLAG,
  92                                 &extend_block);
  93
  94         if (extend_block > 0) {
  95                 dev_dbg(dp->dev, "EDID data includes a single extension!\n");
  96
  97                 /* Read EDID data */
  98                 retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
  99                                                 EDID_HEADER_PATTERN,
 100                                                 EDID_BLOCK_LENGTH,
 101                                                 &edid[EDID_HEADER_PATTERN]);
 102                 if (retval != 0) {
 103                         dev_err(dp->dev, "EDID Read failed!\n");
 104                         return -EIO;
 105                 }
 106                 sum = exynos_dp_calc_edid_check_sum(edid);
 107                 if (sum != 0) {
 108                         dev_err(dp->dev, "EDID bad checksum!\n");
 109                         return -EIO;
 110                 }
 111
 112                 /* Read additional EDID data */
 113                 retval = exynos_dp_read_bytes_from_i2c(dp,
 114                                 I2C_EDID_DEVICE_ADDR,
 115                                 EDID_BLOCK_LENGTH,
 116                                 EDID_BLOCK_LENGTH,
 117                                 &edid[EDID_BLOCK_LENGTH]);
 118                 if (retval != 0) {
 119                         dev_err(dp->dev, "EDID Read failed!\n");
 120                         return -EIO;
 121                 }
 122                 sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 123                 if (sum != 0) {
 124                         dev_err(dp->dev, "EDID bad checksum!\n");
 125                         return -EIO;
 126                 }
 127
 128                 exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_TEST_REQUEST,
 129                                         &test_vector);
 130                 if (test_vector & DPCD_TEST_EDID_READ) {
 131                         exynos_dp_write_byte_to_dpcd(dp,
 132                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 133                                 edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 134                         exynos_dp_write_byte_to_dpcd(dp,
 135                                 DPCD_ADDR_TEST_RESPONSE,
 136                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 137                 }
 138         } else {
 139                 dev_info(dp->dev, "EDID data does not include any extensions.\n");
 140
 141                 /* Read EDID data */
 142                 retval = exynos_dp_read_bytes_from_i2c(dp,
 143                                 I2C_EDID_DEVICE_ADDR,
 144                                 EDID_HEADER_PATTERN,
 145                                 EDID_BLOCK_LENGTH,
 146                                 &edid[EDID_HEADER_PATTERN]);
 147                 if (retval != 0) {
 148                         dev_err(dp->dev, "EDID Read failed!\n");
 149                         return -EIO;
 150                 }
 151                 sum = exynos_dp_calc_edid_check_sum(edid);
 152                 if (sum != 0) {
 153                         dev_err(dp->dev, "EDID bad checksum!\n");
 154                         return -EIO;
 155                 }
 156
 157                 exynos_dp_read_byte_from_dpcd(dp,
 158                         DPCD_ADDR_TEST_REQUEST,
 159                         &test_vector);
 160                 if (test_vector & DPCD_TEST_EDID_READ) {
 161                         exynos_dp_write_byte_to_dpcd(dp,
 162                                 DPCD_ADDR_TEST_EDID_CHECKSUM,
 163                                 edid[EDID_CHECKSUM]);
 164                         exynos_dp_write_byte_to_dpcd(dp,
 165                                 DPCD_ADDR_TEST_RESPONSE,
 166                                 DPCD_TEST_EDID_CHECKSUM_WRITE);
 167                 }
 168         }
 169
 170         dev_err(dp->dev, "EDID Read success!\n");
 171         return 0;
 172 }
 173
 174 static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
 175 {
 176         u8 buf[12];
 177         int i;
 178         int retval;
 179
 180         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 181         exynos_dp_read_bytes_from_dpcd(dp,
 182                 DPCD_ADDR_DPCD_REV,
 183                 12, buf);
 184
 185         /* Read EDID */
 186         for (i = 0; i < 3; i++) {
 187                 retval = exynos_dp_read_edid(dp);
 188                 if (retval == 0)
 189                         break;
 190         }
 191
 192         return retval;
 193 }
 194
 195 static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
 196                                                 bool enable)
 197 {
 198         u8 data;
 199
 200         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET, &data);
 201
 202         if (enable)
 203                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 204                         DPCD_ENHANCED_FRAME_EN |
 205                         DPCD_LANE_COUNT_SET(data));
 206         else
 207                 exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_LANE_COUNT_SET,
 208                         DPCD_LANE_COUNT_SET(data));
 209 }
 210
 211 static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
 212 {
 213         u8 data;
 214         int retval;
 215
 216         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 217         retval = DPCD_ENHANCED_FRAME_CAP(data);
 218
 219         return retval;
 220 }
 221
 222 static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
 223 {
 224         u8 data;
 225
 226         data = exynos_dp_is_enhanced_mode_available(dp);
 227         exynos_dp_enable_rx_to_enhanced_mode(dp, data);
 228         exynos_dp_enable_enhanced_mode(dp, data);
 229 }
 230
 231 static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
 232 {
 233         exynos_dp_set_training_pattern(dp, DP_NONE);
 234
 235         exynos_dp_write_byte_to_dpcd(dp,
 236                 DPCD_ADDR_TRAINING_PATTERN_SET,
 237                 DPCD_TRAINING_PATTERN_DISABLED);
 238 }
 239
 240 static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
 241                                         int pre_emphasis, int lane)
 242 {
 243         switch (lane) {
 244         case 0:
 245                 exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
 246                 break;
 247         case 1:
 248                 exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
 249                 break;
 250
 251         case 2:
 252                 exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
 253                 break;
 254
 255         case 3:
 256                 exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
 257                 break;
 258         }
 259 }
 260
 261 static void exynos_dp_link_start(struct exynos_dp_device *dp)
 262 {
 263         u8 buf[4];
 264         int lane;
 265         int lane_count;
 266
 267         lane_count = dp->link_train.lane_count;
 268
 269         dp->link_train.lt_state = CLOCK_RECOVERY;
 270         dp->link_train.eq_loop = 0;
 271
 272         for (lane = 0; lane < lane_count; lane++)
 273                 dp->link_train.cr_loop[lane] = 0;
 274
 275         /* Set sink to D0 (Sink Not Ready) mode. */
 276         exynos_dp_write_byte_to_dpcd(dp, DPCD_ADDR_SINK_POWER_STATE,
 277                                 DPCD_SET_POWER_STATE_D0);
 278
 279         /* Set link rate and count as you want to establish*/
 280         exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
 281         exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
 282
 283         /* Setup RX configuration */
 284         buf[0] = dp->link_train.link_rate;
 285         buf[1] = dp->link_train.lane_count;
 286         exynos_dp_write_bytes_to_dpcd(dp, DPCD_ADDR_LINK_BW_SET,
 287                                 2, buf);
 288
 289         /* Set TX pre-emphasis to minimum */
 290         for (lane = 0; lane < lane_count; lane++)
 291                 exynos_dp_set_lane_lane_pre_emphasis(dp,
 292                         PRE_EMPHASIS_LEVEL_0, lane);
 293
 294         /* Set training pattern 1 */
 295         exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
 296
 297         /* Set RX training pattern */
 298         exynos_dp_write_byte_to_dpcd(dp,
 299                 DPCD_ADDR_TRAINING_PATTERN_SET,
 300                 DPCD_SCRAMBLING_DISABLED |
 301                 DPCD_TRAINING_PATTERN_1);
 302
 303         for (lane = 0; lane < lane_count; lane++)
 304                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 305                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 306         exynos_dp_write_bytes_to_dpcd(dp,
 307                 DPCD_ADDR_TRAINING_LANE0_SET,
 308                 lane_count, buf);
 309 }
 310
 311 static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
 312 {
 313         int shift = (lane & 1) * 4;
 314         u8 link_value = link_status[lane>>1];
 315
 316         return (link_value >> shift) & 0xf;
 317 }
 318
 319 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 320 {
 321         int lane;
 322         u8 lane_status;
 323
 324         for (lane = 0; lane < lane_count; lane++) {
 325                 lane_status = exynos_dp_get_lane_status(link_status, lane);
 326                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 327                         return -EINVAL;
 328         }
 329         return 0;
 330 }
 331
 332 static int exynos_dp_channel_eq_ok(u8 link_align[3], int lane_count)
 333 {
 334         int lane;
 335         u8 lane_align;
 336         u8 lane_status;
 337
 338         lane_align = link_align[2];
 339         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 340                 return -EINVAL;
 341
 342         for (lane = 0; lane < lane_count; lane++) {
 343                 lane_status = exynos_dp_get_lane_status(link_align, lane);
 344                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 345                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 346                         return -EINVAL;
 347         }
 348
 349         return 0;
 350 }
 351
 352 static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
 353                                                         int lane)
 354 {
 355         int shift = (lane & 1) * 4;
 356         u8 link_value = adjust_request[lane>>1];
 357
 358         return (link_value >> shift) & 0x3;
 359 }
 360
 361 static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
 362                                         u8 adjust_request[2],
 363                                         int lane)
 364 {
 365         int shift = (lane & 1) * 4;
 366         u8 link_value = adjust_request[lane>>1];
 367
 368         return ((link_value >> shift) & 0xc) >> 2;
 369 }
 370
 371 static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
 372                                         u8 training_lane_set, int lane)
 373 {
 374         switch (lane) {
 375         case 0:
 376                 exynos_dp_set_lane0_link_training(dp, training_lane_set);
 377                 break;
 378         case 1:
 379                 exynos_dp_set_lane1_link_training(dp, training_lane_set);
 380                 break;
 381
 382         case 2:
 383                 exynos_dp_set_lane2_link_training(dp, training_lane_set);
 384                 break;
 385
 386         case 3:
 387                 exynos_dp_set_lane3_link_training(dp, training_lane_set);
 388                 break;
 389         }
 390 }
 391
 392 static unsigned int exynos_dp_get_lane_link_training(
 393                                 struct exynos_dp_device *dp,
 394                                 int lane)
 395 {
 396         u32 reg;
 397
 398         switch (lane) {
 399         case 0:
 400                 reg = exynos_dp_get_lane0_link_training(dp);
 401                 break;
 402         case 1:
 403                 reg = exynos_dp_get_lane1_link_training(dp);
 404                 break;
 405         case 2:
 406                 reg = exynos_dp_get_lane2_link_training(dp);
 407                 break;
 408         case 3:
 409                 reg = exynos_dp_get_lane3_link_training(dp);
 410                 break;
 411         default:
 412                 WARN_ON(1);
 413                 return 0;
 414         }
 415
 416         return reg;
 417 }
 418
 419 static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
 420 {
 421         exynos_dp_training_pattern_dis(dp);
 422         exynos_dp_set_enhanced_mode(dp);
 423
 424         dp->link_train.lt_state = FAILED;
 425 }
 426
 427 static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
 428 {
 429         u8 link_status[2];
 430         int lane;
 431         int lane_count;
 432
 433         u8 adjust_request[2];
 434         u8 voltage_swing;
 435         u8 pre_emphasis;
 436         u8 training_lane;
 437
 438         usleep_range(100, 101);
 439
 440         lane_count = dp->link_train.lane_count;
 441
 442         exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 443                                 2, link_status);
 444
 445         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 446                 /* set training pattern 2 for EQ */
 447                 exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
 448
 449                 for (lane = 0; lane < lane_count; lane++) {
 450                         exynos_dp_read_bytes_from_dpcd(dp,
 451                                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
 452                                         2, adjust_request);
 453                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 454                                                         adjust_request, lane);
 455                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 456                                                         adjust_request, lane);
 457                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 458                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 459
 460                         if (voltage_swing == VOLTAGE_LEVEL_3)
 461                                 training_lane |= DPCD_MAX_SWING_REACHED;
 462                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 463                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 464
 465                         dp->link_train.training_lane[lane] = training_lane;
 466
 467                         exynos_dp_set_lane_link_training(dp,
 468                                 dp->link_train.training_lane[lane],
 469                                 lane);
 470                 }
 471
 472                 exynos_dp_write_byte_to_dpcd(dp,
 473                         DPCD_ADDR_TRAINING_PATTERN_SET,
 474                         DPCD_SCRAMBLING_DISABLED |
 475                         DPCD_TRAINING_PATTERN_2);
 476
 477                 exynos_dp_write_bytes_to_dpcd(dp,
 478                         DPCD_ADDR_TRAINING_LANE0_SET,
 479                         lane_count,
 480                         dp->link_train.training_lane);
 481
 482                 dev_info(dp->dev, "Link Training Clock Recovery success\n");
 483                 dp->link_train.lt_state = EQUALIZER_TRAINING;
 484         } else {
 485                 for (lane = 0; lane < lane_count; lane++) {
 486                         training_lane = exynos_dp_get_lane_link_training(
 487                                                         dp, lane);
 488                         exynos_dp_read_bytes_from_dpcd(dp,
 489                                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
 490                                         2, adjust_request);
 491                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 492                                                         adjust_request, lane);
 493                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 494                                                         adjust_request, lane);
 495
 496                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 497                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 498                                 dev_err(dp->dev, "voltage or pre emphasis reached max level\n");
 499                                 goto reduce_link_rate;
 500                         }
 501
 502                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 503                                         voltage_swing) &&
 504                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 505                                         pre_emphasis)) {
 506                                 dp->link_train.cr_loop[lane]++;
 507                                 if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 508                                         dev_err(dp->dev, "CR Max loop\n");
 509                                         goto reduce_link_rate;
 510                                 }
 511                         }
 512
 513                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 514                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 515
 516                         if (voltage_swing == VOLTAGE_LEVEL_3)
 517                                 training_lane |= DPCD_MAX_SWING_REACHED;
 518                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 519                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 520
 521                         dp->link_train.training_lane[lane] = training_lane;
 522
 523                         exynos_dp_set_lane_link_training(dp,
 524                                 dp->link_train.training_lane[lane], lane);
 525                 }
 526
 527                 exynos_dp_write_bytes_to_dpcd(dp,
 528                         DPCD_ADDR_TRAINING_LANE0_SET,
 529                         lane_count,
 530                         dp->link_train.training_lane);
 531         }
 532
 533         return 0;
 534
 535 reduce_link_rate:
 536         exynos_dp_reduce_link_rate(dp);
 537         return -EIO;
 538 }
 539
 540 static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
 541 {
 542         u8 link_status[2];
 543         u8 link_align[3];
 544         int lane;
 545         int lane_count;
 546         u32 reg;
 547
 548         u8 adjust_request[2];
 549         u8 voltage_swing;
 550         u8 pre_emphasis;
 551         u8 training_lane;
 552
 553         usleep_range(400, 401);
 554
 555         lane_count = dp->link_train.lane_count;
 556
 557         exynos_dp_read_bytes_from_dpcd(dp, DPCD_ADDR_LANE0_1_STATUS,
 558                                 2, link_status);
 559
 560         if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
 561                 link_align[0] = link_status[0];
 562                 link_align[1] = link_status[1];
 563
 564                 exynos_dp_read_byte_from_dpcd(dp,
 565                         DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED,
 566                         &link_align[2]);
 567
 568                 for (lane = 0; lane < lane_count; lane++) {
 569                         exynos_dp_read_bytes_from_dpcd(dp,
 570                                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
 571                                         2, adjust_request);
 572                         voltage_swing = exynos_dp_get_adjust_request_voltage(
 573                                                         adjust_request, lane);
 574                         pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
 575                                                         adjust_request, lane);
 576                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 577                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 578
 579                         if (voltage_swing == VOLTAGE_LEVEL_3)
 580                                 training_lane |= DPCD_MAX_SWING_REACHED;
 581                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 582                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 583
 584                         dp->link_train.training_lane[lane] = training_lane;
 585                 }
 586
 587                 if (exynos_dp_channel_eq_ok(link_status, lane_count) == 0) {
 588                         /* traing pattern Set to Normal */
 589                         exynos_dp_training_pattern_dis(dp);
 590
 591                         dev_info(dp->dev, "Link Training success!\n");
 592
 593                         exynos_dp_get_link_bandwidth(dp, &reg);
 594                         dp->link_train.link_rate = reg;
 595                         dev_dbg(dp->dev, "final bandwidth = %.2x\n",
 596                                 dp->link_train.link_rate);
 597
 598                         exynos_dp_get_lane_count(dp, &reg);
 599                         dp->link_train.lane_count = reg;
 600                         dev_dbg(dp->dev, "final lane count = %.2x\n",
 601                                 dp->link_train.lane_count);
 602
 603                         /* set enhanced mode if available */
 604                         exynos_dp_set_enhanced_mode(dp);
 605                         dp->link_train.lt_state = FINISHED;
 606                 } else {
 607                         /* not all locked */
 608                         dp->link_train.eq_loop++;
 609
 610                         if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
 611                                 dev_err(dp->dev, "EQ Max loop\n");
 612                                 goto reduce_link_rate;
 613                         }
 614
 615                         for (lane = 0; lane < lane_count; lane++)
 616                                 exynos_dp_set_lane_link_training(dp,
 617                                         dp->link_train.training_lane[lane],
 618                                         lane);
 619
 620                         exynos_dp_write_bytes_to_dpcd(dp,
 621                                 DPCD_ADDR_TRAINING_LANE0_SET,
 622                                 lane_count,
 623                                 dp->link_train.training_lane);
 624                 }
 625         } else {
 626                 goto reduce_link_rate;
 627         }
 628
 629         return 0;
 630
 631 reduce_link_rate:
 632         exynos_dp_reduce_link_rate(dp);
 633         return -EIO;
 634 }
 635
 636 static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
 637                                         u8 *bandwidth)
 638 {
 639         u8 data;
 640
 641         /*
 642          * For DP rev.1.1, Maximum link rate of Main Link lanes
 643          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 644          */
 645         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LINK_RATE, &data);
 646         *bandwidth = data;
 647 }
 648
 649 static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
 650                                         u8 *lane_count)
 651 {
 652         u8 data;
 653
 654         /*
 655          * For DP rev.1.1, Maximum number of Main Link lanes
 656          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 657          */
 658         exynos_dp_read_byte_from_dpcd(dp, DPCD_ADDR_MAX_LANE_COUNT, &data);
 659         *lane_count = DPCD_MAX_LANE_COUNT(data);
 660 }
 661
 662 static void exynos_dp_init_training(struct exynos_dp_device *dp,
 663                         enum link_lane_count_type max_lane,
 664                         enum link_rate_type max_rate)
 665 {
 666         /*
 667          * MACRO_RST must be applied after the PLL_LOCK to avoid
 668          * the DP inter pair skew issue for at least 10 us
 669          */
 670         exynos_dp_reset_macro(dp);
 671
 672         /* Initialize by reading RX's DPCD */
 673         exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 674         exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 675
 676         if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 677            (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 678                 dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 679                         dp->link_train.link_rate);
 680                 dp->link_train.link_rate = LINK_RATE_1_62GBPS;
 681         }
 682
 683         if (dp->link_train.lane_count == 0) {
 684                 dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
 685                         dp->link_train.lane_count);
 686                 dp->link_train.lane_count = (u8)LANE_COUNT1;
 687         }
 688
 689         /* Setup TX lane count & rate */
 690         if (dp->link_train.lane_count > max_lane)
 691                 dp->link_train.lane_count = max_lane;
 692         if (dp->link_train.link_rate > max_rate)
 693                 dp->link_train.link_rate = max_rate;
 694
 695         /* All DP analog module power up */
 696         exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
 697 }
 698
 699 static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
 700 {
 701         int retval = 0;
 702         int training_finished = 0;
 703
 704         dp->link_train.lt_state = START;
 705
 706         /* Process here */
 707         while (!training_finished) {
 708                 switch (dp->link_train.lt_state) {
 709                 case START:
 710                         exynos_dp_link_start(dp);
 711                         break;
 712                 case CLOCK_RECOVERY:
 713                         retval = exynos_dp_process_clock_recovery(dp);
 714                         if (retval)
 715                                 dev_err(dp->dev, "LT CR failed!\n");
 716                         break;
 717                 case EQUALIZER_TRAINING:
 718                         retval = exynos_dp_process_equalizer_training(dp);
 719                         if (retval)
 720                                 dev_err(dp->dev, "LT EQ failed!\n");
 721                         break;
 722                 case FINISHED:
 723                         training_finished = 1;
 724                         break;
 725                 case FAILED:
 726                         return -EREMOTEIO;
 727                 }
 728         }
 729
 730         return retval;
 731 }
 732
 733 static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
 734                                 u32 count,
 735                                 u32 bwtype)
 736 {
 737         int i;
 738         int retval;
 739
 740         for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
 741                 exynos_dp_init_training(dp, count, bwtype);
 742                 retval = exynos_dp_sw_link_training(dp);
 743                 if (retval == 0)
 744                         break;
 745
 746                 usleep_range(100, 110);
 747         }
 748
 749         return retval;
 750 }
 751
 752 static int exynos_dp_config_video(struct exynos_dp_device *dp,
 753                         struct video_info *video_info)
 754 {
 755         int retval = 0;
 756         int timeout_loop = 0;
 757         int done_count = 0;
 758
 759         exynos_dp_config_video_slave_mode(dp, video_info);
 760
 761         exynos_dp_set_video_color_format(dp, video_info->color_depth,
 762                         video_info->color_space,
 763                         video_info->dynamic_range,
 764                         video_info->ycbcr_coeff);
 765
 766         if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 767                 dev_err(dp->dev, "PLL is not locked yet.\n");
 768                 return -EINVAL;
 769         }
 770
 771         for (;;) {
 772                 timeout_loop++;
 773                 if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
 774                         break;
 775                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 776                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 777                         return -ETIMEDOUT;
 778                 }
 779
 780                 usleep_range(1, 2);
 781         }
 782
 783         /* Set to use the register calculated M/N video */
 784         exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
 785
 786         /* For video bist, Video timing must be generated by register */
 787         exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
 788
 789         /* Disable video mute */
 790         exynos_dp_enable_video_mute(dp, 0);
 791
 792         /* Configure video slave mode */
 793         exynos_dp_enable_video_master(dp, 0);
 794
 795         /* Enable video */
 796         exynos_dp_start_video(dp);
 797
 798         timeout_loop = 0;
 799
 800         for (;;) {
 801                 timeout_loop++;
 802                 if (exynos_dp_is_video_stream_on(dp) == 0) {
 803                         done_count++;
 804                         if (done_count > 10)
 805                                 break;
 806                 } else if (done_count) {
 807                         done_count = 0;
 808                 }
 809                 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 810                         dev_err(dp->dev, "Timeout of video streamclk ok\n");
 811                         return -ETIMEDOUT;
 812                 }
 813
 814                 usleep_range(1000, 1001);
 815         }
 816
 817         if (retval != 0)
 818                 dev_err(dp->dev, "Video stream is not detected!\n");
 819
 820         return retval;
 821 }
 822
 823 static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
 824 {
 825         u8 data;
 826
 827         if (enable) {
 828                 exynos_dp_enable_scrambling(dp);
 829
 830                 exynos_dp_read_byte_from_dpcd(dp,
 831                         DPCD_ADDR_TRAINING_PATTERN_SET,
 832                         &data);
 833                 exynos_dp_write_byte_to_dpcd(dp,
 834                         DPCD_ADDR_TRAINING_PATTERN_SET,
 835                         (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
 836         } else {
 837                 exynos_dp_disable_scrambling(dp);
 838
 839                 exynos_dp_read_byte_from_dpcd(dp,
 840                         DPCD_ADDR_TRAINING_PATTERN_SET,
 841                         &data);
 842                 exynos_dp_write_byte_to_dpcd(dp,
 843                         DPCD_ADDR_TRAINING_PATTERN_SET,
 844                         (u8)(data | DPCD_SCRAMBLING_DISABLED));
 845         }
 846 }
 847
 848 static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
 849 {
 850         struct exynos_dp_device *dp = arg;
 851
 852         dev_err(dp->dev, "exynos_dp_irq_handler\n");
 853         return IRQ_HANDLED;
 854 }
 855
 856 static int __devinit exynos_dp_probe(struct platform_device *pdev)
 857 {
 858         struct resource *res;
 859         struct exynos_dp_device *dp;
 860         struct exynos_dp_platdata *pdata;
 861
 862         int ret = 0;
 863
 864         pdata = pdev->dev.platform_data;
 865         if (!pdata) {
 866                 dev_err(&pdev->dev, "no platform data\n");
 867                 return -EINVAL;
 868         }
 869
 870         dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
 871                                 GFP_KERNEL);
 872         if (!dp) {
 873                 dev_err(&pdev->dev, "no memory for device data\n");
 874                 return -ENOMEM;
 875         }
 876
 877         dp->dev = &pdev->dev;
 878
 879         dp->clock = clk_get(&pdev->dev, "dp");
 880         if (IS_ERR(dp->clock)) {
 881                 dev_err(&pdev->dev, "failed to get clock\n");
 882                 return PTR_ERR(dp->clock);
 883         }
 884
 885         clk_enable(dp->clock);
 886
 887         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 888         if (!res) {
 889                 dev_err(&pdev->dev, "failed to get registers\n");
 890                 ret = -EINVAL;
 891                 goto err_clock;
 892         }
 893
 894         dp->reg_base = devm_request_and_ioremap(&pdev->dev, res);
 895         if (!dp->reg_base) {
 896                 dev_err(&pdev->dev, "failed to ioremap\n");
 897                 ret = -ENOMEM;
 898                 goto err_clock;
 899         }
 900
 901         dp->irq = platform_get_irq(pdev, 0);
 902         if (!dp->irq) {
 903                 dev_err(&pdev->dev, "failed to get irq\n");
 904                 ret = -ENODEV;
 905                 goto err_clock;
 906         }
 907
 908         ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler, 0,
 909                                 "exynos-dp", dp);
 910         if (ret) {
 911                 dev_err(&pdev->dev, "failed to request irq\n");
 912                 goto err_clock;
 913         }
 914
 915         dp->video_info = pdata->video_info;
 916         if (pdata->phy_init)
 917                 pdata->phy_init();
 918
 919         exynos_dp_init_dp(dp);
 920
 921         ret = exynos_dp_detect_hpd(dp);
 922         if (ret) {
 923                 dev_err(&pdev->dev, "unable to detect hpd\n");
 924                 goto err_clock;
 925         }
 926
 927         exynos_dp_handle_edid(dp);
 928
 929         ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
 930                                 dp->video_info->link_rate);
 931         if (ret) {
 932                 dev_err(&pdev->dev, "unable to do link train\n");
 933                 goto err_clock;
 934         }
 935
 936         exynos_dp_enable_scramble(dp, 1);
 937         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
 938         exynos_dp_enable_enhanced_mode(dp, 1);
 939
 940         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
 941         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
 942
 943         exynos_dp_init_video(dp);
 944         ret = exynos_dp_config_video(dp, dp->video_info);
 945         if (ret) {
 946                 dev_err(&pdev->dev, "unable to config video\n");
 947                 goto err_clock;
 948         }
 949
 950         platform_set_drvdata(pdev, dp);
 951
 952         return 0;
 953
 954 err_clock:
 955         clk_put(dp->clock);
 956
 957         return ret;
 958 }
 959
 960 static int __devexit exynos_dp_remove(struct platform_device *pdev)
 961 {
 962         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
 963         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
 964
 965         if (pdata && pdata->phy_exit)
 966                 pdata->phy_exit();
 967
 968         clk_disable(dp->clock);
 969         clk_put(dp->clock);
 970
 971         return 0;
 972 }
 973
 974 #ifdef CONFIG_PM_SLEEP
 975 static int exynos_dp_suspend(struct device *dev)
 976 {
 977         struct platform_device *pdev = to_platform_device(dev);
 978         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
 979         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
 980
 981         if (pdata && pdata->phy_exit)
 982                 pdata->phy_exit();
 983
 984         clk_disable(dp->clock);
 985
 986         return 0;
 987 }
 988
 989 static int exynos_dp_resume(struct device *dev)
 990 {
 991         struct platform_device *pdev = to_platform_device(dev);
 992         struct exynos_dp_platdata *pdata = pdev->dev.platform_data;
 993         struct exynos_dp_device *dp = platform_get_drvdata(pdev);
 994
 995         if (pdata && pdata->phy_init)
 996                 pdata->phy_init();
 997
 998         clk_enable(dp->clock);
 999
1000         exynos_dp_init_dp(dp);
1001
1002         exynos_dp_detect_hpd(dp);
1003         exynos_dp_handle_edid(dp);
1004
1005         exynos_dp_set_link_train(dp, dp->video_info->lane_count,
1006                                 dp->video_info->link_rate);
1007
1008         exynos_dp_enable_scramble(dp, 1);
1009         exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
1010         exynos_dp_enable_enhanced_mode(dp, 1);
1011
1012         exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
1013         exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
1014
1015         exynos_dp_init_video(dp);
1016         exynos_dp_config_video(dp, dp->video_info);
1017
1018         return 0;
1019 }
1020 #endif
1021
1022 static const struct dev_pm_ops exynos_dp_pm_ops = {
1023         SET_SYSTEM_SLEEP_PM_OPS(exynos_dp_suspend, exynos_dp_resume)
1024 };
1025
1026 static struct platform_driver exynos_dp_driver = {
1027         .probe          = exynos_dp_probe,
1028         .remove         = __devexit_p(exynos_dp_remove),
1029         .driver         = {
1030                 .name   = "exynos-dp",
1031                 .owner  = THIS_MODULE,
1032                 .pm     = &exynos_dp_pm_ops,
1033         },
1034 };
1035
1036 module_platform_driver(exynos_dp_driver);
1037
1038 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
1039 MODULE_DESCRIPTION("Samsung SoC DP Driver");
1040 MODULE_LICENSE("GPL");