sound/soc/codecs/tlv320aic32x4.c

   1 /*
   2  * linux/sound/soc/codecs/tlv320aic32x4.c
   3  *
   4  * Copyright 2011 Vista Silicon S.L.
   5  *
   6  * Author: Javier Martin <javier.martin@vista-silicon.com>
   7  *
   8  * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  23  * MA 02110-1301, USA.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/init.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31 #include <linux/i2c.h>
  32 #include <linux/cdev.h>
  33 #include <linux/slab.h>
  34
  35 #include <sound/tlv320aic32x4.h>
  36 #include <sound/core.h>
  37 #include <sound/pcm.h>
  38 #include <sound/pcm_params.h>
  39 #include <sound/soc.h>
  40 #include <sound/soc-dapm.h>
  41 #include <sound/initval.h>
  42 #include <sound/tlv.h>
  43
  44 #include "tlv320aic32x4.h"
  45
  46 struct aic32x4_rate_divs {
  47         u32 mclk;
  48         u32 rate;
  49         u8 p_val;
  50         u8 pll_j;
  51         u16 pll_d;
  52         u16 dosr;
  53         u8 ndac;
  54         u8 mdac;
  55         u8 aosr;
  56         u8 nadc;
  57         u8 madc;
  58         u8 blck_N;
  59 };
  60
  61 struct aic32x4_priv {
  62         u32 sysclk;
  63         u8 page_no;
  64         void *control_data;
  65         u32 power_cfg;
  66         u32 micpga_routing;
  67         bool swapdacs;
  68 };
  69
  70 /* 0dB min, 1dB steps */
  71 static DECLARE_TLV_DB_SCALE(tlv_step_1, 0, 100, 0);
  72 /* 0dB min, 0.5dB steps */
  73 static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
  74
  75 static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
  76         SOC_DOUBLE_R_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
  77                         AIC32X4_RDACVOL, 0, 0x30, 0, tlv_step_0_5),
  78         SOC_DOUBLE_R_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
  79                         AIC32X4_HPRGAIN, 0, 0x1D, 0, tlv_step_1),
  80         SOC_DOUBLE_R_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
  81                         AIC32X4_LORGAIN, 0, 0x1D, 0, tlv_step_1),
  82         SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
  83                         AIC32X4_HPRGAIN, 6, 0x01, 1),
  84         SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
  85                         AIC32X4_LORGAIN, 6, 0x01, 1),
  86         SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
  87                         AIC32X4_RMICPGAVOL, 7, 0x01, 1),
  88
  89         SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
  90         SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
  91
  92         SOC_DOUBLE_R_TLV("ADC Level Volume", AIC32X4_LADCVOL,
  93                         AIC32X4_RADCVOL, 0, 0x28, 0, tlv_step_0_5),
  94         SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
  95                         AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
  96
  97         SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
  98
  99         SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
 100         SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
 101         SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
 102                         4, 0x07, 0),
 103         SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
 104                         0, 0x03, 0),
 105         SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
 106                         6, 0x03, 0),
 107         SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
 108                         1, 0x1F, 0),
 109         SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
 110                         0, 0x7F, 0),
 111         SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
 112                         3, 0x1F, 0),
 113         SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
 114                         3, 0x1F, 0),
 115         SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
 116                         0, 0x1F, 0),
 117         SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
 118                         0, 0x0F, 0),
 119 };
 120
 121 static const struct aic32x4_rate_divs aic32x4_divs[] = {
 122         /* 8k rate */
 123         {AIC32X4_FREQ_12000000, 8000, 1, 7, 6800, 768, 5, 3, 128, 5, 18, 24},
 124         {AIC32X4_FREQ_24000000, 8000, 2, 7, 6800, 768, 15, 1, 64, 45, 4, 24},
 125         {AIC32X4_FREQ_25000000, 8000, 2, 7, 3728, 768, 15, 1, 64, 45, 4, 24},
 126         /* 11.025k rate */
 127         {AIC32X4_FREQ_12000000, 11025, 1, 7, 5264, 512, 8, 2, 128, 8, 8, 16},
 128         {AIC32X4_FREQ_24000000, 11025, 2, 7, 5264, 512, 16, 1, 64, 32, 4, 16},
 129         /* 16k rate */
 130         {AIC32X4_FREQ_12000000, 16000, 1, 7, 6800, 384, 5, 3, 128, 5, 9, 12},
 131         {AIC32X4_FREQ_24000000, 16000, 2, 7, 6800, 384, 15, 1, 64, 18, 5, 12},
 132         {AIC32X4_FREQ_25000000, 16000, 2, 7, 3728, 384, 15, 1, 64, 18, 5, 12},
 133         /* 22.05k rate */
 134         {AIC32X4_FREQ_12000000, 22050, 1, 7, 5264, 256, 4, 4, 128, 4, 8, 8},
 135         {AIC32X4_FREQ_24000000, 22050, 2, 7, 5264, 256, 16, 1, 64, 16, 4, 8},
 136         {AIC32X4_FREQ_25000000, 22050, 2, 7, 2253, 256, 16, 1, 64, 16, 4, 8},
 137         /* 32k rate */
 138         {AIC32X4_FREQ_12000000, 32000, 1, 7, 1680, 192, 2, 7, 64, 2, 21, 6},
 139         {AIC32X4_FREQ_24000000, 32000, 2, 7, 1680, 192, 7, 2, 64, 7, 6, 6},
 140         /* 44.1k rate */
 141         {AIC32X4_FREQ_12000000, 44100, 1, 7, 5264, 128, 2, 8, 128, 2, 8, 4},
 142         {AIC32X4_FREQ_24000000, 44100, 2, 7, 5264, 128, 8, 2, 64, 8, 4, 4},
 143         {AIC32X4_FREQ_25000000, 44100, 2, 7, 2253, 128, 8, 2, 64, 8, 4, 4},
 144         /* 48k rate */
 145         {AIC32X4_FREQ_12000000, 48000, 1, 8, 1920, 128, 2, 8, 128, 2, 8, 4},
 146         {AIC32X4_FREQ_24000000, 48000, 2, 8, 1920, 128, 8, 2, 64, 8, 4, 4},
 147         {AIC32X4_FREQ_25000000, 48000, 2, 7, 8643, 128, 8, 2, 64, 8, 4, 4}
 148 };
 149
 150 static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 151         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
 152         SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
 153 };
 154
 155 static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
 156         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
 157         SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
 158 };
 159
 160 static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
 161         SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
 162 };
 163
 164 static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
 165         SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
 166 };
 167
 168 static const struct snd_kcontrol_new left_input_mixer_controls[] = {
 169         SOC_DAPM_SINGLE("IN1_L P Switch", AIC32X4_LMICPGAPIN, 6, 1, 0),
 170         SOC_DAPM_SINGLE("IN2_L P Switch", AIC32X4_LMICPGAPIN, 4, 1, 0),
 171         SOC_DAPM_SINGLE("IN3_L P Switch", AIC32X4_LMICPGAPIN, 2, 1, 0),
 172 };
 173
 174 static const struct snd_kcontrol_new right_input_mixer_controls[] = {
 175         SOC_DAPM_SINGLE("IN1_R P Switch", AIC32X4_RMICPGAPIN, 6, 1, 0),
 176         SOC_DAPM_SINGLE("IN2_R P Switch", AIC32X4_RMICPGAPIN, 4, 1, 0),
 177         SOC_DAPM_SINGLE("IN3_R P Switch", AIC32X4_RMICPGAPIN, 2, 1, 0),
 178 };
 179
 180 static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
 181         SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
 182         SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
 183                            &hpl_output_mixer_controls[0],
 184                            ARRAY_SIZE(hpl_output_mixer_controls)),
 185         SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
 186
 187         SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
 188                            &lol_output_mixer_controls[0],
 189                            ARRAY_SIZE(lol_output_mixer_controls)),
 190         SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
 191
 192         SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
 193         SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
 194                            &hpr_output_mixer_controls[0],
 195                            ARRAY_SIZE(hpr_output_mixer_controls)),
 196         SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
 197         SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
 198                            &lor_output_mixer_controls[0],
 199                            ARRAY_SIZE(lor_output_mixer_controls)),
 200         SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
 201         SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
 202                            &left_input_mixer_controls[0],
 203                            ARRAY_SIZE(left_input_mixer_controls)),
 204         SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
 205                            &right_input_mixer_controls[0],
 206                            ARRAY_SIZE(right_input_mixer_controls)),
 207         SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
 208         SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
 209         SND_SOC_DAPM_MICBIAS("Mic Bias", AIC32X4_MICBIAS, 6, 0),
 210
 211         SND_SOC_DAPM_OUTPUT("HPL"),
 212         SND_SOC_DAPM_OUTPUT("HPR"),
 213         SND_SOC_DAPM_OUTPUT("LOL"),
 214         SND_SOC_DAPM_OUTPUT("LOR"),
 215         SND_SOC_DAPM_INPUT("IN1_L"),
 216         SND_SOC_DAPM_INPUT("IN1_R"),
 217         SND_SOC_DAPM_INPUT("IN2_L"),
 218         SND_SOC_DAPM_INPUT("IN2_R"),
 219         SND_SOC_DAPM_INPUT("IN3_L"),
 220         SND_SOC_DAPM_INPUT("IN3_R"),
 221 };
 222
 223 static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
 224         /* Left Output */
 225         {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
 226         {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
 227
 228         {"HPL Power", NULL, "HPL Output Mixer"},
 229         {"HPL", NULL, "HPL Power"},
 230
 231         {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
 232
 233         {"LOL Power", NULL, "LOL Output Mixer"},
 234         {"LOL", NULL, "LOL Power"},
 235
 236         /* Right Output */
 237         {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
 238         {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
 239
 240         {"HPR Power", NULL, "HPR Output Mixer"},
 241         {"HPR", NULL, "HPR Power"},
 242
 243         {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
 244
 245         {"LOR Power", NULL, "LOR Output Mixer"},
 246         {"LOR", NULL, "LOR Power"},
 247
 248         /* Left input */
 249         {"Left Input Mixer", "IN1_L P Switch", "IN1_L"},
 250         {"Left Input Mixer", "IN2_L P Switch", "IN2_L"},
 251         {"Left Input Mixer", "IN3_L P Switch", "IN3_L"},
 252
 253         {"Left ADC", NULL, "Left Input Mixer"},
 254
 255         /* Right Input */
 256         {"Right Input Mixer", "IN1_R P Switch", "IN1_R"},
 257         {"Right Input Mixer", "IN2_R P Switch", "IN2_R"},
 258         {"Right Input Mixer", "IN3_R P Switch", "IN3_R"},
 259
 260         {"Right ADC", NULL, "Right Input Mixer"},
 261 };
 262
 263 static inline int aic32x4_change_page(struct snd_soc_codec *codec,
 264                                         unsigned int new_page)
 265 {
 266         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 267         u8 data[2];
 268         int ret;
 269
 270         data[0] = 0x00;
 271         data[1] = new_page & 0xff;
 272
 273         ret = codec->hw_write(codec->control_data, data, 2);
 274         if (ret == 2) {
 275                 aic32x4->page_no = new_page;
 276                 return 0;
 277         } else {
 278                 return ret;
 279         }
 280 }
 281
 282 static int aic32x4_write(struct snd_soc_codec *codec, unsigned int reg,
 283                                 unsigned int val)
 284 {
 285         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 286         unsigned int page = reg / 128;
 287         unsigned int fixed_reg = reg % 128;
 288         u8 data[2];
 289         int ret;
 290
 291         /* A write to AIC32X4_PSEL is really a non-explicit page change */
 292         if (reg == AIC32X4_PSEL)
 293                 return aic32x4_change_page(codec, val);
 294
 295         if (aic32x4->page_no != page) {
 296                 ret = aic32x4_change_page(codec, page);
 297                 if (ret != 0)
 298                         return ret;
 299         }
 300
 301         data[0] = fixed_reg & 0xff;
 302         data[1] = val & 0xff;
 303
 304         if (codec->hw_write(codec->control_data, data, 2) == 2)
 305                 return 0;
 306         else
 307                 return -EIO;
 308 }
 309
 310 static unsigned int aic32x4_read(struct snd_soc_codec *codec, unsigned int reg)
 311 {
 312         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 313         unsigned int page = reg / 128;
 314         unsigned int fixed_reg = reg % 128;
 315         int ret;
 316
 317         if (aic32x4->page_no != page) {
 318                 ret = aic32x4_change_page(codec, page);
 319                 if (ret != 0)
 320                         return ret;
 321         }
 322         return i2c_smbus_read_byte_data(codec->control_data, fixed_reg & 0xff);
 323 }
 324
 325 static inline int aic32x4_get_divs(int mclk, int rate)
 326 {
 327         int i;
 328
 329         for (i = 0; i < ARRAY_SIZE(aic32x4_divs); i++) {
 330                 if ((aic32x4_divs[i].rate == rate)
 331                     && (aic32x4_divs[i].mclk == mclk)) {
 332                         return i;
 333                 }
 334         }
 335         printk(KERN_ERR "aic32x4: master clock and sample rate is not supported\n");
 336         return -EINVAL;
 337 }
 338
 339 static int aic32x4_add_widgets(struct snd_soc_codec *codec)
 340 {
 341         snd_soc_dapm_new_controls(&codec->dapm, aic32x4_dapm_widgets,
 342                                   ARRAY_SIZE(aic32x4_dapm_widgets));
 343
 344         snd_soc_dapm_add_routes(&codec->dapm, aic32x4_dapm_routes,
 345                                 ARRAY_SIZE(aic32x4_dapm_routes));
 346
 347         snd_soc_dapm_new_widgets(&codec->dapm);
 348         return 0;
 349 }
 350
 351 static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 352                                   int clk_id, unsigned int freq, int dir)
 353 {
 354         struct snd_soc_codec *codec = codec_dai->codec;
 355         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 356
 357         switch (freq) {
 358         case AIC32X4_FREQ_12000000:
 359         case AIC32X4_FREQ_24000000:
 360         case AIC32X4_FREQ_25000000:
 361                 aic32x4->sysclk = freq;
 362                 return 0;
 363         }
 364         printk(KERN_ERR "aic32x4: invalid frequency to set DAI system clock\n");
 365         return -EINVAL;
 366 }
 367
 368 static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 369 {
 370         struct snd_soc_codec *codec = codec_dai->codec;
 371         u8 iface_reg_1;
 372         u8 iface_reg_2;
 373         u8 iface_reg_3;
 374
 375         iface_reg_1 = snd_soc_read(codec, AIC32X4_IFACE1);
 376         iface_reg_1 = iface_reg_1 & ~(3 << 6 | 3 << 2);
 377         iface_reg_2 = snd_soc_read(codec, AIC32X4_IFACE2);
 378         iface_reg_2 = 0;
 379         iface_reg_3 = snd_soc_read(codec, AIC32X4_IFACE3);
 380         iface_reg_3 = iface_reg_3 & ~(1 << 3);
 381
 382         /* set master/slave audio interface */
 383         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 384         case SND_SOC_DAIFMT_CBM_CFM:
 385                 iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
 386                 break;
 387         case SND_SOC_DAIFMT_CBS_CFS:
 388                 break;
 389         default:
 390                 printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
 391                 return -EINVAL;
 392         }
 393
 394         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 395         case SND_SOC_DAIFMT_I2S:
 396                 break;
 397         case SND_SOC_DAIFMT_DSP_A:
 398                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 399                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 400                 iface_reg_2 = 0x01; /* add offset 1 */
 401                 break;
 402         case SND_SOC_DAIFMT_DSP_B:
 403                 iface_reg_1 |= (AIC32X4_DSP_MODE << AIC32X4_PLLJ_SHIFT);
 404                 iface_reg_3 |= (1 << 3); /* invert bit clock */
 405                 break;
 406         case SND_SOC_DAIFMT_RIGHT_J:
 407                 iface_reg_1 |=
 408                         (AIC32X4_RIGHT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 409                 break;
 410         case SND_SOC_DAIFMT_LEFT_J:
 411                 iface_reg_1 |=
 412                         (AIC32X4_LEFT_JUSTIFIED_MODE << AIC32X4_PLLJ_SHIFT);
 413                 break;
 414         default:
 415                 printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
 416                 return -EINVAL;
 417         }
 418
 419         snd_soc_write(codec, AIC32X4_IFACE1, iface_reg_1);
 420         snd_soc_write(codec, AIC32X4_IFACE2, iface_reg_2);
 421         snd_soc_write(codec, AIC32X4_IFACE3, iface_reg_3);
 422         return 0;
 423 }
 424
 425 static int aic32x4_hw_params(struct snd_pcm_substream *substream,
 426                              struct snd_pcm_hw_params *params,
 427                              struct snd_soc_dai *dai)
 428 {
 429         struct snd_soc_codec *codec = dai->codec;
 430         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 431         u8 data;
 432         int i;
 433
 434         i = aic32x4_get_divs(aic32x4->sysclk, params_rate(params));
 435         if (i < 0) {
 436                 printk(KERN_ERR "aic32x4: sampling rate not supported\n");
 437                 return i;
 438         }
 439
 440         /* Use PLL as CODEC_CLKIN and DAC_MOD_CLK as BDIV_CLKIN */
 441         snd_soc_write(codec, AIC32X4_CLKMUX, AIC32X4_PLLCLKIN);
 442         snd_soc_write(codec, AIC32X4_IFACE3, AIC32X4_DACMOD2BCLK);
 443
 444         /* We will fix R value to 1 and will make P & J=K.D as varialble */
 445         data = snd_soc_read(codec, AIC32X4_PLLPR);
 446         data &= ~(7 << 4);
 447         snd_soc_write(codec, AIC32X4_PLLPR,
 448                       (data | (aic32x4_divs[i].p_val << 4) | 0x01));
 449
 450         snd_soc_write(codec, AIC32X4_PLLJ, aic32x4_divs[i].pll_j);
 451
 452         snd_soc_write(codec, AIC32X4_PLLDMSB, (aic32x4_divs[i].pll_d >> 8));
 453         snd_soc_write(codec, AIC32X4_PLLDLSB,
 454                       (aic32x4_divs[i].pll_d & 0xff));
 455
 456         /* NDAC divider value */
 457         data = snd_soc_read(codec, AIC32X4_NDAC);
 458         data &= ~(0x7f);
 459         snd_soc_write(codec, AIC32X4_NDAC, data | aic32x4_divs[i].ndac);
 460
 461         /* MDAC divider value */
 462         data = snd_soc_read(codec, AIC32X4_MDAC);
 463         data &= ~(0x7f);
 464         snd_soc_write(codec, AIC32X4_MDAC, data | aic32x4_divs[i].mdac);
 465
 466         /* DOSR MSB & LSB values */
 467         snd_soc_write(codec, AIC32X4_DOSRMSB, aic32x4_divs[i].dosr >> 8);
 468         snd_soc_write(codec, AIC32X4_DOSRLSB,
 469                       (aic32x4_divs[i].dosr & 0xff));
 470
 471         /* NADC divider value */
 472         data = snd_soc_read(codec, AIC32X4_NADC);
 473         data &= ~(0x7f);
 474         snd_soc_write(codec, AIC32X4_NADC, data | aic32x4_divs[i].nadc);
 475
 476         /* MADC divider value */
 477         data = snd_soc_read(codec, AIC32X4_MADC);
 478         data &= ~(0x7f);
 479         snd_soc_write(codec, AIC32X4_MADC, data | aic32x4_divs[i].madc);
 480
 481         /* AOSR value */
 482         snd_soc_write(codec, AIC32X4_AOSR, aic32x4_divs[i].aosr);
 483
 484         /* BCLK N divider */
 485         data = snd_soc_read(codec, AIC32X4_BCLKN);
 486         data &= ~(0x7f);
 487         snd_soc_write(codec, AIC32X4_BCLKN, data | aic32x4_divs[i].blck_N);
 488
 489         data = snd_soc_read(codec, AIC32X4_IFACE1);
 490         data = data & ~(3 << 4);
 491         switch (params_format(params)) {
 492         case SNDRV_PCM_FORMAT_S16_LE:
 493                 break;
 494         case SNDRV_PCM_FORMAT_S20_3LE:
 495                 data |= (AIC32X4_WORD_LEN_20BITS << AIC32X4_DOSRMSB_SHIFT);
 496                 break;
 497         case SNDRV_PCM_FORMAT_S24_LE:
 498                 data |= (AIC32X4_WORD_LEN_24BITS << AIC32X4_DOSRMSB_SHIFT);
 499                 break;
 500         case SNDRV_PCM_FORMAT_S32_LE:
 501                 data |= (AIC32X4_WORD_LEN_32BITS << AIC32X4_DOSRMSB_SHIFT);
 502                 break;
 503         }
 504         snd_soc_write(codec, AIC32X4_IFACE1, data);
 505
 506         return 0;
 507 }
 508
 509 static int aic32x4_mute(struct snd_soc_dai *dai, int mute)
 510 {
 511         struct snd_soc_codec *codec = dai->codec;
 512         u8 dac_reg;
 513
 514         dac_reg = snd_soc_read(codec, AIC32X4_DACMUTE) & ~AIC32X4_MUTEON;
 515         if (mute)
 516                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg | AIC32X4_MUTEON);
 517         else
 518                 snd_soc_write(codec, AIC32X4_DACMUTE, dac_reg);
 519         return 0;
 520 }
 521
 522 static int aic32x4_set_bias_level(struct snd_soc_codec *codec,
 523                                   enum snd_soc_bias_level level)
 524 {
 525         switch (level) {
 526         case SND_SOC_BIAS_ON:
 527                 /* Switch on PLL */
 528                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 529                                     AIC32X4_PLLEN, AIC32X4_PLLEN);
 530
 531                 /* Switch on NDAC Divider */
 532                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 533                                     AIC32X4_NDACEN, AIC32X4_NDACEN);
 534
 535                 /* Switch on MDAC Divider */
 536                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 537                                     AIC32X4_MDACEN, AIC32X4_MDACEN);
 538
 539                 /* Switch on NADC Divider */
 540                 snd_soc_update_bits(codec, AIC32X4_NADC,
 541                                     AIC32X4_NADCEN, AIC32X4_NADCEN);
 542
 543                 /* Switch on MADC Divider */
 544                 snd_soc_update_bits(codec, AIC32X4_MADC,
 545                                     AIC32X4_MADCEN, AIC32X4_MADCEN);
 546
 547                 /* Switch on BCLK_N Divider */
 548                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 549                                     AIC32X4_BCLKEN, AIC32X4_BCLKEN);
 550                 break;
 551         case SND_SOC_BIAS_PREPARE:
 552                 break;
 553         case SND_SOC_BIAS_STANDBY:
 554                 /* Switch off PLL */
 555                 snd_soc_update_bits(codec, AIC32X4_PLLPR,
 556                                     AIC32X4_PLLEN, 0);
 557
 558                 /* Switch off NDAC Divider */
 559                 snd_soc_update_bits(codec, AIC32X4_NDAC,
 560                                     AIC32X4_NDACEN, 0);
 561
 562                 /* Switch off MDAC Divider */
 563                 snd_soc_update_bits(codec, AIC32X4_MDAC,
 564                                     AIC32X4_MDACEN, 0);
 565
 566                 /* Switch off NADC Divider */
 567                 snd_soc_update_bits(codec, AIC32X4_NADC,
 568                                     AIC32X4_NADCEN, 0);
 569
 570                 /* Switch off MADC Divider */
 571                 snd_soc_update_bits(codec, AIC32X4_MADC,
 572                                     AIC32X4_MADCEN, 0);
 573
 574                 /* Switch off BCLK_N Divider */
 575                 snd_soc_update_bits(codec, AIC32X4_BCLKN,
 576                                     AIC32X4_BCLKEN, 0);
 577                 break;
 578         case SND_SOC_BIAS_OFF:
 579                 break;
 580         }
 581         codec->dapm.bias_level = level;
 582         return 0;
 583 }
 584
 585 #define AIC32X4_RATES   SNDRV_PCM_RATE_8000_48000
 586 #define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 587                          | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
 588
 589 static const struct snd_soc_dai_ops aic32x4_ops = {
 590         .hw_params = aic32x4_hw_params,
 591         .digital_mute = aic32x4_mute,
 592         .set_fmt = aic32x4_set_dai_fmt,
 593         .set_sysclk = aic32x4_set_dai_sysclk,
 594 };
 595
 596 static struct snd_soc_dai_driver aic32x4_dai = {
 597         .name = "tlv320aic32x4-hifi",
 598         .playback = {
 599                      .stream_name = "Playback",
 600                      .channels_min = 1,
 601                      .channels_max = 2,
 602                      .rates = AIC32X4_RATES,
 603                      .formats = AIC32X4_FORMATS,},
 604         .capture = {
 605                     .stream_name = "Capture",
 606                     .channels_min = 1,
 607                     .channels_max = 2,
 608                     .rates = AIC32X4_RATES,
 609                     .formats = AIC32X4_FORMATS,},
 610         .ops = &aic32x4_ops,
 611         .symmetric_rates = 1,
 612 };
 613
 614 static int aic32x4_suspend(struct snd_soc_codec *codec)
 615 {
 616         aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
 617         return 0;
 618 }
 619
 620 static int aic32x4_resume(struct snd_soc_codec *codec)
 621 {
 622         aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 623         return 0;
 624 }
 625
 626 static int aic32x4_probe(struct snd_soc_codec *codec)
 627 {
 628         struct aic32x4_priv *aic32x4 = snd_soc_codec_get_drvdata(codec);
 629         u32 tmp_reg;
 630
 631         codec->hw_write = (hw_write_t) i2c_master_send;
 632         codec->control_data = aic32x4->control_data;
 633
 634         snd_soc_write(codec, AIC32X4_RESET, 0x01);
 635
 636         /* Power platform configuration */
 637         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
 638                 snd_soc_write(codec, AIC32X4_MICBIAS, AIC32X4_MICBIAS_LDOIN |
 639                                                       AIC32X4_MICBIAS_2075V);
 640         }
 641         if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE) {
 642                 snd_soc_write(codec, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
 643         }
 644
 645         tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
 646                         AIC32X4_LDOCTLEN : 0;
 647         snd_soc_write(codec, AIC32X4_LDOCTL, tmp_reg);
 648
 649         tmp_reg = snd_soc_read(codec, AIC32X4_CMMODE);
 650         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36) {
 651                 tmp_reg |= AIC32X4_LDOIN_18_36;
 652         }
 653         if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED) {
 654                 tmp_reg |= AIC32X4_LDOIN2HP;
 655         }
 656         snd_soc_write(codec, AIC32X4_CMMODE, tmp_reg);
 657
 658         /* Do DACs need to be swapped? */
 659         if (aic32x4->swapdacs) {
 660                 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2RCHN | AIC32X4_RDAC2LCHN);
 661         } else {
 662                 snd_soc_write(codec, AIC32X4_DACSETUP, AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN);
 663         }
 664
 665         /* Mic PGA routing */
 666         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K) {
 667                 snd_soc_write(codec, AIC32X4_LMICPGANIN, AIC32X4_LMICPGANIN_IN2R_10K);
 668         }
 669         if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K) {
 670                 snd_soc_write(codec, AIC32X4_RMICPGANIN, AIC32X4_RMICPGANIN_IN1L_10K);
 671         }
 672
 673         aic32x4_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 674         snd_soc_add_controls(codec, aic32x4_snd_controls,
 675                              ARRAY_SIZE(aic32x4_snd_controls));
 676         aic32x4_add_widgets(codec);
 677
 678         return 0;
 679 }
 680
 681 static int aic32x4_remove(struct snd_soc_codec *codec)
 682 {
 683         aic32x4_set_bias_level(codec, SND_SOC_BIAS_OFF);
 684         return 0;
 685 }
 686
 687 static struct snd_soc_codec_driver soc_codec_dev_aic32x4 = {
 688         .read = aic32x4_read,
 689         .write = aic32x4_write,
 690         .probe = aic32x4_probe,
 691         .remove = aic32x4_remove,
 692         .suspend = aic32x4_suspend,
 693         .resume = aic32x4_resume,
 694         .set_bias_level = aic32x4_set_bias_level,
 695 };
 696
 697 static __devinit int aic32x4_i2c_probe(struct i2c_client *i2c,
 698                                       const struct i2c_device_id *id)
 699 {
 700         struct aic32x4_pdata *pdata = i2c->dev.platform_data;
 701         struct aic32x4_priv *aic32x4;
 702         int ret;
 703
 704         aic32x4 = devm_kzalloc(&i2c->dev, sizeof(struct aic32x4_priv),
 705                                GFP_KERNEL);
 706         if (aic32x4 == NULL)
 707                 return -ENOMEM;
 708
 709         aic32x4->control_data = i2c;
 710         i2c_set_clientdata(i2c, aic32x4);
 711
 712         if (pdata) {
 713                 aic32x4->power_cfg = pdata->power_cfg;
 714                 aic32x4->swapdacs = pdata->swapdacs;
 715                 aic32x4->micpga_routing = pdata->micpga_routing;
 716         } else {
 717                 aic32x4->power_cfg = 0;
 718                 aic32x4->swapdacs = false;
 719                 aic32x4->micpga_routing = 0;
 720         }
 721
 722         ret = snd_soc_register_codec(&i2c->dev,
 723                         &soc_codec_dev_aic32x4, &aic32x4_dai, 1);
 724         return ret;
 725 }
 726
 727 static __devexit int aic32x4_i2c_remove(struct i2c_client *client)
 728 {
 729         snd_soc_unregister_codec(&client->dev);
 730         return 0;
 731 }
 732
 733 static const struct i2c_device_id aic32x4_i2c_id[] = {
 734         { "tlv320aic32x4", 0 },
 735         { }
 736 };
 737 MODULE_DEVICE_TABLE(i2c, aic32x4_i2c_id);
 738
 739 static struct i2c_driver aic32x4_i2c_driver = {
 740         .driver = {
 741                 .name = "tlv320aic32x4",
 742                 .owner = THIS_MODULE,
 743         },
 744         .probe =    aic32x4_i2c_probe,
 745         .remove =   __devexit_p(aic32x4_i2c_remove),
 746         .id_table = aic32x4_i2c_id,
 747 };
 748
 749 static int __init aic32x4_modinit(void)
 750 {
 751         int ret = 0;
 752
 753         ret = i2c_add_driver(&aic32x4_i2c_driver);
 754         if (ret != 0) {
 755                 printk(KERN_ERR "Failed to register aic32x4 I2C driver: %d\n",
 756                        ret);
 757         }
 758         return ret;
 759 }
 760 module_init(aic32x4_modinit);
 761
 762 static void __exit aic32x4_exit(void)
 763 {
 764         i2c_del_driver(&aic32x4_i2c_driver);
 765 }
 766 module_exit(aic32x4_exit);
 767
 768 MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
 769 MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
 770 MODULE_LICENSE("GPL");