2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 #define NV_DEBUG_NOTRACE
27 #include "nouveau_drv.h"
28 #include "nouveau_hw.h"
29 #include "nouveau_encoder.h"
31 #include <linux/io-mapping.h>
33 /* these defines are made up */
34 #define NV_CIO_CRE_44_HEADA 0x0
35 #define NV_CIO_CRE_44_HEADB 0x3
36 #define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
37 #define LEGACY_I2C_CRT 0x80
38 #define LEGACY_I2C_PANEL 0x81
39 #define LEGACY_I2C_TV 0x82
43 #define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
44 #define LOG_OLD_VALUE(x)
46 #define ROM16(x) le16_to_cpu(*(uint16_t *)&(x))
47 #define ROM32(x) le32_to_cpu(*(uint32_t *)&(x))
54 static bool nv_cksum(const uint8_t *data
, unsigned int length
)
57 * There's a few checksums in the BIOS, so here's a generic checking
63 for (i
= 0; i
< length
; i
++)
73 score_vbios(struct drm_device
*dev
, const uint8_t *data
, const bool writeable
)
75 if (!(data
[0] == 0x55 && data
[1] == 0xAA)) {
76 NV_TRACEWARN(dev
, "... BIOS signature not found\n");
80 if (nv_cksum(data
, data
[2] * 512)) {
81 NV_TRACEWARN(dev
, "... BIOS checksum invalid\n");
82 /* if a ro image is somewhat bad, it's probably all rubbish */
83 return writeable
? 2 : 1;
85 NV_TRACE(dev
, "... appears to be valid\n");
90 static void load_vbios_prom(struct drm_device
*dev
, uint8_t *data
)
92 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
93 uint32_t pci_nv_20
, save_pci_nv_20
;
97 if (dev_priv
->card_type
>= NV_50
)
100 pci_nv_20
= NV_PBUS_PCI_NV_20
;
102 /* enable ROM access */
103 save_pci_nv_20
= nvReadMC(dev
, pci_nv_20
);
104 nvWriteMC(dev
, pci_nv_20
,
105 save_pci_nv_20
& ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
);
107 /* bail if no rom signature */
108 if (nv_rd08(dev
, NV_PROM_OFFSET
) != 0x55 ||
109 nv_rd08(dev
, NV_PROM_OFFSET
+ 1) != 0xaa)
112 /* additional check (see note below) - read PCI record header */
113 pcir_ptr
= nv_rd08(dev
, NV_PROM_OFFSET
+ 0x18) |
114 nv_rd08(dev
, NV_PROM_OFFSET
+ 0x19) << 8;
115 if (nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
) != 'P' ||
116 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 1) != 'C' ||
117 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 2) != 'I' ||
118 nv_rd08(dev
, NV_PROM_OFFSET
+ pcir_ptr
+ 3) != 'R')
121 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
122 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
123 * each byte. we'll hope pramin has something usable instead
125 for (i
= 0; i
< NV_PROM_SIZE
; i
++)
126 data
[i
] = nv_rd08(dev
, NV_PROM_OFFSET
+ i
);
129 /* disable ROM access */
130 nvWriteMC(dev
, pci_nv_20
,
131 save_pci_nv_20
| NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
);
134 static void load_vbios_pramin(struct drm_device
*dev
, uint8_t *data
)
136 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
137 uint32_t old_bar0_pramin
= 0;
140 if (dev_priv
->card_type
>= NV_50
) {
141 uint32_t vbios_vram
= (nv_rd32(dev
, 0x619f04) & ~0xff) << 8;
144 vbios_vram
= (nv_rd32(dev
, 0x1700) << 16) + 0xf0000;
146 old_bar0_pramin
= nv_rd32(dev
, 0x1700);
147 nv_wr32(dev
, 0x1700, vbios_vram
>> 16);
150 /* bail if no rom signature */
151 if (nv_rd08(dev
, NV_PRAMIN_OFFSET
) != 0x55 ||
152 nv_rd08(dev
, NV_PRAMIN_OFFSET
+ 1) != 0xaa)
155 for (i
= 0; i
< NV_PROM_SIZE
; i
++)
156 data
[i
] = nv_rd08(dev
, NV_PRAMIN_OFFSET
+ i
);
159 if (dev_priv
->card_type
>= NV_50
)
160 nv_wr32(dev
, 0x1700, old_bar0_pramin
);
163 static void load_vbios_pci(struct drm_device
*dev
, uint8_t *data
)
165 void __iomem
*rom
= NULL
;
169 ret
= pci_enable_rom(dev
->pdev
);
173 rom
= pci_map_rom(dev
->pdev
, &rom_len
);
176 memcpy_fromio(data
, rom
, rom_len
);
177 pci_unmap_rom(dev
->pdev
, rom
);
180 pci_disable_rom(dev
->pdev
);
183 static void load_vbios_acpi(struct drm_device
*dev
, uint8_t *data
)
187 int size
= 64 * 1024;
189 if (!nouveau_acpi_rom_supported(dev
->pdev
))
192 for (i
= 0; i
< (size
/ ROM_BIOS_PAGE
); i
++) {
193 ret
= nouveau_acpi_get_bios_chunk(data
,
204 void (*loadbios
)(struct drm_device
*, uint8_t *);
208 static struct methods shadow_methods
[] = {
209 { "PRAMIN", load_vbios_pramin
, true },
210 { "PROM", load_vbios_prom
, false },
211 { "PCIROM", load_vbios_pci
, true },
212 { "ACPI", load_vbios_acpi
, true },
214 #define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
216 static bool NVShadowVBIOS(struct drm_device
*dev
, uint8_t *data
)
218 struct methods
*methods
= shadow_methods
;
220 int scores
[NUM_SHADOW_METHODS
], i
;
223 for (i
= 0; i
< NUM_SHADOW_METHODS
; i
++)
224 if (!strcasecmp(nouveau_vbios
, methods
[i
].desc
))
227 if (i
< NUM_SHADOW_METHODS
) {
228 NV_INFO(dev
, "Attempting to use BIOS image from %s\n",
231 methods
[i
].loadbios(dev
, data
);
232 if (score_vbios(dev
, data
, methods
[i
].rw
))
236 NV_ERROR(dev
, "VBIOS source \'%s\' invalid\n", nouveau_vbios
);
239 for (i
= 0; i
< NUM_SHADOW_METHODS
; i
++) {
240 NV_TRACE(dev
, "Attempting to load BIOS image from %s\n",
242 data
[0] = data
[1] = 0; /* avoid reuse of previous image */
243 methods
[i
].loadbios(dev
, data
);
244 scores
[i
] = score_vbios(dev
, data
, methods
[i
].rw
);
245 if (scores
[i
] == testscore
)
249 while (--testscore
> 0) {
250 for (i
= 0; i
< NUM_SHADOW_METHODS
; i
++) {
251 if (scores
[i
] == testscore
) {
252 NV_TRACE(dev
, "Using BIOS image from %s\n",
254 methods
[i
].loadbios(dev
, data
);
260 NV_ERROR(dev
, "No valid BIOS image found\n");
264 struct init_tbl_entry
{
268 * > 0: success, length of opcode
269 * 0: success, but abort further parsing of table (INIT_DONE etc)
270 * < 0: failure, table parsing will be aborted
272 int (*handler
)(struct nvbios
*, uint16_t, struct init_exec
*);
281 static int parse_init_table(struct nvbios
*, unsigned int, struct init_exec
*);
283 #define MACRO_INDEX_SIZE 2
285 #define CONDITION_SIZE 12
286 #define IO_FLAG_CONDITION_SIZE 9
287 #define IO_CONDITION_SIZE 5
288 #define MEM_INIT_SIZE 66
290 static void still_alive(void)
299 munge_reg(struct nvbios
*bios
, uint32_t reg
)
301 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
302 struct dcb_entry
*dcbent
= bios
->display
.output
;
304 if (dev_priv
->card_type
< NV_50
)
307 if (reg
& 0x40000000) {
310 reg
+= (ffs(dcbent
->or) - 1) * 0x800;
311 if ((reg
& 0x20000000) && !(dcbent
->sorconf
.link
& 1))
320 valid_reg(struct nvbios
*bios
, uint32_t reg
)
322 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
323 struct drm_device
*dev
= bios
->dev
;
325 /* C51 has misaligned regs on purpose. Marvellous */
327 (reg
& 0x1 && dev_priv
->vbios
.chip_version
!= 0x51))
328 NV_ERROR(dev
, "======= misaligned reg 0x%08X =======\n", reg
);
330 /* warn on C51 regs that haven't been verified accessible in tracing */
331 if (reg
& 0x1 && dev_priv
->vbios
.chip_version
== 0x51 &&
332 reg
!= 0x130d && reg
!= 0x1311 && reg
!= 0x60081d)
333 NV_WARN(dev
, "=== C51 misaligned reg 0x%08X not verified ===\n",
336 if (reg
>= (8*1024*1024)) {
337 NV_ERROR(dev
, "=== reg 0x%08x out of mapped bounds ===\n", reg
);
345 valid_idx_port(struct nvbios
*bios
, uint16_t port
)
347 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
348 struct drm_device
*dev
= bios
->dev
;
351 * If adding more ports here, the read/write functions below will need
352 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
353 * used for the port in question
355 if (dev_priv
->card_type
< NV_50
) {
356 if (port
== NV_CIO_CRX__COLOR
)
358 if (port
== NV_VIO_SRX
)
361 if (port
== NV_CIO_CRX__COLOR
)
365 NV_ERROR(dev
, "========== unknown indexed io port 0x%04X ==========\n",
372 valid_port(struct nvbios
*bios
, uint16_t port
)
374 struct drm_device
*dev
= bios
->dev
;
377 * If adding more ports here, the read/write functions below will need
378 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
379 * used for the port in question
381 if (port
== NV_VIO_VSE2
)
384 NV_ERROR(dev
, "========== unknown io port 0x%04X ==========\n", port
);
390 bios_rd32(struct nvbios
*bios
, uint32_t reg
)
394 reg
= munge_reg(bios
, reg
);
395 if (!valid_reg(bios
, reg
))
399 * C51 sometimes uses regs with bit0 set in the address. For these
400 * cases there should exist a translation in a BIOS table to an IO
401 * port address which the BIOS uses for accessing the reg
403 * These only seem to appear for the power control regs to a flat panel,
404 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
405 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
406 * suspend-resume mmio trace from a C51 will be required to see if this
407 * is true for the power microcode in 0x14.., or whether the direct IO
408 * port access method is needed
413 data
= nv_rd32(bios
->dev
, reg
);
415 BIOSLOG(bios
, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg
, data
);
421 bios_wr32(struct nvbios
*bios
, uint32_t reg
, uint32_t data
)
423 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
425 reg
= munge_reg(bios
, reg
);
426 if (!valid_reg(bios
, reg
))
429 /* see note in bios_rd32 */
433 LOG_OLD_VALUE(bios_rd32(bios
, reg
));
434 BIOSLOG(bios
, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg
, data
);
436 if (dev_priv
->vbios
.execute
) {
438 nv_wr32(bios
->dev
, reg
, data
);
443 bios_idxprt_rd(struct nvbios
*bios
, uint16_t port
, uint8_t index
)
445 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
446 struct drm_device
*dev
= bios
->dev
;
449 if (!valid_idx_port(bios
, port
))
452 if (dev_priv
->card_type
< NV_50
) {
453 if (port
== NV_VIO_SRX
)
454 data
= NVReadVgaSeq(dev
, bios
->state
.crtchead
, index
);
455 else /* assume NV_CIO_CRX__COLOR */
456 data
= NVReadVgaCrtc(dev
, bios
->state
.crtchead
, index
);
460 data32
= bios_rd32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3));
461 data
= (data32
>> ((index
& 3) << 3)) & 0xff;
464 BIOSLOG(bios
, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
465 "Head: 0x%02X, Data: 0x%02X\n",
466 port
, index
, bios
->state
.crtchead
, data
);
471 bios_idxprt_wr(struct nvbios
*bios
, uint16_t port
, uint8_t index
, uint8_t data
)
473 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
474 struct drm_device
*dev
= bios
->dev
;
476 if (!valid_idx_port(bios
, port
))
480 * The current head is maintained in the nvbios member state.crtchead.
481 * We trap changes to CR44 and update the head variable and hence the
482 * register set written.
483 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
484 * of the write, and to head1 after the write
486 if (port
== NV_CIO_CRX__COLOR
&& index
== NV_CIO_CRE_44
&&
487 data
!= NV_CIO_CRE_44_HEADB
)
488 bios
->state
.crtchead
= 0;
490 LOG_OLD_VALUE(bios_idxprt_rd(bios
, port
, index
));
491 BIOSLOG(bios
, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
492 "Head: 0x%02X, Data: 0x%02X\n",
493 port
, index
, bios
->state
.crtchead
, data
);
495 if (bios
->execute
&& dev_priv
->card_type
< NV_50
) {
497 if (port
== NV_VIO_SRX
)
498 NVWriteVgaSeq(dev
, bios
->state
.crtchead
, index
, data
);
499 else /* assume NV_CIO_CRX__COLOR */
500 NVWriteVgaCrtc(dev
, bios
->state
.crtchead
, index
, data
);
503 uint32_t data32
, shift
= (index
& 3) << 3;
507 data32
= bios_rd32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3));
508 data32
&= ~(0xff << shift
);
509 data32
|= (data
<< shift
);
510 bios_wr32(bios
, NV50_PDISPLAY_VGACRTC(index
& ~3), data32
);
513 if (port
== NV_CIO_CRX__COLOR
&&
514 index
== NV_CIO_CRE_44
&& data
== NV_CIO_CRE_44_HEADB
)
515 bios
->state
.crtchead
= 1;
519 bios_port_rd(struct nvbios
*bios
, uint16_t port
)
521 uint8_t data
, head
= bios
->state
.crtchead
;
523 if (!valid_port(bios
, port
))
526 data
= NVReadPRMVIO(bios
->dev
, head
, NV_PRMVIO0_OFFSET
+ port
);
528 BIOSLOG(bios
, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
535 bios_port_wr(struct nvbios
*bios
, uint16_t port
, uint8_t data
)
537 int head
= bios
->state
.crtchead
;
539 if (!valid_port(bios
, port
))
542 LOG_OLD_VALUE(bios_port_rd(bios
, port
));
543 BIOSLOG(bios
, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
550 NVWritePRMVIO(bios
->dev
, head
, NV_PRMVIO0_OFFSET
+ port
, data
);
554 io_flag_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
557 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
558 * for the CRTC index; 1 byte for the mask to apply to the value
559 * retrieved from the CRTC; 1 byte for the shift right to apply to the
560 * masked CRTC value; 2 bytes for the offset to the flag array, to
561 * which the shifted value is added; 1 byte for the mask applied to the
562 * value read from the flag array; and 1 byte for the value to compare
563 * against the masked byte from the flag table.
566 uint16_t condptr
= bios
->io_flag_condition_tbl_ptr
+ cond
* IO_FLAG_CONDITION_SIZE
;
567 uint16_t crtcport
= ROM16(bios
->data
[condptr
]);
568 uint8_t crtcindex
= bios
->data
[condptr
+ 2];
569 uint8_t mask
= bios
->data
[condptr
+ 3];
570 uint8_t shift
= bios
->data
[condptr
+ 4];
571 uint16_t flagarray
= ROM16(bios
->data
[condptr
+ 5]);
572 uint8_t flagarraymask
= bios
->data
[condptr
+ 7];
573 uint8_t cmpval
= bios
->data
[condptr
+ 8];
576 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
577 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
579 offset
, crtcport
, crtcindex
, mask
, shift
, flagarray
, flagarraymask
, cmpval
);
581 data
= bios_idxprt_rd(bios
, crtcport
, crtcindex
);
583 data
= bios
->data
[flagarray
+ ((data
& mask
) >> shift
)];
584 data
&= flagarraymask
;
586 BIOSLOG(bios
, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
587 offset
, data
, cmpval
);
589 return (data
== cmpval
);
593 bios_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
596 * The condition table entry has 4 bytes for the address of the
597 * register to check, 4 bytes for a mask to apply to the register and
598 * 4 for a test comparison value
601 uint16_t condptr
= bios
->condition_tbl_ptr
+ cond
* CONDITION_SIZE
;
602 uint32_t reg
= ROM32(bios
->data
[condptr
]);
603 uint32_t mask
= ROM32(bios
->data
[condptr
+ 4]);
604 uint32_t cmpval
= ROM32(bios
->data
[condptr
+ 8]);
607 BIOSLOG(bios
, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
608 offset
, cond
, reg
, mask
);
610 data
= bios_rd32(bios
, reg
) & mask
;
612 BIOSLOG(bios
, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
613 offset
, data
, cmpval
);
615 return (data
== cmpval
);
619 io_condition_met(struct nvbios
*bios
, uint16_t offset
, uint8_t cond
)
622 * The IO condition entry has 2 bytes for the IO port address; 1 byte
623 * for the index to write to io_port; 1 byte for the mask to apply to
624 * the byte read from io_port+1; and 1 byte for the value to compare
625 * against the masked byte.
628 uint16_t condptr
= bios
->io_condition_tbl_ptr
+ cond
* IO_CONDITION_SIZE
;
629 uint16_t io_port
= ROM16(bios
->data
[condptr
]);
630 uint8_t port_index
= bios
->data
[condptr
+ 2];
631 uint8_t mask
= bios
->data
[condptr
+ 3];
632 uint8_t cmpval
= bios
->data
[condptr
+ 4];
634 uint8_t data
= bios_idxprt_rd(bios
, io_port
, port_index
) & mask
;
636 BIOSLOG(bios
, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
637 offset
, data
, cmpval
);
639 return (data
== cmpval
);
643 nv50_pll_set(struct drm_device
*dev
, uint32_t reg
, uint32_t clk
)
645 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
646 uint32_t reg0
= nv_rd32(dev
, reg
+ 0);
647 uint32_t reg1
= nv_rd32(dev
, reg
+ 4);
648 struct nouveau_pll_vals pll
;
649 struct pll_lims pll_limits
;
652 ret
= get_pll_limits(dev
, reg
, &pll_limits
);
656 clk
= nouveau_calc_pll_mnp(dev
, &pll_limits
, clk
, &pll
);
660 reg0
= (reg0
& 0xfff8ffff) | (pll
.log2P
<< 16);
661 reg1
= (reg1
& 0xffff0000) | (pll
.N1
<< 8) | pll
.M1
;
663 if (dev_priv
->vbios
.execute
) {
665 nv_wr32(dev
, reg
+ 4, reg1
);
666 nv_wr32(dev
, reg
+ 0, reg0
);
673 setPLL(struct nvbios
*bios
, uint32_t reg
, uint32_t clk
)
675 struct drm_device
*dev
= bios
->dev
;
676 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
678 struct pll_lims pll_lim
;
679 struct nouveau_pll_vals pllvals
;
682 if (dev_priv
->card_type
>= NV_50
)
683 return nv50_pll_set(dev
, reg
, clk
);
685 /* high regs (such as in the mac g5 table) are not -= 4 */
686 ret
= get_pll_limits(dev
, reg
> 0x405c ? reg
: reg
- 4, &pll_lim
);
690 clk
= nouveau_calc_pll_mnp(dev
, &pll_lim
, clk
, &pllvals
);
696 nouveau_hw_setpll(dev
, reg
, &pllvals
);
702 static int dcb_entry_idx_from_crtchead(struct drm_device
*dev
)
704 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
705 struct nvbios
*bios
= &dev_priv
->vbios
;
708 * For the results of this function to be correct, CR44 must have been
709 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
710 * and the DCB table parsed, before the script calling the function is
711 * run. run_digital_op_script is example of how to do such setup
714 uint8_t dcb_entry
= NVReadVgaCrtc5758(dev
, bios
->state
.crtchead
, 0);
716 if (dcb_entry
> bios
->dcb
.entries
) {
717 NV_ERROR(dev
, "CR58 doesn't have a valid DCB entry currently "
718 "(%02X)\n", dcb_entry
);
719 dcb_entry
= 0x7f; /* unused / invalid marker */
726 read_dcb_i2c_entry(struct drm_device
*dev
, int dcb_version
, uint8_t *i2ctable
, int index
, struct dcb_i2c_entry
*i2c
)
728 uint8_t dcb_i2c_ver
= dcb_version
, headerlen
= 0, entry_len
= 4;
729 int i2c_entries
= DCB_MAX_NUM_I2C_ENTRIES
;
730 int recordoffset
= 0, rdofs
= 1, wrofs
= 0;
731 uint8_t port_type
= 0;
736 if (dcb_version
>= 0x30) {
737 if (i2ctable
[0] != dcb_version
) /* necessary? */
739 "DCB I2C table version mismatch (%02X vs %02X)\n",
740 i2ctable
[0], dcb_version
);
741 dcb_i2c_ver
= i2ctable
[0];
742 headerlen
= i2ctable
[1];
743 if (i2ctable
[2] <= DCB_MAX_NUM_I2C_ENTRIES
)
744 i2c_entries
= i2ctable
[2];
747 "DCB I2C table has more entries than indexable "
748 "(%d entries, max %d)\n", i2ctable
[2],
749 DCB_MAX_NUM_I2C_ENTRIES
);
750 entry_len
= i2ctable
[3];
751 /* [4] is i2c_default_indices, read in parse_dcb_table() */
754 * It's your own fault if you call this function on a DCB 1.1 BIOS --
755 * the test below is for DCB 1.2
757 if (dcb_version
< 0x14) {
765 if (index
>= i2c_entries
) {
766 NV_ERROR(dev
, "DCB I2C index too big (%d >= %d)\n",
770 if (i2ctable
[headerlen
+ entry_len
* index
+ 3] == 0xff) {
771 NV_ERROR(dev
, "DCB I2C entry invalid\n");
775 if (dcb_i2c_ver
>= 0x30) {
776 port_type
= i2ctable
[headerlen
+ recordoffset
+ 3 + entry_len
* index
];
779 * Fixup for chips using same address offset for read and
782 if (port_type
== 4) /* seen on C51 */
784 if (port_type
>= 5) /* G80+ */
788 if (dcb_i2c_ver
>= 0x40) {
789 if (port_type
!= 5 && port_type
!= 6)
790 NV_WARN(dev
, "DCB I2C table has port type %d\n", port_type
);
792 i2c
->entry
= ROM32(i2ctable
[headerlen
+ recordoffset
+ entry_len
* index
]);
795 i2c
->port_type
= port_type
;
796 i2c
->read
= i2ctable
[headerlen
+ recordoffset
+ rdofs
+ entry_len
* index
];
797 i2c
->write
= i2ctable
[headerlen
+ recordoffset
+ wrofs
+ entry_len
* index
];
802 static struct nouveau_i2c_chan
*
803 init_i2c_device_find(struct drm_device
*dev
, int i2c_index
)
805 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
806 struct dcb_table
*dcb
= &dev_priv
->vbios
.dcb
;
808 if (i2c_index
== 0xff) {
809 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
810 int idx
= dcb_entry_idx_from_crtchead(dev
), shift
= 0;
811 int default_indices
= dcb
->i2c_default_indices
;
813 if (idx
!= 0x7f && dcb
->entry
[idx
].i2c_upper_default
)
816 i2c_index
= (default_indices
>> shift
) & 0xf;
818 if (i2c_index
== 0x80) /* g80+ */
819 i2c_index
= dcb
->i2c_default_indices
& 0xf;
821 if (i2c_index
== 0x81)
822 i2c_index
= (dcb
->i2c_default_indices
& 0xf0) >> 4;
824 if (i2c_index
>= DCB_MAX_NUM_I2C_ENTRIES
) {
825 NV_ERROR(dev
, "invalid i2c_index 0x%x\n", i2c_index
);
829 /* Make sure i2c table entry has been parsed, it may not
830 * have been if this is a bus not referenced by a DCB encoder
832 read_dcb_i2c_entry(dev
, dcb
->version
, dcb
->i2c_table
,
833 i2c_index
, &dcb
->i2c
[i2c_index
]);
835 return nouveau_i2c_find(dev
, i2c_index
);
839 get_tmds_index_reg(struct drm_device
*dev
, uint8_t mlv
)
842 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
843 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
844 * CR58 for CR57 = 0 to index a table of offsets to the basic
846 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
847 * CR58 for CR57 = 0 to index a table of offsets to the basic
848 * 0x6808b0 address, and then flip the offset by 8.
851 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
852 struct nvbios
*bios
= &dev_priv
->vbios
;
853 const int pramdac_offset
[13] = {
854 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
855 const uint32_t pramdac_table
[4] = {
856 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
859 int dcb_entry
, dacoffset
;
861 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
862 dcb_entry
= dcb_entry_idx_from_crtchead(dev
);
863 if (dcb_entry
== 0x7f)
865 dacoffset
= pramdac_offset
[bios
->dcb
.entry
[dcb_entry
].or];
868 return 0x6808b0 + dacoffset
;
870 if (mlv
>= ARRAY_SIZE(pramdac_table
)) {
871 NV_ERROR(dev
, "Magic Lookup Value too big (%02X)\n",
875 return pramdac_table
[mlv
];
880 init_io_restrict_prog(struct nvbios
*bios
, uint16_t offset
,
881 struct init_exec
*iexec
)
884 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
886 * offset (8 bit): opcode
887 * offset + 1 (16 bit): CRTC port
888 * offset + 3 (8 bit): CRTC index
889 * offset + 4 (8 bit): mask
890 * offset + 5 (8 bit): shift
891 * offset + 6 (8 bit): count
892 * offset + 7 (32 bit): register
893 * offset + 11 (32 bit): configuration 1
896 * Starting at offset + 11 there are "count" 32 bit values.
897 * To find out which value to use read index "CRTC index" on "CRTC
898 * port", AND this value with "mask" and then bit shift right "shift"
899 * bits. Read the appropriate value using this index and write to
903 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
904 uint8_t crtcindex
= bios
->data
[offset
+ 3];
905 uint8_t mask
= bios
->data
[offset
+ 4];
906 uint8_t shift
= bios
->data
[offset
+ 5];
907 uint8_t count
= bios
->data
[offset
+ 6];
908 uint32_t reg
= ROM32(bios
->data
[offset
+ 7]);
911 int len
= 11 + count
* 4;
916 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
917 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
918 offset
, crtcport
, crtcindex
, mask
, shift
, count
, reg
);
920 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
921 if (config
> count
) {
923 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
924 offset
, config
, count
);
928 configval
= ROM32(bios
->data
[offset
+ 11 + config
* 4]);
930 BIOSLOG(bios
, "0x%04X: Writing config %02X\n", offset
, config
);
932 bios_wr32(bios
, reg
, configval
);
938 init_repeat(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
941 * INIT_REPEAT opcode: 0x33 ('3')
943 * offset (8 bit): opcode
944 * offset + 1 (8 bit): count
946 * Execute script following this opcode up to INIT_REPEAT_END
950 uint8_t count
= bios
->data
[offset
+ 1];
953 /* no iexec->execute check by design */
955 BIOSLOG(bios
, "0x%04X: Repeating following segment %d times\n",
958 iexec
->repeat
= true;
961 * count - 1, as the script block will execute once when we leave this
962 * opcode -- this is compatible with bios behaviour as:
963 * a) the block is always executed at least once, even if count == 0
964 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
967 for (i
= 0; i
< count
- 1; i
++)
968 parse_init_table(bios
, offset
+ 2, iexec
);
970 iexec
->repeat
= false;
976 init_io_restrict_pll(struct nvbios
*bios
, uint16_t offset
,
977 struct init_exec
*iexec
)
980 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
982 * offset (8 bit): opcode
983 * offset + 1 (16 bit): CRTC port
984 * offset + 3 (8 bit): CRTC index
985 * offset + 4 (8 bit): mask
986 * offset + 5 (8 bit): shift
987 * offset + 6 (8 bit): IO flag condition index
988 * offset + 7 (8 bit): count
989 * offset + 8 (32 bit): register
990 * offset + 12 (16 bit): frequency 1
993 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
994 * Set PLL register "register" to coefficients for frequency n,
995 * selected by reading index "CRTC index" of "CRTC port" ANDed with
996 * "mask" and shifted right by "shift".
998 * If "IO flag condition index" > 0, and condition met, double
999 * frequency before setting it.
1002 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
1003 uint8_t crtcindex
= bios
->data
[offset
+ 3];
1004 uint8_t mask
= bios
->data
[offset
+ 4];
1005 uint8_t shift
= bios
->data
[offset
+ 5];
1006 int8_t io_flag_condition_idx
= bios
->data
[offset
+ 6];
1007 uint8_t count
= bios
->data
[offset
+ 7];
1008 uint32_t reg
= ROM32(bios
->data
[offset
+ 8]);
1011 int len
= 12 + count
* 2;
1013 if (!iexec
->execute
)
1016 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1017 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1018 "Count: 0x%02X, Reg: 0x%08X\n",
1019 offset
, crtcport
, crtcindex
, mask
, shift
,
1020 io_flag_condition_idx
, count
, reg
);
1022 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
1023 if (config
> count
) {
1025 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1026 offset
, config
, count
);
1030 freq
= ROM16(bios
->data
[offset
+ 12 + config
* 2]);
1032 if (io_flag_condition_idx
> 0) {
1033 if (io_flag_condition_met(bios
, offset
, io_flag_condition_idx
)) {
1034 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- "
1035 "frequency doubled\n", offset
);
1038 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- "
1039 "frequency unchanged\n", offset
);
1042 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1043 offset
, reg
, config
, freq
);
1045 setPLL(bios
, reg
, freq
* 10);
1051 init_end_repeat(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1054 * INIT_END_REPEAT opcode: 0x36 ('6')
1056 * offset (8 bit): opcode
1058 * Marks the end of the block for INIT_REPEAT to repeat
1061 /* no iexec->execute check by design */
1064 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1065 * we're not in repeat mode
1074 init_copy(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1077 * INIT_COPY opcode: 0x37 ('7')
1079 * offset (8 bit): opcode
1080 * offset + 1 (32 bit): register
1081 * offset + 5 (8 bit): shift
1082 * offset + 6 (8 bit): srcmask
1083 * offset + 7 (16 bit): CRTC port
1084 * offset + 9 (8 bit): CRTC index
1085 * offset + 10 (8 bit): mask
1087 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1088 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1092 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1093 uint8_t shift
= bios
->data
[offset
+ 5];
1094 uint8_t srcmask
= bios
->data
[offset
+ 6];
1095 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 7]);
1096 uint8_t crtcindex
= bios
->data
[offset
+ 9];
1097 uint8_t mask
= bios
->data
[offset
+ 10];
1101 if (!iexec
->execute
)
1104 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1105 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1106 offset
, reg
, shift
, srcmask
, crtcport
, crtcindex
, mask
);
1108 data
= bios_rd32(bios
, reg
);
1113 data
<<= (0x100 - shift
);
1117 crtcdata
= bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
;
1118 crtcdata
|= (uint8_t)data
;
1119 bios_idxprt_wr(bios
, crtcport
, crtcindex
, crtcdata
);
1125 init_not(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1128 * INIT_NOT opcode: 0x38 ('8')
1130 * offset (8 bit): opcode
1132 * Invert the current execute / no-execute condition (i.e. "else")
1135 BIOSLOG(bios
, "0x%04X: ------ Skipping following commands ------\n", offset
);
1137 BIOSLOG(bios
, "0x%04X: ------ Executing following commands ------\n", offset
);
1139 iexec
->execute
= !iexec
->execute
;
1144 init_io_flag_condition(struct nvbios
*bios
, uint16_t offset
,
1145 struct init_exec
*iexec
)
1148 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1150 * offset (8 bit): opcode
1151 * offset + 1 (8 bit): condition number
1153 * Check condition "condition number" in the IO flag condition table.
1154 * If condition not met skip subsequent opcodes until condition is
1155 * inverted (INIT_NOT), or we hit INIT_RESUME
1158 uint8_t cond
= bios
->data
[offset
+ 1];
1160 if (!iexec
->execute
)
1163 if (io_flag_condition_met(bios
, offset
, cond
))
1164 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
1166 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
1167 iexec
->execute
= false;
1174 init_dp_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1177 * INIT_DP_CONDITION opcode: 0x3A ('')
1179 * offset (8 bit): opcode
1180 * offset + 1 (8 bit): "sub" opcode
1181 * offset + 2 (8 bit): unknown
1185 struct bit_displayport_encoder_table
*dpe
= NULL
;
1186 struct dcb_entry
*dcb
= bios
->display
.output
;
1187 struct drm_device
*dev
= bios
->dev
;
1188 uint8_t cond
= bios
->data
[offset
+ 1];
1191 BIOSLOG(bios
, "0x%04X: subop 0x%02X\n", offset
, cond
);
1193 if (!iexec
->execute
)
1196 dpe
= nouveau_bios_dp_table(dev
, dcb
, &dummy
);
1198 NV_ERROR(dev
, "0x%04X: INIT_3A: no encoder table!!\n", offset
);
1205 struct dcb_connector_table_entry
*ent
=
1206 &bios
->dcb
.connector
.entry
[dcb
->connector
];
1208 if (ent
->type
!= DCB_CONNECTOR_eDP
)
1209 iexec
->execute
= false;
1214 if (!(dpe
->unknown
& cond
))
1215 iexec
->execute
= false;
1219 struct nouveau_i2c_chan
*auxch
;
1222 auxch
= nouveau_i2c_find(dev
, bios
->display
.output
->i2c_index
);
1224 NV_ERROR(dev
, "0x%04X: couldn't get auxch\n", offset
);
1228 ret
= nouveau_dp_auxch(auxch
, 9, 0xd, &cond
, 1);
1230 NV_ERROR(dev
, "0x%04X: auxch rd fail: %d\n", offset
, ret
);
1235 iexec
->execute
= false;
1239 NV_WARN(dev
, "0x%04X: unknown INIT_3A op: %d\n", offset
, cond
);
1244 BIOSLOG(bios
, "0x%04X: continuing to execute\n", offset
);
1246 BIOSLOG(bios
, "0x%04X: skipping following commands\n", offset
);
1252 init_op_3b(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1255 * INIT_3B opcode: 0x3B ('')
1257 * offset (8 bit): opcode
1258 * offset + 1 (8 bit): crtc index
1262 uint8_t or = ffs(bios
->display
.output
->or) - 1;
1263 uint8_t index
= bios
->data
[offset
+ 1];
1266 if (!iexec
->execute
)
1269 data
= bios_idxprt_rd(bios
, 0x3d4, index
);
1270 bios_idxprt_wr(bios
, 0x3d4, index
, data
& ~(1 << or));
1275 init_op_3c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1278 * INIT_3C opcode: 0x3C ('')
1280 * offset (8 bit): opcode
1281 * offset + 1 (8 bit): crtc index
1285 uint8_t or = ffs(bios
->display
.output
->or) - 1;
1286 uint8_t index
= bios
->data
[offset
+ 1];
1289 if (!iexec
->execute
)
1292 data
= bios_idxprt_rd(bios
, 0x3d4, index
);
1293 bios_idxprt_wr(bios
, 0x3d4, index
, data
| (1 << or));
1298 init_idx_addr_latched(struct nvbios
*bios
, uint16_t offset
,
1299 struct init_exec
*iexec
)
1302 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1304 * offset (8 bit): opcode
1305 * offset + 1 (32 bit): control register
1306 * offset + 5 (32 bit): data register
1307 * offset + 9 (32 bit): mask
1308 * offset + 13 (32 bit): data
1309 * offset + 17 (8 bit): count
1310 * offset + 18 (8 bit): address 1
1311 * offset + 19 (8 bit): data 1
1314 * For each of "count" address and data pairs, write "data n" to
1315 * "data register", read the current value of "control register",
1316 * and write it back once ANDed with "mask", ORed with "data",
1317 * and ORed with "address n"
1320 uint32_t controlreg
= ROM32(bios
->data
[offset
+ 1]);
1321 uint32_t datareg
= ROM32(bios
->data
[offset
+ 5]);
1322 uint32_t mask
= ROM32(bios
->data
[offset
+ 9]);
1323 uint32_t data
= ROM32(bios
->data
[offset
+ 13]);
1324 uint8_t count
= bios
->data
[offset
+ 17];
1325 int len
= 18 + count
* 2;
1329 if (!iexec
->execute
)
1332 BIOSLOG(bios
, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1333 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1334 offset
, controlreg
, datareg
, mask
, data
, count
);
1336 for (i
= 0; i
< count
; i
++) {
1337 uint8_t instaddress
= bios
->data
[offset
+ 18 + i
* 2];
1338 uint8_t instdata
= bios
->data
[offset
+ 19 + i
* 2];
1340 BIOSLOG(bios
, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1341 offset
, instaddress
, instdata
);
1343 bios_wr32(bios
, datareg
, instdata
);
1344 value
= bios_rd32(bios
, controlreg
) & mask
;
1346 value
|= instaddress
;
1347 bios_wr32(bios
, controlreg
, value
);
1354 init_io_restrict_pll2(struct nvbios
*bios
, uint16_t offset
,
1355 struct init_exec
*iexec
)
1358 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1360 * offset (8 bit): opcode
1361 * offset + 1 (16 bit): CRTC port
1362 * offset + 3 (8 bit): CRTC index
1363 * offset + 4 (8 bit): mask
1364 * offset + 5 (8 bit): shift
1365 * offset + 6 (8 bit): count
1366 * offset + 7 (32 bit): register
1367 * offset + 11 (32 bit): frequency 1
1370 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1371 * Set PLL register "register" to coefficients for frequency n,
1372 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1373 * "mask" and shifted right by "shift".
1376 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
1377 uint8_t crtcindex
= bios
->data
[offset
+ 3];
1378 uint8_t mask
= bios
->data
[offset
+ 4];
1379 uint8_t shift
= bios
->data
[offset
+ 5];
1380 uint8_t count
= bios
->data
[offset
+ 6];
1381 uint32_t reg
= ROM32(bios
->data
[offset
+ 7]);
1382 int len
= 11 + count
* 4;
1386 if (!iexec
->execute
)
1389 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1390 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1391 offset
, crtcport
, crtcindex
, mask
, shift
, count
, reg
);
1396 config
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) >> shift
;
1397 if (config
> count
) {
1399 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1400 offset
, config
, count
);
1404 freq
= ROM32(bios
->data
[offset
+ 11 + config
* 4]);
1406 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1407 offset
, reg
, config
, freq
);
1409 setPLL(bios
, reg
, freq
);
1415 init_pll2(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1418 * INIT_PLL2 opcode: 0x4B ('K')
1420 * offset (8 bit): opcode
1421 * offset + 1 (32 bit): register
1422 * offset + 5 (32 bit): freq
1424 * Set PLL register "register" to coefficients for frequency "freq"
1427 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
1428 uint32_t freq
= ROM32(bios
->data
[offset
+ 5]);
1430 if (!iexec
->execute
)
1433 BIOSLOG(bios
, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1436 setPLL(bios
, reg
, freq
);
1441 init_i2c_byte(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1444 * INIT_I2C_BYTE opcode: 0x4C ('L')
1446 * offset (8 bit): opcode
1447 * offset + 1 (8 bit): DCB I2C table entry index
1448 * offset + 2 (8 bit): I2C slave address
1449 * offset + 3 (8 bit): count
1450 * offset + 4 (8 bit): I2C register 1
1451 * offset + 5 (8 bit): mask 1
1452 * offset + 6 (8 bit): data 1
1455 * For each of "count" registers given by "I2C register n" on the device
1456 * addressed by "I2C slave address" on the I2C bus given by
1457 * "DCB I2C table entry index", read the register, AND the result with
1458 * "mask n" and OR it with "data n" before writing it back to the device
1461 struct drm_device
*dev
= bios
->dev
;
1462 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1463 uint8_t i2c_address
= bios
->data
[offset
+ 2] >> 1;
1464 uint8_t count
= bios
->data
[offset
+ 3];
1465 struct nouveau_i2c_chan
*chan
;
1466 int len
= 4 + count
* 3;
1469 if (!iexec
->execute
)
1472 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1474 offset
, i2c_index
, i2c_address
, count
);
1476 chan
= init_i2c_device_find(dev
, i2c_index
);
1478 NV_ERROR(dev
, "0x%04X: i2c bus not found\n", offset
);
1482 for (i
= 0; i
< count
; i
++) {
1483 uint8_t reg
= bios
->data
[offset
+ 4 + i
* 3];
1484 uint8_t mask
= bios
->data
[offset
+ 5 + i
* 3];
1485 uint8_t data
= bios
->data
[offset
+ 6 + i
* 3];
1486 union i2c_smbus_data val
;
1488 ret
= i2c_smbus_xfer(&chan
->adapter
, i2c_address
, 0,
1489 I2C_SMBUS_READ
, reg
,
1490 I2C_SMBUS_BYTE_DATA
, &val
);
1492 NV_ERROR(dev
, "0x%04X: i2c rd fail: %d\n", offset
, ret
);
1496 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1497 "Mask: 0x%02X, Data: 0x%02X\n",
1498 offset
, reg
, val
.byte
, mask
, data
);
1505 ret
= i2c_smbus_xfer(&chan
->adapter
, i2c_address
, 0,
1506 I2C_SMBUS_WRITE
, reg
,
1507 I2C_SMBUS_BYTE_DATA
, &val
);
1509 NV_ERROR(dev
, "0x%04X: i2c wr fail: %d\n", offset
, ret
);
1518 init_zm_i2c_byte(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1521 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1523 * offset (8 bit): opcode
1524 * offset + 1 (8 bit): DCB I2C table entry index
1525 * offset + 2 (8 bit): I2C slave address
1526 * offset + 3 (8 bit): count
1527 * offset + 4 (8 bit): I2C register 1
1528 * offset + 5 (8 bit): data 1
1531 * For each of "count" registers given by "I2C register n" on the device
1532 * addressed by "I2C slave address" on the I2C bus given by
1533 * "DCB I2C table entry index", set the register to "data n"
1536 struct drm_device
*dev
= bios
->dev
;
1537 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1538 uint8_t i2c_address
= bios
->data
[offset
+ 2] >> 1;
1539 uint8_t count
= bios
->data
[offset
+ 3];
1540 struct nouveau_i2c_chan
*chan
;
1541 int len
= 4 + count
* 2;
1544 if (!iexec
->execute
)
1547 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1549 offset
, i2c_index
, i2c_address
, count
);
1551 chan
= init_i2c_device_find(dev
, i2c_index
);
1553 NV_ERROR(dev
, "0x%04X: i2c bus not found\n", offset
);
1557 for (i
= 0; i
< count
; i
++) {
1558 uint8_t reg
= bios
->data
[offset
+ 4 + i
* 2];
1559 union i2c_smbus_data val
;
1561 val
.byte
= bios
->data
[offset
+ 5 + i
* 2];
1563 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
1564 offset
, reg
, val
.byte
);
1569 ret
= i2c_smbus_xfer(&chan
->adapter
, i2c_address
, 0,
1570 I2C_SMBUS_WRITE
, reg
,
1571 I2C_SMBUS_BYTE_DATA
, &val
);
1573 NV_ERROR(dev
, "0x%04X: i2c wr fail: %d\n", offset
, ret
);
1582 init_zm_i2c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1585 * INIT_ZM_I2C opcode: 0x4E ('N')
1587 * offset (8 bit): opcode
1588 * offset + 1 (8 bit): DCB I2C table entry index
1589 * offset + 2 (8 bit): I2C slave address
1590 * offset + 3 (8 bit): count
1591 * offset + 4 (8 bit): data 1
1594 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1595 * address" on the I2C bus given by "DCB I2C table entry index"
1598 struct drm_device
*dev
= bios
->dev
;
1599 uint8_t i2c_index
= bios
->data
[offset
+ 1];
1600 uint8_t i2c_address
= bios
->data
[offset
+ 2] >> 1;
1601 uint8_t count
= bios
->data
[offset
+ 3];
1602 int len
= 4 + count
;
1603 struct nouveau_i2c_chan
*chan
;
1608 if (!iexec
->execute
)
1611 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1613 offset
, i2c_index
, i2c_address
, count
);
1615 chan
= init_i2c_device_find(dev
, i2c_index
);
1617 NV_ERROR(dev
, "0x%04X: i2c bus not found\n", offset
);
1621 for (i
= 0; i
< count
; i
++) {
1622 data
[i
] = bios
->data
[offset
+ 4 + i
];
1624 BIOSLOG(bios
, "0x%04X: Data: 0x%02X\n", offset
, data
[i
]);
1627 if (bios
->execute
) {
1628 msg
.addr
= i2c_address
;
1632 ret
= i2c_transfer(&chan
->adapter
, &msg
, 1);
1634 NV_ERROR(dev
, "0x%04X: i2c wr fail: %d\n", offset
, ret
);
1643 init_tmds(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1646 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1648 * offset (8 bit): opcode
1649 * offset + 1 (8 bit): magic lookup value
1650 * offset + 2 (8 bit): TMDS address
1651 * offset + 3 (8 bit): mask
1652 * offset + 4 (8 bit): data
1654 * Read the data reg for TMDS address "TMDS address", AND it with mask
1655 * and OR it with data, then write it back
1656 * "magic lookup value" determines which TMDS base address register is
1657 * used -- see get_tmds_index_reg()
1660 struct drm_device
*dev
= bios
->dev
;
1661 uint8_t mlv
= bios
->data
[offset
+ 1];
1662 uint32_t tmdsaddr
= bios
->data
[offset
+ 2];
1663 uint8_t mask
= bios
->data
[offset
+ 3];
1664 uint8_t data
= bios
->data
[offset
+ 4];
1665 uint32_t reg
, value
;
1667 if (!iexec
->execute
)
1670 BIOSLOG(bios
, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1671 "Mask: 0x%02X, Data: 0x%02X\n",
1672 offset
, mlv
, tmdsaddr
, mask
, data
);
1674 reg
= get_tmds_index_reg(bios
->dev
, mlv
);
1676 NV_ERROR(dev
, "0x%04X: no tmds_index_reg\n", offset
);
1680 bios_wr32(bios
, reg
,
1681 tmdsaddr
| NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE
);
1682 value
= (bios_rd32(bios
, reg
+ 4) & mask
) | data
;
1683 bios_wr32(bios
, reg
+ 4, value
);
1684 bios_wr32(bios
, reg
, tmdsaddr
);
1690 init_zm_tmds_group(struct nvbios
*bios
, uint16_t offset
,
1691 struct init_exec
*iexec
)
1694 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1696 * offset (8 bit): opcode
1697 * offset + 1 (8 bit): magic lookup value
1698 * offset + 2 (8 bit): count
1699 * offset + 3 (8 bit): addr 1
1700 * offset + 4 (8 bit): data 1
1703 * For each of "count" TMDS address and data pairs write "data n" to
1704 * "addr n". "magic lookup value" determines which TMDS base address
1705 * register is used -- see get_tmds_index_reg()
1708 struct drm_device
*dev
= bios
->dev
;
1709 uint8_t mlv
= bios
->data
[offset
+ 1];
1710 uint8_t count
= bios
->data
[offset
+ 2];
1711 int len
= 3 + count
* 2;
1715 if (!iexec
->execute
)
1718 BIOSLOG(bios
, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1719 offset
, mlv
, count
);
1721 reg
= get_tmds_index_reg(bios
->dev
, mlv
);
1723 NV_ERROR(dev
, "0x%04X: no tmds_index_reg\n", offset
);
1727 for (i
= 0; i
< count
; i
++) {
1728 uint8_t tmdsaddr
= bios
->data
[offset
+ 3 + i
* 2];
1729 uint8_t tmdsdata
= bios
->data
[offset
+ 4 + i
* 2];
1731 bios_wr32(bios
, reg
+ 4, tmdsdata
);
1732 bios_wr32(bios
, reg
, tmdsaddr
);
1739 init_cr_idx_adr_latch(struct nvbios
*bios
, uint16_t offset
,
1740 struct init_exec
*iexec
)
1743 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1745 * offset (8 bit): opcode
1746 * offset + 1 (8 bit): CRTC index1
1747 * offset + 2 (8 bit): CRTC index2
1748 * offset + 3 (8 bit): baseaddr
1749 * offset + 4 (8 bit): count
1750 * offset + 5 (8 bit): data 1
1753 * For each of "count" address and data pairs, write "baseaddr + n" to
1754 * "CRTC index1" and "data n" to "CRTC index2"
1755 * Once complete, restore initial value read from "CRTC index1"
1757 uint8_t crtcindex1
= bios
->data
[offset
+ 1];
1758 uint8_t crtcindex2
= bios
->data
[offset
+ 2];
1759 uint8_t baseaddr
= bios
->data
[offset
+ 3];
1760 uint8_t count
= bios
->data
[offset
+ 4];
1761 int len
= 5 + count
;
1762 uint8_t oldaddr
, data
;
1765 if (!iexec
->execute
)
1768 BIOSLOG(bios
, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1769 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1770 offset
, crtcindex1
, crtcindex2
, baseaddr
, count
);
1772 oldaddr
= bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, crtcindex1
);
1774 for (i
= 0; i
< count
; i
++) {
1775 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex1
,
1777 data
= bios
->data
[offset
+ 5 + i
];
1778 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex2
, data
);
1781 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex1
, oldaddr
);
1787 init_cr(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1790 * INIT_CR opcode: 0x52 ('R')
1792 * offset (8 bit): opcode
1793 * offset + 1 (8 bit): CRTC index
1794 * offset + 2 (8 bit): mask
1795 * offset + 3 (8 bit): data
1797 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1798 * data back to "CRTC index"
1801 uint8_t crtcindex
= bios
->data
[offset
+ 1];
1802 uint8_t mask
= bios
->data
[offset
+ 2];
1803 uint8_t data
= bios
->data
[offset
+ 3];
1806 if (!iexec
->execute
)
1809 BIOSLOG(bios
, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1810 offset
, crtcindex
, mask
, data
);
1812 value
= bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, crtcindex
) & mask
;
1814 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex
, value
);
1820 init_zm_cr(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1823 * INIT_ZM_CR opcode: 0x53 ('S')
1825 * offset (8 bit): opcode
1826 * offset + 1 (8 bit): CRTC index
1827 * offset + 2 (8 bit): value
1829 * Assign "value" to CRTC register with index "CRTC index".
1832 uint8_t crtcindex
= ROM32(bios
->data
[offset
+ 1]);
1833 uint8_t data
= bios
->data
[offset
+ 2];
1835 if (!iexec
->execute
)
1838 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, crtcindex
, data
);
1844 init_zm_cr_group(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1847 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1849 * offset (8 bit): opcode
1850 * offset + 1 (8 bit): count
1851 * offset + 2 (8 bit): CRTC index 1
1852 * offset + 3 (8 bit): value 1
1855 * For "count", assign "value n" to CRTC register with index
1859 uint8_t count
= bios
->data
[offset
+ 1];
1860 int len
= 2 + count
* 2;
1863 if (!iexec
->execute
)
1866 for (i
= 0; i
< count
; i
++)
1867 init_zm_cr(bios
, offset
+ 2 + 2 * i
- 1, iexec
);
1873 init_condition_time(struct nvbios
*bios
, uint16_t offset
,
1874 struct init_exec
*iexec
)
1877 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1879 * offset (8 bit): opcode
1880 * offset + 1 (8 bit): condition number
1881 * offset + 2 (8 bit): retries / 50
1883 * Check condition "condition number" in the condition table.
1884 * Bios code then sleeps for 2ms if the condition is not met, and
1885 * repeats up to "retries" times, but on one C51 this has proved
1886 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1887 * this, and bail after "retries" times, or 2s, whichever is less.
1888 * If still not met after retries, clear execution flag for this table.
1891 uint8_t cond
= bios
->data
[offset
+ 1];
1892 uint16_t retries
= bios
->data
[offset
+ 2] * 50;
1895 if (!iexec
->execute
)
1901 BIOSLOG(bios
, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1902 offset
, cond
, retries
);
1904 if (!bios
->execute
) /* avoid 2s delays when "faking" execution */
1907 for (cnt
= 0; cnt
< retries
; cnt
++) {
1908 if (bios_condition_met(bios
, offset
, cond
)) {
1909 BIOSLOG(bios
, "0x%04X: Condition met, continuing\n",
1913 BIOSLOG(bios
, "0x%04X: "
1914 "Condition not met, sleeping for 20ms\n",
1920 if (!bios_condition_met(bios
, offset
, cond
)) {
1922 "0x%04X: Condition still not met after %dms, "
1923 "skipping following opcodes\n", offset
, 20 * retries
);
1924 iexec
->execute
= false;
1931 init_ltime(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1934 * INIT_LTIME opcode: 0x57 ('V')
1936 * offset (8 bit): opcode
1937 * offset + 1 (16 bit): time
1939 * Sleep for "time" miliseconds.
1942 unsigned time
= ROM16(bios
->data
[offset
+ 1]);
1944 if (!iexec
->execute
)
1947 BIOSLOG(bios
, "0x%04X: Sleeping for 0x%04X miliseconds\n",
1956 init_zm_reg_sequence(struct nvbios
*bios
, uint16_t offset
,
1957 struct init_exec
*iexec
)
1960 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1962 * offset (8 bit): opcode
1963 * offset + 1 (32 bit): base register
1964 * offset + 5 (8 bit): count
1965 * offset + 6 (32 bit): value 1
1968 * Starting at offset + 6 there are "count" 32 bit values.
1969 * For "count" iterations set "base register" + 4 * current_iteration
1970 * to "value current_iteration"
1973 uint32_t basereg
= ROM32(bios
->data
[offset
+ 1]);
1974 uint32_t count
= bios
->data
[offset
+ 5];
1975 int len
= 6 + count
* 4;
1978 if (!iexec
->execute
)
1981 BIOSLOG(bios
, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1982 offset
, basereg
, count
);
1984 for (i
= 0; i
< count
; i
++) {
1985 uint32_t reg
= basereg
+ i
* 4;
1986 uint32_t data
= ROM32(bios
->data
[offset
+ 6 + i
* 4]);
1988 bios_wr32(bios
, reg
, data
);
1995 init_sub_direct(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
1998 * INIT_SUB_DIRECT opcode: 0x5B ('[')
2000 * offset (8 bit): opcode
2001 * offset + 1 (16 bit): subroutine offset (in bios)
2003 * Calls a subroutine that will execute commands until INIT_DONE
2007 uint16_t sub_offset
= ROM16(bios
->data
[offset
+ 1]);
2009 if (!iexec
->execute
)
2012 BIOSLOG(bios
, "0x%04X: Executing subroutine at 0x%04X\n",
2013 offset
, sub_offset
);
2015 parse_init_table(bios
, sub_offset
, iexec
);
2017 BIOSLOG(bios
, "0x%04X: End of 0x%04X subroutine\n", offset
, sub_offset
);
2023 init_i2c_if(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2026 * INIT_I2C_IF opcode: 0x5E ('^')
2028 * offset (8 bit): opcode
2029 * offset + 1 (8 bit): DCB I2C table entry index
2030 * offset + 2 (8 bit): I2C slave address
2031 * offset + 3 (8 bit): I2C register
2032 * offset + 4 (8 bit): mask
2033 * offset + 5 (8 bit): data
2035 * Read the register given by "I2C register" on the device addressed
2036 * by "I2C slave address" on the I2C bus given by "DCB I2C table
2037 * entry index". Compare the result AND "mask" to "data".
2038 * If they're not equal, skip subsequent opcodes until condition is
2039 * inverted (INIT_NOT), or we hit INIT_RESUME
2042 uint8_t i2c_index
= bios
->data
[offset
+ 1];
2043 uint8_t i2c_address
= bios
->data
[offset
+ 2] >> 1;
2044 uint8_t reg
= bios
->data
[offset
+ 3];
2045 uint8_t mask
= bios
->data
[offset
+ 4];
2046 uint8_t data
= bios
->data
[offset
+ 5];
2047 struct nouveau_i2c_chan
*chan
;
2048 union i2c_smbus_data val
;
2051 /* no execute check by design */
2053 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2054 offset
, i2c_index
, i2c_address
);
2056 chan
= init_i2c_device_find(bios
->dev
, i2c_index
);
2060 ret
= i2c_smbus_xfer(&chan
->adapter
, i2c_address
, 0,
2061 I2C_SMBUS_READ
, reg
,
2062 I2C_SMBUS_BYTE_DATA
, &val
);
2064 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2065 "Mask: 0x%02X, Data: 0x%02X\n",
2066 offset
, reg
, mask
, data
);
2071 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2072 "Mask: 0x%02X, Data: 0x%02X\n",
2073 offset
, reg
, val
.byte
, mask
, data
);
2075 iexec
->execute
= ((val
.byte
& mask
) == data
);
2081 init_copy_nv_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2084 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2086 * offset (8 bit): opcode
2087 * offset + 1 (32 bit): src reg
2088 * offset + 5 (8 bit): shift
2089 * offset + 6 (32 bit): src mask
2090 * offset + 10 (32 bit): xor
2091 * offset + 14 (32 bit): dst reg
2092 * offset + 18 (32 bit): dst mask
2094 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2095 * "src mask", then XOR with "xor". Write this OR'd with
2096 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2099 uint32_t srcreg
= *((uint32_t *)(&bios
->data
[offset
+ 1]));
2100 uint8_t shift
= bios
->data
[offset
+ 5];
2101 uint32_t srcmask
= *((uint32_t *)(&bios
->data
[offset
+ 6]));
2102 uint32_t xor = *((uint32_t *)(&bios
->data
[offset
+ 10]));
2103 uint32_t dstreg
= *((uint32_t *)(&bios
->data
[offset
+ 14]));
2104 uint32_t dstmask
= *((uint32_t *)(&bios
->data
[offset
+ 18]));
2105 uint32_t srcvalue
, dstvalue
;
2107 if (!iexec
->execute
)
2110 BIOSLOG(bios
, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2111 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2112 offset
, srcreg
, shift
, srcmask
, xor, dstreg
, dstmask
);
2114 srcvalue
= bios_rd32(bios
, srcreg
);
2119 srcvalue
<<= (0x100 - shift
);
2121 srcvalue
= (srcvalue
& srcmask
) ^ xor;
2123 dstvalue
= bios_rd32(bios
, dstreg
) & dstmask
;
2125 bios_wr32(bios
, dstreg
, dstvalue
| srcvalue
);
2131 init_zm_index_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2134 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2136 * offset (8 bit): opcode
2137 * offset + 1 (16 bit): CRTC port
2138 * offset + 3 (8 bit): CRTC index
2139 * offset + 4 (8 bit): data
2141 * Write "data" to index "CRTC index" of "CRTC port"
2143 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
2144 uint8_t crtcindex
= bios
->data
[offset
+ 3];
2145 uint8_t data
= bios
->data
[offset
+ 4];
2147 if (!iexec
->execute
)
2150 bios_idxprt_wr(bios
, crtcport
, crtcindex
, data
);
2156 bios_md32(struct nvbios
*bios
, uint32_t reg
,
2157 uint32_t mask
, uint32_t val
)
2159 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & ~mask
) | val
);
2163 peek_fb(struct drm_device
*dev
, struct io_mapping
*fb
,
2168 if (off
< pci_resource_len(dev
->pdev
, 1)) {
2169 uint8_t __iomem
*p
=
2170 io_mapping_map_atomic_wc(fb
, off
& PAGE_MASK
, KM_USER0
);
2172 val
= ioread32(p
+ (off
& ~PAGE_MASK
));
2174 io_mapping_unmap_atomic(p
, KM_USER0
);
2181 poke_fb(struct drm_device
*dev
, struct io_mapping
*fb
,
2182 uint32_t off
, uint32_t val
)
2184 if (off
< pci_resource_len(dev
->pdev
, 1)) {
2185 uint8_t __iomem
*p
=
2186 io_mapping_map_atomic_wc(fb
, off
& PAGE_MASK
, KM_USER0
);
2188 iowrite32(val
, p
+ (off
& ~PAGE_MASK
));
2191 io_mapping_unmap_atomic(p
, KM_USER0
);
2196 read_back_fb(struct drm_device
*dev
, struct io_mapping
*fb
,
2197 uint32_t off
, uint32_t val
)
2199 poke_fb(dev
, fb
, off
, val
);
2200 return val
== peek_fb(dev
, fb
, off
);
2204 nv04_init_compute_mem(struct nvbios
*bios
)
2206 struct drm_device
*dev
= bios
->dev
;
2207 uint32_t patt
= 0xdeadbeef;
2208 struct io_mapping
*fb
;
2211 /* Map the framebuffer aperture */
2212 fb
= io_mapping_create_wc(pci_resource_start(dev
->pdev
, 1),
2213 pci_resource_len(dev
->pdev
, 1));
2217 /* Sequencer and refresh off */
2218 NVWriteVgaSeq(dev
, 0, 1, NVReadVgaSeq(dev
, 0, 1) | 0x20);
2219 bios_md32(bios
, NV04_PFB_DEBUG_0
, 0, NV04_PFB_DEBUG_0_REFRESH_OFF
);
2221 bios_md32(bios
, NV04_PFB_BOOT_0
, ~0,
2222 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB
|
2223 NV04_PFB_BOOT_0_RAM_WIDTH_128
|
2224 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT
);
2226 for (i
= 0; i
< 4; i
++)
2227 poke_fb(dev
, fb
, 4 * i
, patt
);
2229 poke_fb(dev
, fb
, 0x400000, patt
+ 1);
2231 if (peek_fb(dev
, fb
, 0) == patt
+ 1) {
2232 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_TYPE
,
2233 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT
);
2234 bios_md32(bios
, NV04_PFB_DEBUG_0
,
2235 NV04_PFB_DEBUG_0_REFRESH_OFF
, 0);
2237 for (i
= 0; i
< 4; i
++)
2238 poke_fb(dev
, fb
, 4 * i
, patt
);
2240 if ((peek_fb(dev
, fb
, 0xc) & 0xffff) != (patt
& 0xffff))
2241 bios_md32(bios
, NV04_PFB_BOOT_0
,
2242 NV04_PFB_BOOT_0_RAM_WIDTH_128
|
2243 NV04_PFB_BOOT_0_RAM_AMOUNT
,
2244 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
);
2246 } else if ((peek_fb(dev
, fb
, 0xc) & 0xffff0000) !=
2247 (patt
& 0xffff0000)) {
2248 bios_md32(bios
, NV04_PFB_BOOT_0
,
2249 NV04_PFB_BOOT_0_RAM_WIDTH_128
|
2250 NV04_PFB_BOOT_0_RAM_AMOUNT
,
2251 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB
);
2253 } else if (peek_fb(dev
, fb
, 0) != patt
) {
2254 if (read_back_fb(dev
, fb
, 0x800000, patt
))
2255 bios_md32(bios
, NV04_PFB_BOOT_0
,
2256 NV04_PFB_BOOT_0_RAM_AMOUNT
,
2257 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
);
2259 bios_md32(bios
, NV04_PFB_BOOT_0
,
2260 NV04_PFB_BOOT_0_RAM_AMOUNT
,
2261 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB
);
2263 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_TYPE
,
2264 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT
);
2266 } else if (!read_back_fb(dev
, fb
, 0x800000, patt
)) {
2267 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_AMOUNT
,
2268 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
);
2272 /* Refresh on, sequencer on */
2273 bios_md32(bios
, NV04_PFB_DEBUG_0
, NV04_PFB_DEBUG_0_REFRESH_OFF
, 0);
2274 NVWriteVgaSeq(dev
, 0, 1, NVReadVgaSeq(dev
, 0, 1) & ~0x20);
2276 io_mapping_free(fb
);
2280 static const uint8_t *
2281 nv05_memory_config(struct nvbios
*bios
)
2283 /* Defaults for BIOSes lacking a memory config table */
2284 static const uint8_t default_config_tab
[][2] = {
2294 int i
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) &
2295 NV_PEXTDEV_BOOT_0_RAMCFG
) >> 2;
2297 if (bios
->legacy
.mem_init_tbl_ptr
)
2298 return &bios
->data
[bios
->legacy
.mem_init_tbl_ptr
+ 2 * i
];
2300 return default_config_tab
[i
];
2304 nv05_init_compute_mem(struct nvbios
*bios
)
2306 struct drm_device
*dev
= bios
->dev
;
2307 const uint8_t *ramcfg
= nv05_memory_config(bios
);
2308 uint32_t patt
= 0xdeadbeef;
2309 struct io_mapping
*fb
;
2312 /* Map the framebuffer aperture */
2313 fb
= io_mapping_create_wc(pci_resource_start(dev
->pdev
, 1),
2314 pci_resource_len(dev
->pdev
, 1));
2319 NVWriteVgaSeq(dev
, 0, 1, NVReadVgaSeq(dev
, 0, 1) | 0x20);
2321 if (bios_rd32(bios
, NV04_PFB_BOOT_0
) & NV04_PFB_BOOT_0_UMA_ENABLE
)
2324 bios_md32(bios
, NV04_PFB_DEBUG_0
, NV04_PFB_DEBUG_0_REFRESH_OFF
, 0);
2326 /* If present load the hardcoded scrambling table */
2327 if (bios
->legacy
.mem_init_tbl_ptr
) {
2328 uint32_t *scramble_tab
= (uint32_t *)&bios
->data
[
2329 bios
->legacy
.mem_init_tbl_ptr
+ 0x10];
2331 for (i
= 0; i
< 8; i
++)
2332 bios_wr32(bios
, NV04_PFB_SCRAMBLE(i
),
2333 ROM32(scramble_tab
[i
]));
2336 /* Set memory type/width/length defaults depending on the straps */
2337 bios_md32(bios
, NV04_PFB_BOOT_0
, 0x3f, ramcfg
[0]);
2339 if (ramcfg
[1] & 0x80)
2340 bios_md32(bios
, NV04_PFB_CFG0
, 0, NV04_PFB_CFG0_SCRAMBLE
);
2342 bios_md32(bios
, NV04_PFB_CFG1
, 0x700001, (ramcfg
[1] & 1) << 20);
2343 bios_md32(bios
, NV04_PFB_CFG1
, 0, 1);
2345 /* Probe memory bus width */
2346 for (i
= 0; i
< 4; i
++)
2347 poke_fb(dev
, fb
, 4 * i
, patt
);
2349 if (peek_fb(dev
, fb
, 0xc) != patt
)
2350 bios_md32(bios
, NV04_PFB_BOOT_0
,
2351 NV04_PFB_BOOT_0_RAM_WIDTH_128
, 0);
2353 /* Probe memory length */
2354 v
= bios_rd32(bios
, NV04_PFB_BOOT_0
) & NV04_PFB_BOOT_0_RAM_AMOUNT
;
2356 if (v
== NV04_PFB_BOOT_0_RAM_AMOUNT_32MB
&&
2357 (!read_back_fb(dev
, fb
, 0x1000000, ++patt
) ||
2358 !read_back_fb(dev
, fb
, 0, ++patt
)))
2359 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_AMOUNT
,
2360 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB
);
2362 if (v
== NV04_PFB_BOOT_0_RAM_AMOUNT_16MB
&&
2363 !read_back_fb(dev
, fb
, 0x800000, ++patt
))
2364 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_AMOUNT
,
2365 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB
);
2367 if (!read_back_fb(dev
, fb
, 0x400000, ++patt
))
2368 bios_md32(bios
, NV04_PFB_BOOT_0
, NV04_PFB_BOOT_0_RAM_AMOUNT
,
2369 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB
);
2373 NVWriteVgaSeq(dev
, 0, 1, NVReadVgaSeq(dev
, 0, 1) & ~0x20);
2375 io_mapping_free(fb
);
2380 nv10_init_compute_mem(struct nvbios
*bios
)
2382 struct drm_device
*dev
= bios
->dev
;
2383 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2384 const int mem_width
[] = { 0x10, 0x00, 0x20 };
2385 const int mem_width_count
= (dev_priv
->chipset
>= 0x17 ? 3 : 2);
2386 uint32_t patt
= 0xdeadbeef;
2387 struct io_mapping
*fb
;
2390 /* Map the framebuffer aperture */
2391 fb
= io_mapping_create_wc(pci_resource_start(dev
->pdev
, 1),
2392 pci_resource_len(dev
->pdev
, 1));
2396 bios_wr32(bios
, NV10_PFB_REFCTRL
, NV10_PFB_REFCTRL_VALID_1
);
2398 /* Probe memory bus width */
2399 for (i
= 0; i
< mem_width_count
; i
++) {
2400 bios_md32(bios
, NV04_PFB_CFG0
, 0x30, mem_width
[i
]);
2402 for (j
= 0; j
< 4; j
++) {
2403 for (k
= 0; k
< 4; k
++)
2404 poke_fb(dev
, fb
, 0x1c, 0);
2406 poke_fb(dev
, fb
, 0x1c, patt
);
2407 poke_fb(dev
, fb
, 0x3c, 0);
2409 if (peek_fb(dev
, fb
, 0x1c) == patt
)
2410 goto mem_width_found
;
2417 /* Probe amount of installed memory */
2418 for (i
= 0; i
< 4; i
++) {
2419 int off
= bios_rd32(bios
, NV04_PFB_FIFO_DATA
) - 0x100000;
2421 poke_fb(dev
, fb
, off
, patt
);
2422 poke_fb(dev
, fb
, 0, 0);
2424 peek_fb(dev
, fb
, 0);
2425 peek_fb(dev
, fb
, 0);
2426 peek_fb(dev
, fb
, 0);
2427 peek_fb(dev
, fb
, 0);
2429 if (peek_fb(dev
, fb
, off
) == patt
)
2433 /* IC missing - disable the upper half memory space. */
2434 bios_md32(bios
, NV04_PFB_CFG0
, 0x1000, 0);
2437 io_mapping_free(fb
);
2442 nv20_init_compute_mem(struct nvbios
*bios
)
2444 struct drm_device
*dev
= bios
->dev
;
2445 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2446 uint32_t mask
= (dev_priv
->chipset
>= 0x25 ? 0x300 : 0x900);
2447 uint32_t amount
, off
;
2448 struct io_mapping
*fb
;
2450 /* Map the framebuffer aperture */
2451 fb
= io_mapping_create_wc(pci_resource_start(dev
->pdev
, 1),
2452 pci_resource_len(dev
->pdev
, 1));
2456 bios_wr32(bios
, NV10_PFB_REFCTRL
, NV10_PFB_REFCTRL_VALID_1
);
2458 /* Allow full addressing */
2459 bios_md32(bios
, NV04_PFB_CFG0
, 0, mask
);
2461 amount
= bios_rd32(bios
, NV04_PFB_FIFO_DATA
);
2462 for (off
= amount
; off
> 0x2000000; off
-= 0x2000000)
2463 poke_fb(dev
, fb
, off
- 4, off
);
2465 amount
= bios_rd32(bios
, NV04_PFB_FIFO_DATA
);
2466 if (amount
!= peek_fb(dev
, fb
, amount
- 4))
2467 /* IC missing - disable the upper half memory space. */
2468 bios_md32(bios
, NV04_PFB_CFG0
, mask
, 0);
2470 io_mapping_free(fb
);
2475 init_compute_mem(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2478 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2480 * offset (8 bit): opcode
2482 * This opcode is meant to set the PFB memory config registers
2483 * appropriately so that we can correctly calculate how much VRAM it
2484 * has (on nv10 and better chipsets the amount of installed VRAM is
2485 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
2487 * The implementation of this opcode in general consists of several
2490 * 1) Determination of memory type and density. Only necessary for
2491 * really old chipsets, the memory type reported by the strap bits
2492 * (0x101000) is assumed to be accurate on nv05 and newer.
2494 * 2) Determination of the memory bus width. Usually done by a cunning
2495 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2496 * seeing whether the written values are read back correctly.
2498 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2501 * 3) Determination of how many of the card's RAM pads have ICs
2502 * attached, usually done by a cunning combination of writes to an
2503 * offset slightly less than the maximum memory reported by
2504 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
2506 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2507 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2508 * card show nothing being done for this opcode. Why is it still listed
2512 /* no iexec->execute check by design */
2514 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2517 if (dev_priv
->chipset
>= 0x40 ||
2518 dev_priv
->chipset
== 0x1a ||
2519 dev_priv
->chipset
== 0x1f)
2521 else if (dev_priv
->chipset
>= 0x20 &&
2522 dev_priv
->chipset
!= 0x34)
2523 ret
= nv20_init_compute_mem(bios
);
2524 else if (dev_priv
->chipset
>= 0x10)
2525 ret
= nv10_init_compute_mem(bios
);
2526 else if (dev_priv
->chipset
>= 0x5)
2527 ret
= nv05_init_compute_mem(bios
);
2529 ret
= nv04_init_compute_mem(bios
);
2538 init_reset(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2541 * INIT_RESET opcode: 0x65 ('e')
2543 * offset (8 bit): opcode
2544 * offset + 1 (32 bit): register
2545 * offset + 5 (32 bit): value1
2546 * offset + 9 (32 bit): value2
2548 * Assign "value1" to "register", then assign "value2" to "register"
2551 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2552 uint32_t value1
= ROM32(bios
->data
[offset
+ 5]);
2553 uint32_t value2
= ROM32(bios
->data
[offset
+ 9]);
2554 uint32_t pci_nv_19
, pci_nv_20
;
2556 /* no iexec->execute check by design */
2558 pci_nv_19
= bios_rd32(bios
, NV_PBUS_PCI_NV_19
);
2559 bios_wr32(bios
, NV_PBUS_PCI_NV_19
, pci_nv_19
& ~0xf00);
2561 bios_wr32(bios
, reg
, value1
);
2565 bios_wr32(bios
, reg
, value2
);
2566 bios_wr32(bios
, NV_PBUS_PCI_NV_19
, pci_nv_19
);
2568 pci_nv_20
= bios_rd32(bios
, NV_PBUS_PCI_NV_20
);
2569 pci_nv_20
&= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED
; /* 0xfffffffe */
2570 bios_wr32(bios
, NV_PBUS_PCI_NV_20
, pci_nv_20
);
2576 init_configure_mem(struct nvbios
*bios
, uint16_t offset
,
2577 struct init_exec
*iexec
)
2580 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2582 * offset (8 bit): opcode
2584 * Equivalent to INIT_DONE on bios version 3 or greater.
2585 * For early bios versions, sets up the memory registers, using values
2586 * taken from the memory init table
2589 /* no iexec->execute check by design */
2591 uint16_t meminitoffs
= bios
->legacy
.mem_init_tbl_ptr
+ MEM_INIT_SIZE
* (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_SCRATCH4__INDEX
) >> 4);
2592 uint16_t seqtbloffs
= bios
->legacy
.sdr_seq_tbl_ptr
, meminitdata
= meminitoffs
+ 6;
2595 if (bios
->major_version
> 2)
2598 bios_idxprt_wr(bios
, NV_VIO_SRX
, NV_VIO_SR_CLOCK_INDEX
, bios_idxprt_rd(
2599 bios
, NV_VIO_SRX
, NV_VIO_SR_CLOCK_INDEX
) | 0x20);
2601 if (bios
->data
[meminitoffs
] & 1)
2602 seqtbloffs
= bios
->legacy
.ddr_seq_tbl_ptr
;
2604 for (reg
= ROM32(bios
->data
[seqtbloffs
]);
2606 reg
= ROM32(bios
->data
[seqtbloffs
+= 4])) {
2610 data
= NV04_PFB_PRE_CMD_PRECHARGE
;
2613 data
= NV04_PFB_PAD_CKE_NORMAL
;
2616 data
= NV04_PFB_REF_CMD_REFRESH
;
2619 data
= ROM32(bios
->data
[meminitdata
]);
2621 if (data
== 0xffffffff)
2625 bios_wr32(bios
, reg
, data
);
2632 init_configure_clk(struct nvbios
*bios
, uint16_t offset
,
2633 struct init_exec
*iexec
)
2636 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2638 * offset (8 bit): opcode
2640 * Equivalent to INIT_DONE on bios version 3 or greater.
2641 * For early bios versions, sets up the NVClk and MClk PLLs, using
2642 * values taken from the memory init table
2645 /* no iexec->execute check by design */
2647 uint16_t meminitoffs
= bios
->legacy
.mem_init_tbl_ptr
+ MEM_INIT_SIZE
* (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_SCRATCH4__INDEX
) >> 4);
2650 if (bios
->major_version
> 2)
2653 clock
= ROM16(bios
->data
[meminitoffs
+ 4]) * 10;
2654 setPLL(bios
, NV_PRAMDAC_NVPLL_COEFF
, clock
);
2656 clock
= ROM16(bios
->data
[meminitoffs
+ 2]) * 10;
2657 if (bios
->data
[meminitoffs
] & 1) /* DDR */
2659 setPLL(bios
, NV_PRAMDAC_MPLL_COEFF
, clock
);
2665 init_configure_preinit(struct nvbios
*bios
, uint16_t offset
,
2666 struct init_exec
*iexec
)
2669 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2671 * offset (8 bit): opcode
2673 * Equivalent to INIT_DONE on bios version 3 or greater.
2674 * For early bios versions, does early init, loading ram and crystal
2675 * configuration from straps into CR3C
2678 /* no iexec->execute check by design */
2680 uint32_t straps
= bios_rd32(bios
, NV_PEXTDEV_BOOT_0
);
2681 uint8_t cr3c
= ((straps
<< 2) & 0xf0) | (straps
& 0x40) >> 6;
2683 if (bios
->major_version
> 2)
2686 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
,
2687 NV_CIO_CRE_SCRATCH4__INDEX
, cr3c
);
2693 init_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2696 * INIT_IO opcode: 0x69 ('i')
2698 * offset (8 bit): opcode
2699 * offset + 1 (16 bit): CRTC port
2700 * offset + 3 (8 bit): mask
2701 * offset + 4 (8 bit): data
2703 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2706 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
2707 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
2708 uint8_t mask
= bios
->data
[offset
+ 3];
2709 uint8_t data
= bios
->data
[offset
+ 4];
2711 if (!iexec
->execute
)
2714 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2715 offset
, crtcport
, mask
, data
);
2718 * I have no idea what this does, but NVIDIA do this magic sequence
2719 * in the places where this INIT_IO happens..
2721 if (dev_priv
->card_type
>= NV_50
&& crtcport
== 0x3c3 && data
== 1) {
2724 bios_wr32(bios
, 0x614100, (bios_rd32(
2725 bios
, 0x614100) & 0x0fffffff) | 0x00800000);
2727 bios_wr32(bios
, 0x00e18c, bios_rd32(
2728 bios
, 0x00e18c) | 0x00020000);
2730 bios_wr32(bios
, 0x614900, (bios_rd32(
2731 bios
, 0x614900) & 0x0fffffff) | 0x00800000);
2733 bios_wr32(bios
, 0x000200, bios_rd32(
2734 bios
, 0x000200) & ~0x40000000);
2738 bios_wr32(bios
, 0x00e18c, bios_rd32(
2739 bios
, 0x00e18c) & ~0x00020000);
2741 bios_wr32(bios
, 0x000200, bios_rd32(
2742 bios
, 0x000200) | 0x40000000);
2744 bios_wr32(bios
, 0x614100, 0x00800018);
2745 bios_wr32(bios
, 0x614900, 0x00800018);
2749 bios_wr32(bios
, 0x614100, 0x10000018);
2750 bios_wr32(bios
, 0x614900, 0x10000018);
2752 for (i
= 0; i
< 3; i
++)
2753 bios_wr32(bios
, 0x614280 + (i
*0x800), bios_rd32(
2754 bios
, 0x614280 + (i
*0x800)) & 0xf0f0f0f0);
2756 for (i
= 0; i
< 2; i
++)
2757 bios_wr32(bios
, 0x614300 + (i
*0x800), bios_rd32(
2758 bios
, 0x614300 + (i
*0x800)) & 0xfffff0f0);
2760 for (i
= 0; i
< 3; i
++)
2761 bios_wr32(bios
, 0x614380 + (i
*0x800), bios_rd32(
2762 bios
, 0x614380 + (i
*0x800)) & 0xfffff0f0);
2764 for (i
= 0; i
< 2; i
++)
2765 bios_wr32(bios
, 0x614200 + (i
*0x800), bios_rd32(
2766 bios
, 0x614200 + (i
*0x800)) & 0xfffffff0);
2768 for (i
= 0; i
< 2; i
++)
2769 bios_wr32(bios
, 0x614108 + (i
*0x800), bios_rd32(
2770 bios
, 0x614108 + (i
*0x800)) & 0x0fffffff);
2774 bios_port_wr(bios
, crtcport
, (bios_port_rd(bios
, crtcport
) & mask
) |
2780 init_sub(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2783 * INIT_SUB opcode: 0x6B ('k')
2785 * offset (8 bit): opcode
2786 * offset + 1 (8 bit): script number
2788 * Execute script number "script number", as a subroutine
2791 uint8_t sub
= bios
->data
[offset
+ 1];
2793 if (!iexec
->execute
)
2796 BIOSLOG(bios
, "0x%04X: Calling script %d\n", offset
, sub
);
2798 parse_init_table(bios
,
2799 ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ sub
* 2]),
2802 BIOSLOG(bios
, "0x%04X: End of script %d\n", offset
, sub
);
2808 init_ram_condition(struct nvbios
*bios
, uint16_t offset
,
2809 struct init_exec
*iexec
)
2812 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2814 * offset (8 bit): opcode
2815 * offset + 1 (8 bit): mask
2816 * offset + 2 (8 bit): cmpval
2818 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
2819 * If condition not met skip subsequent opcodes until condition is
2820 * inverted (INIT_NOT), or we hit INIT_RESUME
2823 uint8_t mask
= bios
->data
[offset
+ 1];
2824 uint8_t cmpval
= bios
->data
[offset
+ 2];
2827 if (!iexec
->execute
)
2830 data
= bios_rd32(bios
, NV04_PFB_BOOT_0
) & mask
;
2832 BIOSLOG(bios
, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2833 offset
, data
, cmpval
);
2836 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
2838 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
2839 iexec
->execute
= false;
2846 init_nv_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2849 * INIT_NV_REG opcode: 0x6E ('n')
2851 * offset (8 bit): opcode
2852 * offset + 1 (32 bit): register
2853 * offset + 5 (32 bit): mask
2854 * offset + 9 (32 bit): data
2856 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2859 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
2860 uint32_t mask
= ROM32(bios
->data
[offset
+ 5]);
2861 uint32_t data
= ROM32(bios
->data
[offset
+ 9]);
2863 if (!iexec
->execute
)
2866 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2867 offset
, reg
, mask
, data
);
2869 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & mask
) | data
);
2875 init_macro(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2878 * INIT_MACRO opcode: 0x6F ('o')
2880 * offset (8 bit): opcode
2881 * offset + 1 (8 bit): macro number
2883 * Look up macro index "macro number" in the macro index table.
2884 * The macro index table entry has 1 byte for the index in the macro
2885 * table, and 1 byte for the number of times to repeat the macro.
2886 * The macro table entry has 4 bytes for the register address and
2887 * 4 bytes for the value to write to that register
2890 uint8_t macro_index_tbl_idx
= bios
->data
[offset
+ 1];
2891 uint16_t tmp
= bios
->macro_index_tbl_ptr
+ (macro_index_tbl_idx
* MACRO_INDEX_SIZE
);
2892 uint8_t macro_tbl_idx
= bios
->data
[tmp
];
2893 uint8_t count
= bios
->data
[tmp
+ 1];
2897 if (!iexec
->execute
)
2900 BIOSLOG(bios
, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2902 offset
, macro_index_tbl_idx
, macro_tbl_idx
, count
);
2904 for (i
= 0; i
< count
; i
++) {
2905 uint16_t macroentryptr
= bios
->macro_tbl_ptr
+ (macro_tbl_idx
+ i
) * MACRO_SIZE
;
2907 reg
= ROM32(bios
->data
[macroentryptr
]);
2908 data
= ROM32(bios
->data
[macroentryptr
+ 4]);
2910 bios_wr32(bios
, reg
, data
);
2917 init_done(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2920 * INIT_DONE opcode: 0x71 ('q')
2922 * offset (8 bit): opcode
2924 * End the current script
2927 /* mild retval abuse to stop parsing this table */
2932 init_resume(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2935 * INIT_RESUME opcode: 0x72 ('r')
2937 * offset (8 bit): opcode
2939 * End the current execute / no-execute condition
2945 iexec
->execute
= true;
2946 BIOSLOG(bios
, "0x%04X: ---- Executing following commands ----\n", offset
);
2952 init_time(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2955 * INIT_TIME opcode: 0x74 ('t')
2957 * offset (8 bit): opcode
2958 * offset + 1 (16 bit): time
2960 * Sleep for "time" microseconds.
2963 unsigned time
= ROM16(bios
->data
[offset
+ 1]);
2965 if (!iexec
->execute
)
2968 BIOSLOG(bios
, "0x%04X: Sleeping for 0x%04X microseconds\n",
2974 msleep((time
+ 900) / 1000);
2980 init_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
2983 * INIT_CONDITION opcode: 0x75 ('u')
2985 * offset (8 bit): opcode
2986 * offset + 1 (8 bit): condition number
2988 * Check condition "condition number" in the condition table.
2989 * If condition not met skip subsequent opcodes until condition is
2990 * inverted (INIT_NOT), or we hit INIT_RESUME
2993 uint8_t cond
= bios
->data
[offset
+ 1];
2995 if (!iexec
->execute
)
2998 BIOSLOG(bios
, "0x%04X: Condition: 0x%02X\n", offset
, cond
);
3000 if (bios_condition_met(bios
, offset
, cond
))
3001 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
3003 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
3004 iexec
->execute
= false;
3011 init_io_condition(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3014 * INIT_IO_CONDITION opcode: 0x76
3016 * offset (8 bit): opcode
3017 * offset + 1 (8 bit): condition number
3019 * Check condition "condition number" in the io condition table.
3020 * If condition not met skip subsequent opcodes until condition is
3021 * inverted (INIT_NOT), or we hit INIT_RESUME
3024 uint8_t cond
= bios
->data
[offset
+ 1];
3026 if (!iexec
->execute
)
3029 BIOSLOG(bios
, "0x%04X: IO condition: 0x%02X\n", offset
, cond
);
3031 if (io_condition_met(bios
, offset
, cond
))
3032 BIOSLOG(bios
, "0x%04X: Condition fulfilled -- continuing to execute\n", offset
);
3034 BIOSLOG(bios
, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset
);
3035 iexec
->execute
= false;
3042 init_index_io(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3045 * INIT_INDEX_IO opcode: 0x78 ('x')
3047 * offset (8 bit): opcode
3048 * offset + 1 (16 bit): CRTC port
3049 * offset + 3 (8 bit): CRTC index
3050 * offset + 4 (8 bit): mask
3051 * offset + 5 (8 bit): data
3053 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3054 * OR with "data", write-back
3057 uint16_t crtcport
= ROM16(bios
->data
[offset
+ 1]);
3058 uint8_t crtcindex
= bios
->data
[offset
+ 3];
3059 uint8_t mask
= bios
->data
[offset
+ 4];
3060 uint8_t data
= bios
->data
[offset
+ 5];
3063 if (!iexec
->execute
)
3066 BIOSLOG(bios
, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3068 offset
, crtcport
, crtcindex
, mask
, data
);
3070 value
= (bios_idxprt_rd(bios
, crtcport
, crtcindex
) & mask
) | data
;
3071 bios_idxprt_wr(bios
, crtcport
, crtcindex
, value
);
3077 init_pll(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3080 * INIT_PLL opcode: 0x79 ('y')
3082 * offset (8 bit): opcode
3083 * offset + 1 (32 bit): register
3084 * offset + 5 (16 bit): freq
3086 * Set PLL register "register" to coefficients for frequency (10kHz)
3090 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3091 uint16_t freq
= ROM16(bios
->data
[offset
+ 5]);
3093 if (!iexec
->execute
)
3096 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset
, reg
, freq
);
3098 setPLL(bios
, reg
, freq
* 10);
3104 init_zm_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3107 * INIT_ZM_REG opcode: 0x7A ('z')
3109 * offset (8 bit): opcode
3110 * offset + 1 (32 bit): register
3111 * offset + 5 (32 bit): value
3113 * Assign "value" to "register"
3116 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3117 uint32_t value
= ROM32(bios
->data
[offset
+ 5]);
3119 if (!iexec
->execute
)
3122 if (reg
== 0x000200)
3125 bios_wr32(bios
, reg
, value
);
3131 init_ram_restrict_pll(struct nvbios
*bios
, uint16_t offset
,
3132 struct init_exec
*iexec
)
3135 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3137 * offset (8 bit): opcode
3138 * offset + 1 (8 bit): PLL type
3139 * offset + 2 (32 bit): frequency 0
3141 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3142 * ram_restrict_table_ptr. The value read from there is used to select
3143 * a frequency from the table starting at 'frequency 0' to be
3144 * programmed into the PLL corresponding to 'type'.
3146 * The PLL limits table on cards using this opcode has a mapping of
3147 * 'type' to the relevant registers.
3150 struct drm_device
*dev
= bios
->dev
;
3151 uint32_t strap
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) & 0x0000003c) >> 2;
3152 uint8_t index
= bios
->data
[bios
->ram_restrict_tbl_ptr
+ strap
];
3153 uint8_t type
= bios
->data
[offset
+ 1];
3154 uint32_t freq
= ROM32(bios
->data
[offset
+ 2 + (index
* 4)]);
3155 uint8_t *pll_limits
= &bios
->data
[bios
->pll_limit_tbl_ptr
], *entry
;
3156 int len
= 2 + bios
->ram_restrict_group_count
* 4;
3159 if (!iexec
->execute
)
3162 if (!bios
->pll_limit_tbl_ptr
|| (pll_limits
[0] & 0xf0) != 0x30) {
3163 NV_ERROR(dev
, "PLL limits table not version 3.x\n");
3164 return len
; /* deliberate, allow default clocks to remain */
3167 entry
= pll_limits
+ pll_limits
[1];
3168 for (i
= 0; i
< pll_limits
[3]; i
++, entry
+= pll_limits
[2]) {
3169 if (entry
[0] == type
) {
3170 uint32_t reg
= ROM32(entry
[3]);
3172 BIOSLOG(bios
, "0x%04X: "
3173 "Type %02x Reg 0x%08x Freq %dKHz\n",
3174 offset
, type
, reg
, freq
);
3176 setPLL(bios
, reg
, freq
);
3181 NV_ERROR(dev
, "PLL type 0x%02x not found in PLL limits table", type
);
3186 init_8c(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3189 * INIT_8C opcode: 0x8C ('')
3199 init_8d(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3202 * INIT_8D opcode: 0x8D ('')
3212 init_gpio(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3215 * INIT_GPIO opcode: 0x8E ('')
3217 * offset (8 bit): opcode
3219 * Loop over all entries in the DCB GPIO table, and initialise
3220 * each GPIO according to various values listed in each entry
3223 struct drm_nouveau_private
*dev_priv
= bios
->dev
->dev_private
;
3224 struct nouveau_gpio_engine
*pgpio
= &dev_priv
->engine
.gpio
;
3225 const uint32_t nv50_gpio_ctl
[2] = { 0xe100, 0xe28c };
3228 if (dev_priv
->card_type
< NV_50
) {
3229 NV_ERROR(bios
->dev
, "INIT_GPIO on unsupported chipset\n");
3233 if (!iexec
->execute
)
3236 for (i
= 0; i
< bios
->dcb
.gpio
.entries
; i
++) {
3237 struct dcb_gpio_entry
*gpio
= &bios
->dcb
.gpio
.entry
[i
];
3240 BIOSLOG(bios
, "0x%04X: Entry: 0x%08X\n", offset
, gpio
->entry
);
3242 BIOSLOG(bios
, "0x%04X: set gpio 0x%02x, state %d\n",
3243 offset
, gpio
->tag
, gpio
->state_default
);
3245 pgpio
->set(bios
->dev
, gpio
->tag
, gpio
->state_default
);
3247 /* The NVIDIA binary driver doesn't appear to actually do
3248 * any of this, my VBIOS does however.
3250 /* Not a clue, needs de-magicing */
3251 r
= nv50_gpio_ctl
[gpio
->line
>> 4];
3252 s
= (gpio
->line
& 0x0f);
3253 v
= bios_rd32(bios
, r
) & ~(0x00010001 << s
);
3254 switch ((gpio
->entry
& 0x06000000) >> 25) {
3256 v
|= (0x00000001 << s
);
3259 v
|= (0x00010000 << s
);
3264 bios_wr32(bios
, r
, v
);
3271 init_ram_restrict_zm_reg_group(struct nvbios
*bios
, uint16_t offset
,
3272 struct init_exec
*iexec
)
3275 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3277 * offset (8 bit): opcode
3278 * offset + 1 (32 bit): reg
3279 * offset + 5 (8 bit): regincrement
3280 * offset + 6 (8 bit): count
3281 * offset + 7 (32 bit): value 1,1
3284 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3285 * ram_restrict_table_ptr. The value read from here is 'n', and
3286 * "value 1,n" gets written to "reg". This repeats "count" times and on
3287 * each iteration 'm', "reg" increases by "regincrement" and
3288 * "value m,n" is used. The extent of n is limited by a number read
3289 * from the 'M' BIT table, herein called "blocklen"
3292 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3293 uint8_t regincrement
= bios
->data
[offset
+ 5];
3294 uint8_t count
= bios
->data
[offset
+ 6];
3295 uint32_t strap_ramcfg
, data
;
3296 /* previously set by 'M' BIT table */
3297 uint16_t blocklen
= bios
->ram_restrict_group_count
* 4;
3298 int len
= 7 + count
* blocklen
;
3302 /* critical! to know the length of the opcode */;
3305 "0x%04X: Zero block length - has the M table "
3306 "been parsed?\n", offset
);
3310 if (!iexec
->execute
)
3313 strap_ramcfg
= (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 2) & 0xf;
3314 index
= bios
->data
[bios
->ram_restrict_tbl_ptr
+ strap_ramcfg
];
3316 BIOSLOG(bios
, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3317 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3318 offset
, reg
, regincrement
, count
, strap_ramcfg
, index
);
3320 for (i
= 0; i
< count
; i
++) {
3321 data
= ROM32(bios
->data
[offset
+ 7 + index
* 4 + blocklen
* i
]);
3323 bios_wr32(bios
, reg
, data
);
3325 reg
+= regincrement
;
3332 init_copy_zm_reg(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3335 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3337 * offset (8 bit): opcode
3338 * offset + 1 (32 bit): src reg
3339 * offset + 5 (32 bit): dst reg
3341 * Put contents of "src reg" into "dst reg"
3344 uint32_t srcreg
= ROM32(bios
->data
[offset
+ 1]);
3345 uint32_t dstreg
= ROM32(bios
->data
[offset
+ 5]);
3347 if (!iexec
->execute
)
3350 bios_wr32(bios
, dstreg
, bios_rd32(bios
, srcreg
));
3356 init_zm_reg_group_addr_latched(struct nvbios
*bios
, uint16_t offset
,
3357 struct init_exec
*iexec
)
3360 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3362 * offset (8 bit): opcode
3363 * offset + 1 (32 bit): dst reg
3364 * offset + 5 (8 bit): count
3365 * offset + 6 (32 bit): data 1
3368 * For each of "count" values write "data n" to "dst reg"
3371 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3372 uint8_t count
= bios
->data
[offset
+ 5];
3373 int len
= 6 + count
* 4;
3376 if (!iexec
->execute
)
3379 for (i
= 0; i
< count
; i
++) {
3380 uint32_t data
= ROM32(bios
->data
[offset
+ 6 + 4 * i
]);
3381 bios_wr32(bios
, reg
, data
);
3388 init_reserved(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3391 * INIT_RESERVED opcode: 0x92 ('')
3393 * offset (8 bit): opcode
3395 * Seemingly does nothing
3402 init_96(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3405 * INIT_96 opcode: 0x96 ('')
3407 * offset (8 bit): opcode
3408 * offset + 1 (32 bit): sreg
3409 * offset + 5 (8 bit): sshift
3410 * offset + 6 (8 bit): smask
3411 * offset + 7 (8 bit): index
3412 * offset + 8 (32 bit): reg
3413 * offset + 12 (32 bit): mask
3414 * offset + 16 (8 bit): shift
3418 uint16_t xlatptr
= bios
->init96_tbl_ptr
+ (bios
->data
[offset
+ 7] * 2);
3419 uint32_t reg
= ROM32(bios
->data
[offset
+ 8]);
3420 uint32_t mask
= ROM32(bios
->data
[offset
+ 12]);
3423 val
= bios_rd32(bios
, ROM32(bios
->data
[offset
+ 1]));
3424 if (bios
->data
[offset
+ 5] < 0x80)
3425 val
>>= bios
->data
[offset
+ 5];
3427 val
<<= (0x100 - bios
->data
[offset
+ 5]);
3428 val
&= bios
->data
[offset
+ 6];
3430 val
= bios
->data
[ROM16(bios
->data
[xlatptr
]) + val
];
3431 val
<<= bios
->data
[offset
+ 16];
3433 if (!iexec
->execute
)
3436 bios_wr32(bios
, reg
, (bios_rd32(bios
, reg
) & mask
) | val
);
3441 init_97(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3444 * INIT_97 opcode: 0x97 ('')
3446 * offset (8 bit): opcode
3447 * offset + 1 (32 bit): register
3448 * offset + 5 (32 bit): mask
3449 * offset + 9 (32 bit): value
3451 * Adds "value" to "register" preserving the fields specified
3455 uint32_t reg
= ROM32(bios
->data
[offset
+ 1]);
3456 uint32_t mask
= ROM32(bios
->data
[offset
+ 5]);
3457 uint32_t add
= ROM32(bios
->data
[offset
+ 9]);
3460 val
= bios_rd32(bios
, reg
);
3461 val
= (val
& mask
) | ((val
+ add
) & ~mask
);
3463 if (!iexec
->execute
)
3466 bios_wr32(bios
, reg
, val
);
3471 init_auxch(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3474 * INIT_AUXCH opcode: 0x98 ('')
3476 * offset (8 bit): opcode
3477 * offset + 1 (32 bit): address
3478 * offset + 5 (8 bit): count
3479 * offset + 6 (8 bit): mask 0
3480 * offset + 7 (8 bit): data 0
3485 struct drm_device
*dev
= bios
->dev
;
3486 struct nouveau_i2c_chan
*auxch
;
3487 uint32_t addr
= ROM32(bios
->data
[offset
+ 1]);
3488 uint8_t count
= bios
->data
[offset
+ 5];
3489 int len
= 6 + count
* 2;
3492 if (!bios
->display
.output
) {
3493 NV_ERROR(dev
, "INIT_AUXCH: no active output\n");
3497 auxch
= init_i2c_device_find(dev
, bios
->display
.output
->i2c_index
);
3499 NV_ERROR(dev
, "INIT_AUXCH: couldn't get auxch %d\n",
3500 bios
->display
.output
->i2c_index
);
3504 if (!iexec
->execute
)
3508 for (i
= 0; i
< count
; i
++, offset
+= 2) {
3511 ret
= nouveau_dp_auxch(auxch
, 9, addr
, &data
, 1);
3513 NV_ERROR(dev
, "INIT_AUXCH: rd auxch fail %d\n", ret
);
3517 data
&= bios
->data
[offset
+ 0];
3518 data
|= bios
->data
[offset
+ 1];
3520 ret
= nouveau_dp_auxch(auxch
, 8, addr
, &data
, 1);
3522 NV_ERROR(dev
, "INIT_AUXCH: wr auxch fail %d\n", ret
);
3531 init_zm_auxch(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3534 * INIT_ZM_AUXCH opcode: 0x99 ('')
3536 * offset (8 bit): opcode
3537 * offset + 1 (32 bit): address
3538 * offset + 5 (8 bit): count
3539 * offset + 6 (8 bit): data 0
3544 struct drm_device
*dev
= bios
->dev
;
3545 struct nouveau_i2c_chan
*auxch
;
3546 uint32_t addr
= ROM32(bios
->data
[offset
+ 1]);
3547 uint8_t count
= bios
->data
[offset
+ 5];
3548 int len
= 6 + count
;
3551 if (!bios
->display
.output
) {
3552 NV_ERROR(dev
, "INIT_ZM_AUXCH: no active output\n");
3556 auxch
= init_i2c_device_find(dev
, bios
->display
.output
->i2c_index
);
3558 NV_ERROR(dev
, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3559 bios
->display
.output
->i2c_index
);
3563 if (!iexec
->execute
)
3567 for (i
= 0; i
< count
; i
++, offset
++) {
3568 ret
= nouveau_dp_auxch(auxch
, 8, addr
, &bios
->data
[offset
], 1);
3570 NV_ERROR(dev
, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret
);
3579 init_i2c_long_if(struct nvbios
*bios
, uint16_t offset
, struct init_exec
*iexec
)
3582 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3584 * offset (8 bit): opcode
3585 * offset + 1 (8 bit): DCB I2C table entry index
3586 * offset + 2 (8 bit): I2C slave address
3587 * offset + 3 (16 bit): I2C register
3588 * offset + 5 (8 bit): mask
3589 * offset + 6 (8 bit): data
3591 * Read the register given by "I2C register" on the device addressed
3592 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3593 * entry index". Compare the result AND "mask" to "data".
3594 * If they're not equal, skip subsequent opcodes until condition is
3595 * inverted (INIT_NOT), or we hit INIT_RESUME
3598 uint8_t i2c_index
= bios
->data
[offset
+ 1];
3599 uint8_t i2c_address
= bios
->data
[offset
+ 2] >> 1;
3600 uint8_t reglo
= bios
->data
[offset
+ 3];
3601 uint8_t reghi
= bios
->data
[offset
+ 4];
3602 uint8_t mask
= bios
->data
[offset
+ 5];
3603 uint8_t data
= bios
->data
[offset
+ 6];
3604 struct nouveau_i2c_chan
*chan
;
3605 uint8_t buf0
[2] = { reghi
, reglo
};
3607 struct i2c_msg msg
[2] = {
3608 { i2c_address
, 0, 1, buf0
},
3609 { i2c_address
, I2C_M_RD
, 1, buf1
},
3613 /* no execute check by design */
3615 BIOSLOG(bios
, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3616 offset
, i2c_index
, i2c_address
);
3618 chan
= init_i2c_device_find(bios
->dev
, i2c_index
);
3623 ret
= i2c_transfer(&chan
->adapter
, msg
, 2);
3625 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3626 "Mask: 0x%02X, Data: 0x%02X\n",
3627 offset
, reghi
, reglo
, mask
, data
);
3632 BIOSLOG(bios
, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3633 "Mask: 0x%02X, Data: 0x%02X\n",
3634 offset
, reghi
, reglo
, buf1
[0], mask
, data
);
3636 iexec
->execute
= ((buf1
[0] & mask
) == data
);
3641 static struct init_tbl_entry itbl_entry
[] = {
3642 /* command name , id , length , offset , mult , command handler */
3643 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
3644 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog
},
3645 { "INIT_REPEAT" , 0x33, init_repeat
},
3646 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll
},
3647 { "INIT_END_REPEAT" , 0x36, init_end_repeat
},
3648 { "INIT_COPY" , 0x37, init_copy
},
3649 { "INIT_NOT" , 0x38, init_not
},
3650 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition
},
3651 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition
},
3652 { "INIT_OP_3B" , 0x3B, init_op_3b
},
3653 { "INIT_OP_3C" , 0x3C, init_op_3c
},
3654 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched
},
3655 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2
},
3656 { "INIT_PLL2" , 0x4B, init_pll2
},
3657 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte
},
3658 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte
},
3659 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c
},
3660 { "INIT_TMDS" , 0x4F, init_tmds
},
3661 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group
},
3662 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch
},
3663 { "INIT_CR" , 0x52, init_cr
},
3664 { "INIT_ZM_CR" , 0x53, init_zm_cr
},
3665 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group
},
3666 { "INIT_CONDITION_TIME" , 0x56, init_condition_time
},
3667 { "INIT_LTIME" , 0x57, init_ltime
},
3668 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence
},
3669 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
3670 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct
},
3671 { "INIT_I2C_IF" , 0x5E, init_i2c_if
},
3672 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg
},
3673 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io
},
3674 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem
},
3675 { "INIT_RESET" , 0x65, init_reset
},
3676 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem
},
3677 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk
},
3678 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit
},
3679 { "INIT_IO" , 0x69, init_io
},
3680 { "INIT_SUB" , 0x6B, init_sub
},
3681 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition
},
3682 { "INIT_NV_REG" , 0x6E, init_nv_reg
},
3683 { "INIT_MACRO" , 0x6F, init_macro
},
3684 { "INIT_DONE" , 0x71, init_done
},
3685 { "INIT_RESUME" , 0x72, init_resume
},
3686 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
3687 { "INIT_TIME" , 0x74, init_time
},
3688 { "INIT_CONDITION" , 0x75, init_condition
},
3689 { "INIT_IO_CONDITION" , 0x76, init_io_condition
},
3690 { "INIT_INDEX_IO" , 0x78, init_index_io
},
3691 { "INIT_PLL" , 0x79, init_pll
},
3692 { "INIT_ZM_REG" , 0x7A, init_zm_reg
},
3693 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll
},
3694 { "INIT_8C" , 0x8C, init_8c
},
3695 { "INIT_8D" , 0x8D, init_8d
},
3696 { "INIT_GPIO" , 0x8E, init_gpio
},
3697 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group
},
3698 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg
},
3699 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched
},
3700 { "INIT_RESERVED" , 0x92, init_reserved
},
3701 { "INIT_96" , 0x96, init_96
},
3702 { "INIT_97" , 0x97, init_97
},
3703 { "INIT_AUXCH" , 0x98, init_auxch
},
3704 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch
},
3705 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if
},
3709 #define MAX_TABLE_OPS 1000
3712 parse_init_table(struct nvbios
*bios
, unsigned int offset
,
3713 struct init_exec
*iexec
)
3716 * Parses all commands in an init table.
3718 * We start out executing all commands found in the init table. Some
3719 * opcodes may change the status of iexec->execute to SKIP, which will
3720 * cause the following opcodes to perform no operation until the value
3721 * is changed back to EXECUTE.
3724 int count
= 0, i
, ret
;
3728 * Loop until INIT_DONE causes us to break out of the loop
3729 * (or until offset > bios length just in case... )
3730 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3732 while ((offset
< bios
->length
) && (count
++ < MAX_TABLE_OPS
)) {
3733 id
= bios
->data
[offset
];
3735 /* Find matching id in itbl_entry */
3736 for (i
= 0; itbl_entry
[i
].name
&& (itbl_entry
[i
].id
!= id
); i
++)
3739 if (!itbl_entry
[i
].name
) {
3741 "0x%04X: Init table command not found: "
3742 "0x%02X\n", offset
, id
);
3746 BIOSLOG(bios
, "0x%04X: [ (0x%02X) - %s ]\n", offset
,
3747 itbl_entry
[i
].id
, itbl_entry
[i
].name
);
3749 /* execute eventual command handler */
3750 ret
= (*itbl_entry
[i
].handler
)(bios
, offset
, iexec
);
3752 NV_ERROR(bios
->dev
, "0x%04X: Failed parsing init "
3753 "table opcode: %s %d\n", offset
,
3754 itbl_entry
[i
].name
, ret
);
3761 * Add the offset of the current command including all data
3762 * of that command. The offset will then be pointing on the
3768 if (offset
>= bios
->length
)
3770 "Offset 0x%04X greater than known bios image length. "
3771 "Corrupt image?\n", offset
);
3772 if (count
>= MAX_TABLE_OPS
)
3774 "More than %d opcodes to a table is unlikely, "
3775 "is the bios image corrupt?\n", MAX_TABLE_OPS
);
3781 parse_init_tables(struct nvbios
*bios
)
3783 /* Loops and calls parse_init_table() for each present table. */
3787 struct init_exec iexec
= {true, false};
3789 if (bios
->old_style_init
) {
3790 if (bios
->init_script_tbls_ptr
)
3791 parse_init_table(bios
, bios
->init_script_tbls_ptr
, &iexec
);
3792 if (bios
->extra_init_script_tbl_ptr
)
3793 parse_init_table(bios
, bios
->extra_init_script_tbl_ptr
, &iexec
);
3798 while ((table
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ i
]))) {
3800 "Parsing VBIOS init table %d at offset 0x%04X\n",
3802 BIOSLOG(bios
, "0x%04X: ------ Executing following commands ------\n", table
);
3804 parse_init_table(bios
, table
, &iexec
);
3809 static uint16_t clkcmptable(struct nvbios
*bios
, uint16_t clktable
, int pxclk
)
3811 int compare_record_len
, i
= 0;
3812 uint16_t compareclk
, scriptptr
= 0;
3814 if (bios
->major_version
< 5) /* pre BIT */
3815 compare_record_len
= 3;
3817 compare_record_len
= 4;
3820 compareclk
= ROM16(bios
->data
[clktable
+ compare_record_len
* i
]);
3821 if (pxclk
>= compareclk
* 10) {
3822 if (bios
->major_version
< 5) {
3823 uint8_t tmdssub
= bios
->data
[clktable
+ 2 + compare_record_len
* i
];
3824 scriptptr
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ tmdssub
* 2]);
3826 scriptptr
= ROM16(bios
->data
[clktable
+ 2 + compare_record_len
* i
]);
3830 } while (compareclk
);
3836 run_digital_op_script(struct drm_device
*dev
, uint16_t scriptptr
,
3837 struct dcb_entry
*dcbent
, int head
, bool dl
)
3839 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3840 struct nvbios
*bios
= &dev_priv
->vbios
;
3841 struct init_exec iexec
= {true, false};
3843 NV_TRACE(dev
, "0x%04X: Parsing digital output script table\n",
3845 bios_idxprt_wr(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_44
,
3846 head
? NV_CIO_CRE_44_HEADB
: NV_CIO_CRE_44_HEADA
);
3847 /* note: if dcb entries have been merged, index may be misleading */
3848 NVWriteVgaCrtc5758(dev
, head
, 0, dcbent
->index
);
3849 parse_init_table(bios
, scriptptr
, &iexec
);
3851 nv04_dfp_bind_head(dev
, dcbent
, head
, dl
);
3854 static int call_lvds_manufacturer_script(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
)
3856 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3857 struct nvbios
*bios
= &dev_priv
->vbios
;
3858 uint8_t sub
= bios
->data
[bios
->fp
.xlated_entry
+ script
] + (bios
->fp
.link_c_increment
&& dcbent
->or & OUTPUT_C
? 1 : 0);
3859 uint16_t scriptofs
= ROM16(bios
->data
[bios
->init_script_tbls_ptr
+ sub
* 2]);
3861 if (!bios
->fp
.xlated_entry
|| !sub
|| !scriptofs
)
3864 run_digital_op_script(dev
, scriptofs
, dcbent
, head
, bios
->fp
.dual_link
);
3866 if (script
== LVDS_PANEL_OFF
) {
3867 /* off-on delay in ms */
3868 msleep(ROM16(bios
->data
[bios
->fp
.xlated_entry
+ 7]));
3871 /* Powerbook specific quirks */
3872 if (script
== LVDS_RESET
&&
3873 (dev
->pci_device
== 0x0179 || dev
->pci_device
== 0x0189 ||
3874 dev
->pci_device
== 0x0329))
3875 nv_write_tmds(dev
, dcbent
->or, 0, 0x02, 0x72);
3881 static int run_lvds_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
, int pxclk
)
3884 * The BIT LVDS table's header has the information to setup the
3885 * necessary registers. Following the standard 4 byte header are:
3886 * A bitmask byte and a dual-link transition pxclk value for use in
3887 * selecting the init script when not using straps; 4 script pointers
3888 * for panel power, selected by output and on/off; and 8 table pointers
3889 * for panel init, the needed one determined by output, and bits in the
3890 * conf byte. These tables are similar to the TMDS tables, consisting
3891 * of a list of pxclks and script pointers.
3893 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3894 struct nvbios
*bios
= &dev_priv
->vbios
;
3895 unsigned int outputset
= (dcbent
->or == 4) ? 1 : 0;
3896 uint16_t scriptptr
= 0, clktable
;
3899 * For now we assume version 3.0 table - g80 support will need some
3906 case LVDS_BACKLIGHT_ON
:
3908 scriptptr
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 7 + outputset
* 2]);
3910 case LVDS_BACKLIGHT_OFF
:
3911 case LVDS_PANEL_OFF
:
3912 scriptptr
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 11 + outputset
* 2]);
3915 clktable
= bios
->fp
.lvdsmanufacturerpointer
+ 15;
3916 if (dcbent
->or == 4)
3919 if (dcbent
->lvdsconf
.use_straps_for_mode
) {
3920 if (bios
->fp
.dual_link
)
3922 if (bios
->fp
.if_is_24bit
)
3926 int cmpval_24bit
= (dcbent
->or == 4) ? 4 : 1;
3928 if (bios
->fp
.dual_link
) {
3933 if (bios
->fp
.strapless_is_24bit
& cmpval_24bit
)
3937 clktable
= ROM16(bios
->data
[clktable
]);
3939 NV_ERROR(dev
, "Pixel clock comparison table not found\n");
3942 scriptptr
= clkcmptable(bios
, clktable
, pxclk
);
3946 NV_ERROR(dev
, "LVDS output init script not found\n");
3949 run_digital_op_script(dev
, scriptptr
, dcbent
, head
, bios
->fp
.dual_link
);
3954 int call_lvds_script(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, enum LVDS_script script
, int pxclk
)
3957 * LVDS operations are multiplexed in an effort to present a single API
3958 * which works with two vastly differing underlying structures.
3959 * This acts as the demux
3962 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
3963 struct nvbios
*bios
= &dev_priv
->vbios
;
3964 uint8_t lvds_ver
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
];
3965 uint32_t sel_clk_binding
, sel_clk
;
3968 if (bios
->fp
.last_script_invoc
== (script
<< 1 | head
) || !lvds_ver
||
3969 (lvds_ver
>= 0x30 && script
== LVDS_INIT
))
3972 if (!bios
->fp
.lvds_init_run
) {
3973 bios
->fp
.lvds_init_run
= true;
3974 call_lvds_script(dev
, dcbent
, head
, LVDS_INIT
, pxclk
);
3977 if (script
== LVDS_PANEL_ON
&& bios
->fp
.reset_after_pclk_change
)
3978 call_lvds_script(dev
, dcbent
, head
, LVDS_RESET
, pxclk
);
3979 if (script
== LVDS_RESET
&& bios
->fp
.power_off_for_reset
)
3980 call_lvds_script(dev
, dcbent
, head
, LVDS_PANEL_OFF
, pxclk
);
3982 NV_TRACE(dev
, "Calling LVDS script %d:\n", script
);
3984 /* don't let script change pll->head binding */
3985 sel_clk_binding
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
) & 0x50000;
3987 if (lvds_ver
< 0x30)
3988 ret
= call_lvds_manufacturer_script(dev
, dcbent
, head
, script
);
3990 ret
= run_lvds_table(dev
, dcbent
, head
, script
, pxclk
);
3992 bios
->fp
.last_script_invoc
= (script
<< 1 | head
);
3994 sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
) & ~0x50000;
3995 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, sel_clk
| sel_clk_binding
);
3996 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3997 nvWriteMC(dev
, NV_PBUS_POWERCTRL_2
, 0);
4002 struct lvdstableheader
{
4003 uint8_t lvds_ver
, headerlen
, recordlen
;
4006 static int parse_lvds_manufacturer_table_header(struct drm_device
*dev
, struct nvbios
*bios
, struct lvdstableheader
*lth
)
4009 * BMP version (0xa) LVDS table has a simple header of version and
4010 * record length. The BIT LVDS table has the typical BIT table header:
4011 * version byte, header length byte, record length byte, and a byte for
4012 * the maximum number of records that can be held in the table.
4015 uint8_t lvds_ver
, headerlen
, recordlen
;
4017 memset(lth
, 0, sizeof(struct lvdstableheader
));
4019 if (bios
->fp
.lvdsmanufacturerpointer
== 0x0) {
4020 NV_ERROR(dev
, "Pointer to LVDS manufacturer table invalid\n");
4024 lvds_ver
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
];
4027 case 0x0a: /* pre NV40 */
4029 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
4031 case 0x30: /* NV4x */
4032 headerlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
4033 if (headerlen
< 0x1f) {
4034 NV_ERROR(dev
, "LVDS table header not understood\n");
4037 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 2];
4039 case 0x40: /* G80/G90 */
4040 headerlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 1];
4041 if (headerlen
< 0x7) {
4042 NV_ERROR(dev
, "LVDS table header not understood\n");
4045 recordlen
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 2];
4049 "LVDS table revision %d.%d not currently supported\n",
4050 lvds_ver
>> 4, lvds_ver
& 0xf);
4054 lth
->lvds_ver
= lvds_ver
;
4055 lth
->headerlen
= headerlen
;
4056 lth
->recordlen
= recordlen
;
4062 get_fp_strap(struct drm_device
*dev
, struct nvbios
*bios
)
4064 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4067 * The fp strap is normally dictated by the "User Strap" in
4068 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
4069 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4070 * by the PCI subsystem ID during POST, but not before the previous user
4071 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4072 * read and used instead
4075 if (bios
->major_version
< 5 && bios
->data
[0x48] & 0x4)
4076 return NVReadVgaCrtc5758(dev
, 0, 0xf) & 0xf;
4078 if (dev_priv
->card_type
>= NV_50
)
4079 return (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 24) & 0xf;
4081 return (bios_rd32(bios
, NV_PEXTDEV_BOOT_0
) >> 16) & 0xf;
4084 static int parse_fp_mode_table(struct drm_device
*dev
, struct nvbios
*bios
)
4087 uint8_t fptable_ver
, headerlen
= 0, recordlen
, fpentries
= 0xf, fpindex
;
4088 int ret
, ofs
, fpstrapping
;
4089 struct lvdstableheader lth
;
4091 if (bios
->fp
.fptablepointer
== 0x0) {
4092 /* Apple cards don't have the fp table; the laptops use DDC */
4093 /* The table is also missing on some x86 IGPs */
4095 NV_ERROR(dev
, "Pointer to flat panel table invalid\n");
4097 bios
->digital_min_front_porch
= 0x4b;
4101 fptable
= &bios
->data
[bios
->fp
.fptablepointer
];
4102 fptable_ver
= fptable
[0];
4104 switch (fptable_ver
) {
4106 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4107 * version field, and miss one of the spread spectrum/PWM bytes.
4108 * This could affect early GF2Go parts (not seen any appropriate ROMs
4109 * though). Here we assume that a version of 0x05 matches this case
4110 * (combining with a BMP version check would be better), as the
4111 * common case for the panel type field is 0x0005, and that is in
4112 * fact what we are reading the first byte of.
4114 case 0x05: /* some NV10, 11, 15, 16 */
4118 case 0x10: /* some NV15/16, and NV11+ */
4122 case 0x20: /* NV40+ */
4123 headerlen
= fptable
[1];
4124 recordlen
= fptable
[2];
4125 fpentries
= fptable
[3];
4127 * fptable[4] is the minimum
4128 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4130 bios
->digital_min_front_porch
= fptable
[4];
4135 "FP table revision %d.%d not currently supported\n",
4136 fptable_ver
>> 4, fptable_ver
& 0xf);
4140 if (!bios
->is_mobile
) /* !mobile only needs digital_min_front_porch */
4143 ret
= parse_lvds_manufacturer_table_header(dev
, bios
, <h
);
4147 if (lth
.lvds_ver
== 0x30 || lth
.lvds_ver
== 0x40) {
4148 bios
->fp
.fpxlatetableptr
= bios
->fp
.lvdsmanufacturerpointer
+
4150 bios
->fp
.xlatwidth
= lth
.recordlen
;
4152 if (bios
->fp
.fpxlatetableptr
== 0x0) {
4153 NV_ERROR(dev
, "Pointer to flat panel xlat table invalid\n");
4157 fpstrapping
= get_fp_strap(dev
, bios
);
4159 fpindex
= bios
->data
[bios
->fp
.fpxlatetableptr
+
4160 fpstrapping
* bios
->fp
.xlatwidth
];
4162 if (fpindex
> fpentries
) {
4163 NV_ERROR(dev
, "Bad flat panel table index\n");
4167 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4168 if (lth
.lvds_ver
> 0x10)
4169 bios
->fp_no_ddc
= fpstrapping
!= 0xf || fpindex
!= 0xf;
4172 * If either the strap or xlated fpindex value are 0xf there is no
4173 * panel using a strap-derived bios mode present. this condition
4174 * includes, but is different from, the DDC panel indicator above
4176 if (fpstrapping
== 0xf || fpindex
== 0xf)
4179 bios
->fp
.mode_ptr
= bios
->fp
.fptablepointer
+ headerlen
+
4180 recordlen
* fpindex
+ ofs
;
4182 NV_TRACE(dev
, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4183 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 11]) + 1,
4184 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 25]) + 1,
4185 ROM16(bios
->data
[bios
->fp
.mode_ptr
+ 7]) * 10);
4190 bool nouveau_bios_fp_mode(struct drm_device
*dev
, struct drm_display_mode
*mode
)
4192 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4193 struct nvbios
*bios
= &dev_priv
->vbios
;
4194 uint8_t *mode_entry
= &bios
->data
[bios
->fp
.mode_ptr
];
4196 if (!mode
) /* just checking whether we can produce a mode */
4197 return bios
->fp
.mode_ptr
;
4199 memset(mode
, 0, sizeof(struct drm_display_mode
));
4201 * For version 1.0 (version in byte 0):
4202 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4203 * single/dual link, and type (TFT etc.)
4204 * bytes 3-6 are bits per colour in RGBX
4206 mode
->clock
= ROM16(mode_entry
[7]) * 10;
4207 /* bytes 9-10 is HActive */
4208 mode
->hdisplay
= ROM16(mode_entry
[11]) + 1;
4210 * bytes 13-14 is HValid Start
4211 * bytes 15-16 is HValid End
4213 mode
->hsync_start
= ROM16(mode_entry
[17]) + 1;
4214 mode
->hsync_end
= ROM16(mode_entry
[19]) + 1;
4215 mode
->htotal
= ROM16(mode_entry
[21]) + 1;
4216 /* bytes 23-24, 27-30 similarly, but vertical */
4217 mode
->vdisplay
= ROM16(mode_entry
[25]) + 1;
4218 mode
->vsync_start
= ROM16(mode_entry
[31]) + 1;
4219 mode
->vsync_end
= ROM16(mode_entry
[33]) + 1;
4220 mode
->vtotal
= ROM16(mode_entry
[35]) + 1;
4221 mode
->flags
|= (mode_entry
[37] & 0x10) ?
4222 DRM_MODE_FLAG_PHSYNC
: DRM_MODE_FLAG_NHSYNC
;
4223 mode
->flags
|= (mode_entry
[37] & 0x1) ?
4224 DRM_MODE_FLAG_PVSYNC
: DRM_MODE_FLAG_NVSYNC
;
4226 * bytes 38-39 relate to spread spectrum settings
4227 * bytes 40-43 are something to do with PWM
4230 mode
->status
= MODE_OK
;
4231 mode
->type
= DRM_MODE_TYPE_DRIVER
| DRM_MODE_TYPE_PREFERRED
;
4232 drm_mode_set_name(mode
);
4233 return bios
->fp
.mode_ptr
;
4236 int nouveau_bios_parse_lvds_table(struct drm_device
*dev
, int pxclk
, bool *dl
, bool *if_is_24bit
)
4239 * The LVDS table header is (mostly) described in
4240 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4241 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4242 * straps are not being used for the panel, this specifies the frequency
4243 * at which modes should be set up in the dual link style.
4245 * Following the header, the BMP (ver 0xa) table has several records,
4246 * indexed by a separate xlat table, indexed in turn by the fp strap in
4247 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4248 * numbers for use by INIT_SUB which controlled panel init and power,
4249 * and finally a dword of ms to sleep between power off and on
4252 * In the BIT versions, the table following the header serves as an
4253 * integrated config and xlat table: the records in the table are
4254 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4255 * two bytes - the first as a config byte, the second for indexing the
4256 * fp mode table pointed to by the BIT 'D' table
4258 * DDC is not used until after card init, so selecting the correct table
4259 * entry and setting the dual link flag for EDID equipped panels,
4260 * requiring tests against the native-mode pixel clock, cannot be done
4261 * until later, when this function should be called with non-zero pxclk
4263 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4264 struct nvbios
*bios
= &dev_priv
->vbios
;
4265 int fpstrapping
= get_fp_strap(dev
, bios
), lvdsmanufacturerindex
= 0;
4266 struct lvdstableheader lth
;
4268 int ret
, chip_version
= bios
->chip_version
;
4270 ret
= parse_lvds_manufacturer_table_header(dev
, bios
, <h
);
4274 switch (lth
.lvds_ver
) {
4275 case 0x0a: /* pre NV40 */
4276 lvdsmanufacturerindex
= bios
->data
[
4277 bios
->fp
.fpxlatemanufacturertableptr
+
4280 /* we're done if this isn't the EDID panel case */
4284 if (chip_version
< 0x25) {
4287 * It seems the old style lvds script pointer is reused
4288 * to select 18/24 bit colour depth for EDID panels.
4290 lvdsmanufacturerindex
=
4291 (bios
->legacy
.lvds_single_a_script_ptr
& 1) ?
4293 if (pxclk
>= bios
->fp
.duallink_transition_clk
)
4294 lvdsmanufacturerindex
++;
4295 } else if (chip_version
< 0x30) {
4296 /* nv28 behaviour (off-chip encoder)
4298 * nv28 does a complex dance of first using byte 121 of
4299 * the EDID to choose the lvdsmanufacturerindex, then
4300 * later attempting to match the EDID manufacturer and
4301 * product IDs in a table (signature 'pidt' (panel id
4302 * table?)), setting an lvdsmanufacturerindex of 0 and
4303 * an fp strap of the match index (or 0xf if none)
4305 lvdsmanufacturerindex
= 0;
4307 /* nv31, nv34 behaviour */
4308 lvdsmanufacturerindex
= 0;
4309 if (pxclk
>= bios
->fp
.duallink_transition_clk
)
4310 lvdsmanufacturerindex
= 2;
4311 if (pxclk
>= 140000)
4312 lvdsmanufacturerindex
= 3;
4316 * nvidia set the high nibble of (cr57=f, cr58) to
4317 * lvdsmanufacturerindex in this case; we don't
4320 case 0x30: /* NV4x */
4321 case 0x40: /* G80/G90 */
4322 lvdsmanufacturerindex
= fpstrapping
;
4325 NV_ERROR(dev
, "LVDS table revision not currently supported\n");
4329 lvdsofs
= bios
->fp
.xlated_entry
= bios
->fp
.lvdsmanufacturerpointer
+ lth
.headerlen
+ lth
.recordlen
* lvdsmanufacturerindex
;
4330 switch (lth
.lvds_ver
) {
4332 bios
->fp
.power_off_for_reset
= bios
->data
[lvdsofs
] & 1;
4333 bios
->fp
.reset_after_pclk_change
= bios
->data
[lvdsofs
] & 2;
4334 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 4;
4335 bios
->fp
.link_c_increment
= bios
->data
[lvdsofs
] & 8;
4336 *if_is_24bit
= bios
->data
[lvdsofs
] & 16;
4341 * No sign of the "power off for reset" or "reset for panel
4342 * on" bits, but it's safer to assume we should
4344 bios
->fp
.power_off_for_reset
= true;
4345 bios
->fp
.reset_after_pclk_change
= true;
4348 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
4349 * over-written, and if_is_24bit isn't used
4351 bios
->fp
.dual_link
= bios
->data
[lvdsofs
] & 1;
4352 bios
->fp
.if_is_24bit
= bios
->data
[lvdsofs
] & 2;
4353 bios
->fp
.strapless_is_24bit
= bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 4];
4354 bios
->fp
.duallink_transition_clk
= ROM16(bios
->data
[bios
->fp
.lvdsmanufacturerpointer
+ 5]) * 10;
4358 /* Dell Latitude D620 reports a too-high value for the dual-link
4359 * transition freq, causing us to program the panel incorrectly.
4361 * It doesn't appear the VBIOS actually uses its transition freq
4362 * (90000kHz), instead it uses the "Number of LVDS channels" field
4363 * out of the panel ID structure (http://www.spwg.org/).
4365 * For the moment, a quirk will do :)
4367 if (nv_match_device(dev
, 0x01d7, 0x1028, 0x01c2))
4368 bios
->fp
.duallink_transition_clk
= 80000;
4370 /* set dual_link flag for EDID case */
4371 if (pxclk
&& (chip_version
< 0x25 || chip_version
> 0x28))
4372 bios
->fp
.dual_link
= (pxclk
>= bios
->fp
.duallink_transition_clk
);
4374 *dl
= bios
->fp
.dual_link
;
4380 bios_output_config_match(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
4381 uint16_t record
, int record_len
, int record_nr
,
4384 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4385 struct nvbios
*bios
= &dev_priv
->vbios
;
4390 switch (dcbent
->type
) {
4400 for (i
= 0; i
< record_nr
; i
++, record
+= record_len
) {
4401 table
= ROM16(bios
->data
[record
]);
4404 entry
= ROM32(bios
->data
[table
]);
4407 v
= (entry
& 0x00c00000) >> 22;
4408 if (!(v
& dcbent
->sorconf
.link
))
4412 v
= (entry
& 0x000f0000) >> 16;
4413 if (!(v
& dcbent
->or))
4416 v
= (entry
& 0x000000f0) >> 4;
4417 if (v
!= dcbent
->location
)
4420 v
= (entry
& 0x0000000f);
4421 if (v
!= dcbent
->type
)
4424 return &bios
->data
[table
];
4431 nouveau_bios_dp_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
4434 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4435 struct nvbios
*bios
= &dev_priv
->vbios
;
4438 if (!bios
->display
.dp_table_ptr
) {
4439 NV_ERROR(dev
, "No pointer to DisplayPort table\n");
4442 table
= &bios
->data
[bios
->display
.dp_table_ptr
];
4444 if (table
[0] != 0x20 && table
[0] != 0x21) {
4445 NV_ERROR(dev
, "DisplayPort table version 0x%02x unknown\n",
4451 return bios_output_config_match(dev
, dcbent
,
4452 bios
->display
.dp_table_ptr
+ table
[1],
4453 table
[2], table
[3], table
[0] >= 0x21);
4457 nouveau_bios_run_display_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
,
4458 uint32_t sub
, int pxclk
)
4461 * The display script table is located by the BIT 'U' table.
4463 * It contains an array of pointers to various tables describing
4464 * a particular output type. The first 32-bits of the output
4465 * tables contains similar information to a DCB entry, and is
4466 * used to decide whether that particular table is suitable for
4467 * the output you want to access.
4469 * The "record header length" field here seems to indicate the
4470 * offset of the first configuration entry in the output tables.
4471 * This is 10 on most cards I've seen, but 12 has been witnessed
4472 * on DP cards, and there's another script pointer within the
4475 * offset + 0 ( 8 bits): version
4476 * offset + 1 ( 8 bits): header length
4477 * offset + 2 ( 8 bits): record length
4478 * offset + 3 ( 8 bits): number of records
4479 * offset + 4 ( 8 bits): record header length
4480 * offset + 5 (16 bits): pointer to first output script table
4483 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4484 struct nvbios
*bios
= &dev_priv
->vbios
;
4485 uint8_t *table
= &bios
->data
[bios
->display
.script_table_ptr
];
4486 uint8_t *otable
= NULL
;
4490 if (!bios
->display
.script_table_ptr
) {
4491 NV_ERROR(dev
, "No pointer to output script table\n");
4496 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4497 * so until they are, we really don't need to care.
4499 if (table
[0] < 0x20)
4502 if (table
[0] != 0x20 && table
[0] != 0x21) {
4503 NV_ERROR(dev
, "Output script table version 0x%02x unknown\n",
4509 * The output script tables describing a particular output type
4512 * offset + 0 (32 bits): output this table matches (hash of DCB)
4513 * offset + 4 ( 8 bits): unknown
4514 * offset + 5 ( 8 bits): number of configurations
4515 * offset + 6 (16 bits): pointer to some script
4516 * offset + 8 (16 bits): pointer to some script
4519 * offset + 10 : configuration 0
4522 * offset + 10 : pointer to some script
4523 * offset + 12 : configuration 0
4525 * Each config entry is as follows:
4527 * offset + 0 (16 bits): unknown, assumed to be a match value
4528 * offset + 2 (16 bits): pointer to script table (clock set?)
4529 * offset + 4 (16 bits): pointer to script table (reset?)
4531 * There doesn't appear to be a count value to say how many
4532 * entries exist in each script table, instead, a 0 value in
4533 * the first 16-bit word seems to indicate both the end of the
4534 * list and the default entry. The second 16-bit word in the
4535 * script tables is a pointer to the script to execute.
4538 NV_DEBUG_KMS(dev
, "Searching for output entry for %d %d %d\n",
4539 dcbent
->type
, dcbent
->location
, dcbent
->or);
4540 otable
= bios_output_config_match(dev
, dcbent
, table
[1] +
4541 bios
->display
.script_table_ptr
,
4542 table
[2], table
[3], table
[0] >= 0x21);
4544 NV_DEBUG_KMS(dev
, "failed to match any output table\n");
4548 if (pxclk
< -2 || pxclk
> 0) {
4549 /* Try to find matching script table entry */
4550 for (i
= 0; i
< otable
[5]; i
++) {
4551 if (ROM16(otable
[table
[4] + i
*6]) == sub
)
4555 if (i
== otable
[5]) {
4556 NV_ERROR(dev
, "Table 0x%04x not found for %d/%d, "
4558 sub
, dcbent
->type
, dcbent
->or);
4564 script
= ROM16(otable
[6]);
4566 NV_DEBUG_KMS(dev
, "output script 0 not found\n");
4570 NV_DEBUG_KMS(dev
, "0x%04X: parsing output script 0\n", script
);
4571 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4574 script
= ROM16(otable
[8]);
4576 NV_DEBUG_KMS(dev
, "output script 1 not found\n");
4580 NV_DEBUG_KMS(dev
, "0x%04X: parsing output script 1\n", script
);
4581 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4585 script
= ROM16(otable
[10]);
4589 NV_DEBUG_KMS(dev
, "output script 2 not found\n");
4593 NV_DEBUG_KMS(dev
, "0x%04X: parsing output script 2\n", script
);
4594 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4597 script
= ROM16(otable
[table
[4] + i
*6 + 2]);
4599 script
= clkcmptable(bios
, script
, pxclk
);
4601 NV_DEBUG_KMS(dev
, "clock script 0 not found\n");
4605 NV_DEBUG_KMS(dev
, "0x%04X: parsing clock script 0\n", script
);
4606 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4609 script
= ROM16(otable
[table
[4] + i
*6 + 4]);
4611 script
= clkcmptable(bios
, script
, -pxclk
);
4613 NV_DEBUG_KMS(dev
, "clock script 1 not found\n");
4617 NV_DEBUG_KMS(dev
, "0x%04X: parsing clock script 1\n", script
);
4618 nouveau_bios_run_init_table(dev
, script
, dcbent
);
4625 int run_tmds_table(struct drm_device
*dev
, struct dcb_entry
*dcbent
, int head
, int pxclk
)
4628 * the pxclk parameter is in kHz
4630 * This runs the TMDS regs setting code found on BIT bios cards
4632 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4633 * ffs(or) == 3, use the second.
4636 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4637 struct nvbios
*bios
= &dev_priv
->vbios
;
4638 int cv
= bios
->chip_version
;
4639 uint16_t clktable
= 0, scriptptr
;
4640 uint32_t sel_clk_binding
, sel_clk
;
4642 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4643 if (cv
>= 0x17 && cv
!= 0x1a && cv
!= 0x20 &&
4644 dcbent
->location
!= DCB_LOC_ON_CHIP
)
4647 switch (ffs(dcbent
->or)) {
4649 clktable
= bios
->tmds
.output0_script_ptr
;
4653 clktable
= bios
->tmds
.output1_script_ptr
;
4658 NV_ERROR(dev
, "Pixel clock comparison table not found\n");
4662 scriptptr
= clkcmptable(bios
, clktable
, pxclk
);
4665 NV_ERROR(dev
, "TMDS output init script not found\n");
4669 /* don't let script change pll->head binding */
4670 sel_clk_binding
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
) & 0x50000;
4671 run_digital_op_script(dev
, scriptptr
, dcbent
, head
, pxclk
>= 165000);
4672 sel_clk
= NVReadRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
) & ~0x50000;
4673 NVWriteRAMDAC(dev
, 0, NV_PRAMDAC_SEL_CLK
, sel_clk
| sel_clk_binding
);
4678 int get_pll_limits(struct drm_device
*dev
, uint32_t limit_match
, struct pll_lims
*pll_lim
)
4683 * Version 0x10: NV30, NV31
4684 * One byte header (version), one record of 24 bytes
4685 * Version 0x11: NV36 - Not implemented
4686 * Seems to have same record style as 0x10, but 3 records rather than 1
4687 * Version 0x20: Found on Geforce 6 cards
4688 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4689 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4690 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4691 * length in general, some (integrated) have an extra configuration byte
4692 * Version 0x30: Found on Geforce 8, separates the register mapping
4693 * from the limits tables.
4696 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
4697 struct nvbios
*bios
= &dev_priv
->vbios
;
4698 int cv
= bios
->chip_version
, pllindex
= 0;
4699 uint8_t pll_lim_ver
= 0, headerlen
= 0, recordlen
= 0, entries
= 0;
4700 uint32_t crystal_strap_mask
, crystal_straps
;
4702 if (!bios
->pll_limit_tbl_ptr
) {
4703 if (cv
== 0x30 || cv
== 0x31 || cv
== 0x35 || cv
== 0x36 ||
4705 NV_ERROR(dev
, "Pointer to PLL limits table invalid\n");
4709 pll_lim_ver
= bios
->data
[bios
->pll_limit_tbl_ptr
];
4711 crystal_strap_mask
= 1 << 6;
4712 /* open coded dev->twoHeads test */
4713 if (cv
> 0x10 && cv
!= 0x15 && cv
!= 0x1a && cv
!= 0x20)
4714 crystal_strap_mask
|= 1 << 22;
4715 crystal_straps
= nvReadEXTDEV(dev
, NV_PEXTDEV_BOOT_0
) &
4718 switch (pll_lim_ver
) {
4720 * We use version 0 to indicate a pre limit table bios (single stage
4721 * pll) and load the hard coded limits instead.
4728 * Strictly v0x11 has 3 entries, but the last two don't seem
4740 headerlen
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 1];
4741 recordlen
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 2];
4742 entries
= bios
->data
[bios
->pll_limit_tbl_ptr
+ 3];
4745 NV_ERROR(dev
, "PLL limits table revision 0x%X not currently "
4746 "supported\n", pll_lim_ver
);
4750 /* initialize all members to zero */
4751 memset(pll_lim
, 0, sizeof(struct pll_lims
));
4753 if (pll_lim_ver
== 0x10 || pll_lim_ver
== 0x11) {
4754 uint8_t *pll_rec
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
+ recordlen
* pllindex
];
4756 pll_lim
->vco1
.minfreq
= ROM32(pll_rec
[0]);
4757 pll_lim
->vco1
.maxfreq
= ROM32(pll_rec
[4]);
4758 pll_lim
->vco2
.minfreq
= ROM32(pll_rec
[8]);
4759 pll_lim
->vco2
.maxfreq
= ROM32(pll_rec
[12]);
4760 pll_lim
->vco1
.min_inputfreq
= ROM32(pll_rec
[16]);
4761 pll_lim
->vco2
.min_inputfreq
= ROM32(pll_rec
[20]);
4762 pll_lim
->vco1
.max_inputfreq
= pll_lim
->vco2
.max_inputfreq
= INT_MAX
;
4764 /* these values taken from nv30/31/36 */
4765 pll_lim
->vco1
.min_n
= 0x1;
4767 pll_lim
->vco1
.min_n
= 0x5;
4768 pll_lim
->vco1
.max_n
= 0xff;
4769 pll_lim
->vco1
.min_m
= 0x1;
4770 pll_lim
->vco1
.max_m
= 0xd;
4771 pll_lim
->vco2
.min_n
= 0x4;
4773 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4774 * table version (apart from nv35)), N2 is compared to
4775 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4778 pll_lim
->vco2
.max_n
= 0x28;
4779 if (cv
== 0x30 || cv
== 0x35)
4780 /* only 5 bits available for N2 on nv30/35 */
4781 pll_lim
->vco2
.max_n
= 0x1f;
4782 pll_lim
->vco2
.min_m
= 0x1;
4783 pll_lim
->vco2
.max_m
= 0x4;
4784 pll_lim
->max_log2p
= 0x7;
4785 pll_lim
->max_usable_log2p
= 0x6;
4786 } else if (pll_lim_ver
== 0x20 || pll_lim_ver
== 0x21) {
4787 uint16_t plloffs
= bios
->pll_limit_tbl_ptr
+ headerlen
;
4788 uint32_t reg
= 0; /* default match */
4793 * First entry is default match, if nothing better. warn if
4796 if (ROM32(bios
->data
[plloffs
]))
4797 NV_WARN(dev
, "Default PLL limit entry has non-zero "
4798 "register field\n");
4800 if (limit_match
> MAX_PLL_TYPES
)
4801 /* we've been passed a reg as the match */
4803 else /* limit match is a pll type */
4804 for (i
= 1; i
< entries
&& !reg
; i
++) {
4805 uint32_t cmpreg
= ROM32(bios
->data
[plloffs
+ recordlen
* i
]);
4807 if (limit_match
== NVPLL
&&
4808 (cmpreg
== NV_PRAMDAC_NVPLL_COEFF
|| cmpreg
== 0x4000))
4810 if (limit_match
== MPLL
&&
4811 (cmpreg
== NV_PRAMDAC_MPLL_COEFF
|| cmpreg
== 0x4020))
4813 if (limit_match
== VPLL1
&&
4814 (cmpreg
== NV_PRAMDAC_VPLL_COEFF
|| cmpreg
== 0x4010))
4816 if (limit_match
== VPLL2
&&
4817 (cmpreg
== NV_RAMDAC_VPLL2
|| cmpreg
== 0x4018))
4821 for (i
= 1; i
< entries
; i
++)
4822 if (ROM32(bios
->data
[plloffs
+ recordlen
* i
]) == reg
) {
4827 pll_rec
= &bios
->data
[plloffs
+ recordlen
* pllindex
];
4829 BIOSLOG(bios
, "Loading PLL limits for reg 0x%08x\n",
4830 pllindex
? reg
: 0);
4833 * Frequencies are stored in tables in MHz, kHz are more
4834 * useful, so we convert.
4837 /* What output frequencies can each VCO generate? */
4838 pll_lim
->vco1
.minfreq
= ROM16(pll_rec
[4]) * 1000;
4839 pll_lim
->vco1
.maxfreq
= ROM16(pll_rec
[6]) * 1000;
4840 pll_lim
->vco2
.minfreq
= ROM16(pll_rec
[8]) * 1000;
4841 pll_lim
->vco2
.maxfreq
= ROM16(pll_rec
[10]) * 1000;
4843 /* What input frequencies they accept (past the m-divider)? */
4844 pll_lim
->vco1
.min_inputfreq
= ROM16(pll_rec
[12]) * 1000;
4845 pll_lim
->vco2
.min_inputfreq
= ROM16(pll_rec
[14]) * 1000;
4846 pll_lim
->vco1
.max_inputfreq
= ROM16(pll_rec
[16]) * 1000;
4847 pll_lim
->vco2
.max_inputfreq
= ROM16(pll_rec
[18]) * 1000;
4849 /* What values are accepted as multiplier and divider? */
4850 pll_lim
->vco1
.min_n
= pll_rec
[20];
4851 pll_lim
->vco1
.max_n
= pll_rec
[21];
4852 pll_lim
->vco1
.min_m
= pll_rec
[22];
4853 pll_lim
->vco1
.max_m
= pll_rec
[23];
4854 pll_lim
->vco2
.min_n
= pll_rec
[24];
4855 pll_lim
->vco2
.max_n
= pll_rec
[25];
4856 pll_lim
->vco2
.min_m
= pll_rec
[26];
4857 pll_lim
->vco2
.max_m
= pll_rec
[27];
4859 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
= pll_rec
[29];
4860 if (pll_lim
->max_log2p
> 0x7)
4861 /* pll decoding in nv_hw.c assumes never > 7 */
4862 NV_WARN(dev
, "Max log2 P value greater than 7 (%d)\n",
4863 pll_lim
->max_log2p
);
4865 pll_lim
->max_usable_log2p
= 0x6;
4866 pll_lim
->log2p_bias
= pll_rec
[30];
4868 if (recordlen
> 0x22)
4869 pll_lim
->refclk
= ROM32(pll_rec
[31]);
4871 if (recordlen
> 0x23 && pll_rec
[35])
4873 "Bits set in PLL configuration byte (%x)\n",
4876 /* C51 special not seen elsewhere */
4877 if (cv
== 0x51 && !pll_lim
->refclk
) {
4878 uint32_t sel_clk
= bios_rd32(bios
, NV_PRAMDAC_SEL_CLK
);
4880 if (((limit_match
== NV_PRAMDAC_VPLL_COEFF
|| limit_match
== VPLL1
) && sel_clk
& 0x20) ||
4881 ((limit_match
== NV_RAMDAC_VPLL2
|| limit_match
== VPLL2
) && sel_clk
& 0x80)) {
4882 if (bios_idxprt_rd(bios
, NV_CIO_CRX__COLOR
, NV_CIO_CRE_CHIP_ID_INDEX
) < 0xa3)
4883 pll_lim
->refclk
= 200000;
4885 pll_lim
->refclk
= 25000;
4888 } else if (pll_lim_ver
== 0x30) { /* ver 0x30 */
4889 uint8_t *entry
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
];
4890 uint8_t *record
= NULL
;
4893 BIOSLOG(bios
, "Loading PLL limits for register 0x%08x\n",
4896 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
4897 if (ROM32(entry
[3]) == limit_match
) {
4898 record
= &bios
->data
[ROM16(entry
[1])];
4904 NV_ERROR(dev
, "Register 0x%08x not found in PLL "
4905 "limits table", limit_match
);
4909 pll_lim
->vco1
.minfreq
= ROM16(record
[0]) * 1000;
4910 pll_lim
->vco1
.maxfreq
= ROM16(record
[2]) * 1000;
4911 pll_lim
->vco2
.minfreq
= ROM16(record
[4]) * 1000;
4912 pll_lim
->vco2
.maxfreq
= ROM16(record
[6]) * 1000;
4913 pll_lim
->vco1
.min_inputfreq
= ROM16(record
[8]) * 1000;
4914 pll_lim
->vco2
.min_inputfreq
= ROM16(record
[10]) * 1000;
4915 pll_lim
->vco1
.max_inputfreq
= ROM16(record
[12]) * 1000;
4916 pll_lim
->vco2
.max_inputfreq
= ROM16(record
[14]) * 1000;
4917 pll_lim
->vco1
.min_n
= record
[16];
4918 pll_lim
->vco1
.max_n
= record
[17];
4919 pll_lim
->vco1
.min_m
= record
[18];
4920 pll_lim
->vco1
.max_m
= record
[19];
4921 pll_lim
->vco2
.min_n
= record
[20];
4922 pll_lim
->vco2
.max_n
= record
[21];
4923 pll_lim
->vco2
.min_m
= record
[22];
4924 pll_lim
->vco2
.max_m
= record
[23];
4925 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
= record
[25];
4926 pll_lim
->log2p_bias
= record
[27];
4927 pll_lim
->refclk
= ROM32(record
[28]);
4928 } else if (pll_lim_ver
) { /* ver 0x40 */
4929 uint8_t *entry
= &bios
->data
[bios
->pll_limit_tbl_ptr
+ headerlen
];
4930 uint8_t *record
= NULL
;
4933 BIOSLOG(bios
, "Loading PLL limits for register 0x%08x\n",
4936 for (i
= 0; i
< entries
; i
++, entry
+= recordlen
) {
4937 if (ROM32(entry
[3]) == limit_match
) {
4938 record
= &bios
->data
[ROM16(entry
[1])];
4944 NV_ERROR(dev
, "Register 0x%08x not found in PLL "
4945 "limits table", limit_match
);
4949 pll_lim
->vco1
.minfreq
= ROM16(record
[0]) * 1000;
4950 pll_lim
->vco1
.maxfreq
= ROM16(record
[2]) * 1000;
4951 pll_lim
->vco1
.min_inputfreq
= ROM16(record
[4]) * 1000;
4952 pll_lim
->vco1
.max_inputfreq
= ROM16(record
[6]) * 1000;
4953 pll_lim
->vco1
.min_m
= record
[8];
4954 pll_lim
->vco1
.max_m
= record
[9];
4955 pll_lim
->vco1
.min_n
= record
[10];
4956 pll_lim
->vco1
.max_n
= record
[11];
4957 pll_lim
->min_p
= record
[12];
4958 pll_lim
->max_p
= record
[13];
4959 /* where did this go to?? */
4960 if ((entry
[0] & 0xf0) == 0x80)
4961 pll_lim
->refclk
= 27000;
4963 pll_lim
->refclk
= 100000;
4967 * By now any valid limit table ought to have set a max frequency for
4968 * vco1, so if it's zero it's either a pre limit table bios, or one
4969 * with an empty limit table (seen on nv18)
4971 if (!pll_lim
->vco1
.maxfreq
) {
4972 pll_lim
->vco1
.minfreq
= bios
->fminvco
;
4973 pll_lim
->vco1
.maxfreq
= bios
->fmaxvco
;
4974 pll_lim
->vco1
.min_inputfreq
= 0;
4975 pll_lim
->vco1
.max_inputfreq
= INT_MAX
;
4976 pll_lim
->vco1
.min_n
= 0x1;
4977 pll_lim
->vco1
.max_n
= 0xff;
4978 pll_lim
->vco1
.min_m
= 0x1;
4979 if (crystal_straps
== 0) {
4980 /* nv05 does this, nv11 doesn't, nv10 unknown */
4982 pll_lim
->vco1
.min_m
= 0x7;
4983 pll_lim
->vco1
.max_m
= 0xd;
4986 pll_lim
->vco1
.min_m
= 0x8;
4987 pll_lim
->vco1
.max_m
= 0xe;
4989 if (cv
< 0x17 || cv
== 0x1a || cv
== 0x20)
4990 pll_lim
->max_log2p
= 4;
4992 pll_lim
->max_log2p
= 5;
4993 pll_lim
->max_usable_log2p
= pll_lim
->max_log2p
;
4996 if (!pll_lim
->refclk
)
4997 switch (crystal_straps
) {
4999 pll_lim
->refclk
= 13500;
5002 pll_lim
->refclk
= 14318;
5005 pll_lim
->refclk
= 27000;
5007 case (1 << 22 | 1 << 6):
5008 pll_lim
->refclk
= 25000;
5012 NV_DEBUG(dev
, "pll.vco1.minfreq: %d\n", pll_lim
->vco1
.minfreq
);
5013 NV_DEBUG(dev
, "pll.vco1.maxfreq: %d\n", pll_lim
->vco1
.maxfreq
);
5014 NV_DEBUG(dev
, "pll.vco1.min_inputfreq: %d\n", pll_lim
->vco1
.min_inputfreq
);
5015 NV_DEBUG(dev
, "pll.vco1.max_inputfreq: %d\n", pll_lim
->vco1
.max_inputfreq
);
5016 NV_DEBUG(dev
, "pll.vco1.min_n: %d\n", pll_lim
->vco1
.min_n
);
5017 NV_DEBUG(dev
, "pll.vco1.max_n: %d\n", pll_lim
->vco1
.max_n
);
5018 NV_DEBUG(dev
, "pll.vco1.min_m: %d\n", pll_lim
->vco1
.min_m
);
5019 NV_DEBUG(dev
, "pll.vco1.max_m: %d\n", pll_lim
->vco1
.max_m
);
5020 if (pll_lim
->vco2
.maxfreq
) {
5021 NV_DEBUG(dev
, "pll.vco2.minfreq: %d\n", pll_lim
->vco2
.minfreq
);
5022 NV_DEBUG(dev
, "pll.vco2.maxfreq: %d\n", pll_lim
->vco2
.maxfreq
);
5023 NV_DEBUG(dev
, "pll.vco2.min_inputfreq: %d\n", pll_lim
->vco2
.min_inputfreq
);
5024 NV_DEBUG(dev
, "pll.vco2.max_inputfreq: %d\n", pll_lim
->vco2
.max_inputfreq
);
5025 NV_DEBUG(dev
, "pll.vco2.min_n: %d\n", pll_lim
->vco2
.min_n
);
5026 NV_DEBUG(dev
, "pll.vco2.max_n: %d\n", pll_lim
->vco2
.max_n
);
5027 NV_DEBUG(dev
, "pll.vco2.min_m: %d\n", pll_lim
->vco2
.min_m
);
5028 NV_DEBUG(dev
, "pll.vco2.max_m: %d\n", pll_lim
->vco2
.max_m
);
5030 if (!pll_lim
->max_p
) {
5031 NV_DEBUG(dev
, "pll.max_log2p: %d\n", pll_lim
->max_log2p
);
5032 NV_DEBUG(dev
, "pll.log2p_bias: %d\n", pll_lim
->log2p_bias
);
5034 NV_DEBUG(dev
, "pll.min_p: %d\n", pll_lim
->min_p
);
5035 NV_DEBUG(dev
, "pll.max_p: %d\n", pll_lim
->max_p
);
5037 NV_DEBUG(dev
, "pll.refclk: %d\n", pll_lim
->refclk
);
5042 static void parse_bios_version(struct drm_device
*dev
, struct nvbios
*bios
, uint16_t offset
)
5045 * offset + 0 (8 bits): Micro version
5046 * offset + 1 (8 bits): Minor version
5047 * offset + 2 (8 bits): Chip version
5048 * offset + 3 (8 bits): Major version
5051 bios
->major_version
= bios
->data
[offset
+ 3];
5052 bios
->chip_version
= bios
->data
[offset
+ 2];
5053 NV_TRACE(dev
, "Bios version %02x.%02x.%02x.%02x\n",
5054 bios
->data
[offset
+ 3], bios
->data
[offset
+ 2],
5055 bios
->data
[offset
+ 1], bios
->data
[offset
]);
5058 static void parse_script_table_pointers(struct nvbios
*bios
, uint16_t offset
)
5061 * Parses the init table segment for pointers used in script execution.
5063 * offset + 0 (16 bits): init script tables pointer
5064 * offset + 2 (16 bits): macro index table pointer
5065 * offset + 4 (16 bits): macro table pointer
5066 * offset + 6 (16 bits): condition table pointer
5067 * offset + 8 (16 bits): io condition table pointer
5068 * offset + 10 (16 bits): io flag condition table pointer
5069 * offset + 12 (16 bits): init function table pointer
5072 bios
->init_script_tbls_ptr
= ROM16(bios
->data
[offset
]);
5073 bios
->macro_index_tbl_ptr
= ROM16(bios
->data
[offset
+ 2]);
5074 bios
->macro_tbl_ptr
= ROM16(bios
->data
[offset
+ 4]);
5075 bios
->condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 6]);
5076 bios
->io_condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 8]);
5077 bios
->io_flag_condition_tbl_ptr
= ROM16(bios
->data
[offset
+ 10]);
5078 bios
->init_function_tbl_ptr
= ROM16(bios
->data
[offset
+ 12]);
5081 static int parse_bit_A_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5084 * Parses the load detect values for g80 cards.
5086 * offset + 0 (16 bits): loadval table pointer
5089 uint16_t load_table_ptr
;
5090 uint8_t version
, headerlen
, entrylen
, num_entries
;
5092 if (bitentry
->length
!= 3) {
5093 NV_ERROR(dev
, "Do not understand BIT A table\n");
5097 load_table_ptr
= ROM16(bios
->data
[bitentry
->offset
]);
5099 if (load_table_ptr
== 0x0) {
5100 NV_ERROR(dev
, "Pointer to BIT loadval table invalid\n");
5104 version
= bios
->data
[load_table_ptr
];
5106 if (version
!= 0x10) {
5107 NV_ERROR(dev
, "BIT loadval table version %d.%d not supported\n",
5108 version
>> 4, version
& 0xF);
5112 headerlen
= bios
->data
[load_table_ptr
+ 1];
5113 entrylen
= bios
->data
[load_table_ptr
+ 2];
5114 num_entries
= bios
->data
[load_table_ptr
+ 3];
5116 if (headerlen
!= 4 || entrylen
!= 4 || num_entries
!= 2) {
5117 NV_ERROR(dev
, "Do not understand BIT loadval table\n");
5121 /* First entry is normal dac, 2nd tv-out perhaps? */
5122 bios
->dactestval
= ROM32(bios
->data
[load_table_ptr
+ headerlen
]) & 0x3ff;
5127 static int parse_bit_C_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5130 * offset + 8 (16 bits): PLL limits table pointer
5132 * There's more in here, but that's unknown.
5135 if (bitentry
->length
< 10) {
5136 NV_ERROR(dev
, "Do not understand BIT C table\n");
5140 bios
->pll_limit_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 8]);
5145 static int parse_bit_display_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5148 * Parses the flat panel table segment that the bit entry points to.
5149 * Starting at bitentry->offset:
5151 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5152 * records beginning with a freq.
5153 * offset + 2 (16 bits): mode table pointer
5156 if (bitentry
->length
!= 4) {
5157 NV_ERROR(dev
, "Do not understand BIT display table\n");
5161 bios
->fp
.fptablepointer
= ROM16(bios
->data
[bitentry
->offset
+ 2]);
5166 static int parse_bit_init_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5169 * Parses the init table segment that the bit entry points to.
5171 * See parse_script_table_pointers for layout
5174 if (bitentry
->length
< 14) {
5175 NV_ERROR(dev
, "Do not understand init table\n");
5179 parse_script_table_pointers(bios
, bitentry
->offset
);
5181 if (bitentry
->length
>= 16)
5182 bios
->some_script_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 14]);
5183 if (bitentry
->length
>= 18)
5184 bios
->init96_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 16]);
5189 static int parse_bit_i_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5192 * BIT 'i' (info?) table
5194 * offset + 0 (32 bits): BIOS version dword (as in B table)
5195 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5196 * offset + 13 (16 bits): pointer to table containing DAC load
5197 * detection comparison values
5199 * There's other things in the table, purpose unknown
5202 uint16_t daccmpoffset
;
5203 uint8_t dacver
, dacheaderlen
;
5205 if (bitentry
->length
< 6) {
5206 NV_ERROR(dev
, "BIT i table too short for needed information\n");
5210 parse_bios_version(dev
, bios
, bitentry
->offset
);
5213 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5214 * Quadro identity crisis), other bits possibly as for BMP feature byte
5216 bios
->feature_byte
= bios
->data
[bitentry
->offset
+ 5];
5217 bios
->is_mobile
= bios
->feature_byte
& FEATURE_MOBILE
;
5219 if (bitentry
->length
< 15) {
5220 NV_WARN(dev
, "BIT i table not long enough for DAC load "
5221 "detection comparison table\n");
5225 daccmpoffset
= ROM16(bios
->data
[bitentry
->offset
+ 13]);
5227 /* doesn't exist on g80 */
5232 * The first value in the table, following the header, is the
5233 * comparison value, the second entry is a comparison value for
5234 * TV load detection.
5237 dacver
= bios
->data
[daccmpoffset
];
5238 dacheaderlen
= bios
->data
[daccmpoffset
+ 1];
5240 if (dacver
!= 0x00 && dacver
!= 0x10) {
5241 NV_WARN(dev
, "DAC load detection comparison table version "
5242 "%d.%d not known\n", dacver
>> 4, dacver
& 0xf);
5246 bios
->dactestval
= ROM32(bios
->data
[daccmpoffset
+ dacheaderlen
]);
5247 bios
->tvdactestval
= ROM32(bios
->data
[daccmpoffset
+ dacheaderlen
+ 4]);
5252 static int parse_bit_lvds_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5255 * Parses the LVDS table segment that the bit entry points to.
5256 * Starting at bitentry->offset:
5258 * offset + 0 (16 bits): LVDS strap xlate table pointer
5261 if (bitentry
->length
!= 2) {
5262 NV_ERROR(dev
, "Do not understand BIT LVDS table\n");
5267 * No idea if it's still called the LVDS manufacturer table, but
5268 * the concept's close enough.
5270 bios
->fp
.lvdsmanufacturerpointer
= ROM16(bios
->data
[bitentry
->offset
]);
5276 parse_bit_M_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
5277 struct bit_entry
*bitentry
)
5280 * offset + 2 (8 bits): number of options in an
5281 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5282 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5283 * restrict option selection
5285 * There's a bunch of bits in this table other than the RAM restrict
5286 * stuff that we don't use - their use currently unknown
5290 * Older bios versions don't have a sufficiently long table for
5293 if (bitentry
->length
< 0x5)
5296 if (bitentry
->id
[1] < 2) {
5297 bios
->ram_restrict_group_count
= bios
->data
[bitentry
->offset
+ 2];
5298 bios
->ram_restrict_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 3]);
5300 bios
->ram_restrict_group_count
= bios
->data
[bitentry
->offset
+ 0];
5301 bios
->ram_restrict_tbl_ptr
= ROM16(bios
->data
[bitentry
->offset
+ 1]);
5307 static int parse_bit_tmds_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
, struct bit_entry
*bitentry
)
5310 * Parses the pointer to the TMDS table
5312 * Starting at bitentry->offset:
5314 * offset + 0 (16 bits): TMDS table pointer
5316 * The TMDS table is typically found just before the DCB table, with a
5317 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5320 * At offset +7 is a pointer to a script, which I don't know how to
5322 * At offset +9 is a pointer to another script, likewise
5323 * Offset +11 has a pointer to a table where the first word is a pxclk
5324 * frequency and the second word a pointer to a script, which should be
5325 * run if the comparison pxclk frequency is less than the pxclk desired.
5326 * This repeats for decreasing comparison frequencies
5327 * Offset +13 has a pointer to a similar table
5328 * The selection of table (and possibly +7/+9 script) is dictated by
5329 * "or" from the DCB.
5332 uint16_t tmdstableptr
, script1
, script2
;
5334 if (bitentry
->length
!= 2) {
5335 NV_ERROR(dev
, "Do not understand BIT TMDS table\n");
5339 tmdstableptr
= ROM16(bios
->data
[bitentry
->offset
]);
5340 if (!tmdstableptr
) {
5341 NV_ERROR(dev
, "Pointer to TMDS table invalid\n");
5345 NV_INFO(dev
, "TMDS table version %d.%d\n",
5346 bios
->data
[tmdstableptr
] >> 4, bios
->data
[tmdstableptr
] & 0xf);
5348 /* nv50+ has v2.0, but we don't parse it atm */
5349 if (bios
->data
[tmdstableptr
] != 0x11)
5353 * These two scripts are odd: they don't seem to get run even when
5354 * they are not stubbed.
5356 script1
= ROM16(bios
->data
[tmdstableptr
+ 7]);
5357 script2
= ROM16(bios
->data
[tmdstableptr
+ 9]);
5358 if (bios
->data
[script1
] != 'q' || bios
->data
[script2
] != 'q')
5359 NV_WARN(dev
, "TMDS table script pointers not stubbed\n");
5361 bios
->tmds
.output0_script_ptr
= ROM16(bios
->data
[tmdstableptr
+ 11]);
5362 bios
->tmds
.output1_script_ptr
= ROM16(bios
->data
[tmdstableptr
+ 13]);
5368 parse_bit_U_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
5369 struct bit_entry
*bitentry
)
5372 * Parses the pointer to the G80 output script tables
5374 * Starting at bitentry->offset:
5376 * offset + 0 (16 bits): output script table pointer
5379 uint16_t outputscripttableptr
;
5381 if (bitentry
->length
!= 3) {
5382 NV_ERROR(dev
, "Do not understand BIT U table\n");
5386 outputscripttableptr
= ROM16(bios
->data
[bitentry
->offset
]);
5387 bios
->display
.script_table_ptr
= outputscripttableptr
;
5392 parse_bit_displayport_tbl_entry(struct drm_device
*dev
, struct nvbios
*bios
,
5393 struct bit_entry
*bitentry
)
5395 bios
->display
.dp_table_ptr
= ROM16(bios
->data
[bitentry
->offset
]);
5401 int (* const parse_fn
)(struct drm_device
*, struct nvbios
*, struct bit_entry
*);
5404 #define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5407 parse_bit_table(struct nvbios
*bios
, const uint16_t bitoffset
,
5408 struct bit_table
*table
)
5410 struct drm_device
*dev
= bios
->dev
;
5411 uint8_t maxentries
= bios
->data
[bitoffset
+ 4];
5413 struct bit_entry bitentry
;
5415 for (i
= 0, offset
= bitoffset
+ 6; i
< maxentries
; i
++, offset
+= 6) {
5416 bitentry
.id
[0] = bios
->data
[offset
];
5418 if (bitentry
.id
[0] != table
->id
)
5421 bitentry
.id
[1] = bios
->data
[offset
+ 1];
5422 bitentry
.length
= ROM16(bios
->data
[offset
+ 2]);
5423 bitentry
.offset
= ROM16(bios
->data
[offset
+ 4]);
5425 return table
->parse_fn(dev
, bios
, &bitentry
);
5428 NV_INFO(dev
, "BIT table '%c' not found\n", table
->id
);
5433 parse_bit_structure(struct nvbios
*bios
, const uint16_t bitoffset
)
5438 * The only restriction on parsing order currently is having 'i' first
5439 * for use of bios->*_version or bios->feature_byte while parsing;
5440 * functions shouldn't be actually *doing* anything apart from pulling
5441 * data from the image into the bios struct, thus no interdependencies
5443 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('i', i
));
5444 if (ret
) /* info? */
5446 if (bios
->major_version
>= 0x60) /* g80+ */
5447 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('A', A
));
5448 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('C', C
));
5451 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('D', display
));
5452 ret
= parse_bit_table(bios
, bitoffset
, &BIT_TABLE('I', init
));
5455 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('M', M
)); /* memory? */
5456 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('L', lvds
));
5457 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('T', tmds
));
5458 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('U', U
));
5459 parse_bit_table(bios
, bitoffset
, &BIT_TABLE('d', displayport
));
5464 static int parse_bmp_structure(struct drm_device
*dev
, struct nvbios
*bios
, unsigned int offset
)
5467 * Parses the BMP structure for useful things, but does not act on them
5469 * offset + 5: BMP major version
5470 * offset + 6: BMP minor version
5471 * offset + 9: BMP feature byte
5472 * offset + 10: BCD encoded BIOS version
5474 * offset + 18: init script table pointer (for bios versions < 5.10h)
5475 * offset + 20: extra init script table pointer (for bios
5478 * offset + 24: memory init table pointer (used on early bios versions)
5479 * offset + 26: SDR memory sequencing setup data table
5480 * offset + 28: DDR memory sequencing setup data table
5482 * offset + 54: index of I2C CRTC pair to use for CRT output
5483 * offset + 55: index of I2C CRTC pair to use for TV output
5484 * offset + 56: index of I2C CRTC pair to use for flat panel output
5485 * offset + 58: write CRTC index for I2C pair 0
5486 * offset + 59: read CRTC index for I2C pair 0
5487 * offset + 60: write CRTC index for I2C pair 1
5488 * offset + 61: read CRTC index for I2C pair 1
5490 * offset + 67: maximum internal PLL frequency (single stage PLL)
5491 * offset + 71: minimum internal PLL frequency (single stage PLL)
5493 * offset + 75: script table pointers, as described in
5494 * parse_script_table_pointers
5496 * offset + 89: TMDS single link output A table pointer
5497 * offset + 91: TMDS single link output B table pointer
5498 * offset + 95: LVDS single link output A table pointer
5499 * offset + 105: flat panel timings table pointer
5500 * offset + 107: flat panel strapping translation table pointer
5501 * offset + 117: LVDS manufacturer panel config table pointer
5502 * offset + 119: LVDS manufacturer strapping translation table pointer
5504 * offset + 142: PLL limits table pointer
5506 * offset + 156: minimum pixel clock for LVDS dual link
5509 uint8_t *bmp
= &bios
->data
[offset
], bmp_version_major
, bmp_version_minor
;
5511 uint16_t legacy_scripts_offset
, legacy_i2c_offset
;
5513 /* load needed defaults in case we can't parse this info */
5514 bios
->dcb
.i2c
[0].write
= NV_CIO_CRE_DDC_WR__INDEX
;
5515 bios
->dcb
.i2c
[0].read
= NV_CIO_CRE_DDC_STATUS__INDEX
;
5516 bios
->dcb
.i2c
[1].write
= NV_CIO_CRE_DDC0_WR__INDEX
;
5517 bios
->dcb
.i2c
[1].read
= NV_CIO_CRE_DDC0_STATUS__INDEX
;
5518 bios
->digital_min_front_porch
= 0x4b;
5519 bios
->fmaxvco
= 256000;
5520 bios
->fminvco
= 128000;
5521 bios
->fp
.duallink_transition_clk
= 90000;
5523 bmp_version_major
= bmp
[5];
5524 bmp_version_minor
= bmp
[6];
5526 NV_TRACE(dev
, "BMP version %d.%d\n",
5527 bmp_version_major
, bmp_version_minor
);
5530 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5531 * pointer on early versions
5533 if (bmp_version_major
< 5)
5534 *(uint16_t *)&bios
->data
[0x36] = 0;
5537 * Seems that the minor version was 1 for all major versions prior
5538 * to 5. Version 6 could theoretically exist, but I suspect BIT
5541 if ((bmp_version_major
< 5 && bmp_version_minor
!= 1) || bmp_version_major
> 5) {
5542 NV_ERROR(dev
, "You have an unsupported BMP version. "
5543 "Please send in your bios\n");
5547 if (bmp_version_major
== 0)
5548 /* nothing that's currently useful in this version */
5550 else if (bmp_version_major
== 1)
5551 bmplength
= 44; /* exact for 1.01 */
5552 else if (bmp_version_major
== 2)
5553 bmplength
= 48; /* exact for 2.01 */
5554 else if (bmp_version_major
== 3)
5556 /* guessed - mem init tables added in this version */
5557 else if (bmp_version_major
== 4 || bmp_version_minor
< 0x1)
5558 /* don't know if 5.0 exists... */
5560 /* guessed - BMP I2C indices added in version 4*/
5561 else if (bmp_version_minor
< 0x6)
5562 bmplength
= 67; /* exact for 5.01 */
5563 else if (bmp_version_minor
< 0x10)
5564 bmplength
= 75; /* exact for 5.06 */
5565 else if (bmp_version_minor
== 0x10)
5566 bmplength
= 89; /* exact for 5.10h */
5567 else if (bmp_version_minor
< 0x14)
5568 bmplength
= 118; /* exact for 5.11h */
5569 else if (bmp_version_minor
< 0x24)
5571 * Not sure of version where pll limits came in;
5572 * certainly exist by 0x24 though.
5574 /* length not exact: this is long enough to get lvds members */
5576 else if (bmp_version_minor
< 0x27)
5578 * Length not exact: this is long enough to get pll limit
5584 * Length not exact: this is long enough to get dual link
5590 if (nv_cksum(bmp
, 8)) {
5591 NV_ERROR(dev
, "Bad BMP checksum\n");
5596 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5597 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5598 * (not nv10gl), bit 5 that the flat panel tables are present, and
5601 bios
->feature_byte
= bmp
[9];
5603 parse_bios_version(dev
, bios
, offset
+ 10);
5605 if (bmp_version_major
< 5 || bmp_version_minor
< 0x10)
5606 bios
->old_style_init
= true;
5607 legacy_scripts_offset
= 18;
5608 if (bmp_version_major
< 2)
5609 legacy_scripts_offset
-= 4;
5610 bios
->init_script_tbls_ptr
= ROM16(bmp
[legacy_scripts_offset
]);
5611 bios
->extra_init_script_tbl_ptr
= ROM16(bmp
[legacy_scripts_offset
+ 2]);
5613 if (bmp_version_major
> 2) { /* appears in BMP 3 */
5614 bios
->legacy
.mem_init_tbl_ptr
= ROM16(bmp
[24]);
5615 bios
->legacy
.sdr_seq_tbl_ptr
= ROM16(bmp
[26]);
5616 bios
->legacy
.ddr_seq_tbl_ptr
= ROM16(bmp
[28]);
5619 legacy_i2c_offset
= 0x48; /* BMP version 2 & 3 */
5621 legacy_i2c_offset
= offset
+ 54;
5622 bios
->legacy
.i2c_indices
.crt
= bios
->data
[legacy_i2c_offset
];
5623 bios
->legacy
.i2c_indices
.tv
= bios
->data
[legacy_i2c_offset
+ 1];
5624 bios
->legacy
.i2c_indices
.panel
= bios
->data
[legacy_i2c_offset
+ 2];
5625 if (bios
->data
[legacy_i2c_offset
+ 4])
5626 bios
->dcb
.i2c
[0].write
= bios
->data
[legacy_i2c_offset
+ 4];
5627 if (bios
->data
[legacy_i2c_offset
+ 5])
5628 bios
->dcb
.i2c
[0].read
= bios
->data
[legacy_i2c_offset
+ 5];
5629 if (bios
->data
[legacy_i2c_offset
+ 6])
5630 bios
->dcb
.i2c
[1].write
= bios
->data
[legacy_i2c_offset
+ 6];
5631 if (bios
->data
[legacy_i2c_offset
+ 7])
5632 bios
->dcb
.i2c
[1].read
= bios
->data
[legacy_i2c_offset
+ 7];
5634 if (bmplength
> 74) {
5635 bios
->fmaxvco
= ROM32(bmp
[67]);
5636 bios
->fminvco
= ROM32(bmp
[71]);
5639 parse_script_table_pointers(bios
, offset
+ 75);
5640 if (bmplength
> 94) {
5641 bios
->tmds
.output0_script_ptr
= ROM16(bmp
[89]);
5642 bios
->tmds
.output1_script_ptr
= ROM16(bmp
[91]);
5644 * Never observed in use with lvds scripts, but is reused for
5645 * 18/24 bit panel interface default for EDID equipped panels
5646 * (if_is_24bit not set directly to avoid any oscillation).
5648 bios
->legacy
.lvds_single_a_script_ptr
= ROM16(bmp
[95]);
5650 if (bmplength
> 108) {
5651 bios
->fp
.fptablepointer
= ROM16(bmp
[105]);
5652 bios
->fp
.fpxlatetableptr
= ROM16(bmp
[107]);
5653 bios
->fp
.xlatwidth
= 1;
5655 if (bmplength
> 120) {
5656 bios
->fp
.lvdsmanufacturerpointer
= ROM16(bmp
[117]);
5657 bios
->fp
.fpxlatemanufacturertableptr
= ROM16(bmp
[119]);
5659 if (bmplength
> 143)
5660 bios
->pll_limit_tbl_ptr
= ROM16(bmp
[142]);
5662 if (bmplength
> 157)
5663 bios
->fp
.duallink_transition_clk
= ROM16(bmp
[156]) * 10;
5668 static uint16_t findstr(uint8_t *data
, int n
, const uint8_t *str
, int len
)
5672 for (i
= 0; i
<= (n
- len
); i
++) {
5673 for (j
= 0; j
< len
; j
++)
5674 if (data
[i
+ j
] != str
[j
])
5683 static struct dcb_gpio_entry
*
5684 new_gpio_entry(struct nvbios
*bios
)
5686 struct dcb_gpio_table
*gpio
= &bios
->dcb
.gpio
;
5688 return &gpio
->entry
[gpio
->entries
++];
5691 struct dcb_gpio_entry
*
5692 nouveau_bios_gpio_entry(struct drm_device
*dev
, enum dcb_gpio_tag tag
)
5694 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5695 struct nvbios
*bios
= &dev_priv
->vbios
;
5698 for (i
= 0; i
< bios
->dcb
.gpio
.entries
; i
++) {
5699 if (bios
->dcb
.gpio
.entry
[i
].tag
!= tag
)
5702 return &bios
->dcb
.gpio
.entry
[i
];
5709 parse_dcb30_gpio_entry(struct nvbios
*bios
, uint16_t offset
)
5711 struct dcb_gpio_entry
*gpio
;
5712 uint16_t ent
= ROM16(bios
->data
[offset
]);
5713 uint8_t line
= ent
& 0x1f,
5714 tag
= ent
>> 5 & 0x3f,
5715 flags
= ent
>> 11 & 0x1f;
5720 gpio
= new_gpio_entry(bios
);
5724 gpio
->invert
= flags
!= 4;
5729 parse_dcb40_gpio_entry(struct nvbios
*bios
, uint16_t offset
)
5731 uint32_t entry
= ROM32(bios
->data
[offset
]);
5732 struct dcb_gpio_entry
*gpio
;
5734 if ((entry
& 0x0000ff00) == 0x0000ff00)
5737 gpio
= new_gpio_entry(bios
);
5738 gpio
->tag
= (entry
& 0x0000ff00) >> 8;
5739 gpio
->line
= (entry
& 0x0000001f) >> 0;
5740 gpio
->state_default
= (entry
& 0x01000000) >> 24;
5741 gpio
->state
[0] = (entry
& 0x18000000) >> 27;
5742 gpio
->state
[1] = (entry
& 0x60000000) >> 29;
5743 gpio
->entry
= entry
;
5747 parse_dcb_gpio_table(struct nvbios
*bios
)
5749 struct drm_device
*dev
= bios
->dev
;
5750 uint16_t gpio_table_ptr
= bios
->dcb
.gpio_table_ptr
;
5751 uint8_t *gpio_table
= &bios
->data
[gpio_table_ptr
];
5752 int header_len
= gpio_table
[1],
5753 entries
= gpio_table
[2],
5754 entry_len
= gpio_table
[3];
5755 void (*parse_entry
)(struct nvbios
*, uint16_t) = NULL
;
5758 if (bios
->dcb
.version
>= 0x40) {
5759 if (gpio_table_ptr
&& entry_len
!= 4) {
5760 NV_WARN(dev
, "Invalid DCB GPIO table entry length.\n");
5764 parse_entry
= parse_dcb40_gpio_entry
;
5766 } else if (bios
->dcb
.version
>= 0x30) {
5767 if (gpio_table_ptr
&& entry_len
!= 2) {
5768 NV_WARN(dev
, "Invalid DCB GPIO table entry length.\n");
5772 parse_entry
= parse_dcb30_gpio_entry
;
5774 } else if (bios
->dcb
.version
>= 0x22) {
5776 * DCBs older than v3.0 don't really have a GPIO
5777 * table, instead they keep some GPIO info at fixed
5780 uint16_t dcbptr
= ROM16(bios
->data
[0x36]);
5781 uint8_t *tvdac_gpio
= &bios
->data
[dcbptr
- 5];
5783 if (tvdac_gpio
[0] & 1) {
5784 struct dcb_gpio_entry
*gpio
= new_gpio_entry(bios
);
5786 gpio
->tag
= DCB_GPIO_TVDAC0
;
5787 gpio
->line
= tvdac_gpio
[1] >> 4;
5788 gpio
->invert
= tvdac_gpio
[0] & 2;
5792 * No systematic way to store GPIO info on pre-v2.2
5793 * DCBs, try to match the PCI device IDs.
5796 /* Apple iMac G4 NV18 */
5797 if (nv_match_device(dev
, 0x0189, 0x10de, 0x0010)) {
5798 struct dcb_gpio_entry
*gpio
= new_gpio_entry(bios
);
5800 gpio
->tag
= DCB_GPIO_TVDAC0
;
5806 if (!gpio_table_ptr
)
5809 if (entries
> DCB_MAX_NUM_GPIO_ENTRIES
) {
5810 NV_WARN(dev
, "Too many entries in the DCB GPIO table.\n");
5811 entries
= DCB_MAX_NUM_GPIO_ENTRIES
;
5814 for (i
= 0; i
< entries
; i
++)
5815 parse_entry(bios
, gpio_table_ptr
+ header_len
+ entry_len
* i
);
5818 struct dcb_connector_table_entry
*
5819 nouveau_bios_connector_entry(struct drm_device
*dev
, int index
)
5821 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
5822 struct nvbios
*bios
= &dev_priv
->vbios
;
5823 struct dcb_connector_table_entry
*cte
;
5825 if (index
>= bios
->dcb
.connector
.entries
)
5828 cte
= &bios
->dcb
.connector
.entry
[index
];
5829 if (cte
->type
== 0xff)
5835 static enum dcb_connector_type
5836 divine_connector_type(struct nvbios
*bios
, int index
)
5838 struct dcb_table
*dcb
= &bios
->dcb
;
5839 unsigned encoders
= 0, type
= DCB_CONNECTOR_NONE
;
5842 for (i
= 0; i
< dcb
->entries
; i
++) {
5843 if (dcb
->entry
[i
].connector
== index
)
5844 encoders
|= (1 << dcb
->entry
[i
].type
);
5847 if (encoders
& (1 << OUTPUT_DP
)) {
5848 if (encoders
& (1 << OUTPUT_TMDS
))
5849 type
= DCB_CONNECTOR_DP
;
5851 type
= DCB_CONNECTOR_eDP
;
5853 if (encoders
& (1 << OUTPUT_TMDS
)) {
5854 if (encoders
& (1 << OUTPUT_ANALOG
))
5855 type
= DCB_CONNECTOR_DVI_I
;
5857 type
= DCB_CONNECTOR_DVI_D
;
5859 if (encoders
& (1 << OUTPUT_ANALOG
)) {
5860 type
= DCB_CONNECTOR_VGA
;
5862 if (encoders
& (1 << OUTPUT_LVDS
)) {
5863 type
= DCB_CONNECTOR_LVDS
;
5865 if (encoders
& (1 << OUTPUT_TV
)) {
5866 type
= DCB_CONNECTOR_TV_0
;
5873 apply_dcb_connector_quirks(struct nvbios
*bios
, int idx
)
5875 struct dcb_connector_table_entry
*cte
= &bios
->dcb
.connector
.entry
[idx
];
5876 struct drm_device
*dev
= bios
->dev
;
5878 /* Gigabyte NX85T */
5879 if (nv_match_device(dev
, 0x0421, 0x1458, 0x344c)) {
5880 if (cte
->type
== DCB_CONNECTOR_HDMI_1
)
5881 cte
->type
= DCB_CONNECTOR_DVI_I
;
5886 parse_dcb_connector_table(struct nvbios
*bios
)
5888 struct drm_device
*dev
= bios
->dev
;
5889 struct dcb_connector_table
*ct
= &bios
->dcb
.connector
;
5890 struct dcb_connector_table_entry
*cte
;
5891 uint8_t *conntab
= &bios
->data
[bios
->dcb
.connector_table_ptr
];
5895 if (!bios
->dcb
.connector_table_ptr
) {
5896 NV_DEBUG_KMS(dev
, "No DCB connector table present\n");
5900 NV_INFO(dev
, "DCB connector table: VHER 0x%02x %d %d %d\n",
5901 conntab
[0], conntab
[1], conntab
[2], conntab
[3]);
5902 if ((conntab
[0] != 0x30 && conntab
[0] != 0x40) ||
5903 (conntab
[3] != 2 && conntab
[3] != 4)) {
5904 NV_ERROR(dev
, " Unknown! Please report.\n");
5908 ct
->entries
= conntab
[2];
5910 entry
= conntab
+ conntab
[1];
5911 cte
= &ct
->entry
[0];
5912 for (i
= 0; i
< conntab
[2]; i
++, entry
+= conntab
[3], cte
++) {
5914 if (conntab
[3] == 2)
5915 cte
->entry
= ROM16(entry
[0]);
5917 cte
->entry
= ROM32(entry
[0]);
5919 cte
->type
= (cte
->entry
& 0x000000ff) >> 0;
5920 cte
->index2
= (cte
->entry
& 0x00000f00) >> 8;
5921 switch (cte
->entry
& 0x00033000) {
5923 cte
->gpio_tag
= 0x07;
5926 cte
->gpio_tag
= 0x08;
5929 cte
->gpio_tag
= 0x51;
5932 cte
->gpio_tag
= 0x52;
5935 cte
->gpio_tag
= 0xff;
5939 if (cte
->type
== 0xff)
5942 apply_dcb_connector_quirks(bios
, i
);
5944 NV_INFO(dev
, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5945 i
, cte
->entry
, cte
->type
, cte
->index
, cte
->gpio_tag
);
5947 /* check for known types, fallback to guessing the type
5948 * from attached encoders if we hit an unknown.
5950 switch (cte
->type
) {
5951 case DCB_CONNECTOR_VGA
:
5952 case DCB_CONNECTOR_TV_0
:
5953 case DCB_CONNECTOR_TV_1
:
5954 case DCB_CONNECTOR_TV_3
:
5955 case DCB_CONNECTOR_DVI_I
:
5956 case DCB_CONNECTOR_DVI_D
:
5957 case DCB_CONNECTOR_LVDS
:
5958 case DCB_CONNECTOR_DP
:
5959 case DCB_CONNECTOR_eDP
:
5960 case DCB_CONNECTOR_HDMI_0
:
5961 case DCB_CONNECTOR_HDMI_1
:
5964 cte
->type
= divine_connector_type(bios
, cte
->index
);
5965 NV_WARN(dev
, "unknown type, using 0x%02x\n", cte
->type
);
5969 if (nouveau_override_conntype
) {
5970 int type
= divine_connector_type(bios
, cte
->index
);
5971 if (type
!= cte
->type
)
5972 NV_WARN(dev
, " -> type 0x%02x\n", cte
->type
);
5978 static struct dcb_entry
*new_dcb_entry(struct dcb_table
*dcb
)
5980 struct dcb_entry
*entry
= &dcb
->entry
[dcb
->entries
];
5982 memset(entry
, 0, sizeof(struct dcb_entry
));
5983 entry
->index
= dcb
->entries
++;
5988 static void fabricate_vga_output(struct dcb_table
*dcb
, int i2c
, int heads
)
5990 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
5993 entry
->i2c_index
= i2c
;
5994 entry
->heads
= heads
;
5995 entry
->location
= DCB_LOC_ON_CHIP
;
5999 static void fabricate_dvi_i_output(struct dcb_table
*dcb
, bool twoHeads
)
6001 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
6004 entry
->i2c_index
= LEGACY_I2C_PANEL
;
6005 entry
->heads
= twoHeads
? 3 : 1;
6006 entry
->location
= !DCB_LOC_ON_CHIP
; /* ie OFF CHIP */
6007 entry
->or = 1; /* means |0x10 gets set on CRE_LCD__INDEX */
6008 entry
->duallink_possible
= false; /* SiI164 and co. are single link */
6012 * For dvi-a either crtc probably works, but my card appears to only
6013 * support dvi-d. "nvidia" still attempts to program it for dvi-a,
6014 * doing the full fp output setup (program 0x6808.. fp dimension regs,
6015 * setting 0x680848 to 0x10000111 to enable, maybe setting 0x680880);
6016 * the monitor picks up the mode res ok and lights up, but no pixel
6017 * data appears, so the board manufacturer probably connected up the
6018 * sync lines, but missed the video traces / components
6020 * with this introduction, dvi-a left as an exercise for the reader.
6022 fabricate_vga_output(dcb
, LEGACY_I2C_PANEL
, entry
->heads
);
6026 static void fabricate_tv_output(struct dcb_table
*dcb
, bool twoHeads
)
6028 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
6031 entry
->i2c_index
= LEGACY_I2C_TV
;
6032 entry
->heads
= twoHeads
? 3 : 1;
6033 entry
->location
= !DCB_LOC_ON_CHIP
; /* ie OFF CHIP */
6037 parse_dcb20_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
6038 uint32_t conn
, uint32_t conf
, struct dcb_entry
*entry
)
6040 entry
->type
= conn
& 0xf;
6041 entry
->i2c_index
= (conn
>> 4) & 0xf;
6042 entry
->heads
= (conn
>> 8) & 0xf;
6043 if (dcb
->version
>= 0x40)
6044 entry
->connector
= (conn
>> 12) & 0xf;
6045 entry
->bus
= (conn
>> 16) & 0xf;
6046 entry
->location
= (conn
>> 20) & 0x3;
6047 entry
->or = (conn
>> 24) & 0xf;
6049 switch (entry
->type
) {
6052 * Although the rest of a CRT conf dword is usually
6053 * zeros, mac biosen have stuff there so we must mask
6055 entry
->crtconf
.maxfreq
= (dcb
->version
< 0x30) ?
6056 (conf
& 0xffff) * 10 :
6057 (conf
& 0xff) * 10000;
6063 entry
->lvdsconf
.use_straps_for_mode
= true;
6064 if (dcb
->version
< 0x22) {
6067 * The laptop in bug 14567 lies and claims to not use
6068 * straps when it does, so assume all DCB 2.0 laptops
6069 * use straps, until a broken EDID using one is produced
6071 entry
->lvdsconf
.use_straps_for_mode
= true;
6073 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
6074 * mean the same thing (probably wrong, but might work)
6076 if (conf
& 0x4 || conf
& 0x8)
6077 entry
->lvdsconf
.use_power_scripts
= true;
6081 entry
->lvdsconf
.use_acpi_for_edid
= true;
6083 entry
->lvdsconf
.use_power_scripts
= true;
6084 entry
->lvdsconf
.sor
.link
= (conf
& 0x00000030) >> 4;
6088 * Until we even try to use these on G8x, it's
6089 * useless reporting unknown bits. They all are.
6091 if (dcb
->version
>= 0x40)
6094 NV_ERROR(dev
, "Unknown LVDS configuration bits, "
6101 if (dcb
->version
>= 0x30)
6102 entry
->tvconf
.has_component_output
= conf
& (0x8 << 4);
6104 entry
->tvconf
.has_component_output
= false;
6109 entry
->dpconf
.sor
.link
= (conf
& 0x00000030) >> 4;
6110 entry
->dpconf
.link_bw
= (conf
& 0x00e00000) >> 21;
6111 switch ((conf
& 0x0f000000) >> 24) {
6113 entry
->dpconf
.link_nr
= 4;
6116 entry
->dpconf
.link_nr
= 2;
6119 entry
->dpconf
.link_nr
= 1;
6124 if (dcb
->version
>= 0x40)
6125 entry
->tmdsconf
.sor
.link
= (conf
& 0x00000030) >> 4;
6126 else if (dcb
->version
>= 0x30)
6127 entry
->tmdsconf
.slave_addr
= (conf
& 0x00000700) >> 8;
6128 else if (dcb
->version
>= 0x22)
6129 entry
->tmdsconf
.slave_addr
= (conf
& 0x00000070) >> 4;
6133 /* weird g80 mobile type that "nv" treats as a terminator */
6140 if (dcb
->version
< 0x40) {
6141 /* Normal entries consist of a single bit, but dual link has
6142 * the next most significant bit set too
6144 entry
->duallink_possible
=
6145 ((1 << (ffs(entry
->or) - 1)) * 3 == entry
->or);
6147 entry
->duallink_possible
= (entry
->sorconf
.link
== 3);
6150 /* unsure what DCB version introduces this, 3.0? */
6151 if (conf
& 0x100000)
6152 entry
->i2c_upper_default
= true;
6158 parse_dcb15_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
6159 uint32_t conn
, uint32_t conf
, struct dcb_entry
*entry
)
6161 switch (conn
& 0x0000000f) {
6163 entry
->type
= OUTPUT_ANALOG
;
6166 entry
->type
= OUTPUT_TV
;
6170 entry
->type
= OUTPUT_LVDS
;
6173 switch ((conn
& 0x000000f0) >> 4) {
6175 entry
->type
= OUTPUT_TMDS
;
6178 entry
->type
= OUTPUT_LVDS
;
6181 NV_ERROR(dev
, "Unknown DCB subtype 4/%d\n",
6182 (conn
& 0x000000f0) >> 4);
6187 NV_ERROR(dev
, "Unknown DCB type %d\n", conn
& 0x0000000f);
6191 entry
->i2c_index
= (conn
& 0x0003c000) >> 14;
6192 entry
->heads
= ((conn
& 0x001c0000) >> 18) + 1;
6193 entry
->or = entry
->heads
; /* same as heads, hopefully safe enough */
6194 entry
->location
= (conn
& 0x01e00000) >> 21;
6195 entry
->bus
= (conn
& 0x0e000000) >> 25;
6196 entry
->duallink_possible
= false;
6198 switch (entry
->type
) {
6200 entry
->crtconf
.maxfreq
= (conf
& 0xffff) * 10;
6203 entry
->tvconf
.has_component_output
= false;
6206 if ((conn
& 0x00003f00) != 0x10)
6207 entry
->lvdsconf
.use_straps_for_mode
= true;
6208 entry
->lvdsconf
.use_power_scripts
= true;
6217 static bool parse_dcb_entry(struct drm_device
*dev
, struct dcb_table
*dcb
,
6218 uint32_t conn
, uint32_t conf
)
6220 struct dcb_entry
*entry
= new_dcb_entry(dcb
);
6223 if (dcb
->version
>= 0x20)
6224 ret
= parse_dcb20_entry(dev
, dcb
, conn
, conf
, entry
);
6226 ret
= parse_dcb15_entry(dev
, dcb
, conn
, conf
, entry
);
6230 read_dcb_i2c_entry(dev
, dcb
->version
, dcb
->i2c_table
,
6231 entry
->i2c_index
, &dcb
->i2c
[entry
->i2c_index
]);
6237 void merge_like_dcb_entries(struct drm_device
*dev
, struct dcb_table
*dcb
)
6240 * DCB v2.0 lists each output combination separately.
6241 * Here we merge compatible entries to have fewer outputs, with
6245 int i
, newentries
= 0;
6247 for (i
= 0; i
< dcb
->entries
; i
++) {
6248 struct dcb_entry
*ient
= &dcb
->entry
[i
];
6251 for (j
= i
+ 1; j
< dcb
->entries
; j
++) {
6252 struct dcb_entry
*jent
= &dcb
->entry
[j
];
6254 if (jent
->type
== 100) /* already merged entry */
6257 /* merge heads field when all other fields the same */
6258 if (jent
->i2c_index
== ient
->i2c_index
&&
6259 jent
->type
== ient
->type
&&
6260 jent
->location
== ient
->location
&&
6261 jent
->or == ient
->or) {
6262 NV_TRACE(dev
, "Merging DCB entries %d and %d\n",
6264 ient
->heads
|= jent
->heads
;
6265 jent
->type
= 100; /* dummy value */
6270 /* Compact entries merged into others out of dcb */
6271 for (i
= 0; i
< dcb
->entries
; i
++) {
6272 if (dcb
->entry
[i
].type
== 100)
6275 if (newentries
!= i
) {
6276 dcb
->entry
[newentries
] = dcb
->entry
[i
];
6277 dcb
->entry
[newentries
].index
= newentries
;
6282 dcb
->entries
= newentries
;
6286 apply_dcb_encoder_quirks(struct drm_device
*dev
, int idx
, u32
*conn
, u32
*conf
)
6288 /* Dell Precision M6300
6289 * DCB entry 2: 02025312 00000010
6290 * DCB entry 3: 02026312 00000020
6292 * Identical, except apparently a different connector on a
6293 * different SOR link. Not a clue how we're supposed to know
6294 * which one is in use if it even shares an i2c line...
6296 * Ignore the connector on the second SOR link to prevent
6297 * nasty problems until this is sorted (assuming it's not a
6300 if (nv_match_device(dev
, 0x040d, 0x1028, 0x019b)) {
6301 if (*conn
== 0x02026312 && *conf
== 0x00000020)
6309 parse_dcb_table(struct drm_device
*dev
, struct nvbios
*bios
, bool twoHeads
)
6311 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6312 struct dcb_table
*dcb
= &bios
->dcb
;
6313 uint16_t dcbptr
= 0, i2ctabptr
= 0;
6315 uint8_t headerlen
= 0x4, entries
= DCB_MAX_NUM_ENTRIES
;
6316 bool configblock
= true;
6317 int recordlength
= 8, confofs
= 4;
6320 /* get the offset from 0x36 */
6321 if (dev_priv
->card_type
> NV_04
) {
6322 dcbptr
= ROM16(bios
->data
[0x36]);
6323 if (dcbptr
== 0x0000)
6324 NV_WARN(dev
, "No output data (DCB) found in BIOS\n");
6327 /* this situation likely means a really old card, pre DCB */
6328 if (dcbptr
== 0x0) {
6329 NV_INFO(dev
, "Assuming a CRT output exists\n");
6330 fabricate_vga_output(dcb
, LEGACY_I2C_CRT
, 1);
6332 if (nv04_tv_identify(dev
, bios
->legacy
.i2c_indices
.tv
) >= 0)
6333 fabricate_tv_output(dcb
, twoHeads
);
6338 dcbtable
= &bios
->data
[dcbptr
];
6340 /* get DCB version */
6341 dcb
->version
= dcbtable
[0];
6342 NV_TRACE(dev
, "Found Display Configuration Block version %d.%d\n",
6343 dcb
->version
>> 4, dcb
->version
& 0xf);
6345 if (dcb
->version
>= 0x20) { /* NV17+ */
6348 if (dcb
->version
>= 0x30) { /* NV40+ */
6349 headerlen
= dcbtable
[1];
6350 entries
= dcbtable
[2];
6351 recordlength
= dcbtable
[3];
6352 i2ctabptr
= ROM16(dcbtable
[4]);
6353 sig
= ROM32(dcbtable
[6]);
6354 dcb
->gpio_table_ptr
= ROM16(dcbtable
[10]);
6355 dcb
->connector_table_ptr
= ROM16(dcbtable
[20]);
6357 i2ctabptr
= ROM16(dcbtable
[2]);
6358 sig
= ROM32(dcbtable
[4]);
6362 if (sig
!= 0x4edcbdcb) {
6363 NV_ERROR(dev
, "Bad Display Configuration Block "
6364 "signature (%08X)\n", sig
);
6367 } else if (dcb
->version
>= 0x15) { /* some NV11 and NV20 */
6368 char sig
[8] = { 0 };
6370 strncpy(sig
, (char *)&dcbtable
[-7], 7);
6371 i2ctabptr
= ROM16(dcbtable
[2]);
6375 if (strcmp(sig
, "DEV_REC")) {
6376 NV_ERROR(dev
, "Bad Display Configuration Block "
6377 "signature (%s)\n", sig
);
6382 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6383 * has the same single (crt) entry, even when tv-out present, so
6384 * the conclusion is this version cannot really be used.
6385 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6386 * 5 entries, which are not specific to the card and so no use.
6387 * v1.2 does have an I2C table that read_dcb_i2c_table can
6388 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6389 * pointer, so use the indices parsed in parse_bmp_structure.
6390 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6392 NV_TRACEWARN(dev
, "No useful information in BIOS output table; "
6393 "adding all possible outputs\n");
6394 fabricate_vga_output(dcb
, LEGACY_I2C_CRT
, 1);
6397 * Attempt to detect TV before DVI because the test
6398 * for the former is more accurate and it rules the
6401 if (nv04_tv_identify(dev
,
6402 bios
->legacy
.i2c_indices
.tv
) >= 0)
6403 fabricate_tv_output(dcb
, twoHeads
);
6405 else if (bios
->tmds
.output0_script_ptr
||
6406 bios
->tmds
.output1_script_ptr
)
6407 fabricate_dvi_i_output(dcb
, twoHeads
);
6413 NV_WARN(dev
, "No pointer to DCB I2C port table\n");
6415 dcb
->i2c_table
= &bios
->data
[i2ctabptr
];
6416 if (dcb
->version
>= 0x30)
6417 dcb
->i2c_default_indices
= dcb
->i2c_table
[4];
6420 * Parse the "management" I2C bus, used for hardware
6421 * monitoring and some external TMDS transmitters.
6423 if (dcb
->version
>= 0x22) {
6424 int idx
= (dcb
->version
>= 0x40 ?
6425 dcb
->i2c_default_indices
& 0xf :
6428 read_dcb_i2c_entry(dev
, dcb
->version
, dcb
->i2c_table
,
6429 idx
, &dcb
->i2c
[idx
]);
6433 if (entries
> DCB_MAX_NUM_ENTRIES
)
6434 entries
= DCB_MAX_NUM_ENTRIES
;
6436 for (i
= 0; i
< entries
; i
++) {
6437 uint32_t connection
, config
= 0;
6439 connection
= ROM32(dcbtable
[headerlen
+ recordlength
* i
]);
6441 config
= ROM32(dcbtable
[headerlen
+ confofs
+ recordlength
* i
]);
6443 /* seen on an NV11 with DCB v1.5 */
6444 if (connection
== 0x00000000)
6447 /* seen on an NV17 with DCB v2.0 */
6448 if (connection
== 0xffffffff)
6451 if ((connection
& 0x0000000f) == 0x0000000f)
6454 if (!apply_dcb_encoder_quirks(dev
, i
, &connection
, &config
))
6457 NV_TRACEWARN(dev
, "Raw DCB entry %d: %08x %08x\n",
6458 dcb
->entries
, connection
, config
);
6460 if (!parse_dcb_entry(dev
, dcb
, connection
, config
))
6465 * apart for v2.1+ not being known for requiring merging, this
6466 * guarantees dcbent->index is the index of the entry in the rom image
6468 if (dcb
->version
< 0x21)
6469 merge_like_dcb_entries(dev
, dcb
);
6474 parse_dcb_gpio_table(bios
);
6475 parse_dcb_connector_table(bios
);
6480 fixup_legacy_connector(struct nvbios
*bios
)
6482 struct dcb_table
*dcb
= &bios
->dcb
;
6483 int i
, i2c
, i2c_conn
[DCB_MAX_NUM_I2C_ENTRIES
] = { };
6486 * DCB 3.0 also has the table in most cases, but there are some cards
6487 * where the table is filled with stub entries, and the DCB entriy
6488 * indices are all 0. We don't need the connector indices on pre-G80
6489 * chips (yet?) so limit the use to DCB 4.0 and above.
6491 if (dcb
->version
>= 0x40)
6494 dcb
->connector
.entries
= 0;
6497 * No known connector info before v3.0, so make it up. the rule here
6498 * is: anything on the same i2c bus is considered to be on the same
6499 * connector. any output without an associated i2c bus is assigned
6500 * its own unique connector index.
6502 for (i
= 0; i
< dcb
->entries
; i
++) {
6504 * Ignore the I2C index for on-chip TV-out, as there
6505 * are cards with bogus values (nv31m in bug 23212),
6506 * and it's otherwise useless.
6508 if (dcb
->entry
[i
].type
== OUTPUT_TV
&&
6509 dcb
->entry
[i
].location
== DCB_LOC_ON_CHIP
)
6510 dcb
->entry
[i
].i2c_index
= 0xf;
6511 i2c
= dcb
->entry
[i
].i2c_index
;
6513 if (i2c_conn
[i2c
]) {
6514 dcb
->entry
[i
].connector
= i2c_conn
[i2c
] - 1;
6518 dcb
->entry
[i
].connector
= dcb
->connector
.entries
++;
6520 i2c_conn
[i2c
] = dcb
->connector
.entries
;
6523 /* Fake the connector table as well as just connector indices */
6524 for (i
= 0; i
< dcb
->connector
.entries
; i
++) {
6525 dcb
->connector
.entry
[i
].index
= i
;
6526 dcb
->connector
.entry
[i
].type
= divine_connector_type(bios
, i
);
6527 dcb
->connector
.entry
[i
].gpio_tag
= 0xff;
6532 fixup_legacy_i2c(struct nvbios
*bios
)
6534 struct dcb_table
*dcb
= &bios
->dcb
;
6537 for (i
= 0; i
< dcb
->entries
; i
++) {
6538 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_CRT
)
6539 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.crt
;
6540 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_PANEL
)
6541 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.panel
;
6542 if (dcb
->entry
[i
].i2c_index
== LEGACY_I2C_TV
)
6543 dcb
->entry
[i
].i2c_index
= bios
->legacy
.i2c_indices
.tv
;
6547 static int load_nv17_hwsq_ucode_entry(struct drm_device
*dev
, struct nvbios
*bios
, uint16_t hwsq_offset
, int entry
)
6550 * The header following the "HWSQ" signature has the number of entries,
6551 * and the entry size
6553 * An entry consists of a dword to write to the sequencer control reg
6554 * (0x00001304), followed by the ucode bytes, written sequentially,
6555 * starting at reg 0x00001400
6558 uint8_t bytes_to_write
;
6559 uint16_t hwsq_entry_offset
;
6562 if (bios
->data
[hwsq_offset
] <= entry
) {
6563 NV_ERROR(dev
, "Too few entries in HW sequencer table for "
6564 "requested entry\n");
6568 bytes_to_write
= bios
->data
[hwsq_offset
+ 1];
6570 if (bytes_to_write
!= 36) {
6571 NV_ERROR(dev
, "Unknown HW sequencer entry size\n");
6575 NV_TRACE(dev
, "Loading NV17 power sequencing microcode\n");
6577 hwsq_entry_offset
= hwsq_offset
+ 2 + entry
* bytes_to_write
;
6579 /* set sequencer control */
6580 bios_wr32(bios
, 0x00001304, ROM32(bios
->data
[hwsq_entry_offset
]));
6581 bytes_to_write
-= 4;
6584 for (i
= 0; i
< bytes_to_write
; i
+= 4)
6585 bios_wr32(bios
, 0x00001400 + i
, ROM32(bios
->data
[hwsq_entry_offset
+ i
+ 4]));
6587 /* twiddle NV_PBUS_DEBUG_4 */
6588 bios_wr32(bios
, NV_PBUS_DEBUG_4
, bios_rd32(bios
, NV_PBUS_DEBUG_4
) | 0x18);
6593 static int load_nv17_hw_sequencer_ucode(struct drm_device
*dev
,
6594 struct nvbios
*bios
)
6597 * BMP based cards, from NV17, need a microcode loading to correctly
6598 * control the GPIO etc for LVDS panels
6600 * BIT based cards seem to do this directly in the init scripts
6602 * The microcode entries are found by the "HWSQ" signature.
6605 const uint8_t hwsq_signature
[] = { 'H', 'W', 'S', 'Q' };
6606 const int sz
= sizeof(hwsq_signature
);
6609 hwsq_offset
= findstr(bios
->data
, bios
->length
, hwsq_signature
, sz
);
6613 /* always use entry 0? */
6614 return load_nv17_hwsq_ucode_entry(dev
, bios
, hwsq_offset
+ sz
, 0);
6617 uint8_t *nouveau_bios_embedded_edid(struct drm_device
*dev
)
6619 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6620 struct nvbios
*bios
= &dev_priv
->vbios
;
6621 const uint8_t edid_sig
[] = {
6622 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6623 uint16_t offset
= 0;
6625 int searchlen
= NV_PROM_SIZE
;
6628 return bios
->fp
.edid
;
6631 newoffset
= findstr(&bios
->data
[offset
], searchlen
,
6635 offset
+= newoffset
;
6636 if (!nv_cksum(&bios
->data
[offset
], EDID1_LEN
))
6639 searchlen
-= offset
;
6643 NV_TRACE(dev
, "Found EDID in BIOS\n");
6645 return bios
->fp
.edid
= &bios
->data
[offset
];
6649 nouveau_bios_run_init_table(struct drm_device
*dev
, uint16_t table
,
6650 struct dcb_entry
*dcbent
)
6652 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6653 struct nvbios
*bios
= &dev_priv
->vbios
;
6654 struct init_exec iexec
= { true, false };
6656 mutex_lock(&bios
->lock
);
6657 bios
->display
.output
= dcbent
;
6658 parse_init_table(bios
, table
, &iexec
);
6659 bios
->display
.output
= NULL
;
6660 mutex_unlock(&bios
->lock
);
6663 static bool NVInitVBIOS(struct drm_device
*dev
)
6665 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6666 struct nvbios
*bios
= &dev_priv
->vbios
;
6668 memset(bios
, 0, sizeof(struct nvbios
));
6669 mutex_init(&bios
->lock
);
6672 if (!NVShadowVBIOS(dev
, bios
->data
))
6675 bios
->length
= NV_PROM_SIZE
;
6679 static int nouveau_parse_vbios_struct(struct drm_device
*dev
)
6681 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6682 struct nvbios
*bios
= &dev_priv
->vbios
;
6683 const uint8_t bit_signature
[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6684 const uint8_t bmp_signature
[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6687 offset
= findstr(bios
->data
, bios
->length
,
6688 bit_signature
, sizeof(bit_signature
));
6690 NV_TRACE(dev
, "BIT BIOS found\n");
6691 return parse_bit_structure(bios
, offset
+ 6);
6694 offset
= findstr(bios
->data
, bios
->length
,
6695 bmp_signature
, sizeof(bmp_signature
));
6697 NV_TRACE(dev
, "BMP BIOS found\n");
6698 return parse_bmp_structure(dev
, bios
, offset
);
6701 NV_ERROR(dev
, "No known BIOS signature found\n");
6706 nouveau_run_vbios_init(struct drm_device
*dev
)
6708 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6709 struct nvbios
*bios
= &dev_priv
->vbios
;
6712 /* Reset the BIOS head to 0. */
6713 bios
->state
.crtchead
= 0;
6715 if (bios
->major_version
< 5) /* BMP only */
6716 load_nv17_hw_sequencer_ucode(dev
, bios
);
6718 if (bios
->execute
) {
6719 bios
->fp
.last_script_invoc
= 0;
6720 bios
->fp
.lvds_init_run
= false;
6723 parse_init_tables(bios
);
6726 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6727 * parser will run this right after the init tables, the binary
6728 * driver appears to run it at some point later.
6730 if (bios
->some_script_ptr
) {
6731 struct init_exec iexec
= {true, false};
6733 NV_INFO(dev
, "Parsing VBIOS init table at offset 0x%04X\n",
6734 bios
->some_script_ptr
);
6735 parse_init_table(bios
, bios
->some_script_ptr
, &iexec
);
6738 if (dev_priv
->card_type
>= NV_50
) {
6739 for (i
= 0; i
< bios
->dcb
.entries
; i
++) {
6740 nouveau_bios_run_display_table(dev
,
6741 &bios
->dcb
.entry
[i
],
6750 nouveau_bios_i2c_devices_takedown(struct drm_device
*dev
)
6752 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6753 struct nvbios
*bios
= &dev_priv
->vbios
;
6754 struct dcb_i2c_entry
*entry
;
6757 entry
= &bios
->dcb
.i2c
[0];
6758 for (i
= 0; i
< DCB_MAX_NUM_I2C_ENTRIES
; i
++, entry
++)
6759 nouveau_i2c_fini(dev
, entry
);
6763 nouveau_bios_posted(struct drm_device
*dev
)
6765 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6768 if (dev_priv
->chipset
>= NV_50
) {
6769 if (NVReadVgaCrtc(dev
, 0, 0x00) == 0 &&
6770 NVReadVgaCrtc(dev
, 0, 0x1a) == 0)
6775 htotal
= NVReadVgaCrtc(dev
, 0, 0x06);
6776 htotal
|= (NVReadVgaCrtc(dev
, 0, 0x07) & 0x01) << 8;
6777 htotal
|= (NVReadVgaCrtc(dev
, 0, 0x07) & 0x20) << 4;
6778 htotal
|= (NVReadVgaCrtc(dev
, 0, 0x25) & 0x01) << 10;
6779 htotal
|= (NVReadVgaCrtc(dev
, 0, 0x41) & 0x01) << 11;
6781 return (htotal
!= 0);
6785 nouveau_bios_init(struct drm_device
*dev
)
6787 struct drm_nouveau_private
*dev_priv
= dev
->dev_private
;
6788 struct nvbios
*bios
= &dev_priv
->vbios
;
6791 if (!NVInitVBIOS(dev
))
6794 ret
= nouveau_parse_vbios_struct(dev
);
6798 ret
= parse_dcb_table(dev
, bios
, nv_two_heads(dev
));
6802 fixup_legacy_i2c(bios
);
6803 fixup_legacy_connector(bios
);
6805 if (!bios
->major_version
) /* we don't run version 0 bios */
6808 /* init script execution disabled */
6809 bios
->execute
= false;
6811 /* ... unless card isn't POSTed already */
6812 if (!nouveau_bios_posted(dev
)) {
6813 NV_INFO(dev
, "Adaptor not initialised, "
6814 "running VBIOS init tables.\n");
6815 bios
->execute
= true;
6818 ret
= nouveau_run_vbios_init(dev
);
6822 /* feature_byte on BMP is poor, but init always sets CR4B */
6823 if (bios
->major_version
< 5)
6824 bios
->is_mobile
= NVReadVgaCrtc(dev
, 0, NV_CIO_CRE_4B
) & 0x40;
6826 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6827 if (bios
->is_mobile
|| bios
->major_version
>= 5)
6828 ret
= parse_fp_mode_table(dev
, bios
);
6830 /* allow subsequent scripts to execute */
6831 bios
->execute
= true;
6837 nouveau_bios_takedown(struct drm_device
*dev
)
6839 nouveau_bios_i2c_devices_takedown(dev
);