3 * Purpose: Generic MCA handling layer
5 * Updated for latest kernel
6 * Copyright (C) 2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Dell Inc.
10 * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
12 * Copyright (C) 2002 Intel
13 * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
15 * Copyright (C) 2001 Intel
16 * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
18 * Copyright (C) 2000 Intel
19 * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
21 * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22 * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
24 * 03/04/15 D. Mosberger Added INIT backtrace support.
25 * 02/03/25 M. Domsch GUID cleanups
27 * 02/01/04 J. Hall Aligned MCA stack to 16 bytes, added platform vs. CPU
28 * error flag, set SAL default return values, changed
29 * error record structure to linked list, added init call
30 * to sal_get_state_info_size().
32 * 01/01/03 F. Lewis Added setup of CMCI and CPEI IRQs, logging of corrected
33 * platform errors, completed code for logging of
34 * corrected & uncorrected machine check errors, and
35 * updated for conformance with Nov. 2000 revision of the
37 * 00/03/29 C. Fleckenstein Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38 * added min save state dump, added INIT handler.
40 * 2003-12-08 Keith Owens <kaos@sgi.com>
41 * smp_call_function() must not be called from interrupt context (can
42 * deadlock on tasklist_lock). Use keventd to call smp_call_function().
44 * 2004-02-01 Keith Owens <kaos@sgi.com>
45 * Avoid deadlock when using printk() for MCA and INIT records.
46 * Delete all record printing code, moved to salinfo_decode in user space.
47 * Mark variables and functions static where possible.
48 * Delete dead variables and functions.
49 * Reorder to remove the need for forward declarations and to consolidate
52 * 2005-08-12 Keith Owens <kaos@sgi.com>
53 * Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
55 * 2005-10-07 Keith Owens <kaos@sgi.com>
56 * Add notify_die() hooks.
58 #include <linux/config.h>
59 #include <linux/types.h>
60 #include <linux/init.h>
61 #include <linux/sched.h>
62 #include <linux/interrupt.h>
63 #include <linux/irq.h>
64 #include <linux/smp_lock.h>
65 #include <linux/bootmem.h>
66 #include <linux/acpi.h>
67 #include <linux/timer.h>
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/smp.h>
71 #include <linux/workqueue.h>
73 #include <asm/delay.h>
74 #include <asm/kdebug.h>
75 #include <asm/machvec.h>
76 #include <asm/meminit.h>
78 #include <asm/ptrace.h>
79 #include <asm/system.h>
84 #include <asm/hw_irq.h>
89 #if defined(IA64_MCA_DEBUG_INFO)
90 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
92 # define IA64_MCA_DEBUG(fmt...)
95 /* Used by mca_asm.S */
96 u32 ia64_mca_serialize
;
97 DEFINE_PER_CPU(u64
, ia64_mca_data
); /* == __per_cpu_mca[smp_processor_id()] */
98 DEFINE_PER_CPU(u64
, ia64_mca_per_cpu_pte
); /* PTE to map per-CPU area */
99 DEFINE_PER_CPU(u64
, ia64_mca_pal_pte
); /* PTE to map PAL code */
100 DEFINE_PER_CPU(u64
, ia64_mca_pal_base
); /* vaddr PAL code granule */
102 unsigned long __per_cpu_mca
[NR_CPUS
];
105 extern void ia64_os_init_dispatch_monarch (void);
106 extern void ia64_os_init_dispatch_slave (void);
108 static int monarch_cpu
= -1;
110 static ia64_mc_info_t ia64_mc_info
;
112 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
113 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
114 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
115 #define CPE_HISTORY_LENGTH 5
116 #define CMC_HISTORY_LENGTH 5
118 static struct timer_list cpe_poll_timer
;
119 static struct timer_list cmc_poll_timer
;
121 * This variable tells whether we are currently in polling mode.
122 * Start with this in the wrong state so we won't play w/ timers
123 * before the system is ready.
125 static int cmc_polling_enabled
= 1;
128 * Clearing this variable prevents CPE polling from getting activated
129 * in mca_late_init. Use it if your system doesn't provide a CPEI,
130 * but encounters problems retrieving CPE logs. This should only be
131 * necessary for debugging.
133 static int cpe_poll_enabled
= 1;
135 extern void salinfo_log_wakeup(int type
, u8
*buffer
, u64 size
, int irqsafe
);
137 static int mca_init __initdata
;
141 ia64_mca_spin(const char *func
)
143 printk(KERN_EMERG
"%s: spinning here, not returning to SAL\n", func
);
148 * IA64_MCA log support
150 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
151 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
153 typedef struct ia64_state_log_s
157 unsigned long isl_count
;
158 ia64_err_rec_t
*isl_log
[IA64_MAX_LOGS
]; /* need space to store header + error log */
161 static ia64_state_log_t ia64_state_log
[IA64_MAX_LOG_TYPES
];
163 #define IA64_LOG_ALLOCATE(it, size) \
164 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
165 (ia64_err_rec_t *)alloc_bootmem(size); \
166 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
167 (ia64_err_rec_t *)alloc_bootmem(size);}
168 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
169 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
170 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
171 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
172 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
173 #define IA64_LOG_INDEX_INC(it) \
174 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
175 ia64_state_log[it].isl_count++;}
176 #define IA64_LOG_INDEX_DEC(it) \
177 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
178 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
179 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
180 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
184 * Reset the OS ia64 log buffer
185 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
189 ia64_log_init(int sal_info_type
)
193 IA64_LOG_NEXT_INDEX(sal_info_type
) = 0;
194 IA64_LOG_LOCK_INIT(sal_info_type
);
196 // SAL will tell us the maximum size of any error record of this type
197 max_size
= ia64_sal_get_state_info_size(sal_info_type
);
199 /* alloc_bootmem() doesn't like zero-sized allocations! */
202 // set up OS data structures to hold error info
203 IA64_LOG_ALLOCATE(sal_info_type
, max_size
);
204 memset(IA64_LOG_CURR_BUFFER(sal_info_type
), 0, max_size
);
205 memset(IA64_LOG_NEXT_BUFFER(sal_info_type
), 0, max_size
);
211 * Get the current MCA log from SAL and copy it into the OS log buffer.
213 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
214 * irq_safe whether you can use printk at this point
215 * Outputs : size (total record length)
216 * *buffer (ptr to error record)
220 ia64_log_get(int sal_info_type
, u8
**buffer
, int irq_safe
)
222 sal_log_record_header_t
*log_buffer
;
226 IA64_LOG_LOCK(sal_info_type
);
228 /* Get the process state information */
229 log_buffer
= IA64_LOG_NEXT_BUFFER(sal_info_type
);
231 total_len
= ia64_sal_get_state_info(sal_info_type
, (u64
*)log_buffer
);
234 IA64_LOG_INDEX_INC(sal_info_type
);
235 IA64_LOG_UNLOCK(sal_info_type
);
237 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
238 "Record length = %ld\n", __FUNCTION__
, sal_info_type
, total_len
);
240 *buffer
= (u8
*) log_buffer
;
243 IA64_LOG_UNLOCK(sal_info_type
);
249 * ia64_mca_log_sal_error_record
251 * This function retrieves a specified error record type from SAL
252 * and wakes up any processes waiting for error records.
254 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
255 * FIXME: remove MCA and irq_safe.
258 ia64_mca_log_sal_error_record(int sal_info_type
)
261 sal_log_record_header_t
*rh
;
263 int irq_safe
= sal_info_type
!= SAL_INFO_TYPE_MCA
;
264 #ifdef IA64_MCA_DEBUG_INFO
265 static const char * const rec_name
[] = { "MCA", "INIT", "CMC", "CPE" };
268 size
= ia64_log_get(sal_info_type
, &buffer
, irq_safe
);
272 salinfo_log_wakeup(sal_info_type
, buffer
, size
, irq_safe
);
275 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
277 sal_info_type
< ARRAY_SIZE(rec_name
) ? rec_name
[sal_info_type
] : "UNKNOWN");
279 /* Clear logs from corrected errors in case there's no user-level logger */
280 rh
= (sal_log_record_header_t
*)buffer
;
281 if (rh
->severity
== sal_log_severity_corrected
)
282 ia64_sal_clear_state_info(sal_info_type
);
287 * See if the MCA surfaced in an instruction range
288 * that has been tagged as recoverable.
291 * first First address range to check
292 * last Last address range to check
293 * ip Instruction pointer, address we are looking for
296 * 1 on Success (in the table)/ 0 on Failure (not in the table)
299 search_mca_table (const struct mca_table_entry
*first
,
300 const struct mca_table_entry
*last
,
303 const struct mca_table_entry
*curr
;
304 u64 curr_start
, curr_end
;
307 while (curr
<= last
) {
308 curr_start
= (u64
) &curr
->start_addr
+ curr
->start_addr
;
309 curr_end
= (u64
) &curr
->end_addr
+ curr
->end_addr
;
311 if ((ip
>= curr_start
) && (ip
<= curr_end
)) {
319 /* Given an address, look for it in the mca tables. */
320 int mca_recover_range(unsigned long addr
)
322 extern struct mca_table_entry __start___mca_table
[];
323 extern struct mca_table_entry __stop___mca_table
[];
325 return search_mca_table(__start___mca_table
, __stop___mca_table
-1, addr
);
327 EXPORT_SYMBOL_GPL(mca_recover_range
);
332 int ia64_cpe_irq
= -1;
335 ia64_mca_cpe_int_handler (int cpe_irq
, void *arg
, struct pt_regs
*ptregs
)
337 static unsigned long cpe_history
[CPE_HISTORY_LENGTH
];
339 static DEFINE_SPINLOCK(cpe_history_lock
);
341 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
342 __FUNCTION__
, cpe_irq
, smp_processor_id());
344 /* SAL spec states this should run w/ interrupts enabled */
347 /* Get the CPE error record and log it */
348 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE
);
350 spin_lock(&cpe_history_lock
);
351 if (!cpe_poll_enabled
&& cpe_vector
>= 0) {
353 int i
, count
= 1; /* we know 1 happened now */
354 unsigned long now
= jiffies
;
356 for (i
= 0; i
< CPE_HISTORY_LENGTH
; i
++) {
357 if (now
- cpe_history
[i
] <= HZ
)
361 IA64_MCA_DEBUG(KERN_INFO
"CPE threshold %d/%d\n", count
, CPE_HISTORY_LENGTH
);
362 if (count
>= CPE_HISTORY_LENGTH
) {
364 cpe_poll_enabled
= 1;
365 spin_unlock(&cpe_history_lock
);
366 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR
));
369 * Corrected errors will still be corrected, but
370 * make sure there's a log somewhere that indicates
371 * something is generating more than we can handle.
373 printk(KERN_WARNING
"WARNING: Switching to polling CPE handler; error records may be lost\n");
375 mod_timer(&cpe_poll_timer
, jiffies
+ MIN_CPE_POLL_INTERVAL
);
377 /* lock already released, get out now */
380 cpe_history
[index
++] = now
;
381 if (index
== CPE_HISTORY_LENGTH
)
385 spin_unlock(&cpe_history_lock
);
389 #endif /* CONFIG_ACPI */
393 * ia64_mca_register_cpev
395 * Register the corrected platform error vector with SAL.
398 * cpev Corrected Platform Error Vector number
404 ia64_mca_register_cpev (int cpev
)
406 /* Register the CPE interrupt vector with SAL */
407 struct ia64_sal_retval isrv
;
409 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT
, SAL_MC_PARAM_MECHANISM_INT
, cpev
, 0, 0);
411 printk(KERN_ERR
"Failed to register Corrected Platform "
412 "Error interrupt vector with SAL (status %ld)\n", isrv
.status
);
416 IA64_MCA_DEBUG("%s: corrected platform error "
417 "vector %#x registered\n", __FUNCTION__
, cpev
);
419 #endif /* CONFIG_ACPI */
422 * ia64_mca_cmc_vector_setup
424 * Setup the corrected machine check vector register in the processor.
425 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
426 * This function is invoked on a per-processor basis.
435 ia64_mca_cmc_vector_setup (void)
439 cmcv
.cmcv_regval
= 0;
440 cmcv
.cmcv_mask
= 1; /* Mask/disable interrupt at first */
441 cmcv
.cmcv_vector
= IA64_CMC_VECTOR
;
442 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
444 IA64_MCA_DEBUG("%s: CPU %d corrected "
445 "machine check vector %#x registered.\n",
446 __FUNCTION__
, smp_processor_id(), IA64_CMC_VECTOR
);
448 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
449 __FUNCTION__
, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV
));
453 * ia64_mca_cmc_vector_disable
455 * Mask the corrected machine check vector register in the processor.
456 * This function is invoked on a per-processor basis.
465 ia64_mca_cmc_vector_disable (void *dummy
)
469 cmcv
.cmcv_regval
= ia64_getreg(_IA64_REG_CR_CMCV
);
471 cmcv
.cmcv_mask
= 1; /* Mask/disable interrupt */
472 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
474 IA64_MCA_DEBUG("%s: CPU %d corrected "
475 "machine check vector %#x disabled.\n",
476 __FUNCTION__
, smp_processor_id(), cmcv
.cmcv_vector
);
480 * ia64_mca_cmc_vector_enable
482 * Unmask the corrected machine check vector register in the processor.
483 * This function is invoked on a per-processor basis.
492 ia64_mca_cmc_vector_enable (void *dummy
)
496 cmcv
.cmcv_regval
= ia64_getreg(_IA64_REG_CR_CMCV
);
498 cmcv
.cmcv_mask
= 0; /* Unmask/enable interrupt */
499 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
501 IA64_MCA_DEBUG("%s: CPU %d corrected "
502 "machine check vector %#x enabled.\n",
503 __FUNCTION__
, smp_processor_id(), cmcv
.cmcv_vector
);
507 * ia64_mca_cmc_vector_disable_keventd
509 * Called via keventd (smp_call_function() is not safe in interrupt context) to
510 * disable the cmc interrupt vector.
513 ia64_mca_cmc_vector_disable_keventd(void *unused
)
515 on_each_cpu(ia64_mca_cmc_vector_disable
, NULL
, 1, 0);
519 * ia64_mca_cmc_vector_enable_keventd
521 * Called via keventd (smp_call_function() is not safe in interrupt context) to
522 * enable the cmc interrupt vector.
525 ia64_mca_cmc_vector_enable_keventd(void *unused
)
527 on_each_cpu(ia64_mca_cmc_vector_enable
, NULL
, 1, 0);
533 * Send an inter-cpu interrupt to wake-up a particular cpu
534 * and mark that cpu to be out of rendez.
540 ia64_mca_wakeup(int cpu
)
542 platform_send_ipi(cpu
, IA64_MCA_WAKEUP_VECTOR
, IA64_IPI_DM_INT
, 0);
543 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
548 * ia64_mca_wakeup_all
550 * Wakeup all the cpus which have rendez'ed previously.
556 ia64_mca_wakeup_all(void)
560 /* Clear the Rendez checkin flag for all cpus */
561 for_each_online_cpu(cpu
) {
562 if (ia64_mc_info
.imi_rendez_checkin
[cpu
] == IA64_MCA_RENDEZ_CHECKIN_DONE
)
563 ia64_mca_wakeup(cpu
);
569 * ia64_mca_rendez_interrupt_handler
571 * This is handler used to put slave processors into spinloop
572 * while the monarch processor does the mca handling and later
573 * wake each slave up once the monarch is done.
579 ia64_mca_rendez_int_handler(int rendez_irq
, void *arg
, struct pt_regs
*regs
)
582 int cpu
= smp_processor_id();
584 /* Mask all interrupts */
585 local_irq_save(flags
);
586 if (notify_die(DIE_MCA_RENDZVOUS_ENTER
, "MCA", regs
, 0, 0, 0)
588 ia64_mca_spin(__FUNCTION__
);
590 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_DONE
;
591 /* Register with the SAL monarch that the slave has
594 ia64_sal_mc_rendez();
596 if (notify_die(DIE_MCA_RENDZVOUS_PROCESS
, "MCA", regs
, 0, 0, 0)
598 ia64_mca_spin(__FUNCTION__
);
600 /* Wait for the monarch cpu to exit. */
601 while (monarch_cpu
!= -1)
602 cpu_relax(); /* spin until monarch leaves */
604 if (notify_die(DIE_MCA_RENDZVOUS_LEAVE
, "MCA", regs
, 0, 0, 0)
606 ia64_mca_spin(__FUNCTION__
);
608 /* Enable all interrupts */
609 local_irq_restore(flags
);
614 * ia64_mca_wakeup_int_handler
616 * The interrupt handler for processing the inter-cpu interrupt to the
617 * slave cpu which was spinning in the rendez loop.
618 * Since this spinning is done by turning off the interrupts and
619 * polling on the wakeup-interrupt bit in the IRR, there is
620 * nothing useful to be done in the handler.
622 * Inputs : wakeup_irq (Wakeup-interrupt bit)
623 * arg (Interrupt handler specific argument)
624 * ptregs (Exception frame at the time of the interrupt)
629 ia64_mca_wakeup_int_handler(int wakeup_irq
, void *arg
, struct pt_regs
*ptregs
)
634 /* Function pointer for extra MCA recovery */
635 int (*ia64_mca_ucmc_extension
)
636 (void*,struct ia64_sal_os_state
*)
640 ia64_reg_MCA_extension(int (*fn
)(void *, struct ia64_sal_os_state
*))
642 if (ia64_mca_ucmc_extension
)
645 ia64_mca_ucmc_extension
= fn
;
650 ia64_unreg_MCA_extension(void)
652 if (ia64_mca_ucmc_extension
)
653 ia64_mca_ucmc_extension
= NULL
;
656 EXPORT_SYMBOL(ia64_reg_MCA_extension
);
657 EXPORT_SYMBOL(ia64_unreg_MCA_extension
);
661 copy_reg(const u64
*fr
, u64 fnat
, u64
*tr
, u64
*tnat
)
663 u64 fslot
, tslot
, nat
;
665 fslot
= ((unsigned long)fr
>> 3) & 63;
666 tslot
= ((unsigned long)tr
>> 3) & 63;
667 *tnat
&= ~(1UL << tslot
);
668 nat
= (fnat
>> fslot
) & 1;
669 *tnat
|= (nat
<< tslot
);
672 /* Change the comm field on the MCA/INT task to include the pid that
673 * was interrupted, it makes for easier debugging. If that pid was 0
674 * (swapper or nested MCA/INIT) then use the start of the previous comm
675 * field suffixed with its cpu.
679 ia64_mca_modify_comm(const task_t
*previous_current
)
681 char *p
, comm
[sizeof(current
->comm
)];
682 if (previous_current
->pid
)
683 snprintf(comm
, sizeof(comm
), "%s %d",
684 current
->comm
, previous_current
->pid
);
687 if ((p
= strchr(previous_current
->comm
, ' ')))
688 l
= p
- previous_current
->comm
;
690 l
= strlen(previous_current
->comm
);
691 snprintf(comm
, sizeof(comm
), "%s %*s %d",
692 current
->comm
, l
, previous_current
->comm
,
693 task_thread_info(previous_current
)->cpu
);
695 memcpy(current
->comm
, comm
, sizeof(current
->comm
));
698 /* On entry to this routine, we are running on the per cpu stack, see
699 * mca_asm.h. The original stack has not been touched by this event. Some of
700 * the original stack's registers will be in the RBS on this stack. This stack
701 * also contains a partial pt_regs and switch_stack, the rest of the data is in
704 * The first thing to do is modify the original stack to look like a blocked
705 * task so we can run backtrace on the original task. Also mark the per cpu
706 * stack as current to ensure that we use the correct task state, it also means
707 * that we can do backtrace on the MCA/INIT handler code itself.
711 ia64_mca_modify_original_stack(struct pt_regs
*regs
,
712 const struct switch_stack
*sw
,
713 struct ia64_sal_os_state
*sos
,
718 extern char ia64_leave_kernel
[]; /* Need asm address, not function descriptor */
719 const pal_min_state_area_t
*ms
= sos
->pal_min_state
;
720 task_t
*previous_current
;
721 struct pt_regs
*old_regs
;
722 struct switch_stack
*old_sw
;
723 unsigned size
= sizeof(struct pt_regs
) +
724 sizeof(struct switch_stack
) + 16;
725 u64
*old_bspstore
, *old_bsp
;
726 u64
*new_bspstore
, *new_bsp
;
727 u64 old_unat
, old_rnat
, new_rnat
, nat
;
728 u64 slots
, loadrs
= regs
->loadrs
;
729 u64 r12
= ms
->pmsa_gr
[12-1], r13
= ms
->pmsa_gr
[13-1];
730 u64 ar_bspstore
= regs
->ar_bspstore
;
731 u64 ar_bsp
= regs
->ar_bspstore
+ (loadrs
>> 16);
734 int cpu
= smp_processor_id();
736 previous_current
= curr_task(cpu
);
737 set_curr_task(cpu
, current
);
738 if ((p
= strchr(current
->comm
, ' ')))
741 /* Best effort attempt to cope with MCA/INIT delivered while in
744 regs
->cr_ipsr
= ms
->pmsa_ipsr
;
745 if (ia64_psr(regs
)->dt
== 0) {
757 if (ia64_psr(regs
)->rt
== 0) {
770 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
771 * have been copied to the old stack, the old stack may fail the
772 * validation tests below. So ia64_old_stack() must restore the dirty
773 * registers from the new stack. The old and new bspstore probably
774 * have different alignments, so loadrs calculated on the old bsp
775 * cannot be used to restore from the new bsp. Calculate a suitable
776 * loadrs for the new stack and save it in the new pt_regs, where
777 * ia64_old_stack() can get it.
779 old_bspstore
= (u64
*)ar_bspstore
;
780 old_bsp
= (u64
*)ar_bsp
;
781 slots
= ia64_rse_num_regs(old_bspstore
, old_bsp
);
782 new_bspstore
= (u64
*)((u64
)current
+ IA64_RBS_OFFSET
);
783 new_bsp
= ia64_rse_skip_regs(new_bspstore
, slots
);
784 regs
->loadrs
= (new_bsp
- new_bspstore
) * 8 << 16;
786 /* Verify the previous stack state before we change it */
787 if (user_mode(regs
)) {
788 msg
= "occurred in user space";
789 /* previous_current is guaranteed to be valid when the task was
790 * in user space, so ...
792 ia64_mca_modify_comm(previous_current
);
796 if (!mca_recover_range(ms
->pmsa_iip
)) {
797 if (r13
!= sos
->prev_IA64_KR_CURRENT
) {
798 msg
= "inconsistent previous current and r13";
801 if ((r12
- r13
) >= KERNEL_STACK_SIZE
) {
802 msg
= "inconsistent r12 and r13";
805 if ((ar_bspstore
- r13
) >= KERNEL_STACK_SIZE
) {
806 msg
= "inconsistent ar.bspstore and r13";
811 msg
= "old_bspstore is in the wrong region";
814 if ((ar_bsp
- r13
) >= KERNEL_STACK_SIZE
) {
815 msg
= "inconsistent ar.bsp and r13";
818 size
+= (ia64_rse_skip_regs(old_bspstore
, slots
) - old_bspstore
) * 8;
819 if (ar_bspstore
+ size
> r12
) {
820 msg
= "no room for blocked state";
825 ia64_mca_modify_comm(previous_current
);
827 /* Make the original task look blocked. First stack a struct pt_regs,
828 * describing the state at the time of interrupt. mca_asm.S built a
829 * partial pt_regs, copy it and fill in the blanks using minstate.
831 p
= (char *)r12
- sizeof(*regs
);
832 old_regs
= (struct pt_regs
*)p
;
833 memcpy(old_regs
, regs
, sizeof(*regs
));
834 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
835 * pmsa_{xip,xpsr,xfs}
837 if (ia64_psr(regs
)->ic
) {
838 old_regs
->cr_iip
= ms
->pmsa_iip
;
839 old_regs
->cr_ipsr
= ms
->pmsa_ipsr
;
840 old_regs
->cr_ifs
= ms
->pmsa_ifs
;
842 old_regs
->cr_iip
= ms
->pmsa_xip
;
843 old_regs
->cr_ipsr
= ms
->pmsa_xpsr
;
844 old_regs
->cr_ifs
= ms
->pmsa_xfs
;
846 old_regs
->pr
= ms
->pmsa_pr
;
847 old_regs
->b0
= ms
->pmsa_br0
;
848 old_regs
->loadrs
= loadrs
;
849 old_regs
->ar_rsc
= ms
->pmsa_rsc
;
850 old_unat
= old_regs
->ar_unat
;
851 copy_reg(&ms
->pmsa_gr
[1-1], ms
->pmsa_nat_bits
, &old_regs
->r1
, &old_unat
);
852 copy_reg(&ms
->pmsa_gr
[2-1], ms
->pmsa_nat_bits
, &old_regs
->r2
, &old_unat
);
853 copy_reg(&ms
->pmsa_gr
[3-1], ms
->pmsa_nat_bits
, &old_regs
->r3
, &old_unat
);
854 copy_reg(&ms
->pmsa_gr
[8-1], ms
->pmsa_nat_bits
, &old_regs
->r8
, &old_unat
);
855 copy_reg(&ms
->pmsa_gr
[9-1], ms
->pmsa_nat_bits
, &old_regs
->r9
, &old_unat
);
856 copy_reg(&ms
->pmsa_gr
[10-1], ms
->pmsa_nat_bits
, &old_regs
->r10
, &old_unat
);
857 copy_reg(&ms
->pmsa_gr
[11-1], ms
->pmsa_nat_bits
, &old_regs
->r11
, &old_unat
);
858 copy_reg(&ms
->pmsa_gr
[12-1], ms
->pmsa_nat_bits
, &old_regs
->r12
, &old_unat
);
859 copy_reg(&ms
->pmsa_gr
[13-1], ms
->pmsa_nat_bits
, &old_regs
->r13
, &old_unat
);
860 copy_reg(&ms
->pmsa_gr
[14-1], ms
->pmsa_nat_bits
, &old_regs
->r14
, &old_unat
);
861 copy_reg(&ms
->pmsa_gr
[15-1], ms
->pmsa_nat_bits
, &old_regs
->r15
, &old_unat
);
862 if (ia64_psr(old_regs
)->bn
)
863 bank
= ms
->pmsa_bank1_gr
;
865 bank
= ms
->pmsa_bank0_gr
;
866 copy_reg(&bank
[16-16], ms
->pmsa_nat_bits
, &old_regs
->r16
, &old_unat
);
867 copy_reg(&bank
[17-16], ms
->pmsa_nat_bits
, &old_regs
->r17
, &old_unat
);
868 copy_reg(&bank
[18-16], ms
->pmsa_nat_bits
, &old_regs
->r18
, &old_unat
);
869 copy_reg(&bank
[19-16], ms
->pmsa_nat_bits
, &old_regs
->r19
, &old_unat
);
870 copy_reg(&bank
[20-16], ms
->pmsa_nat_bits
, &old_regs
->r20
, &old_unat
);
871 copy_reg(&bank
[21-16], ms
->pmsa_nat_bits
, &old_regs
->r21
, &old_unat
);
872 copy_reg(&bank
[22-16], ms
->pmsa_nat_bits
, &old_regs
->r22
, &old_unat
);
873 copy_reg(&bank
[23-16], ms
->pmsa_nat_bits
, &old_regs
->r23
, &old_unat
);
874 copy_reg(&bank
[24-16], ms
->pmsa_nat_bits
, &old_regs
->r24
, &old_unat
);
875 copy_reg(&bank
[25-16], ms
->pmsa_nat_bits
, &old_regs
->r25
, &old_unat
);
876 copy_reg(&bank
[26-16], ms
->pmsa_nat_bits
, &old_regs
->r26
, &old_unat
);
877 copy_reg(&bank
[27-16], ms
->pmsa_nat_bits
, &old_regs
->r27
, &old_unat
);
878 copy_reg(&bank
[28-16], ms
->pmsa_nat_bits
, &old_regs
->r28
, &old_unat
);
879 copy_reg(&bank
[29-16], ms
->pmsa_nat_bits
, &old_regs
->r29
, &old_unat
);
880 copy_reg(&bank
[30-16], ms
->pmsa_nat_bits
, &old_regs
->r30
, &old_unat
);
881 copy_reg(&bank
[31-16], ms
->pmsa_nat_bits
, &old_regs
->r31
, &old_unat
);
883 /* Next stack a struct switch_stack. mca_asm.S built a partial
884 * switch_stack, copy it and fill in the blanks using pt_regs and
887 * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
888 * ar.pfs is set to 0.
890 * unwind.c::unw_unwind() does special processing for interrupt frames.
891 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
892 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not
893 * that this is documented, of course. Set PRED_NON_SYSCALL in the
894 * switch_stack on the original stack so it will unwind correctly when
895 * unwind.c reads pt_regs.
897 * thread.ksp is updated to point to the synthesized switch_stack.
899 p
-= sizeof(struct switch_stack
);
900 old_sw
= (struct switch_stack
*)p
;
901 memcpy(old_sw
, sw
, sizeof(*sw
));
902 old_sw
->caller_unat
= old_unat
;
903 old_sw
->ar_fpsr
= old_regs
->ar_fpsr
;
904 copy_reg(&ms
->pmsa_gr
[4-1], ms
->pmsa_nat_bits
, &old_sw
->r4
, &old_unat
);
905 copy_reg(&ms
->pmsa_gr
[5-1], ms
->pmsa_nat_bits
, &old_sw
->r5
, &old_unat
);
906 copy_reg(&ms
->pmsa_gr
[6-1], ms
->pmsa_nat_bits
, &old_sw
->r6
, &old_unat
);
907 copy_reg(&ms
->pmsa_gr
[7-1], ms
->pmsa_nat_bits
, &old_sw
->r7
, &old_unat
);
908 old_sw
->b0
= (u64
)ia64_leave_kernel
;
909 old_sw
->b1
= ms
->pmsa_br1
;
911 old_sw
->ar_unat
= old_unat
;
912 old_sw
->pr
= old_regs
->pr
| (1UL << PRED_NON_SYSCALL
);
913 previous_current
->thread
.ksp
= (u64
)p
- 16;
915 /* Finally copy the original stack's registers back to its RBS.
916 * Registers from ar.bspstore through ar.bsp at the time of the event
917 * are in the current RBS, copy them back to the original stack. The
918 * copy must be done register by register because the original bspstore
919 * and the current one have different alignments, so the saved RNAT
920 * data occurs at different places.
922 * mca_asm does cover, so the old_bsp already includes all registers at
923 * the time of MCA/INIT. It also does flushrs, so all registers before
924 * this function have been written to backing store on the MCA/INIT
927 new_rnat
= ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore
));
928 old_rnat
= regs
->ar_rnat
;
930 if (ia64_rse_is_rnat_slot(new_bspstore
)) {
931 new_rnat
= ia64_get_rnat(new_bspstore
++);
933 if (ia64_rse_is_rnat_slot(old_bspstore
)) {
934 *old_bspstore
++ = old_rnat
;
937 nat
= (new_rnat
>> ia64_rse_slot_num(new_bspstore
)) & 1UL;
938 old_rnat
&= ~(1UL << ia64_rse_slot_num(old_bspstore
));
939 old_rnat
|= (nat
<< ia64_rse_slot_num(old_bspstore
));
940 *old_bspstore
++ = *new_bspstore
++;
942 old_sw
->ar_bspstore
= (unsigned long)old_bspstore
;
943 old_sw
->ar_rnat
= old_rnat
;
945 sos
->prev_task
= previous_current
;
946 return previous_current
;
949 printk(KERN_INFO
"cpu %d, %s %s, original stack not modified\n",
950 smp_processor_id(), type
, msg
);
951 return previous_current
;
954 /* The monarch/slave interaction is based on monarch_cpu and requires that all
955 * slaves have entered rendezvous before the monarch leaves. If any cpu has
956 * not entered rendezvous yet then wait a bit. The assumption is that any
957 * slave that has not rendezvoused after a reasonable time is never going to do
958 * so. In this context, slave includes cpus that respond to the MCA rendezvous
959 * interrupt, as well as cpus that receive the INIT slave event.
963 ia64_wait_for_slaves(int monarch
)
965 int c
, wait
= 0, missing
= 0;
966 for_each_online_cpu(c
) {
969 if (ia64_mc_info
.imi_rendez_checkin
[c
] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE
) {
970 udelay(1000); /* short wait first */
977 for_each_online_cpu(c
) {
980 if (ia64_mc_info
.imi_rendez_checkin
[c
] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE
) {
981 udelay(5*1000000); /* wait 5 seconds for slaves (arbitrary) */
982 if (ia64_mc_info
.imi_rendez_checkin
[c
] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE
)
989 printk(KERN_INFO
"OS MCA slave did not rendezvous on cpu");
990 for_each_online_cpu(c
) {
993 if (ia64_mc_info
.imi_rendez_checkin
[c
] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE
)
1000 printk(KERN_INFO
"All OS MCA slaves have reached rendezvous\n");
1007 * This is uncorrectable machine check handler called from OS_MCA
1008 * dispatch code which is in turn called from SAL_CHECK().
1009 * This is the place where the core of OS MCA handling is done.
1010 * Right now the logs are extracted and displayed in a well-defined
1011 * format. This handler code is supposed to be run only on the
1012 * monarch processor. Once the monarch is done with MCA handling
1013 * further MCA logging is enabled by clearing logs.
1014 * Monarch also has the duty of sending wakeup-IPIs to pull the
1015 * slave processors out of rendezvous spinloop.
1018 ia64_mca_handler(struct pt_regs
*regs
, struct switch_stack
*sw
,
1019 struct ia64_sal_os_state
*sos
)
1021 pal_processor_state_info_t
*psp
= (pal_processor_state_info_t
*)
1022 &sos
->proc_state_param
;
1023 int recover
, cpu
= smp_processor_id();
1024 task_t
*previous_current
;
1026 oops_in_progress
= 1; /* FIXME: make printk NMI/MCA/INIT safe */
1027 console_loglevel
= 15; /* make sure printks make it to console */
1028 printk(KERN_INFO
"Entered OS MCA handler. PSP=%lx cpu=%d monarch=%ld\n",
1029 sos
->proc_state_param
, cpu
, sos
->monarch
);
1031 previous_current
= ia64_mca_modify_original_stack(regs
, sw
, sos
, "MCA");
1033 if (notify_die(DIE_MCA_MONARCH_ENTER
, "MCA", regs
, 0, 0, 0)
1035 ia64_mca_spin(__FUNCTION__
);
1036 ia64_wait_for_slaves(cpu
);
1038 /* Wakeup all the processors which are spinning in the rendezvous loop.
1039 * They will leave SAL, then spin in the OS with interrupts disabled
1040 * until this monarch cpu leaves the MCA handler. That gets control
1041 * back to the OS so we can backtrace the other cpus, backtrace when
1042 * spinning in SAL does not work.
1044 ia64_mca_wakeup_all();
1045 if (notify_die(DIE_MCA_MONARCH_PROCESS
, "MCA", regs
, 0, 0, 0)
1047 ia64_mca_spin(__FUNCTION__
);
1049 /* Get the MCA error record and log it */
1050 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA
);
1052 /* TLB error is only exist in this SAL error record */
1053 recover
= (psp
->tc
&& !(psp
->cc
|| psp
->bc
|| psp
->rc
|| psp
->uc
))
1054 /* other error recovery */
1055 || (ia64_mca_ucmc_extension
1056 && ia64_mca_ucmc_extension(
1057 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA
),
1061 sal_log_record_header_t
*rh
= IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA
);
1062 rh
->severity
= sal_log_severity_corrected
;
1063 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA
);
1064 sos
->os_status
= IA64_MCA_CORRECTED
;
1066 if (notify_die(DIE_MCA_MONARCH_LEAVE
, "MCA", regs
, 0, 0, recover
)
1068 ia64_mca_spin(__FUNCTION__
);
1070 set_curr_task(cpu
, previous_current
);
1074 static DECLARE_WORK(cmc_disable_work
, ia64_mca_cmc_vector_disable_keventd
, NULL
);
1075 static DECLARE_WORK(cmc_enable_work
, ia64_mca_cmc_vector_enable_keventd
, NULL
);
1078 * ia64_mca_cmc_int_handler
1080 * This is corrected machine check interrupt handler.
1081 * Right now the logs are extracted and displayed in a well-defined
1086 * client data arg ptr
1087 * saved registers ptr
1093 ia64_mca_cmc_int_handler(int cmc_irq
, void *arg
, struct pt_regs
*ptregs
)
1095 static unsigned long cmc_history
[CMC_HISTORY_LENGTH
];
1097 static DEFINE_SPINLOCK(cmc_history_lock
);
1099 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1100 __FUNCTION__
, cmc_irq
, smp_processor_id());
1102 /* SAL spec states this should run w/ interrupts enabled */
1105 /* Get the CMC error record and log it */
1106 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC
);
1108 spin_lock(&cmc_history_lock
);
1109 if (!cmc_polling_enabled
) {
1110 int i
, count
= 1; /* we know 1 happened now */
1111 unsigned long now
= jiffies
;
1113 for (i
= 0; i
< CMC_HISTORY_LENGTH
; i
++) {
1114 if (now
- cmc_history
[i
] <= HZ
)
1118 IA64_MCA_DEBUG(KERN_INFO
"CMC threshold %d/%d\n", count
, CMC_HISTORY_LENGTH
);
1119 if (count
>= CMC_HISTORY_LENGTH
) {
1121 cmc_polling_enabled
= 1;
1122 spin_unlock(&cmc_history_lock
);
1123 /* If we're being hit with CMC interrupts, we won't
1124 * ever execute the schedule_work() below. Need to
1125 * disable CMC interrupts on this processor now.
1127 ia64_mca_cmc_vector_disable(NULL
);
1128 schedule_work(&cmc_disable_work
);
1131 * Corrected errors will still be corrected, but
1132 * make sure there's a log somewhere that indicates
1133 * something is generating more than we can handle.
1135 printk(KERN_WARNING
"WARNING: Switching to polling CMC handler; error records may be lost\n");
1137 mod_timer(&cmc_poll_timer
, jiffies
+ CMC_POLL_INTERVAL
);
1139 /* lock already released, get out now */
1142 cmc_history
[index
++] = now
;
1143 if (index
== CMC_HISTORY_LENGTH
)
1147 spin_unlock(&cmc_history_lock
);
1152 * ia64_mca_cmc_int_caller
1154 * Triggered by sw interrupt from CMC polling routine. Calls
1155 * real interrupt handler and either triggers a sw interrupt
1156 * on the next cpu or does cleanup at the end.
1160 * client data arg ptr
1161 * saved registers ptr
1166 ia64_mca_cmc_int_caller(int cmc_irq
, void *arg
, struct pt_regs
*ptregs
)
1168 static int start_count
= -1;
1171 cpuid
= smp_processor_id();
1173 /* If first cpu, update count */
1174 if (start_count
== -1)
1175 start_count
= IA64_LOG_COUNT(SAL_INFO_TYPE_CMC
);
1177 ia64_mca_cmc_int_handler(cmc_irq
, arg
, ptregs
);
1179 for (++cpuid
; cpuid
< NR_CPUS
&& !cpu_online(cpuid
) ; cpuid
++);
1181 if (cpuid
< NR_CPUS
) {
1182 platform_send_ipi(cpuid
, IA64_CMCP_VECTOR
, IA64_IPI_DM_INT
, 0);
1184 /* If no log record, switch out of polling mode */
1185 if (start_count
== IA64_LOG_COUNT(SAL_INFO_TYPE_CMC
)) {
1187 printk(KERN_WARNING
"Returning to interrupt driven CMC handler\n");
1188 schedule_work(&cmc_enable_work
);
1189 cmc_polling_enabled
= 0;
1193 mod_timer(&cmc_poll_timer
, jiffies
+ CMC_POLL_INTERVAL
);
1205 * Poll for Corrected Machine Checks (CMCs)
1207 * Inputs : dummy(unused)
1212 ia64_mca_cmc_poll (unsigned long dummy
)
1214 /* Trigger a CMC interrupt cascade */
1215 platform_send_ipi(first_cpu(cpu_online_map
), IA64_CMCP_VECTOR
, IA64_IPI_DM_INT
, 0);
1219 * ia64_mca_cpe_int_caller
1221 * Triggered by sw interrupt from CPE polling routine. Calls
1222 * real interrupt handler and either triggers a sw interrupt
1223 * on the next cpu or does cleanup at the end.
1227 * client data arg ptr
1228 * saved registers ptr
1235 ia64_mca_cpe_int_caller(int cpe_irq
, void *arg
, struct pt_regs
*ptregs
)
1237 static int start_count
= -1;
1238 static int poll_time
= MIN_CPE_POLL_INTERVAL
;
1241 cpuid
= smp_processor_id();
1243 /* If first cpu, update count */
1244 if (start_count
== -1)
1245 start_count
= IA64_LOG_COUNT(SAL_INFO_TYPE_CPE
);
1247 ia64_mca_cpe_int_handler(cpe_irq
, arg
, ptregs
);
1249 for (++cpuid
; cpuid
< NR_CPUS
&& !cpu_online(cpuid
) ; cpuid
++);
1251 if (cpuid
< NR_CPUS
) {
1252 platform_send_ipi(cpuid
, IA64_CPEP_VECTOR
, IA64_IPI_DM_INT
, 0);
1255 * If a log was recorded, increase our polling frequency,
1256 * otherwise, backoff or return to interrupt mode.
1258 if (start_count
!= IA64_LOG_COUNT(SAL_INFO_TYPE_CPE
)) {
1259 poll_time
= max(MIN_CPE_POLL_INTERVAL
, poll_time
/ 2);
1260 } else if (cpe_vector
< 0) {
1261 poll_time
= min(MAX_CPE_POLL_INTERVAL
, poll_time
* 2);
1263 poll_time
= MIN_CPE_POLL_INTERVAL
;
1265 printk(KERN_WARNING
"Returning to interrupt driven CPE handler\n");
1266 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR
));
1267 cpe_poll_enabled
= 0;
1270 if (cpe_poll_enabled
)
1271 mod_timer(&cpe_poll_timer
, jiffies
+ poll_time
);
1281 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1282 * on first cpu, from there it will trickle through all the cpus.
1284 * Inputs : dummy(unused)
1289 ia64_mca_cpe_poll (unsigned long dummy
)
1291 /* Trigger a CPE interrupt cascade */
1292 platform_send_ipi(first_cpu(cpu_online_map
), IA64_CPEP_VECTOR
, IA64_IPI_DM_INT
, 0);
1295 #endif /* CONFIG_ACPI */
1298 default_monarch_init_process(struct notifier_block
*self
, unsigned long val
, void *data
)
1301 struct task_struct
*g
, *t
;
1302 if (val
!= DIE_INIT_MONARCH_PROCESS
)
1304 printk(KERN_ERR
"Processes interrupted by INIT -");
1305 for_each_online_cpu(c
) {
1306 struct ia64_sal_os_state
*s
;
1307 t
= __va(__per_cpu_mca
[c
] + IA64_MCA_CPU_INIT_STACK_OFFSET
);
1308 s
= (struct ia64_sal_os_state
*)((char *)t
+ MCA_SOS_OFFSET
);
1312 printk(" %d", g
->pid
);
1314 printk(" %d (cpu %d task 0x%p)", g
->pid
, task_cpu(g
), g
);
1318 if (read_trylock(&tasklist_lock
)) {
1319 do_each_thread (g
, t
) {
1320 printk("\nBacktrace of pid %d (%s)\n", t
->pid
, t
->comm
);
1321 show_stack(t
, NULL
);
1322 } while_each_thread (g
, t
);
1323 read_unlock(&tasklist_lock
);
1329 * C portion of the OS INIT handler
1331 * Called from ia64_os_init_dispatch
1333 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for
1334 * this event. This code is used for both monarch and slave INIT events, see
1337 * All INIT events switch to the INIT stack and change the previous process to
1338 * blocked status. If one of the INIT events is the monarch then we are
1339 * probably processing the nmi button/command. Use the monarch cpu to dump all
1340 * the processes. The slave INIT events all spin until the monarch cpu
1341 * returns. We can also get INIT slave events for MCA, in which case the MCA
1342 * process is the monarch.
1346 ia64_init_handler(struct pt_regs
*regs
, struct switch_stack
*sw
,
1347 struct ia64_sal_os_state
*sos
)
1349 static atomic_t slaves
;
1350 static atomic_t monarchs
;
1351 task_t
*previous_current
;
1352 int cpu
= smp_processor_id();
1354 oops_in_progress
= 1; /* FIXME: make printk NMI/MCA/INIT safe */
1355 console_loglevel
= 15; /* make sure printks make it to console */
1357 printk(KERN_INFO
"Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1358 sos
->proc_state_param
, cpu
, sos
->monarch
);
1359 salinfo_log_wakeup(SAL_INFO_TYPE_INIT
, NULL
, 0, 0);
1361 previous_current
= ia64_mca_modify_original_stack(regs
, sw
, sos
, "INIT");
1362 sos
->os_status
= IA64_INIT_RESUME
;
1364 /* FIXME: Workaround for broken proms that drive all INIT events as
1365 * slaves. The last slave that enters is promoted to be a monarch.
1366 * Remove this code in September 2006, that gives platforms a year to
1367 * fix their proms and get their customers updated.
1369 if (!sos
->monarch
&& atomic_add_return(1, &slaves
) == num_online_cpus()) {
1370 printk(KERN_WARNING
"%s: Promoting cpu %d to monarch.\n",
1372 atomic_dec(&slaves
);
1376 /* FIXME: Workaround for broken proms that drive all INIT events as
1377 * monarchs. Second and subsequent monarchs are demoted to slaves.
1378 * Remove this code in September 2006, that gives platforms a year to
1379 * fix their proms and get their customers updated.
1381 if (sos
->monarch
&& atomic_add_return(1, &monarchs
) > 1) {
1382 printk(KERN_WARNING
"%s: Demoting cpu %d to slave.\n",
1384 atomic_dec(&monarchs
);
1388 if (!sos
->monarch
) {
1389 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_INIT
;
1390 while (monarch_cpu
== -1)
1391 cpu_relax(); /* spin until monarch enters */
1392 if (notify_die(DIE_INIT_SLAVE_ENTER
, "INIT", regs
, 0, 0, 0)
1394 ia64_mca_spin(__FUNCTION__
);
1395 if (notify_die(DIE_INIT_SLAVE_PROCESS
, "INIT", regs
, 0, 0, 0)
1397 ia64_mca_spin(__FUNCTION__
);
1398 while (monarch_cpu
!= -1)
1399 cpu_relax(); /* spin until monarch leaves */
1400 if (notify_die(DIE_INIT_SLAVE_LEAVE
, "INIT", regs
, 0, 0, 0)
1402 ia64_mca_spin(__FUNCTION__
);
1403 printk("Slave on cpu %d returning to normal service.\n", cpu
);
1404 set_curr_task(cpu
, previous_current
);
1405 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
1406 atomic_dec(&slaves
);
1411 if (notify_die(DIE_INIT_MONARCH_ENTER
, "INIT", regs
, 0, 0, 0)
1413 ia64_mca_spin(__FUNCTION__
);
1416 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1417 * generated via the BMC's command-line interface, but since the console is on the
1418 * same serial line, the user will need some time to switch out of the BMC before
1421 printk("Delaying for 5 seconds...\n");
1423 ia64_wait_for_slaves(cpu
);
1424 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1425 * to default_monarch_init_process() above and just print all the
1428 if (notify_die(DIE_INIT_MONARCH_PROCESS
, "INIT", regs
, 0, 0, 0)
1430 ia64_mca_spin(__FUNCTION__
);
1431 if (notify_die(DIE_INIT_MONARCH_LEAVE
, "INIT", regs
, 0, 0, 0)
1433 ia64_mca_spin(__FUNCTION__
);
1434 printk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu
);
1435 atomic_dec(&monarchs
);
1436 set_curr_task(cpu
, previous_current
);
1442 ia64_mca_disable_cpe_polling(char *str
)
1444 cpe_poll_enabled
= 0;
1448 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling
);
1450 static struct irqaction cmci_irqaction
= {
1451 .handler
= ia64_mca_cmc_int_handler
,
1452 .flags
= SA_INTERRUPT
,
1456 static struct irqaction cmcp_irqaction
= {
1457 .handler
= ia64_mca_cmc_int_caller
,
1458 .flags
= SA_INTERRUPT
,
1462 static struct irqaction mca_rdzv_irqaction
= {
1463 .handler
= ia64_mca_rendez_int_handler
,
1464 .flags
= SA_INTERRUPT
,
1468 static struct irqaction mca_wkup_irqaction
= {
1469 .handler
= ia64_mca_wakeup_int_handler
,
1470 .flags
= SA_INTERRUPT
,
1475 static struct irqaction mca_cpe_irqaction
= {
1476 .handler
= ia64_mca_cpe_int_handler
,
1477 .flags
= SA_INTERRUPT
,
1481 static struct irqaction mca_cpep_irqaction
= {
1482 .handler
= ia64_mca_cpe_int_caller
,
1483 .flags
= SA_INTERRUPT
,
1486 #endif /* CONFIG_ACPI */
1488 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on
1489 * these stacks can never sleep, they cannot return from the kernel to user
1490 * space, they do not appear in a normal ps listing. So there is no need to
1491 * format most of the fields.
1494 static void __cpuinit
1495 format_mca_init_stack(void *mca_data
, unsigned long offset
,
1496 const char *type
, int cpu
)
1498 struct task_struct
*p
= (struct task_struct
*)((char *)mca_data
+ offset
);
1499 struct thread_info
*ti
;
1500 memset(p
, 0, KERNEL_STACK_SIZE
);
1501 ti
= task_thread_info(p
);
1502 ti
->flags
= _TIF_MCA_INIT
;
1503 ti
->preempt_count
= 1;
1506 p
->thread_info
= ti
;
1507 p
->state
= TASK_UNINTERRUPTIBLE
;
1508 __set_bit(cpu
, &p
->cpus_allowed
);
1509 INIT_LIST_HEAD(&p
->tasks
);
1510 p
->parent
= p
->real_parent
= p
->group_leader
= p
;
1511 INIT_LIST_HEAD(&p
->children
);
1512 INIT_LIST_HEAD(&p
->sibling
);
1513 strncpy(p
->comm
, type
, sizeof(p
->comm
)-1);
1516 /* Do per-CPU MCA-related initialization. */
1519 ia64_mca_cpu_init(void *cpu_data
)
1522 static int first_time
= 1;
1529 mca_data
= alloc_bootmem(sizeof(struct ia64_mca_cpu
)
1530 * NR_CPUS
+ KERNEL_STACK_SIZE
);
1531 mca_data
= (void *)(((unsigned long)mca_data
+
1532 KERNEL_STACK_SIZE
- 1) &
1533 (-KERNEL_STACK_SIZE
));
1534 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1535 format_mca_init_stack(mca_data
,
1536 offsetof(struct ia64_mca_cpu
, mca_stack
),
1538 format_mca_init_stack(mca_data
,
1539 offsetof(struct ia64_mca_cpu
, init_stack
),
1541 __per_cpu_mca
[cpu
] = __pa(mca_data
);
1542 mca_data
+= sizeof(struct ia64_mca_cpu
);
1547 * The MCA info structure was allocated earlier and its
1548 * physical address saved in __per_cpu_mca[cpu]. Copy that
1549 * address * to ia64_mca_data so we can access it as a per-CPU
1552 __get_cpu_var(ia64_mca_data
) = __per_cpu_mca
[smp_processor_id()];
1555 * Stash away a copy of the PTE needed to map the per-CPU page.
1556 * We may need it during MCA recovery.
1558 __get_cpu_var(ia64_mca_per_cpu_pte
) =
1559 pte_val(mk_pte_phys(__pa(cpu_data
), PAGE_KERNEL
));
1562 * Also, stash away a copy of the PAL address and the PTE
1565 pal_vaddr
= efi_get_pal_addr();
1568 __get_cpu_var(ia64_mca_pal_base
) =
1569 GRANULEROUNDDOWN((unsigned long) pal_vaddr
);
1570 __get_cpu_var(ia64_mca_pal_pte
) = pte_val(mk_pte_phys(__pa(pal_vaddr
),
1577 * Do all the system level mca specific initialization.
1579 * 1. Register spinloop and wakeup request interrupt vectors
1581 * 2. Register OS_MCA handler entry point
1583 * 3. Register OS_INIT handler entry point
1585 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1587 * Note that this initialization is done very early before some kernel
1588 * services are available.
1597 ia64_fptr_t
*init_hldlr_ptr_monarch
= (ia64_fptr_t
*)ia64_os_init_dispatch_monarch
;
1598 ia64_fptr_t
*init_hldlr_ptr_slave
= (ia64_fptr_t
*)ia64_os_init_dispatch_slave
;
1599 ia64_fptr_t
*mca_hldlr_ptr
= (ia64_fptr_t
*)ia64_os_mca_dispatch
;
1602 struct ia64_sal_retval isrv
;
1603 u64 timeout
= IA64_MCA_RENDEZ_TIMEOUT
; /* platform specific */
1604 static struct notifier_block default_init_monarch_nb
= {
1605 .notifier_call
= default_monarch_init_process
,
1606 .priority
= 0/* we need to notified last */
1609 IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__
);
1611 /* Clear the Rendez checkin flag for all cpus */
1612 for(i
= 0 ; i
< NR_CPUS
; i
++)
1613 ia64_mc_info
.imi_rendez_checkin
[i
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
1616 * Register the rendezvous spinloop and wakeup mechanism with SAL
1619 /* Register the rendezvous interrupt vector with SAL */
1621 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT
,
1622 SAL_MC_PARAM_MECHANISM_INT
,
1623 IA64_MCA_RENDEZ_VECTOR
,
1625 SAL_MC_PARAM_RZ_ALWAYS
);
1630 printk(KERN_INFO
"Increasing MCA rendezvous timeout from "
1631 "%ld to %ld milliseconds\n", timeout
, isrv
.v0
);
1635 printk(KERN_ERR
"Failed to register rendezvous interrupt "
1636 "with SAL (status %ld)\n", rc
);
1640 /* Register the wakeup interrupt vector with SAL */
1641 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP
,
1642 SAL_MC_PARAM_MECHANISM_INT
,
1643 IA64_MCA_WAKEUP_VECTOR
,
1647 printk(KERN_ERR
"Failed to register wakeup interrupt with SAL "
1648 "(status %ld)\n", rc
);
1652 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__
);
1654 ia64_mc_info
.imi_mca_handler
= ia64_tpa(mca_hldlr_ptr
->fp
);
1656 * XXX - disable SAL checksum by setting size to 0; should be
1657 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1659 ia64_mc_info
.imi_mca_handler_size
= 0;
1661 /* Register the os mca handler with SAL */
1662 if ((rc
= ia64_sal_set_vectors(SAL_VECTOR_OS_MCA
,
1663 ia64_mc_info
.imi_mca_handler
,
1664 ia64_tpa(mca_hldlr_ptr
->gp
),
1665 ia64_mc_info
.imi_mca_handler_size
,
1668 printk(KERN_ERR
"Failed to register OS MCA handler with SAL "
1669 "(status %ld)\n", rc
);
1673 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__
,
1674 ia64_mc_info
.imi_mca_handler
, ia64_tpa(mca_hldlr_ptr
->gp
));
1677 * XXX - disable SAL checksum by setting size to 0, should be
1678 * size of the actual init handler in mca_asm.S.
1680 ia64_mc_info
.imi_monarch_init_handler
= ia64_tpa(init_hldlr_ptr_monarch
->fp
);
1681 ia64_mc_info
.imi_monarch_init_handler_size
= 0;
1682 ia64_mc_info
.imi_slave_init_handler
= ia64_tpa(init_hldlr_ptr_slave
->fp
);
1683 ia64_mc_info
.imi_slave_init_handler_size
= 0;
1685 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__
,
1686 ia64_mc_info
.imi_monarch_init_handler
);
1688 /* Register the os init handler with SAL */
1689 if ((rc
= ia64_sal_set_vectors(SAL_VECTOR_OS_INIT
,
1690 ia64_mc_info
.imi_monarch_init_handler
,
1691 ia64_tpa(ia64_getreg(_IA64_REG_GP
)),
1692 ia64_mc_info
.imi_monarch_init_handler_size
,
1693 ia64_mc_info
.imi_slave_init_handler
,
1694 ia64_tpa(ia64_getreg(_IA64_REG_GP
)),
1695 ia64_mc_info
.imi_slave_init_handler_size
)))
1697 printk(KERN_ERR
"Failed to register m/s INIT handlers with SAL "
1698 "(status %ld)\n", rc
);
1701 if (register_die_notifier(&default_init_monarch_nb
)) {
1702 printk(KERN_ERR
"Failed to register default monarch INIT process\n");
1706 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__
);
1709 * Configure the CMCI/P vector and handler. Interrupts for CMC are
1710 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1712 register_percpu_irq(IA64_CMC_VECTOR
, &cmci_irqaction
);
1713 register_percpu_irq(IA64_CMCP_VECTOR
, &cmcp_irqaction
);
1714 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
1716 /* Setup the MCA rendezvous interrupt vector */
1717 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR
, &mca_rdzv_irqaction
);
1719 /* Setup the MCA wakeup interrupt vector */
1720 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR
, &mca_wkup_irqaction
);
1723 /* Setup the CPEI/P handler */
1724 register_percpu_irq(IA64_CPEP_VECTOR
, &mca_cpep_irqaction
);
1727 /* Initialize the areas set aside by the OS to buffer the
1728 * platform/processor error states for MCA/INIT/CMC
1731 ia64_log_init(SAL_INFO_TYPE_MCA
);
1732 ia64_log_init(SAL_INFO_TYPE_INIT
);
1733 ia64_log_init(SAL_INFO_TYPE_CMC
);
1734 ia64_log_init(SAL_INFO_TYPE_CPE
);
1737 printk(KERN_INFO
"MCA related initialization done\n");
1741 * ia64_mca_late_init
1743 * Opportunity to setup things that require initialization later
1744 * than ia64_mca_init. Setup a timer to poll for CPEs if the
1745 * platform doesn't support an interrupt driven mechanism.
1751 ia64_mca_late_init(void)
1756 /* Setup the CMCI/P vector and handler */
1757 init_timer(&cmc_poll_timer
);
1758 cmc_poll_timer
.function
= ia64_mca_cmc_poll
;
1760 /* Unmask/enable the vector */
1761 cmc_polling_enabled
= 0;
1762 schedule_work(&cmc_enable_work
);
1764 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__
);
1767 /* Setup the CPEI/P vector and handler */
1768 cpe_vector
= acpi_request_vector(ACPI_INTERRUPT_CPEI
);
1769 init_timer(&cpe_poll_timer
);
1770 cpe_poll_timer
.function
= ia64_mca_cpe_poll
;
1776 if (cpe_vector
>= 0) {
1777 /* If platform supports CPEI, enable the irq. */
1778 cpe_poll_enabled
= 0;
1779 for (irq
= 0; irq
< NR_IRQS
; ++irq
)
1780 if (irq_to_vector(irq
) == cpe_vector
) {
1781 desc
= irq_descp(irq
);
1782 desc
->status
|= IRQ_PER_CPU
;
1783 setup_irq(irq
, &mca_cpe_irqaction
);
1786 ia64_mca_register_cpev(cpe_vector
);
1787 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__
);
1789 /* If platform doesn't support CPEI, get the timer going. */
1790 if (cpe_poll_enabled
) {
1791 ia64_mca_cpe_poll(0UL);
1792 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__
);
1801 device_initcall(ia64_mca_late_init
);