drivers/video/geode/display_gx.c

   1 /*
   2  * Geode GX display controller.
   3  *
   4  *   Copyright (C) 2005 Arcom Control Systems Ltd.
   5  *
   6  *   Portions from AMD's original 2.4 driver:
   7  *     Copyright (C) 2004 Advanced Micro Devices, Inc.
   8  *
   9  *   This program is free software; you can redistribute it and/or modify it
  10  *   under the terms of the GNU General Public License as published by * the
  11  *   Free Software Foundation; either version 2 of the License, or * (at your
  12  *   option) any later version.
  13  */
  14 #include <linux/spinlock.h>
  15 #include <linux/fb.h>
  16 #include <linux/delay.h>
  17 #include <asm/io.h>
  18 #include <asm/div64.h>
  19 #include <asm/delay.h>
  20
  21 #include "geodefb.h"
  22 #include "display_gx.h"
  23 #include "gxfb.h"
  24
  25 unsigned int gx_frame_buffer_size(void)
  26 {
  27         unsigned int val;
  28
  29         /* FB size is reported by a virtual register */
  30         /* Virtual register class = 0x02 */
  31         /* VG_MEM_SIZE(512Kb units) = 0x00 */
  32
  33         outw(0xFC53, 0xAC1C);
  34         outw(0x0200, 0xAC1C);
  35
  36         val = (unsigned int)(inw(0xAC1E)) & 0xFFl;
  37         return (val << 19);
  38 }
  39
  40 int gx_line_delta(int xres, int bpp)
  41 {
  42         /* Must be a multiple of 8 bytes. */
  43         return (xres * (bpp >> 3) + 7) & ~0x7;
  44 }
  45
  46 static void gx_set_mode(struct fb_info *info)
  47 {
  48         struct geodefb_par *par = info->par;
  49         u32 gcfg, dcfg;
  50         int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
  51         int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
  52
  53         /* Unlock the display controller registers. */
  54         write_dc(par, DC_UNLOCK, DC_UNLOCK_UNLOCK);
  55
  56         gcfg = read_dc(par, DC_GENERAL_CFG);
  57         dcfg = read_dc(par, DC_DISPLAY_CFG);
  58
  59         /* Disable the timing generator. */
  60         dcfg &= ~DC_DISPLAY_CFG_TGEN;
  61         write_dc(par, DC_DISPLAY_CFG, dcfg);
  62
  63         /* Wait for pending memory requests before disabling the FIFO load. */
  64         udelay(100);
  65
  66         /* Disable FIFO load and compression. */
  67         gcfg &= ~(DC_GENERAL_CFG_DFLE | DC_GENERAL_CFG_CMPE |
  68                         DC_GENERAL_CFG_DECE);
  69         write_dc(par, DC_GENERAL_CFG, gcfg);
  70
  71         /* Setup DCLK and its divisor. */
  72         par->vid_ops->set_dclk(info);
  73
  74         /*
  75          * Setup new mode.
  76          */
  77
  78         /* Clear all unused feature bits. */
  79         gcfg &= DC_GENERAL_CFG_YUVM | DC_GENERAL_CFG_VDSE;
  80         dcfg = 0;
  81
  82         /* Set FIFO priority (default 6/5) and enable. */
  83         /* FIXME: increase fifo priority for 1280x1024 and higher modes? */
  84         gcfg |= (6 << DC_GENERAL_CFG_DFHPEL_SHIFT) |
  85                 (5 << DC_GENERAL_CFG_DFHPSL_SHIFT) | DC_GENERAL_CFG_DFLE;
  86
  87         /* Framebuffer start offset. */
  88         write_dc(par, DC_FB_ST_OFFSET, 0);
  89
  90         /* Line delta and line buffer length. */
  91         write_dc(par, DC_GFX_PITCH, info->fix.line_length >> 3);
  92         write_dc(par, DC_LINE_SIZE,
  93                 ((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2);
  94
  95
  96         /* Enable graphics and video data and unmask address lines. */
  97         dcfg |= DC_DISPLAY_CFG_GDEN | DC_DISPLAY_CFG_VDEN |
  98                 DC_DISPLAY_CFG_A20M | DC_DISPLAY_CFG_A18M;
  99
 100         /* Set pixel format. */
 101         switch (info->var.bits_per_pixel) {
 102         case 8:
 103                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_8BPP;
 104                 break;
 105         case 16:
 106                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_16BPP;
 107                 break;
 108         case 32:
 109                 dcfg |= DC_DISPLAY_CFG_DISP_MODE_24BPP;
 110                 dcfg |= DC_DISPLAY_CFG_PALB;
 111                 break;
 112         }
 113
 114         /* Enable timing generator. */
 115         dcfg |= DC_DISPLAY_CFG_TGEN;
 116
 117         /* Horizontal and vertical timings. */
 118         hactive = info->var.xres;
 119         hblankstart = hactive;
 120         hsyncstart = hblankstart + info->var.right_margin;
 121         hsyncend =  hsyncstart + info->var.hsync_len;
 122         hblankend = hsyncend + info->var.left_margin;
 123         htotal = hblankend;
 124
 125         vactive = info->var.yres;
 126         vblankstart = vactive;
 127         vsyncstart = vblankstart + info->var.lower_margin;
 128         vsyncend =  vsyncstart + info->var.vsync_len;
 129         vblankend = vsyncend + info->var.upper_margin;
 130         vtotal = vblankend;
 131
 132         write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1)    |
 133                         ((htotal - 1) << 16));
 134         write_dc(par, DC_H_BLANK_TIMING, (hblankstart - 1) |
 135                         ((hblankend - 1) << 16));
 136         write_dc(par, DC_H_SYNC_TIMING, (hsyncstart - 1)   |
 137                         ((hsyncend - 1) << 16));
 138
 139         write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1)    |
 140                         ((vtotal - 1) << 16));
 141         write_dc(par, DC_V_BLANK_TIMING, (vblankstart - 1) |
 142                         ((vblankend - 1) << 16));
 143         write_dc(par, DC_V_SYNC_TIMING, (vsyncstart - 1)   |
 144                         ((vsyncend - 1) << 16));
 145
 146         /* Write final register values. */
 147         write_dc(par, DC_DISPLAY_CFG, dcfg);
 148         write_dc(par, DC_GENERAL_CFG, gcfg);
 149
 150         par->vid_ops->configure_display(info);
 151
 152         /* Relock display controller registers */
 153         write_dc(par, DC_UNLOCK, DC_UNLOCK_LOCK);
 154 }
 155
 156 static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
 157                                    unsigned red, unsigned green, unsigned blue)
 158 {
 159         struct geodefb_par *par = info->par;
 160         int val;
 161
 162         /* Hardware palette is in RGB 8-8-8 format. */
 163         val  = (red   << 8) & 0xff0000;
 164         val |= (green)      & 0x00ff00;
 165         val |= (blue  >> 8) & 0x0000ff;
 166
 167         write_dc(par, DC_PAL_ADDRESS, regno);
 168         write_dc(par, DC_PAL_DATA, val);
 169 }
 170
 171 struct geode_dc_ops gx_dc_ops = {
 172         .set_mode        = gx_set_mode,
 173         .set_palette_reg = gx_set_hw_palette_reg,
 174 };