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Merge branch 'drm-nouveau-fixes-3.9' of git://anongit.freedesktop.org/git/nouveau...
[linux-2.6/libata-dev.git] / drivers / usb / musb / musb_host.c
blob1ce1fcf3f3e7bd19be87f8d02b4dcac13ca54f28
1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/init.h>
43 #include <linux/list.h>
44 #include <linux/dma-mapping.h>
45
46 #include "musb_core.h"
47 #include "musb_host.h"
48
49
50 /* MUSB HOST status 22-mar-2006
51 *
52 * - There's still lots of partial code duplication for fault paths, so
53 * they aren't handled as consistently as they need to be.
54 *
55 * - PIO mostly behaved when last tested.
56 * + including ep0, with all usbtest cases 9, 10
57 * + usbtest 14 (ep0out) doesn't seem to run at all
58 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
59 * configurations, but otherwise double buffering passes basic tests.
60 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
61 *
62 * - DMA (CPPI) ... partially behaves, not currently recommended
63 * + about 1/15 the speed of typical EHCI implementations (PCI)
64 * + RX, all too often reqpkt seems to misbehave after tx
65 * + TX, no known issues (other than evident silicon issue)
66 *
67 * - DMA (Mentor/OMAP) ...has at least toggle update problems
68 *
69 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
70 * starvation ... nothing yet for TX, interrupt, or bulk.
71 *
72 * - Not tested with HNP, but some SRP paths seem to behave.
73 *
74 * NOTE 24-August-2006:
75 *
76 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
77 * extra endpoint for periodic use enabling hub + keybd + mouse. That
78 * mostly works, except that with "usbnet" it's easy to trigger cases
79 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
80 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
81 * although ARP RX wins. (That test was done with a full speed link.)
82 */
83
84
85 /*
86 * NOTE on endpoint usage:
87 *
88 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
89 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
90 * (Yes, bulk _could_ use more of the endpoints than that, and would even
91 * benefit from it.)
92 *
93 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
94 * So far that scheduling is both dumb and optimistic: the endpoint will be
95 * "claimed" until its software queue is no longer refilled. No multiplexing
96 * of transfers between endpoints, or anything clever.
97 */
98
99
100 static void musb_ep_program(struct musb *musb, u8 epnum,
101 struct urb *urb, int is_out,
102 u8 *buf, u32 offset, u32 len);
103
104 /*
105 * Clear TX fifo. Needed to avoid BABBLE errors.
106 */
107 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
108 {
109 struct musb *musb = ep->musb;
110 void __iomem *epio = ep->regs;
111 u16 csr;
112 u16 lastcsr = 0;
113 int retries = 1000;
114
115 csr = musb_readw(epio, MUSB_TXCSR);
116 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
117 if (csr != lastcsr)
118 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
119 lastcsr = csr;
120 csr |= MUSB_TXCSR_FLUSHFIFO;
121 musb_writew(epio, MUSB_TXCSR, csr);
122 csr = musb_readw(epio, MUSB_TXCSR);
123 if (WARN(retries-- < 1,
124 "Could not flush host TX%d fifo: csr: %04x\n",
125 ep->epnum, csr))
126 return;
127 mdelay(1);
128 }
129 }
130
131 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
132 {
133 void __iomem *epio = ep->regs;
134 u16 csr;
135 int retries = 5;
136
137 /* scrub any data left in the fifo */
138 do {
139 csr = musb_readw(epio, MUSB_TXCSR);
140 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
141 break;
142 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
143 csr = musb_readw(epio, MUSB_TXCSR);
144 udelay(10);
145 } while (--retries);
146
147 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
148 ep->epnum, csr);
149
150 /* and reset for the next transfer */
151 musb_writew(epio, MUSB_TXCSR, 0);
152 }
153
154 /*
155 * Start transmit. Caller is responsible for locking shared resources.
156 * musb must be locked.
157 */
158 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
159 {
160 u16 txcsr;
161
162 /* NOTE: no locks here; caller should lock and select EP */
163 if (ep->epnum) {
164 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
165 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
166 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
167 } else {
168 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
169 musb_writew(ep->regs, MUSB_CSR0, txcsr);
170 }
171
172 }
173
174 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
175 {
176 u16 txcsr;
177
178 /* NOTE: no locks here; caller should lock and select EP */
179 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
180 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
181 if (is_cppi_enabled())
182 txcsr |= MUSB_TXCSR_DMAMODE;
183 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
184 }
185
186 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
187 {
188 if (is_in != 0 || ep->is_shared_fifo)
189 ep->in_qh = qh;
190 if (is_in == 0 || ep->is_shared_fifo)
191 ep->out_qh = qh;
192 }
193
194 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
195 {
196 return is_in ? ep->in_qh : ep->out_qh;
197 }
198
199 /*
200 * Start the URB at the front of an endpoint's queue
201 * end must be claimed from the caller.
202 *
203 * Context: controller locked, irqs blocked
204 */
205 static void
206 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
207 {
208 u16 frame;
209 u32 len;
210 void __iomem *mbase = musb->mregs;
211 struct urb *urb = next_urb(qh);
212 void *buf = urb->transfer_buffer;
213 u32 offset = 0;
214 struct musb_hw_ep *hw_ep = qh->hw_ep;
215 unsigned pipe = urb->pipe;
216 u8 address = usb_pipedevice(pipe);
217 int epnum = hw_ep->epnum;
218
219 /* initialize software qh state */
220 qh->offset = 0;
221 qh->segsize = 0;
222
223 /* gather right source of data */
224 switch (qh->type) {
225 case USB_ENDPOINT_XFER_CONTROL:
226 /* control transfers always start with SETUP */
227 is_in = 0;
228 musb->ep0_stage = MUSB_EP0_START;
229 buf = urb->setup_packet;
230 len = 8;
231 break;
232 case USB_ENDPOINT_XFER_ISOC:
233 qh->iso_idx = 0;
234 qh->frame = 0;
235 offset = urb->iso_frame_desc[0].offset;
236 len = urb->iso_frame_desc[0].length;
237 break;
238 default: /* bulk, interrupt */
239 /* actual_length may be nonzero on retry paths */
240 buf = urb->transfer_buffer + urb->actual_length;
241 len = urb->transfer_buffer_length - urb->actual_length;
242 }
243
244 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
245 qh, urb, address, qh->epnum,
246 is_in ? "in" : "out",
247 ({char *s; switch (qh->type) {
248 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
249 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
250 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
251 default: s = "-intr"; break;
252 }; s; }),
253 epnum, buf + offset, len);
254
255 /* Configure endpoint */
256 musb_ep_set_qh(hw_ep, is_in, qh);
257 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
258
259 /* transmit may have more work: start it when it is time */
260 if (is_in)
261 return;
262
263 /* determine if the time is right for a periodic transfer */
264 switch (qh->type) {
265 case USB_ENDPOINT_XFER_ISOC:
266 case USB_ENDPOINT_XFER_INT:
267 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
268 frame = musb_readw(mbase, MUSB_FRAME);
269 /* FIXME this doesn't implement that scheduling policy ...
270 * or handle framecounter wrapping
271 */
272 if ((urb->transfer_flags & URB_ISO_ASAP)
273 || (frame >= urb->start_frame)) {
274 /* REVISIT the SOF irq handler shouldn't duplicate
275 * this code; and we don't init urb->start_frame...
276 */
277 qh->frame = 0;
278 goto start;
279 } else {
280 qh->frame = urb->start_frame;
281 /* enable SOF interrupt so we can count down */
282 dev_dbg(musb->controller, "SOF for %d\n", epnum);
283 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
284 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
285 #endif
286 }
287 break;
288 default:
289 start:
290 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
291 hw_ep->tx_channel ? "dma" : "pio");
292
293 if (!hw_ep->tx_channel)
294 musb_h_tx_start(hw_ep);
295 else if (is_cppi_enabled() || tusb_dma_omap())
296 musb_h_tx_dma_start(hw_ep);
297 }
298 }
299
300 /* Context: caller owns controller lock, IRQs are blocked */
301 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
302 __releases(musb->lock)
303 __acquires(musb->lock)
304 {
305 dev_dbg(musb->controller,
306 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
307 urb, urb->complete, status,
308 usb_pipedevice(urb->pipe),
309 usb_pipeendpoint(urb->pipe),
310 usb_pipein(urb->pipe) ? "in" : "out",
311 urb->actual_length, urb->transfer_buffer_length
312 );
313
314 usb_hcd_unlink_urb_from_ep(musb_to_hcd(musb), urb);
315 spin_unlock(&musb->lock);
316 usb_hcd_giveback_urb(musb_to_hcd(musb), urb, status);
317 spin_lock(&musb->lock);
318 }
319
320 /* For bulk/interrupt endpoints only */
321 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
322 struct urb *urb)
323 {
324 void __iomem *epio = qh->hw_ep->regs;
325 u16 csr;
326
327 /*
328 * FIXME: the current Mentor DMA code seems to have
329 * problems getting toggle correct.
330 */
331
332 if (is_in)
333 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
334 else
335 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
336
337 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
338 }
339
340 /*
341 * Advance this hardware endpoint's queue, completing the specified URB and
342 * advancing to either the next URB queued to that qh, or else invalidating
343 * that qh and advancing to the next qh scheduled after the current one.
344 *
345 * Context: caller owns controller lock, IRQs are blocked
346 */
347 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
348 struct musb_hw_ep *hw_ep, int is_in)
349 {
350 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
351 struct musb_hw_ep *ep = qh->hw_ep;
352 int ready = qh->is_ready;
353 int status;
354
355 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
356
357 /* save toggle eagerly, for paranoia */
358 switch (qh->type) {
359 case USB_ENDPOINT_XFER_BULK:
360 case USB_ENDPOINT_XFER_INT:
361 musb_save_toggle(qh, is_in, urb);
362 break;
363 case USB_ENDPOINT_XFER_ISOC:
364 if (status == 0 && urb->error_count)
365 status = -EXDEV;
366 break;
367 }
368
369 qh->is_ready = 0;
370 musb_giveback(musb, urb, status);
371 qh->is_ready = ready;
372
373 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
374 * invalidate qh as soon as list_empty(&hep->urb_list)
375 */
376 if (list_empty(&qh->hep->urb_list)) {
377 struct list_head *head;
378 struct dma_controller *dma = musb->dma_controller;
379
380 if (is_in) {
381 ep->rx_reinit = 1;
382 if (ep->rx_channel) {
383 dma->channel_release(ep->rx_channel);
384 ep->rx_channel = NULL;
385 }
386 } else {
387 ep->tx_reinit = 1;
388 if (ep->tx_channel) {
389 dma->channel_release(ep->tx_channel);
390 ep->tx_channel = NULL;
391 }
392 }
393
394 /* Clobber old pointers to this qh */
395 musb_ep_set_qh(ep, is_in, NULL);
396 qh->hep->hcpriv = NULL;
397
398 switch (qh->type) {
399
400 case USB_ENDPOINT_XFER_CONTROL:
401 case USB_ENDPOINT_XFER_BULK:
402 /* fifo policy for these lists, except that NAKing
403 * should rotate a qh to the end (for fairness).
404 */
405 if (qh->mux == 1) {
406 head = qh->ring.prev;
407 list_del(&qh->ring);
408 kfree(qh);
409 qh = first_qh(head);
410 break;
411 }
412
413 case USB_ENDPOINT_XFER_ISOC:
414 case USB_ENDPOINT_XFER_INT:
415 /* this is where periodic bandwidth should be
416 * de-allocated if it's tracked and allocated;
417 * and where we'd update the schedule tree...
418 */
419 kfree(qh);
420 qh = NULL;
421 break;
422 }
423 }
424
425 if (qh != NULL && qh->is_ready) {
426 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
427 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
428 musb_start_urb(musb, is_in, qh);
429 }
430 }
431
432 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
433 {
434 /* we don't want fifo to fill itself again;
435 * ignore dma (various models),
436 * leave toggle alone (may not have been saved yet)
437 */
438 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
439 csr &= ~(MUSB_RXCSR_H_REQPKT
440 | MUSB_RXCSR_H_AUTOREQ
441 | MUSB_RXCSR_AUTOCLEAR);
442
443 /* write 2x to allow double buffering */
444 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
445 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
446
447 /* flush writebuffer */
448 return musb_readw(hw_ep->regs, MUSB_RXCSR);
449 }
450
451 /*
452 * PIO RX for a packet (or part of it).
453 */
454 static bool
455 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
456 {
457 u16 rx_count;
458 u8 *buf;
459 u16 csr;
460 bool done = false;
461 u32 length;
462 int do_flush = 0;
463 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
464 void __iomem *epio = hw_ep->regs;
465 struct musb_qh *qh = hw_ep->in_qh;
466 int pipe = urb->pipe;
467 void *buffer = urb->transfer_buffer;
468
469 /* musb_ep_select(mbase, epnum); */
470 rx_count = musb_readw(epio, MUSB_RXCOUNT);
471 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
472 urb->transfer_buffer, qh->offset,
473 urb->transfer_buffer_length);
474
475 /* unload FIFO */
476 if (usb_pipeisoc(pipe)) {
477 int status = 0;
478 struct usb_iso_packet_descriptor *d;
479
480 if (iso_err) {
481 status = -EILSEQ;
482 urb->error_count++;
483 }
484
485 d = urb->iso_frame_desc + qh->iso_idx;
486 buf = buffer + d->offset;
487 length = d->length;
488 if (rx_count > length) {
489 if (status == 0) {
490 status = -EOVERFLOW;
491 urb->error_count++;
492 }
493 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
494 do_flush = 1;
495 } else
496 length = rx_count;
497 urb->actual_length += length;
498 d->actual_length = length;
499
500 d->status = status;
501
502 /* see if we are done */
503 done = (++qh->iso_idx >= urb->number_of_packets);
504 } else {
505 /* non-isoch */
506 buf = buffer + qh->offset;
507 length = urb->transfer_buffer_length - qh->offset;
508 if (rx_count > length) {
509 if (urb->status == -EINPROGRESS)
510 urb->status = -EOVERFLOW;
511 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
512 do_flush = 1;
513 } else
514 length = rx_count;
515 urb->actual_length += length;
516 qh->offset += length;
517
518 /* see if we are done */
519 done = (urb->actual_length == urb->transfer_buffer_length)
520 || (rx_count < qh->maxpacket)
521 || (urb->status != -EINPROGRESS);
522 if (done
523 && (urb->status == -EINPROGRESS)
524 && (urb->transfer_flags & URB_SHORT_NOT_OK)
525 && (urb->actual_length
526 < urb->transfer_buffer_length))
527 urb->status = -EREMOTEIO;
528 }
529
530 musb_read_fifo(hw_ep, length, buf);
531
532 csr = musb_readw(epio, MUSB_RXCSR);
533 csr |= MUSB_RXCSR_H_WZC_BITS;
534 if (unlikely(do_flush))
535 musb_h_flush_rxfifo(hw_ep, csr);
536 else {
537 /* REVISIT this assumes AUTOCLEAR is never set */
538 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
539 if (!done)
540 csr |= MUSB_RXCSR_H_REQPKT;
541 musb_writew(epio, MUSB_RXCSR, csr);
542 }
543
544 return done;
545 }
546
547 /* we don't always need to reinit a given side of an endpoint...
548 * when we do, use tx/rx reinit routine and then construct a new CSR
549 * to address data toggle, NYET, and DMA or PIO.
550 *
551 * it's possible that driver bugs (especially for DMA) or aborting a
552 * transfer might have left the endpoint busier than it should be.
553 * the busy/not-empty tests are basically paranoia.
554 */
555 static void
556 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
557 {
558 u16 csr;
559
560 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
561 * That always uses tx_reinit since ep0 repurposes TX register
562 * offsets; the initial SETUP packet is also a kind of OUT.
563 */
564
565 /* if programmed for Tx, put it in RX mode */
566 if (ep->is_shared_fifo) {
567 csr = musb_readw(ep->regs, MUSB_TXCSR);
568 if (csr & MUSB_TXCSR_MODE) {
569 musb_h_tx_flush_fifo(ep);
570 csr = musb_readw(ep->regs, MUSB_TXCSR);
571 musb_writew(ep->regs, MUSB_TXCSR,
572 csr | MUSB_TXCSR_FRCDATATOG);
573 }
574
575 /*
576 * Clear the MODE bit (and everything else) to enable Rx.
577 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
578 */
579 if (csr & MUSB_TXCSR_DMAMODE)
580 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
581 musb_writew(ep->regs, MUSB_TXCSR, 0);
582
583 /* scrub all previous state, clearing toggle */
584 } else {
585 csr = musb_readw(ep->regs, MUSB_RXCSR);
586 if (csr & MUSB_RXCSR_RXPKTRDY)
587 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
588 musb_readw(ep->regs, MUSB_RXCOUNT));
589
590 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
591 }
592
593 /* target addr and (for multipoint) hub addr/port */
594 if (musb->is_multipoint) {
595 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
596 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
597 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
598
599 } else
600 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
601
602 /* protocol/endpoint, interval/NAKlimit, i/o size */
603 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
604 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
605 /* NOTE: bulk combining rewrites high bits of maxpacket */
606 /* Set RXMAXP with the FIFO size of the endpoint
607 * to disable double buffer mode.
608 */
609 if (musb->double_buffer_not_ok)
610 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
611 else
612 musb_writew(ep->regs, MUSB_RXMAXP,
613 qh->maxpacket | ((qh->hb_mult - 1) << 11));
614
615 ep->rx_reinit = 0;
616 }
617
618 static bool musb_tx_dma_program(struct dma_controller *dma,
619 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
620 struct urb *urb, u32 offset, u32 length)
621 {
622 struct dma_channel *channel = hw_ep->tx_channel;
623 void __iomem *epio = hw_ep->regs;
624 u16 pkt_size = qh->maxpacket;
625 u16 csr;
626 u8 mode;
627
628 #ifdef CONFIG_USB_INVENTRA_DMA
629 if (length > channel->max_len)
630 length = channel->max_len;
631
632 csr = musb_readw(epio, MUSB_TXCSR);
633 if (length > pkt_size) {
634 mode = 1;
635 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
636 /* autoset shouldn't be set in high bandwidth */
637 /*
638 * Enable Autoset according to table
639 * below
640 * bulk_split hb_mult Autoset_Enable
641 * 0 1 Yes(Normal)
642 * 0 >1 No(High BW ISO)
643 * 1 1 Yes(HS bulk)
644 * 1 >1 Yes(FS bulk)
645 */
646 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
647 can_bulk_split(hw_ep->musb, qh->type)))
648 csr |= MUSB_TXCSR_AUTOSET;
649 } else {
650 mode = 0;
651 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
652 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
653 }
654 channel->desired_mode = mode;
655 musb_writew(epio, MUSB_TXCSR, csr);
656 #else
657 if (!is_cppi_enabled() && !tusb_dma_omap())
658 return false;
659
660 channel->actual_len = 0;
661
662 /*
663 * TX uses "RNDIS" mode automatically but needs help
664 * to identify the zero-length-final-packet case.
665 */
666 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
667 #endif
668
669 qh->segsize = length;
670
671 /*
672 * Ensure the data reaches to main memory before starting
673 * DMA transfer
674 */
675 wmb();
676
677 if (!dma->channel_program(channel, pkt_size, mode,
678 urb->transfer_dma + offset, length)) {
679 dma->channel_release(channel);
680 hw_ep->tx_channel = NULL;
681
682 csr = musb_readw(epio, MUSB_TXCSR);
683 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
684 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
685 return false;
686 }
687 return true;
688 }
689
690 /*
691 * Program an HDRC endpoint as per the given URB
692 * Context: irqs blocked, controller lock held
693 */
694 static void musb_ep_program(struct musb *musb, u8 epnum,
695 struct urb *urb, int is_out,
696 u8 *buf, u32 offset, u32 len)
697 {
698 struct dma_controller *dma_controller;
699 struct dma_channel *dma_channel;
700 u8 dma_ok;
701 void __iomem *mbase = musb->mregs;
702 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
703 void __iomem *epio = hw_ep->regs;
704 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
705 u16 packet_sz = qh->maxpacket;
706 u8 use_dma = 1;
707 u16 csr;
708
709 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
710 "h_addr%02x h_port%02x bytes %d\n",
711 is_out ? "-->" : "<--",
712 epnum, urb, urb->dev->speed,
713 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
714 qh->h_addr_reg, qh->h_port_reg,
715 len);
716
717 musb_ep_select(mbase, epnum);
718
719 if (is_out && !len) {
720 use_dma = 0;
721 csr = musb_readw(epio, MUSB_TXCSR);
722 csr &= ~MUSB_TXCSR_DMAENAB;
723 musb_writew(epio, MUSB_TXCSR, csr);
724 hw_ep->tx_channel = NULL;
725 }
726
727 /* candidate for DMA? */
728 dma_controller = musb->dma_controller;
729 if (use_dma && is_dma_capable() && epnum && dma_controller) {
730 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
731 if (!dma_channel) {
732 dma_channel = dma_controller->channel_alloc(
733 dma_controller, hw_ep, is_out);
734 if (is_out)
735 hw_ep->tx_channel = dma_channel;
736 else
737 hw_ep->rx_channel = dma_channel;
738 }
739 } else
740 dma_channel = NULL;
741
742 /* make sure we clear DMAEnab, autoSet bits from previous run */
743
744 /* OUT/transmit/EP0 or IN/receive? */
745 if (is_out) {
746 u16 csr;
747 u16 int_txe;
748 u16 load_count;
749
750 csr = musb_readw(epio, MUSB_TXCSR);
751
752 /* disable interrupt in case we flush */
753 int_txe = musb->intrtxe;
754 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
755
756 /* general endpoint setup */
757 if (epnum) {
758 /* flush all old state, set default */
759 /*
760 * We could be flushing valid
761 * packets in double buffering
762 * case
763 */
764 if (!hw_ep->tx_double_buffered)
765 musb_h_tx_flush_fifo(hw_ep);
766
767 /*
768 * We must not clear the DMAMODE bit before or in
769 * the same cycle with the DMAENAB bit, so we clear
770 * the latter first...
771 */
772 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
773 | MUSB_TXCSR_AUTOSET
774 | MUSB_TXCSR_DMAENAB
775 | MUSB_TXCSR_FRCDATATOG
776 | MUSB_TXCSR_H_RXSTALL
777 | MUSB_TXCSR_H_ERROR
778 | MUSB_TXCSR_TXPKTRDY
779 );
780 csr |= MUSB_TXCSR_MODE;
781
782 if (!hw_ep->tx_double_buffered) {
783 if (usb_gettoggle(urb->dev, qh->epnum, 1))
784 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
785 | MUSB_TXCSR_H_DATATOGGLE;
786 else
787 csr |= MUSB_TXCSR_CLRDATATOG;
788 }
789
790 musb_writew(epio, MUSB_TXCSR, csr);
791 /* REVISIT may need to clear FLUSHFIFO ... */
792 csr &= ~MUSB_TXCSR_DMAMODE;
793 musb_writew(epio, MUSB_TXCSR, csr);
794 csr = musb_readw(epio, MUSB_TXCSR);
795 } else {
796 /* endpoint 0: just flush */
797 musb_h_ep0_flush_fifo(hw_ep);
798 }
799
800 /* target addr and (for multipoint) hub addr/port */
801 if (musb->is_multipoint) {
802 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
803 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
804 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
805 /* FIXME if !epnum, do the same for RX ... */
806 } else
807 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
808
809 /* protocol/endpoint/interval/NAKlimit */
810 if (epnum) {
811 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
812 if (musb->double_buffer_not_ok) {
813 musb_writew(epio, MUSB_TXMAXP,
814 hw_ep->max_packet_sz_tx);
815 } else if (can_bulk_split(musb, qh->type)) {
816 qh->hb_mult = hw_ep->max_packet_sz_tx
817 / packet_sz;
818 musb_writew(epio, MUSB_TXMAXP, packet_sz
819 | ((qh->hb_mult) - 1) << 11);
820 } else {
821 musb_writew(epio, MUSB_TXMAXP,
822 qh->maxpacket |
823 ((qh->hb_mult - 1) << 11));
824 }
825 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
826 } else {
827 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
828 if (musb->is_multipoint)
829 musb_writeb(epio, MUSB_TYPE0,
830 qh->type_reg);
831 }
832
833 if (can_bulk_split(musb, qh->type))
834 load_count = min((u32) hw_ep->max_packet_sz_tx,
835 len);
836 else
837 load_count = min((u32) packet_sz, len);
838
839 if (dma_channel && musb_tx_dma_program(dma_controller,
840 hw_ep, qh, urb, offset, len))
841 load_count = 0;
842
843 if (load_count) {
844 /* PIO to load FIFO */
845 qh->segsize = load_count;
846 if (!buf) {
847 sg_miter_start(&qh->sg_miter, urb->sg, 1,
848 SG_MITER_ATOMIC
849 | SG_MITER_FROM_SG);
850 if (!sg_miter_next(&qh->sg_miter)) {
851 dev_err(musb->controller,
852 "error: sg"
853 "list empty\n");
854 sg_miter_stop(&qh->sg_miter);
855 goto finish;
856 }
857 buf = qh->sg_miter.addr + urb->sg->offset +
858 urb->actual_length;
859 load_count = min_t(u32, load_count,
860 qh->sg_miter.length);
861 musb_write_fifo(hw_ep, load_count, buf);
862 qh->sg_miter.consumed = load_count;
863 sg_miter_stop(&qh->sg_miter);
864 } else
865 musb_write_fifo(hw_ep, load_count, buf);
866 }
867 finish:
868 /* re-enable interrupt */
869 musb_writew(mbase, MUSB_INTRTXE, int_txe);
870
871 /* IN/receive */
872 } else {
873 u16 csr;
874
875 if (hw_ep->rx_reinit) {
876 musb_rx_reinit(musb, qh, hw_ep);
877
878 /* init new state: toggle and NYET, maybe DMA later */
879 if (usb_gettoggle(urb->dev, qh->epnum, 0))
880 csr = MUSB_RXCSR_H_WR_DATATOGGLE
881 | MUSB_RXCSR_H_DATATOGGLE;
882 else
883 csr = 0;
884 if (qh->type == USB_ENDPOINT_XFER_INT)
885 csr |= MUSB_RXCSR_DISNYET;
886
887 } else {
888 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
889
890 if (csr & (MUSB_RXCSR_RXPKTRDY
891 | MUSB_RXCSR_DMAENAB
892 | MUSB_RXCSR_H_REQPKT))
893 ERR("broken !rx_reinit, ep%d csr %04x\n",
894 hw_ep->epnum, csr);
895
896 /* scrub any stale state, leaving toggle alone */
897 csr &= MUSB_RXCSR_DISNYET;
898 }
899
900 /* kick things off */
901
902 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
903 /* Candidate for DMA */
904 dma_channel->actual_len = 0L;
905 qh->segsize = len;
906
907 /* AUTOREQ is in a DMA register */
908 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
909 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
910
911 /*
912 * Unless caller treats short RX transfers as
913 * errors, we dare not queue multiple transfers.
914 */
915 dma_ok = dma_controller->channel_program(dma_channel,
916 packet_sz, !(urb->transfer_flags &
917 URB_SHORT_NOT_OK),
918 urb->transfer_dma + offset,
919 qh->segsize);
920 if (!dma_ok) {
921 dma_controller->channel_release(dma_channel);
922 hw_ep->rx_channel = dma_channel = NULL;
923 } else
924 csr |= MUSB_RXCSR_DMAENAB;
925 }
926
927 csr |= MUSB_RXCSR_H_REQPKT;
928 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
929 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
930 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
931 }
932 }
933
934 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
935 * the end; avoids starvation for other endpoints.
936 */
937 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
938 int is_in)
939 {
940 struct dma_channel *dma;
941 struct urb *urb;
942 void __iomem *mbase = musb->mregs;
943 void __iomem *epio = ep->regs;
944 struct musb_qh *cur_qh, *next_qh;
945 u16 rx_csr, tx_csr;
946
947 musb_ep_select(mbase, ep->epnum);
948 if (is_in) {
949 dma = is_dma_capable() ? ep->rx_channel : NULL;
950
951 /* clear nak timeout bit */
952 rx_csr = musb_readw(epio, MUSB_RXCSR);
953 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
954 rx_csr &= ~MUSB_RXCSR_DATAERROR;
955 musb_writew(epio, MUSB_RXCSR, rx_csr);
956
957 cur_qh = first_qh(&musb->in_bulk);
958 } else {
959 dma = is_dma_capable() ? ep->tx_channel : NULL;
960
961 /* clear nak timeout bit */
962 tx_csr = musb_readw(epio, MUSB_TXCSR);
963 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
964 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
965 musb_writew(epio, MUSB_TXCSR, tx_csr);
966
967 cur_qh = first_qh(&musb->out_bulk);
968 }
969 if (cur_qh) {
970 urb = next_urb(cur_qh);
971 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
972 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
973 musb->dma_controller->channel_abort(dma);
974 urb->actual_length += dma->actual_len;
975 dma->actual_len = 0L;
976 }
977 musb_save_toggle(cur_qh, is_in, urb);
978
979 if (is_in) {
980 /* move cur_qh to end of queue */
981 list_move_tail(&cur_qh->ring, &musb->in_bulk);
982
983 /* get the next qh from musb->in_bulk */
984 next_qh = first_qh(&musb->in_bulk);
985
986 /* set rx_reinit and schedule the next qh */
987 ep->rx_reinit = 1;
988 } else {
989 /* move cur_qh to end of queue */
990 list_move_tail(&cur_qh->ring, &musb->out_bulk);
991
992 /* get the next qh from musb->out_bulk */
993 next_qh = first_qh(&musb->out_bulk);
994
995 /* set tx_reinit and schedule the next qh */
996 ep->tx_reinit = 1;
997 }
998 musb_start_urb(musb, is_in, next_qh);
999 }
1000 }
1001
1002 /*
1003 * Service the default endpoint (ep0) as host.
1004 * Return true until it's time to start the status stage.
1005 */
1006 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1007 {
1008 bool more = false;
1009 u8 *fifo_dest = NULL;
1010 u16 fifo_count = 0;
1011 struct musb_hw_ep *hw_ep = musb->control_ep;
1012 struct musb_qh *qh = hw_ep->in_qh;
1013 struct usb_ctrlrequest *request;
1014
1015 switch (musb->ep0_stage) {
1016 case MUSB_EP0_IN:
1017 fifo_dest = urb->transfer_buffer + urb->actual_length;
1018 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1019 urb->actual_length);
1020 if (fifo_count < len)
1021 urb->status = -EOVERFLOW;
1022
1023 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1024
1025 urb->actual_length += fifo_count;
1026 if (len < qh->maxpacket) {
1027 /* always terminate on short read; it's
1028 * rarely reported as an error.
1029 */
1030 } else if (urb->actual_length <
1031 urb->transfer_buffer_length)
1032 more = true;
1033 break;
1034 case MUSB_EP0_START:
1035 request = (struct usb_ctrlrequest *) urb->setup_packet;
1036
1037 if (!request->wLength) {
1038 dev_dbg(musb->controller, "start no-DATA\n");
1039 break;
1040 } else if (request->bRequestType & USB_DIR_IN) {
1041 dev_dbg(musb->controller, "start IN-DATA\n");
1042 musb->ep0_stage = MUSB_EP0_IN;
1043 more = true;
1044 break;
1045 } else {
1046 dev_dbg(musb->controller, "start OUT-DATA\n");
1047 musb->ep0_stage = MUSB_EP0_OUT;
1048 more = true;
1049 }
1050 /* FALLTHROUGH */
1051 case MUSB_EP0_OUT:
1052 fifo_count = min_t(size_t, qh->maxpacket,
1053 urb->transfer_buffer_length -
1054 urb->actual_length);
1055 if (fifo_count) {
1056 fifo_dest = (u8 *) (urb->transfer_buffer
1057 + urb->actual_length);
1058 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
1059 fifo_count,
1060 (fifo_count == 1) ? "" : "s",
1061 fifo_dest);
1062 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1063
1064 urb->actual_length += fifo_count;
1065 more = true;
1066 }
1067 break;
1068 default:
1069 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1070 break;
1071 }
1072
1073 return more;
1074 }
1075
1076 /*
1077 * Handle default endpoint interrupt as host. Only called in IRQ time
1078 * from musb_interrupt().
1079 *
1080 * called with controller irqlocked
1081 */
1082 irqreturn_t musb_h_ep0_irq(struct musb *musb)
1083 {
1084 struct urb *urb;
1085 u16 csr, len;
1086 int status = 0;
1087 void __iomem *mbase = musb->mregs;
1088 struct musb_hw_ep *hw_ep = musb->control_ep;
1089 void __iomem *epio = hw_ep->regs;
1090 struct musb_qh *qh = hw_ep->in_qh;
1091 bool complete = false;
1092 irqreturn_t retval = IRQ_NONE;
1093
1094 /* ep0 only has one queue, "in" */
1095 urb = next_urb(qh);
1096
1097 musb_ep_select(mbase, 0);
1098 csr = musb_readw(epio, MUSB_CSR0);
1099 len = (csr & MUSB_CSR0_RXPKTRDY)
1100 ? musb_readb(epio, MUSB_COUNT0)
1101 : 0;
1102
1103 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1104 csr, qh, len, urb, musb->ep0_stage);
1105
1106 /* if we just did status stage, we are done */
1107 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1108 retval = IRQ_HANDLED;
1109 complete = true;
1110 }
1111
1112 /* prepare status */
1113 if (csr & MUSB_CSR0_H_RXSTALL) {
1114 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1115 status = -EPIPE;
1116
1117 } else if (csr & MUSB_CSR0_H_ERROR) {
1118 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1119 status = -EPROTO;
1120
1121 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1122 dev_dbg(musb->controller, "control NAK timeout\n");
1123
1124 /* NOTE: this code path would be a good place to PAUSE a
1125 * control transfer, if another one is queued, so that
1126 * ep0 is more likely to stay busy. That's already done
1127 * for bulk RX transfers.
1128 *
1129 * if (qh->ring.next != &musb->control), then
1130 * we have a candidate... NAKing is *NOT* an error
1131 */
1132 musb_writew(epio, MUSB_CSR0, 0);
1133 retval = IRQ_HANDLED;
1134 }
1135
1136 if (status) {
1137 dev_dbg(musb->controller, "aborting\n");
1138 retval = IRQ_HANDLED;
1139 if (urb)
1140 urb->status = status;
1141 complete = true;
1142
1143 /* use the proper sequence to abort the transfer */
1144 if (csr & MUSB_CSR0_H_REQPKT) {
1145 csr &= ~MUSB_CSR0_H_REQPKT;
1146 musb_writew(epio, MUSB_CSR0, csr);
1147 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1148 musb_writew(epio, MUSB_CSR0, csr);
1149 } else {
1150 musb_h_ep0_flush_fifo(hw_ep);
1151 }
1152
1153 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1154
1155 /* clear it */
1156 musb_writew(epio, MUSB_CSR0, 0);
1157 }
1158
1159 if (unlikely(!urb)) {
1160 /* stop endpoint since we have no place for its data, this
1161 * SHOULD NEVER HAPPEN! */
1162 ERR("no URB for end 0\n");
1163
1164 musb_h_ep0_flush_fifo(hw_ep);
1165 goto done;
1166 }
1167
1168 if (!complete) {
1169 /* call common logic and prepare response */
1170 if (musb_h_ep0_continue(musb, len, urb)) {
1171 /* more packets required */
1172 csr = (MUSB_EP0_IN == musb->ep0_stage)
1173 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1174 } else {
1175 /* data transfer complete; perform status phase */
1176 if (usb_pipeout(urb->pipe)
1177 || !urb->transfer_buffer_length)
1178 csr = MUSB_CSR0_H_STATUSPKT
1179 | MUSB_CSR0_H_REQPKT;
1180 else
1181 csr = MUSB_CSR0_H_STATUSPKT
1182 | MUSB_CSR0_TXPKTRDY;
1183
1184 /* flag status stage */
1185 musb->ep0_stage = MUSB_EP0_STATUS;
1186
1187 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1188
1189 }
1190 musb_writew(epio, MUSB_CSR0, csr);
1191 retval = IRQ_HANDLED;
1192 } else
1193 musb->ep0_stage = MUSB_EP0_IDLE;
1194
1195 /* call completion handler if done */
1196 if (complete)
1197 musb_advance_schedule(musb, urb, hw_ep, 1);
1198 done:
1199 return retval;
1200 }
1201
1202
1203 #ifdef CONFIG_USB_INVENTRA_DMA
1204
1205 /* Host side TX (OUT) using Mentor DMA works as follows:
1206 submit_urb ->
1207 - if queue was empty, Program Endpoint
1208 - ... which starts DMA to fifo in mode 1 or 0
1209
1210 DMA Isr (transfer complete) -> TxAvail()
1211 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1212 only in musb_cleanup_urb)
1213 - TxPktRdy has to be set in mode 0 or for
1214 short packets in mode 1.
1215 */
1216
1217 #endif
1218
1219 /* Service a Tx-Available or dma completion irq for the endpoint */
1220 void musb_host_tx(struct musb *musb, u8 epnum)
1221 {
1222 int pipe;
1223 bool done = false;
1224 u16 tx_csr;
1225 size_t length = 0;
1226 size_t offset = 0;
1227 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1228 void __iomem *epio = hw_ep->regs;
1229 struct musb_qh *qh = hw_ep->out_qh;
1230 struct urb *urb = next_urb(qh);
1231 u32 status = 0;
1232 void __iomem *mbase = musb->mregs;
1233 struct dma_channel *dma;
1234 bool transfer_pending = false;
1235 static bool use_sg;
1236
1237 musb_ep_select(mbase, epnum);
1238 tx_csr = musb_readw(epio, MUSB_TXCSR);
1239
1240 /* with CPPI, DMA sometimes triggers "extra" irqs */
1241 if (!urb) {
1242 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1243 return;
1244 }
1245
1246 pipe = urb->pipe;
1247 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1248 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1249 dma ? ", dma" : "");
1250
1251 /* check for errors */
1252 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1253 /* dma was disabled, fifo flushed */
1254 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1255
1256 /* stall; record URB status */
1257 status = -EPIPE;
1258
1259 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1260 /* (NON-ISO) dma was disabled, fifo flushed */
1261 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1262
1263 status = -ETIMEDOUT;
1264
1265 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1266 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1267 && !list_is_singular(&musb->out_bulk)) {
1268 dev_dbg(musb->controller,
1269 "NAK timeout on TX%d ep\n", epnum);
1270 musb_bulk_nak_timeout(musb, hw_ep, 0);
1271 } else {
1272 dev_dbg(musb->controller,
1273 "TX end=%d device not responding\n", epnum);
1274 /* NOTE: this code path would be a good place to PAUSE a
1275 * transfer, if there's some other (nonperiodic) tx urb
1276 * that could use this fifo. (dma complicates it...)
1277 * That's already done for bulk RX transfers.
1278 *
1279 * if (bulk && qh->ring.next != &musb->out_bulk), then
1280 * we have a candidate... NAKing is *NOT* an error
1281 */
1282 musb_ep_select(mbase, epnum);
1283 musb_writew(epio, MUSB_TXCSR,
1284 MUSB_TXCSR_H_WZC_BITS
1285 | MUSB_TXCSR_TXPKTRDY);
1286 }
1287 return;
1288 }
1289
1290 done:
1291 if (status) {
1292 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1293 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1294 (void) musb->dma_controller->channel_abort(dma);
1295 }
1296
1297 /* do the proper sequence to abort the transfer in the
1298 * usb core; the dma engine should already be stopped.
1299 */
1300 musb_h_tx_flush_fifo(hw_ep);
1301 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1302 | MUSB_TXCSR_DMAENAB
1303 | MUSB_TXCSR_H_ERROR
1304 | MUSB_TXCSR_H_RXSTALL
1305 | MUSB_TXCSR_H_NAKTIMEOUT
1306 );
1307
1308 musb_ep_select(mbase, epnum);
1309 musb_writew(epio, MUSB_TXCSR, tx_csr);
1310 /* REVISIT may need to clear FLUSHFIFO ... */
1311 musb_writew(epio, MUSB_TXCSR, tx_csr);
1312 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1313
1314 done = true;
1315 }
1316
1317 /* second cppi case */
1318 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1319 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1320 return;
1321 }
1322
1323 if (is_dma_capable() && dma && !status) {
1324 /*
1325 * DMA has completed. But if we're using DMA mode 1 (multi
1326 * packet DMA), we need a terminal TXPKTRDY interrupt before
1327 * we can consider this transfer completed, lest we trash
1328 * its last packet when writing the next URB's data. So we
1329 * switch back to mode 0 to get that interrupt; we'll come
1330 * back here once it happens.
1331 */
1332 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1333 /*
1334 * We shouldn't clear DMAMODE with DMAENAB set; so
1335 * clear them in a safe order. That should be OK
1336 * once TXPKTRDY has been set (and I've never seen
1337 * it being 0 at this moment -- DMA interrupt latency
1338 * is significant) but if it hasn't been then we have
1339 * no choice but to stop being polite and ignore the
1340 * programmer's guide... :-)
1341 *
1342 * Note that we must write TXCSR with TXPKTRDY cleared
1343 * in order not to re-trigger the packet send (this bit
1344 * can't be cleared by CPU), and there's another caveat:
1345 * TXPKTRDY may be set shortly and then cleared in the
1346 * double-buffered FIFO mode, so we do an extra TXCSR
1347 * read for debouncing...
1348 */
1349 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1350 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1351 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1352 MUSB_TXCSR_TXPKTRDY);
1353 musb_writew(epio, MUSB_TXCSR,
1354 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1355 }
1356 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1357 MUSB_TXCSR_TXPKTRDY);
1358 musb_writew(epio, MUSB_TXCSR,
1359 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1360
1361 /*
1362 * There is no guarantee that we'll get an interrupt
1363 * after clearing DMAMODE as we might have done this
1364 * too late (after TXPKTRDY was cleared by controller).
1365 * Re-read TXCSR as we have spoiled its previous value.
1366 */
1367 tx_csr = musb_readw(epio, MUSB_TXCSR);
1368 }
1369
1370 /*
1371 * We may get here from a DMA completion or TXPKTRDY interrupt.
1372 * In any case, we must check the FIFO status here and bail out
1373 * only if the FIFO still has data -- that should prevent the
1374 * "missed" TXPKTRDY interrupts and deal with double-buffered
1375 * FIFO mode too...
1376 */
1377 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1378 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1379 "CSR %04x\n", tx_csr);
1380 return;
1381 }
1382 }
1383
1384 if (!status || dma || usb_pipeisoc(pipe)) {
1385 if (dma)
1386 length = dma->actual_len;
1387 else
1388 length = qh->segsize;
1389 qh->offset += length;
1390
1391 if (usb_pipeisoc(pipe)) {
1392 struct usb_iso_packet_descriptor *d;
1393
1394 d = urb->iso_frame_desc + qh->iso_idx;
1395 d->actual_length = length;
1396 d->status = status;
1397 if (++qh->iso_idx >= urb->number_of_packets) {
1398 done = true;
1399 } else {
1400 d++;
1401 offset = d->offset;
1402 length = d->length;
1403 }
1404 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1405 done = true;
1406 } else {
1407 /* see if we need to send more data, or ZLP */
1408 if (qh->segsize < qh->maxpacket)
1409 done = true;
1410 else if (qh->offset == urb->transfer_buffer_length
1411 && !(urb->transfer_flags
1412 & URB_ZERO_PACKET))
1413 done = true;
1414 if (!done) {
1415 offset = qh->offset;
1416 length = urb->transfer_buffer_length - offset;
1417 transfer_pending = true;
1418 }
1419 }
1420 }
1421
1422 /* urb->status != -EINPROGRESS means request has been faulted,
1423 * so we must abort this transfer after cleanup
1424 */
1425 if (urb->status != -EINPROGRESS) {
1426 done = true;
1427 if (status == 0)
1428 status = urb->status;
1429 }
1430
1431 if (done) {
1432 /* set status */
1433 urb->status = status;
1434 urb->actual_length = qh->offset;
1435 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1436 return;
1437 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1438 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1439 offset, length)) {
1440 if (is_cppi_enabled() || tusb_dma_omap())
1441 musb_h_tx_dma_start(hw_ep);
1442 return;
1443 }
1444 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1445 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1446 return;
1447 }
1448
1449 /*
1450 * PIO: start next packet in this URB.
1451 *
1452 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1453 * (and presumably, FIFO is not half-full) we should write *two*
1454 * packets before updating TXCSR; other docs disagree...
1455 */
1456 if (length > qh->maxpacket)
1457 length = qh->maxpacket;
1458 /* Unmap the buffer so that CPU can use it */
1459 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1460
1461 /*
1462 * We need to map sg if the transfer_buffer is
1463 * NULL.
1464 */
1465 if (!urb->transfer_buffer)
1466 use_sg = true;
1467
1468 if (use_sg) {
1469 /* sg_miter_start is already done in musb_ep_program */
1470 if (!sg_miter_next(&qh->sg_miter)) {
1471 dev_err(musb->controller, "error: sg list empty\n");
1472 sg_miter_stop(&qh->sg_miter);
1473 status = -EINVAL;
1474 goto done;
1475 }
1476 urb->transfer_buffer = qh->sg_miter.addr;
1477 length = min_t(u32, length, qh->sg_miter.length);
1478 musb_write_fifo(hw_ep, length, urb->transfer_buffer);
1479 qh->sg_miter.consumed = length;
1480 sg_miter_stop(&qh->sg_miter);
1481 } else {
1482 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1483 }
1484
1485 qh->segsize = length;
1486
1487 if (use_sg) {
1488 if (offset + length >= urb->transfer_buffer_length)
1489 use_sg = false;
1490 }
1491
1492 musb_ep_select(mbase, epnum);
1493 musb_writew(epio, MUSB_TXCSR,
1494 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1495 }
1496
1497
1498 #ifdef CONFIG_USB_INVENTRA_DMA
1499
1500 /* Host side RX (IN) using Mentor DMA works as follows:
1501 submit_urb ->
1502 - if queue was empty, ProgramEndpoint
1503 - first IN token is sent out (by setting ReqPkt)
1504 LinuxIsr -> RxReady()
1505 /\ => first packet is received
1506 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1507 | -> DMA Isr (transfer complete) -> RxReady()
1508 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1509 | - if urb not complete, send next IN token (ReqPkt)
1510 | | else complete urb.
1511 | |
1512 ---------------------------
1513 *
1514 * Nuances of mode 1:
1515 * For short packets, no ack (+RxPktRdy) is sent automatically
1516 * (even if AutoClear is ON)
1517 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1518 * automatically => major problem, as collecting the next packet becomes
1519 * difficult. Hence mode 1 is not used.
1520 *
1521 * REVISIT
1522 * All we care about at this driver level is that
1523 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1524 * (b) termination conditions are: short RX, or buffer full;
1525 * (c) fault modes include
1526 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1527 * (and that endpoint's dma queue stops immediately)
1528 * - overflow (full, PLUS more bytes in the terminal packet)
1529 *
1530 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1531 * thus be a great candidate for using mode 1 ... for all but the
1532 * last packet of one URB's transfer.
1533 */
1534
1535 #endif
1536
1537 /*
1538 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1539 * and high-bandwidth IN transfer cases.
1540 */
1541 void musb_host_rx(struct musb *musb, u8 epnum)
1542 {
1543 struct urb *urb;
1544 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1545 void __iomem *epio = hw_ep->regs;
1546 struct musb_qh *qh = hw_ep->in_qh;
1547 size_t xfer_len;
1548 void __iomem *mbase = musb->mregs;
1549 int pipe;
1550 u16 rx_csr, val;
1551 bool iso_err = false;
1552 bool done = false;
1553 u32 status;
1554 struct dma_channel *dma;
1555 static bool use_sg;
1556 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
1557
1558 musb_ep_select(mbase, epnum);
1559
1560 urb = next_urb(qh);
1561 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1562 status = 0;
1563 xfer_len = 0;
1564
1565 rx_csr = musb_readw(epio, MUSB_RXCSR);
1566 val = rx_csr;
1567
1568 if (unlikely(!urb)) {
1569 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1570 * usbtest #11 (unlinks) triggers it regularly, sometimes
1571 * with fifo full. (Only with DMA??)
1572 */
1573 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1574 musb_readw(epio, MUSB_RXCOUNT));
1575 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1576 return;
1577 }
1578
1579 pipe = urb->pipe;
1580
1581 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1582 epnum, rx_csr, urb->actual_length,
1583 dma ? dma->actual_len : 0);
1584
1585 /* check for errors, concurrent stall & unlink is not really
1586 * handled yet! */
1587 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1588 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1589
1590 /* stall; record URB status */
1591 status = -EPIPE;
1592
1593 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1594 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1595
1596 status = -EPROTO;
1597 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1598
1599 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1600
1601 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1602 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1603
1604 /* NOTE: NAKing is *NOT* an error, so we want to
1605 * continue. Except ... if there's a request for
1606 * another QH, use that instead of starving it.
1607 *
1608 * Devices like Ethernet and serial adapters keep
1609 * reads posted at all times, which will starve
1610 * other devices without this logic.
1611 */
1612 if (usb_pipebulk(urb->pipe)
1613 && qh->mux == 1
1614 && !list_is_singular(&musb->in_bulk)) {
1615 musb_bulk_nak_timeout(musb, hw_ep, 1);
1616 return;
1617 }
1618 musb_ep_select(mbase, epnum);
1619 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1620 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1621 musb_writew(epio, MUSB_RXCSR, rx_csr);
1622
1623 goto finish;
1624 } else {
1625 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1626 /* packet error reported later */
1627 iso_err = true;
1628 }
1629 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1630 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1631 epnum);
1632 status = -EPROTO;
1633 }
1634
1635 /* faults abort the transfer */
1636 if (status) {
1637 /* clean up dma and collect transfer count */
1638 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1639 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1640 (void) musb->dma_controller->channel_abort(dma);
1641 xfer_len = dma->actual_len;
1642 }
1643 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1644 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1645 done = true;
1646 goto finish;
1647 }
1648
1649 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1650 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1651 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1652 goto finish;
1653 }
1654
1655 /* thorough shutdown for now ... given more precise fault handling
1656 * and better queueing support, we might keep a DMA pipeline going
1657 * while processing this irq for earlier completions.
1658 */
1659
1660 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1661
1662 #ifndef CONFIG_USB_INVENTRA_DMA
1663 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1664 /* REVISIT this happened for a while on some short reads...
1665 * the cleanup still needs investigation... looks bad...
1666 * and also duplicates dma cleanup code above ... plus,
1667 * shouldn't this be the "half full" double buffer case?
1668 */
1669 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1670 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1671 (void) musb->dma_controller->channel_abort(dma);
1672 xfer_len = dma->actual_len;
1673 done = true;
1674 }
1675
1676 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1677 xfer_len, dma ? ", dma" : "");
1678 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1679
1680 musb_ep_select(mbase, epnum);
1681 musb_writew(epio, MUSB_RXCSR,
1682 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1683 }
1684 #endif
1685 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1686 xfer_len = dma->actual_len;
1687
1688 val &= ~(MUSB_RXCSR_DMAENAB
1689 | MUSB_RXCSR_H_AUTOREQ
1690 | MUSB_RXCSR_AUTOCLEAR
1691 | MUSB_RXCSR_RXPKTRDY);
1692 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1693
1694 #ifdef CONFIG_USB_INVENTRA_DMA
1695 if (usb_pipeisoc(pipe)) {
1696 struct usb_iso_packet_descriptor *d;
1697
1698 d = urb->iso_frame_desc + qh->iso_idx;
1699 d->actual_length = xfer_len;
1700
1701 /* even if there was an error, we did the dma
1702 * for iso_frame_desc->length
1703 */
1704 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1705 d->status = 0;
1706
1707 if (++qh->iso_idx >= urb->number_of_packets)
1708 done = true;
1709 else
1710 done = false;
1711
1712 } else {
1713 /* done if urb buffer is full or short packet is recd */
1714 done = (urb->actual_length + xfer_len >=
1715 urb->transfer_buffer_length
1716 || dma->actual_len < qh->maxpacket);
1717 }
1718
1719 /* send IN token for next packet, without AUTOREQ */
1720 if (!done) {
1721 val |= MUSB_RXCSR_H_REQPKT;
1722 musb_writew(epio, MUSB_RXCSR,
1723 MUSB_RXCSR_H_WZC_BITS | val);
1724 }
1725
1726 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1727 done ? "off" : "reset",
1728 musb_readw(epio, MUSB_RXCSR),
1729 musb_readw(epio, MUSB_RXCOUNT));
1730 #else
1731 done = true;
1732 #endif
1733 } else if (urb->status == -EINPROGRESS) {
1734 /* if no errors, be sure a packet is ready for unloading */
1735 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1736 status = -EPROTO;
1737 ERR("Rx interrupt with no errors or packet!\n");
1738
1739 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1740
1741 /* SCRUB (RX) */
1742 /* do the proper sequence to abort the transfer */
1743 musb_ep_select(mbase, epnum);
1744 val &= ~MUSB_RXCSR_H_REQPKT;
1745 musb_writew(epio, MUSB_RXCSR, val);
1746 goto finish;
1747 }
1748
1749 /* we are expecting IN packets */
1750 #ifdef CONFIG_USB_INVENTRA_DMA
1751 if (dma) {
1752 struct dma_controller *c;
1753 u16 rx_count;
1754 int ret, length;
1755 dma_addr_t buf;
1756
1757 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1758
1759 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
1760 epnum, rx_count,
1761 urb->transfer_dma
1762 + urb->actual_length,
1763 qh->offset,
1764 urb->transfer_buffer_length);
1765
1766 c = musb->dma_controller;
1767
1768 if (usb_pipeisoc(pipe)) {
1769 int d_status = 0;
1770 struct usb_iso_packet_descriptor *d;
1771
1772 d = urb->iso_frame_desc + qh->iso_idx;
1773
1774 if (iso_err) {
1775 d_status = -EILSEQ;
1776 urb->error_count++;
1777 }
1778 if (rx_count > d->length) {
1779 if (d_status == 0) {
1780 d_status = -EOVERFLOW;
1781 urb->error_count++;
1782 }
1783 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1784 rx_count, d->length);
1785
1786 length = d->length;
1787 } else
1788 length = rx_count;
1789 d->status = d_status;
1790 buf = urb->transfer_dma + d->offset;
1791 } else {
1792 length = rx_count;
1793 buf = urb->transfer_dma +
1794 urb->actual_length;
1795 }
1796
1797 dma->desired_mode = 0;
1798 #ifdef USE_MODE1
1799 /* because of the issue below, mode 1 will
1800 * only rarely behave with correct semantics.
1801 */
1802 if ((urb->transfer_flags &
1803 URB_SHORT_NOT_OK)
1804 && (urb->transfer_buffer_length -
1805 urb->actual_length)
1806 > qh->maxpacket)
1807 dma->desired_mode = 1;
1808 if (rx_count < hw_ep->max_packet_sz_rx) {
1809 length = rx_count;
1810 dma->desired_mode = 0;
1811 } else {
1812 length = urb->transfer_buffer_length;
1813 }
1814 #endif
1815
1816 /* Disadvantage of using mode 1:
1817 * It's basically usable only for mass storage class; essentially all
1818 * other protocols also terminate transfers on short packets.
1819 *
1820 * Details:
1821 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1822 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1823 * to use the extra IN token to grab the last packet using mode 0, then
1824 * the problem is that you cannot be sure when the device will send the
1825 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1826 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1827 * transfer, while sometimes it is recd just a little late so that if you
1828 * try to configure for mode 0 soon after the mode 1 transfer is
1829 * completed, you will find rxcount 0. Okay, so you might think why not
1830 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1831 */
1832
1833 val = musb_readw(epio, MUSB_RXCSR);
1834 val &= ~MUSB_RXCSR_H_REQPKT;
1835
1836 if (dma->desired_mode == 0)
1837 val &= ~MUSB_RXCSR_H_AUTOREQ;
1838 else
1839 val |= MUSB_RXCSR_H_AUTOREQ;
1840 val |= MUSB_RXCSR_DMAENAB;
1841
1842 /* autoclear shouldn't be set in high bandwidth */
1843 if (qh->hb_mult == 1)
1844 val |= MUSB_RXCSR_AUTOCLEAR;
1845
1846 musb_writew(epio, MUSB_RXCSR,
1847 MUSB_RXCSR_H_WZC_BITS | val);
1848
1849 /* REVISIT if when actual_length != 0,
1850 * transfer_buffer_length needs to be
1851 * adjusted first...
1852 */
1853 ret = c->channel_program(
1854 dma, qh->maxpacket,
1855 dma->desired_mode, buf, length);
1856
1857 if (!ret) {
1858 c->channel_release(dma);
1859 hw_ep->rx_channel = NULL;
1860 dma = NULL;
1861 val = musb_readw(epio, MUSB_RXCSR);
1862 val &= ~(MUSB_RXCSR_DMAENAB
1863 | MUSB_RXCSR_H_AUTOREQ
1864 | MUSB_RXCSR_AUTOCLEAR);
1865 musb_writew(epio, MUSB_RXCSR, val);
1866 }
1867 }
1868 #endif /* Mentor DMA */
1869
1870 if (!dma) {
1871 unsigned int received_len;
1872
1873 /* Unmap the buffer so that CPU can use it */
1874 usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
1875
1876 /*
1877 * We need to map sg if the transfer_buffer is
1878 * NULL.
1879 */
1880 if (!urb->transfer_buffer) {
1881 use_sg = true;
1882 sg_miter_start(&qh->sg_miter, urb->sg, 1,
1883 sg_flags);
1884 }
1885
1886 if (use_sg) {
1887 if (!sg_miter_next(&qh->sg_miter)) {
1888 dev_err(musb->controller, "error: sg list empty\n");
1889 sg_miter_stop(&qh->sg_miter);
1890 status = -EINVAL;
1891 done = true;
1892 goto finish;
1893 }
1894 urb->transfer_buffer = qh->sg_miter.addr;
1895 received_len = urb->actual_length;
1896 qh->offset = 0x0;
1897 done = musb_host_packet_rx(musb, urb, epnum,
1898 iso_err);
1899 /* Calculate the number of bytes received */
1900 received_len = urb->actual_length -
1901 received_len;
1902 qh->sg_miter.consumed = received_len;
1903 sg_miter_stop(&qh->sg_miter);
1904 } else {
1905 done = musb_host_packet_rx(musb, urb,
1906 epnum, iso_err);
1907 }
1908 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
1909 }
1910 }
1911
1912 finish:
1913 urb->actual_length += xfer_len;
1914 qh->offset += xfer_len;
1915 if (done) {
1916 if (use_sg)
1917 use_sg = false;
1918
1919 if (urb->status == -EINPROGRESS)
1920 urb->status = status;
1921 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1922 }
1923 }
1924
1925 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1926 * the software schedule associates multiple such nodes with a given
1927 * host side hardware endpoint + direction; scheduling may activate
1928 * that hardware endpoint.
1929 */
1930 static int musb_schedule(
1931 struct musb *musb,
1932 struct musb_qh *qh,
1933 int is_in)
1934 {
1935 int idle;
1936 int best_diff;
1937 int best_end, epnum;
1938 struct musb_hw_ep *hw_ep = NULL;
1939 struct list_head *head = NULL;
1940 u8 toggle;
1941 u8 txtype;
1942 struct urb *urb = next_urb(qh);
1943
1944 /* use fixed hardware for control and bulk */
1945 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1946 head = &musb->control;
1947 hw_ep = musb->control_ep;
1948 goto success;
1949 }
1950
1951 /* else, periodic transfers get muxed to other endpoints */
1952
1953 /*
1954 * We know this qh hasn't been scheduled, so all we need to do
1955 * is choose which hardware endpoint to put it on ...
1956 *
1957 * REVISIT what we really want here is a regular schedule tree
1958 * like e.g. OHCI uses.
1959 */
1960 best_diff = 4096;
1961 best_end = -1;
1962
1963 for (epnum = 1, hw_ep = musb->endpoints + 1;
1964 epnum < musb->nr_endpoints;
1965 epnum++, hw_ep++) {
1966 int diff;
1967
1968 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1969 continue;
1970
1971 if (hw_ep == musb->bulk_ep)
1972 continue;
1973
1974 if (is_in)
1975 diff = hw_ep->max_packet_sz_rx;
1976 else
1977 diff = hw_ep->max_packet_sz_tx;
1978 diff -= (qh->maxpacket * qh->hb_mult);
1979
1980 if (diff >= 0 && best_diff > diff) {
1981
1982 /*
1983 * Mentor controller has a bug in that if we schedule
1984 * a BULK Tx transfer on an endpoint that had earlier
1985 * handled ISOC then the BULK transfer has to start on
1986 * a zero toggle. If the BULK transfer starts on a 1
1987 * toggle then this transfer will fail as the mentor
1988 * controller starts the Bulk transfer on a 0 toggle
1989 * irrespective of the programming of the toggle bits
1990 * in the TXCSR register. Check for this condition
1991 * while allocating the EP for a Tx Bulk transfer. If
1992 * so skip this EP.
1993 */
1994 hw_ep = musb->endpoints + epnum;
1995 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
1996 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
1997 >> 4) & 0x3;
1998 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
1999 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2000 continue;
2001
2002 best_diff = diff;
2003 best_end = epnum;
2004 }
2005 }
2006 /* use bulk reserved ep1 if no other ep is free */
2007 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
2008 hw_ep = musb->bulk_ep;
2009 if (is_in)
2010 head = &musb->in_bulk;
2011 else
2012 head = &musb->out_bulk;
2013
2014 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are
2015 * multiplexed. This scheme doen't work in high speed to full
2016 * speed scenario as NAK interrupts are not coming from a
2017 * full speed device connected to a high speed device.
2018 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
2019 * 4 (8 frame or 8ms) for FS device.
2020 */
2021 if (qh->dev)
2022 qh->intv_reg =
2023 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
2024 goto success;
2025 } else if (best_end < 0) {
2026 return -ENOSPC;
2027 }
2028
2029 idle = 1;
2030 qh->mux = 0;
2031 hw_ep = musb->endpoints + best_end;
2032 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
2033 success:
2034 if (head) {
2035 idle = list_empty(head);
2036 list_add_tail(&qh->ring, head);
2037 qh->mux = 1;
2038 }
2039 qh->hw_ep = hw_ep;
2040 qh->hep->hcpriv = qh;
2041 if (idle)
2042 musb_start_urb(musb, is_in, qh);
2043 return 0;
2044 }
2045
2046 static int musb_urb_enqueue(
2047 struct usb_hcd *hcd,
2048 struct urb *urb,
2049 gfp_t mem_flags)
2050 {
2051 unsigned long flags;
2052 struct musb *musb = hcd_to_musb(hcd);
2053 struct usb_host_endpoint *hep = urb->ep;
2054 struct musb_qh *qh;
2055 struct usb_endpoint_descriptor *epd = &hep->desc;
2056 int ret;
2057 unsigned type_reg;
2058 unsigned interval;
2059
2060 /* host role must be active */
2061 if (!is_host_active(musb) || !musb->is_active)
2062 return -ENODEV;
2063
2064 spin_lock_irqsave(&musb->lock, flags);
2065 ret = usb_hcd_link_urb_to_ep(hcd, urb);
2066 qh = ret ? NULL : hep->hcpriv;
2067 if (qh)
2068 urb->hcpriv = qh;
2069 spin_unlock_irqrestore(&musb->lock, flags);
2070
2071 /* DMA mapping was already done, if needed, and this urb is on
2072 * hep->urb_list now ... so we're done, unless hep wasn't yet
2073 * scheduled onto a live qh.
2074 *
2075 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
2076 * disabled, testing for empty qh->ring and avoiding qh setup costs
2077 * except for the first urb queued after a config change.
2078 */
2079 if (qh || ret)
2080 return ret;
2081
2082 /* Allocate and initialize qh, minimizing the work done each time
2083 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
2084 *
2085 * REVISIT consider a dedicated qh kmem_cache, so it's harder
2086 * for bugs in other kernel code to break this driver...
2087 */
2088 qh = kzalloc(sizeof *qh, mem_flags);
2089 if (!qh) {
2090 spin_lock_irqsave(&musb->lock, flags);
2091 usb_hcd_unlink_urb_from_ep(hcd, urb);
2092 spin_unlock_irqrestore(&musb->lock, flags);
2093 return -ENOMEM;
2094 }
2095
2096 qh->hep = hep;
2097 qh->dev = urb->dev;
2098 INIT_LIST_HEAD(&qh->ring);
2099 qh->is_ready = 1;
2100
2101 qh->maxpacket = usb_endpoint_maxp(epd);
2102 qh->type = usb_endpoint_type(epd);
2103
2104 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
2105 * Some musb cores don't support high bandwidth ISO transfers; and
2106 * we don't (yet!) support high bandwidth interrupt transfers.
2107 */
2108 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
2109 if (qh->hb_mult > 1) {
2110 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2111
2112 if (ok)
2113 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2114 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2115 if (!ok) {
2116 ret = -EMSGSIZE;
2117 goto done;
2118 }
2119 qh->maxpacket &= 0x7ff;
2120 }
2121
2122 qh->epnum = usb_endpoint_num(epd);
2123
2124 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
2125 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2126
2127 /* precompute rxtype/txtype/type0 register */
2128 type_reg = (qh->type << 4) | qh->epnum;
2129 switch (urb->dev->speed) {
2130 case USB_SPEED_LOW:
2131 type_reg |= 0xc0;
2132 break;
2133 case USB_SPEED_FULL:
2134 type_reg |= 0x80;
2135 break;
2136 default:
2137 type_reg |= 0x40;
2138 }
2139 qh->type_reg = type_reg;
2140
2141 /* Precompute RXINTERVAL/TXINTERVAL register */
2142 switch (qh->type) {
2143 case USB_ENDPOINT_XFER_INT:
2144 /*
2145 * Full/low speeds use the linear encoding,
2146 * high speed uses the logarithmic encoding.
2147 */
2148 if (urb->dev->speed <= USB_SPEED_FULL) {
2149 interval = max_t(u8, epd->bInterval, 1);
2150 break;
2151 }
2152 /* FALLTHROUGH */
2153 case USB_ENDPOINT_XFER_ISOC:
2154 /* ISO always uses logarithmic encoding */
2155 interval = min_t(u8, epd->bInterval, 16);
2156 break;
2157 default:
2158 /* REVISIT we actually want to use NAK limits, hinting to the
2159 * transfer scheduling logic to try some other qh, e.g. try
2160 * for 2 msec first:
2161 *
2162 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2163 *
2164 * The downside of disabling this is that transfer scheduling
2165 * gets VERY unfair for nonperiodic transfers; a misbehaving
2166 * peripheral could make that hurt. That's perfectly normal
2167 * for reads from network or serial adapters ... so we have
2168 * partial NAKlimit support for bulk RX.
2169 *
2170 * The upside of disabling it is simpler transfer scheduling.
2171 */
2172 interval = 0;
2173 }
2174 qh->intv_reg = interval;
2175
2176 /* precompute addressing for external hub/tt ports */
2177 if (musb->is_multipoint) {
2178 struct usb_device *parent = urb->dev->parent;
2179
2180 if (parent != hcd->self.root_hub) {
2181 qh->h_addr_reg = (u8) parent->devnum;
2182
2183 /* set up tt info if needed */
2184 if (urb->dev->tt) {
2185 qh->h_port_reg = (u8) urb->dev->ttport;
2186 if (urb->dev->tt->hub)
2187 qh->h_addr_reg =
2188 (u8) urb->dev->tt->hub->devnum;
2189 if (urb->dev->tt->multi)
2190 qh->h_addr_reg |= 0x80;
2191 }
2192 }
2193 }
2194
2195 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2196 * until we get real dma queues (with an entry for each urb/buffer),
2197 * we only have work to do in the former case.
2198 */
2199 spin_lock_irqsave(&musb->lock, flags);
2200 if (hep->hcpriv || !next_urb(qh)) {
2201 /* some concurrent activity submitted another urb to hep...
2202 * odd, rare, error prone, but legal.
2203 */
2204 kfree(qh);
2205 qh = NULL;
2206 ret = 0;
2207 } else
2208 ret = musb_schedule(musb, qh,
2209 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2210
2211 if (ret == 0) {
2212 urb->hcpriv = qh;
2213 /* FIXME set urb->start_frame for iso/intr, it's tested in
2214 * musb_start_urb(), but otherwise only konicawc cares ...
2215 */
2216 }
2217 spin_unlock_irqrestore(&musb->lock, flags);
2218
2219 done:
2220 if (ret != 0) {
2221 spin_lock_irqsave(&musb->lock, flags);
2222 usb_hcd_unlink_urb_from_ep(hcd, urb);
2223 spin_unlock_irqrestore(&musb->lock, flags);
2224 kfree(qh);
2225 }
2226 return ret;
2227 }
2228
2229
2230 /*
2231 * abort a transfer that's at the head of a hardware queue.
2232 * called with controller locked, irqs blocked
2233 * that hardware queue advances to the next transfer, unless prevented
2234 */
2235 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2236 {
2237 struct musb_hw_ep *ep = qh->hw_ep;
2238 struct musb *musb = ep->musb;
2239 void __iomem *epio = ep->regs;
2240 unsigned hw_end = ep->epnum;
2241 void __iomem *regs = ep->musb->mregs;
2242 int is_in = usb_pipein(urb->pipe);
2243 int status = 0;
2244 u16 csr;
2245
2246 musb_ep_select(regs, hw_end);
2247
2248 if (is_dma_capable()) {
2249 struct dma_channel *dma;
2250
2251 dma = is_in ? ep->rx_channel : ep->tx_channel;
2252 if (dma) {
2253 status = ep->musb->dma_controller->channel_abort(dma);
2254 dev_dbg(musb->controller,
2255 "abort %cX%d DMA for urb %p --> %d\n",
2256 is_in ? 'R' : 'T', ep->epnum,
2257 urb, status);
2258 urb->actual_length += dma->actual_len;
2259 }
2260 }
2261
2262 /* turn off DMA requests, discard state, stop polling ... */
2263 if (ep->epnum && is_in) {
2264 /* giveback saves bulk toggle */
2265 csr = musb_h_flush_rxfifo(ep, 0);
2266
2267 /* REVISIT we still get an irq; should likely clear the
2268 * endpoint's irq status here to avoid bogus irqs.
2269 * clearing that status is platform-specific...
2270 */
2271 } else if (ep->epnum) {
2272 musb_h_tx_flush_fifo(ep);
2273 csr = musb_readw(epio, MUSB_TXCSR);
2274 csr &= ~(MUSB_TXCSR_AUTOSET
2275 | MUSB_TXCSR_DMAENAB
2276 | MUSB_TXCSR_H_RXSTALL
2277 | MUSB_TXCSR_H_NAKTIMEOUT
2278 | MUSB_TXCSR_H_ERROR
2279 | MUSB_TXCSR_TXPKTRDY);
2280 musb_writew(epio, MUSB_TXCSR, csr);
2281 /* REVISIT may need to clear FLUSHFIFO ... */
2282 musb_writew(epio, MUSB_TXCSR, csr);
2283 /* flush cpu writebuffer */
2284 csr = musb_readw(epio, MUSB_TXCSR);
2285 } else {
2286 musb_h_ep0_flush_fifo(ep);
2287 }
2288 if (status == 0)
2289 musb_advance_schedule(ep->musb, urb, ep, is_in);
2290 return status;
2291 }
2292
2293 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2294 {
2295 struct musb *musb = hcd_to_musb(hcd);
2296 struct musb_qh *qh;
2297 unsigned long flags;
2298 int is_in = usb_pipein(urb->pipe);
2299 int ret;
2300
2301 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2302 usb_pipedevice(urb->pipe),
2303 usb_pipeendpoint(urb->pipe),
2304 is_in ? "in" : "out");
2305
2306 spin_lock_irqsave(&musb->lock, flags);
2307 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2308 if (ret)
2309 goto done;
2310
2311 qh = urb->hcpriv;
2312 if (!qh)
2313 goto done;
2314
2315 /*
2316 * Any URB not actively programmed into endpoint hardware can be
2317 * immediately given back; that's any URB not at the head of an
2318 * endpoint queue, unless someday we get real DMA queues. And even
2319 * if it's at the head, it might not be known to the hardware...
2320 *
2321 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2322 * has already been updated. This is a synchronous abort; it'd be
2323 * OK to hold off until after some IRQ, though.
2324 *
2325 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2326 */
2327 if (!qh->is_ready
2328 || urb->urb_list.prev != &qh->hep->urb_list
2329 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2330 int ready = qh->is_ready;
2331
2332 qh->is_ready = 0;
2333 musb_giveback(musb, urb, 0);
2334 qh->is_ready = ready;
2335
2336 /* If nothing else (usually musb_giveback) is using it
2337 * and its URB list has emptied, recycle this qh.
2338 */
2339 if (ready && list_empty(&qh->hep->urb_list)) {
2340 qh->hep->hcpriv = NULL;
2341 list_del(&qh->ring);
2342 kfree(qh);
2343 }
2344 } else
2345 ret = musb_cleanup_urb(urb, qh);
2346 done:
2347 spin_unlock_irqrestore(&musb->lock, flags);
2348 return ret;
2349 }
2350
2351 /* disable an endpoint */
2352 static void
2353 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2354 {
2355 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2356 unsigned long flags;
2357 struct musb *musb = hcd_to_musb(hcd);
2358 struct musb_qh *qh;
2359 struct urb *urb;
2360
2361 spin_lock_irqsave(&musb->lock, flags);
2362
2363 qh = hep->hcpriv;
2364 if (qh == NULL)
2365 goto exit;
2366
2367 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2368
2369 /* Kick the first URB off the hardware, if needed */
2370 qh->is_ready = 0;
2371 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2372 urb = next_urb(qh);
2373
2374 /* make software (then hardware) stop ASAP */
2375 if (!urb->unlinked)
2376 urb->status = -ESHUTDOWN;
2377
2378 /* cleanup */
2379 musb_cleanup_urb(urb, qh);
2380
2381 /* Then nuke all the others ... and advance the
2382 * queue on hw_ep (e.g. bulk ring) when we're done.
2383 */
2384 while (!list_empty(&hep->urb_list)) {
2385 urb = next_urb(qh);
2386 urb->status = -ESHUTDOWN;
2387 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2388 }
2389 } else {
2390 /* Just empty the queue; the hardware is busy with
2391 * other transfers, and since !qh->is_ready nothing
2392 * will activate any of these as it advances.
2393 */
2394 while (!list_empty(&hep->urb_list))
2395 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2396
2397 hep->hcpriv = NULL;
2398 list_del(&qh->ring);
2399 kfree(qh);
2400 }
2401 exit:
2402 spin_unlock_irqrestore(&musb->lock, flags);
2403 }
2404
2405 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2406 {
2407 struct musb *musb = hcd_to_musb(hcd);
2408
2409 return musb_readw(musb->mregs, MUSB_FRAME);
2410 }
2411
2412 static int musb_h_start(struct usb_hcd *hcd)
2413 {
2414 struct musb *musb = hcd_to_musb(hcd);
2415
2416 /* NOTE: musb_start() is called when the hub driver turns
2417 * on port power, or when (OTG) peripheral starts.
2418 */
2419 hcd->state = HC_STATE_RUNNING;
2420 musb->port1_status = 0;
2421 return 0;
2422 }
2423
2424 static void musb_h_stop(struct usb_hcd *hcd)
2425 {
2426 musb_stop(hcd_to_musb(hcd));
2427 hcd->state = HC_STATE_HALT;
2428 }
2429
2430 static int musb_bus_suspend(struct usb_hcd *hcd)
2431 {
2432 struct musb *musb = hcd_to_musb(hcd);
2433 u8 devctl;
2434
2435 if (!is_host_active(musb))
2436 return 0;
2437
2438 switch (musb->xceiv->state) {
2439 case OTG_STATE_A_SUSPEND:
2440 return 0;
2441 case OTG_STATE_A_WAIT_VRISE:
2442 /* ID could be grounded even if there's no device
2443 * on the other end of the cable. NOTE that the
2444 * A_WAIT_VRISE timers are messy with MUSB...
2445 */
2446 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2447 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2448 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2449 break;
2450 default:
2451 break;
2452 }
2453
2454 if (musb->is_active) {
2455 WARNING("trying to suspend as %s while active\n",
2456 otg_state_string(musb->xceiv->state));
2457 return -EBUSY;
2458 } else
2459 return 0;
2460 }
2461
2462 static int musb_bus_resume(struct usb_hcd *hcd)
2463 {
2464 /* resuming child port does the work */
2465 return 0;
2466 }
2467
2468 const struct hc_driver musb_hc_driver = {
2469 .description = "musb-hcd",
2470 .product_desc = "MUSB HDRC host driver",
2471 .hcd_priv_size = sizeof(struct musb),
2472 .flags = HCD_USB2 | HCD_MEMORY,
2473
2474 /* not using irq handler or reset hooks from usbcore, since
2475 * those must be shared with peripheral code for OTG configs
2476 */
2477
2478 .start = musb_h_start,
2479 .stop = musb_h_stop,
2480
2481 .get_frame_number = musb_h_get_frame_number,
2482
2483 .urb_enqueue = musb_urb_enqueue,
2484 .urb_dequeue = musb_urb_dequeue,
2485 .endpoint_disable = musb_h_disable,
2486
2487 .hub_status_data = musb_hub_status_data,
2488 .hub_control = musb_hub_control,
2489 .bus_suspend = musb_bus_suspend,
2490 .bus_resume = musb_bus_resume,
2491 /* .start_port_reset = NULL, */
2492 /* .hub_irq_enable = NULL, */
2493 };
Linux 2.6 libata-dev (mirror)