?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[linux-2.6/libata-dev.git] / drivers / edac / i5100_edac.c
blobe9e7c2a29dc389d9462f50e5b1d17367b9a7d194
1 /*
2 * Intel 5100 Memory Controllers kernel module
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * This module is based on the following document:
8 *
9 * Intel 5100X Chipset Memory Controller Hub (MCH) - Datasheet
10 * http://download.intel.com/design/chipsets/datashts/318378.pdf
11 *
12 * The intel 5100 has two independent channels. EDAC core currently
13 * can not reflect this configuration so instead the chip-select
14 * rows for each respective channel are laid out one after another,
15 * the first half belonging to channel 0, the second half belonging
16 * to channel 1.
17 *
18 * This driver is for DDR2 DIMMs, and it uses chip select to select among the
19 * several ranks. However, instead of showing memories as ranks, it outputs
20 * them as DIMM's. An internal table creates the association between ranks
21 * and DIMM's.
22 */
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/pci_ids.h>
27 #include <linux/edac.h>
28 #include <linux/delay.h>
29 #include <linux/mmzone.h>
30
31 #include "edac_core.h"
32
33 /* register addresses */
34
35 /* device 16, func 1 */
36 #define I5100_MC 0x40 /* Memory Control Register */
37 #define I5100_MC_SCRBEN_MASK (1 << 7)
38 #define I5100_MC_SCRBDONE_MASK (1 << 4)
39 #define I5100_MS 0x44 /* Memory Status Register */
40 #define I5100_SPDDATA 0x48 /* Serial Presence Detect Status Reg */
41 #define I5100_SPDCMD 0x4c /* Serial Presence Detect Command Reg */
42 #define I5100_TOLM 0x6c /* Top of Low Memory */
43 #define I5100_MIR0 0x80 /* Memory Interleave Range 0 */
44 #define I5100_MIR1 0x84 /* Memory Interleave Range 1 */
45 #define I5100_AMIR_0 0x8c /* Adjusted Memory Interleave Range 0 */
46 #define I5100_AMIR_1 0x90 /* Adjusted Memory Interleave Range 1 */
47 #define I5100_FERR_NF_MEM 0xa0 /* MC First Non Fatal Errors */
48 #define I5100_FERR_NF_MEM_M16ERR_MASK (1 << 16)
49 #define I5100_FERR_NF_MEM_M15ERR_MASK (1 << 15)
50 #define I5100_FERR_NF_MEM_M14ERR_MASK (1 << 14)
51 #define I5100_FERR_NF_MEM_M12ERR_MASK (1 << 12)
52 #define I5100_FERR_NF_MEM_M11ERR_MASK (1 << 11)
53 #define I5100_FERR_NF_MEM_M10ERR_MASK (1 << 10)
54 #define I5100_FERR_NF_MEM_M6ERR_MASK (1 << 6)
55 #define I5100_FERR_NF_MEM_M5ERR_MASK (1 << 5)
56 #define I5100_FERR_NF_MEM_M4ERR_MASK (1 << 4)
57 #define I5100_FERR_NF_MEM_M1ERR_MASK (1 << 1)
58 #define I5100_FERR_NF_MEM_ANY_MASK \
59 (I5100_FERR_NF_MEM_M16ERR_MASK | \
60 I5100_FERR_NF_MEM_M15ERR_MASK | \
61 I5100_FERR_NF_MEM_M14ERR_MASK | \
62 I5100_FERR_NF_MEM_M12ERR_MASK | \
63 I5100_FERR_NF_MEM_M11ERR_MASK | \
64 I5100_FERR_NF_MEM_M10ERR_MASK | \
65 I5100_FERR_NF_MEM_M6ERR_MASK | \
66 I5100_FERR_NF_MEM_M5ERR_MASK | \
67 I5100_FERR_NF_MEM_M4ERR_MASK | \
68 I5100_FERR_NF_MEM_M1ERR_MASK)
69 #define I5100_NERR_NF_MEM 0xa4 /* MC Next Non-Fatal Errors */
70 #define I5100_EMASK_MEM 0xa8 /* MC Error Mask Register */
71
72 /* device 21 and 22, func 0 */
73 #define I5100_MTR_0 0x154 /* Memory Technology Registers 0-3 */
74 #define I5100_DMIR 0x15c /* DIMM Interleave Range */
75 #define I5100_VALIDLOG 0x18c /* Valid Log Markers */
76 #define I5100_NRECMEMA 0x190 /* Non-Recoverable Memory Error Log Reg A */
77 #define I5100_NRECMEMB 0x194 /* Non-Recoverable Memory Error Log Reg B */
78 #define I5100_REDMEMA 0x198 /* Recoverable Memory Data Error Log Reg A */
79 #define I5100_REDMEMB 0x19c /* Recoverable Memory Data Error Log Reg B */
80 #define I5100_RECMEMA 0x1a0 /* Recoverable Memory Error Log Reg A */
81 #define I5100_RECMEMB 0x1a4 /* Recoverable Memory Error Log Reg B */
82 #define I5100_MTR_4 0x1b0 /* Memory Technology Registers 4,5 */
83
84 /* bit field accessors */
85
86 static inline u32 i5100_mc_scrben(u32 mc)
87 {
88 return mc >> 7 & 1;
89 }
90
91 static inline u32 i5100_mc_errdeten(u32 mc)
92 {
93 return mc >> 5 & 1;
94 }
95
96 static inline u32 i5100_mc_scrbdone(u32 mc)
97 {
98 return mc >> 4 & 1;
99 }
100
101 static inline u16 i5100_spddata_rdo(u16 a)
102 {
103 return a >> 15 & 1;
104 }
105
106 static inline u16 i5100_spddata_sbe(u16 a)
107 {
108 return a >> 13 & 1;
109 }
110
111 static inline u16 i5100_spddata_busy(u16 a)
112 {
113 return a >> 12 & 1;
114 }
115
116 static inline u16 i5100_spddata_data(u16 a)
117 {
118 return a & ((1 << 8) - 1);
119 }
120
121 static inline u32 i5100_spdcmd_create(u32 dti, u32 ckovrd, u32 sa, u32 ba,
122 u32 data, u32 cmd)
123 {
124 return ((dti & ((1 << 4) - 1)) << 28) |
125 ((ckovrd & 1) << 27) |
126 ((sa & ((1 << 3) - 1)) << 24) |
127 ((ba & ((1 << 8) - 1)) << 16) |
128 ((data & ((1 << 8) - 1)) << 8) |
129 (cmd & 1);
130 }
131
132 static inline u16 i5100_tolm_tolm(u16 a)
133 {
134 return a >> 12 & ((1 << 4) - 1);
135 }
136
137 static inline u16 i5100_mir_limit(u16 a)
138 {
139 return a >> 4 & ((1 << 12) - 1);
140 }
141
142 static inline u16 i5100_mir_way1(u16 a)
143 {
144 return a >> 1 & 1;
145 }
146
147 static inline u16 i5100_mir_way0(u16 a)
148 {
149 return a & 1;
150 }
151
152 static inline u32 i5100_ferr_nf_mem_chan_indx(u32 a)
153 {
154 return a >> 28 & 1;
155 }
156
157 static inline u32 i5100_ferr_nf_mem_any(u32 a)
158 {
159 return a & I5100_FERR_NF_MEM_ANY_MASK;
160 }
161
162 static inline u32 i5100_nerr_nf_mem_any(u32 a)
163 {
164 return i5100_ferr_nf_mem_any(a);
165 }
166
167 static inline u32 i5100_dmir_limit(u32 a)
168 {
169 return a >> 16 & ((1 << 11) - 1);
170 }
171
172 static inline u32 i5100_dmir_rank(u32 a, u32 i)
173 {
174 return a >> (4 * i) & ((1 << 2) - 1);
175 }
176
177 static inline u16 i5100_mtr_present(u16 a)
178 {
179 return a >> 10 & 1;
180 }
181
182 static inline u16 i5100_mtr_ethrottle(u16 a)
183 {
184 return a >> 9 & 1;
185 }
186
187 static inline u16 i5100_mtr_width(u16 a)
188 {
189 return a >> 8 & 1;
190 }
191
192 static inline u16 i5100_mtr_numbank(u16 a)
193 {
194 return a >> 6 & 1;
195 }
196
197 static inline u16 i5100_mtr_numrow(u16 a)
198 {
199 return a >> 2 & ((1 << 2) - 1);
200 }
201
202 static inline u16 i5100_mtr_numcol(u16 a)
203 {
204 return a & ((1 << 2) - 1);
205 }
206
207
208 static inline u32 i5100_validlog_redmemvalid(u32 a)
209 {
210 return a >> 2 & 1;
211 }
212
213 static inline u32 i5100_validlog_recmemvalid(u32 a)
214 {
215 return a >> 1 & 1;
216 }
217
218 static inline u32 i5100_validlog_nrecmemvalid(u32 a)
219 {
220 return a & 1;
221 }
222
223 static inline u32 i5100_nrecmema_merr(u32 a)
224 {
225 return a >> 15 & ((1 << 5) - 1);
226 }
227
228 static inline u32 i5100_nrecmema_bank(u32 a)
229 {
230 return a >> 12 & ((1 << 3) - 1);
231 }
232
233 static inline u32 i5100_nrecmema_rank(u32 a)
234 {
235 return a >> 8 & ((1 << 3) - 1);
236 }
237
238 static inline u32 i5100_nrecmema_dm_buf_id(u32 a)
239 {
240 return a & ((1 << 8) - 1);
241 }
242
243 static inline u32 i5100_nrecmemb_cas(u32 a)
244 {
245 return a >> 16 & ((1 << 13) - 1);
246 }
247
248 static inline u32 i5100_nrecmemb_ras(u32 a)
249 {
250 return a & ((1 << 16) - 1);
251 }
252
253 static inline u32 i5100_redmemb_ecc_locator(u32 a)
254 {
255 return a & ((1 << 18) - 1);
256 }
257
258 static inline u32 i5100_recmema_merr(u32 a)
259 {
260 return i5100_nrecmema_merr(a);
261 }
262
263 static inline u32 i5100_recmema_bank(u32 a)
264 {
265 return i5100_nrecmema_bank(a);
266 }
267
268 static inline u32 i5100_recmema_rank(u32 a)
269 {
270 return i5100_nrecmema_rank(a);
271 }
272
273 static inline u32 i5100_recmema_dm_buf_id(u32 a)
274 {
275 return i5100_nrecmema_dm_buf_id(a);
276 }
277
278 static inline u32 i5100_recmemb_cas(u32 a)
279 {
280 return i5100_nrecmemb_cas(a);
281 }
282
283 static inline u32 i5100_recmemb_ras(u32 a)
284 {
285 return i5100_nrecmemb_ras(a);
286 }
287
288 /* some generic limits */
289 #define I5100_MAX_RANKS_PER_CHAN 6
290 #define I5100_CHANNELS 2
291 #define I5100_MAX_RANKS_PER_DIMM 4
292 #define I5100_DIMM_ADDR_LINES (6 - 3) /* 64 bits / 8 bits per byte */
293 #define I5100_MAX_DIMM_SLOTS_PER_CHAN 4
294 #define I5100_MAX_RANK_INTERLEAVE 4
295 #define I5100_MAX_DMIRS 5
296 #define I5100_SCRUB_REFRESH_RATE (5 * 60 * HZ)
297
298 struct i5100_priv {
299 /* ranks on each dimm -- 0 maps to not present -- obtained via SPD */
300 int dimm_numrank[I5100_CHANNELS][I5100_MAX_DIMM_SLOTS_PER_CHAN];
301
302 /*
303 * mainboard chip select map -- maps i5100 chip selects to
304 * DIMM slot chip selects. In the case of only 4 ranks per
305 * channel, the mapping is fairly obvious but not unique.
306 * we map -1 -> NC and assume both channels use the same
307 * map...
308 *
309 */
310 int dimm_csmap[I5100_MAX_DIMM_SLOTS_PER_CHAN][I5100_MAX_RANKS_PER_DIMM];
311
312 /* memory interleave range */
313 struct {
314 u64 limit;
315 unsigned way[2];
316 } mir[I5100_CHANNELS];
317
318 /* adjusted memory interleave range register */
319 unsigned amir[I5100_CHANNELS];
320
321 /* dimm interleave range */
322 struct {
323 unsigned rank[I5100_MAX_RANK_INTERLEAVE];
324 u64 limit;
325 } dmir[I5100_CHANNELS][I5100_MAX_DMIRS];
326
327 /* memory technology registers... */
328 struct {
329 unsigned present; /* 0 or 1 */
330 unsigned ethrottle; /* 0 or 1 */
331 unsigned width; /* 4 or 8 bits */
332 unsigned numbank; /* 2 or 3 lines */
333 unsigned numrow; /* 13 .. 16 lines */
334 unsigned numcol; /* 11 .. 12 lines */
335 } mtr[I5100_CHANNELS][I5100_MAX_RANKS_PER_CHAN];
336
337 u64 tolm; /* top of low memory in bytes */
338 unsigned ranksperchan; /* number of ranks per channel */
339
340 struct pci_dev *mc; /* device 16 func 1 */
341 struct pci_dev *ch0mm; /* device 21 func 0 */
342 struct pci_dev *ch1mm; /* device 22 func 0 */
343
344 struct delayed_work i5100_scrubbing;
345 int scrub_enable;
346 };
347
348 /* map a rank/chan to a slot number on the mainboard */
349 static int i5100_rank_to_slot(const struct mem_ctl_info *mci,
350 int chan, int rank)
351 {
352 const struct i5100_priv *priv = mci->pvt_info;
353 int i;
354
355 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
356 int j;
357 const int numrank = priv->dimm_numrank[chan][i];
358
359 for (j = 0; j < numrank; j++)
360 if (priv->dimm_csmap[i][j] == rank)
361 return i * 2 + chan;
362 }
363
364 return -1;
365 }
366
367 static const char *i5100_err_msg(unsigned err)
368 {
369 static const char *merrs[] = {
370 "unknown", /* 0 */
371 "uncorrectable data ECC on replay", /* 1 */
372 "unknown", /* 2 */
373 "unknown", /* 3 */
374 "aliased uncorrectable demand data ECC", /* 4 */
375 "aliased uncorrectable spare-copy data ECC", /* 5 */
376 "aliased uncorrectable patrol data ECC", /* 6 */
377 "unknown", /* 7 */
378 "unknown", /* 8 */
379 "unknown", /* 9 */
380 "non-aliased uncorrectable demand data ECC", /* 10 */
381 "non-aliased uncorrectable spare-copy data ECC", /* 11 */
382 "non-aliased uncorrectable patrol data ECC", /* 12 */
383 "unknown", /* 13 */
384 "correctable demand data ECC", /* 14 */
385 "correctable spare-copy data ECC", /* 15 */
386 "correctable patrol data ECC", /* 16 */
387 "unknown", /* 17 */
388 "SPD protocol error", /* 18 */
389 "unknown", /* 19 */
390 "spare copy initiated", /* 20 */
391 "spare copy completed", /* 21 */
392 };
393 unsigned i;
394
395 for (i = 0; i < ARRAY_SIZE(merrs); i++)
396 if (1 << i & err)
397 return merrs[i];
398
399 return "none";
400 }
401
402 /* convert csrow index into a rank (per channel -- 0..5) */
403 static int i5100_csrow_to_rank(const struct mem_ctl_info *mci, int csrow)
404 {
405 const struct i5100_priv *priv = mci->pvt_info;
406
407 return csrow % priv->ranksperchan;
408 }
409
410 /* convert csrow index into a channel (0..1) */
411 static int i5100_csrow_to_chan(const struct mem_ctl_info *mci, int csrow)
412 {
413 const struct i5100_priv *priv = mci->pvt_info;
414
415 return csrow / priv->ranksperchan;
416 }
417
418 static void i5100_handle_ce(struct mem_ctl_info *mci,
419 int chan,
420 unsigned bank,
421 unsigned rank,
422 unsigned long syndrome,
423 unsigned cas,
424 unsigned ras,
425 const char *msg)
426 {
427 char detail[80];
428
429 /* Form out message */
430 snprintf(detail, sizeof(detail),
431 "bank %u, cas %u, ras %u\n",
432 bank, cas, ras);
433
434 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
435 0, 0, syndrome,
436 chan, rank, -1,
437 msg, detail, NULL);
438 }
439
440 static void i5100_handle_ue(struct mem_ctl_info *mci,
441 int chan,
442 unsigned bank,
443 unsigned rank,
444 unsigned long syndrome,
445 unsigned cas,
446 unsigned ras,
447 const char *msg)
448 {
449 char detail[80];
450
451 /* Form out message */
452 snprintf(detail, sizeof(detail),
453 "bank %u, cas %u, ras %u\n",
454 bank, cas, ras);
455
456 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
457 0, 0, syndrome,
458 chan, rank, -1,
459 msg, detail, NULL);
460 }
461
462 static void i5100_read_log(struct mem_ctl_info *mci, int chan,
463 u32 ferr, u32 nerr)
464 {
465 struct i5100_priv *priv = mci->pvt_info;
466 struct pci_dev *pdev = (chan) ? priv->ch1mm : priv->ch0mm;
467 u32 dw;
468 u32 dw2;
469 unsigned syndrome = 0;
470 unsigned ecc_loc = 0;
471 unsigned merr;
472 unsigned bank;
473 unsigned rank;
474 unsigned cas;
475 unsigned ras;
476
477 pci_read_config_dword(pdev, I5100_VALIDLOG, &dw);
478
479 if (i5100_validlog_redmemvalid(dw)) {
480 pci_read_config_dword(pdev, I5100_REDMEMA, &dw2);
481 syndrome = dw2;
482 pci_read_config_dword(pdev, I5100_REDMEMB, &dw2);
483 ecc_loc = i5100_redmemb_ecc_locator(dw2);
484 }
485
486 if (i5100_validlog_recmemvalid(dw)) {
487 const char *msg;
488
489 pci_read_config_dword(pdev, I5100_RECMEMA, &dw2);
490 merr = i5100_recmema_merr(dw2);
491 bank = i5100_recmema_bank(dw2);
492 rank = i5100_recmema_rank(dw2);
493
494 pci_read_config_dword(pdev, I5100_RECMEMB, &dw2);
495 cas = i5100_recmemb_cas(dw2);
496 ras = i5100_recmemb_ras(dw2);
497
498 /* FIXME: not really sure if this is what merr is...
499 */
500 if (!merr)
501 msg = i5100_err_msg(ferr);
502 else
503 msg = i5100_err_msg(nerr);
504
505 i5100_handle_ce(mci, chan, bank, rank, syndrome, cas, ras, msg);
506 }
507
508 if (i5100_validlog_nrecmemvalid(dw)) {
509 const char *msg;
510
511 pci_read_config_dword(pdev, I5100_NRECMEMA, &dw2);
512 merr = i5100_nrecmema_merr(dw2);
513 bank = i5100_nrecmema_bank(dw2);
514 rank = i5100_nrecmema_rank(dw2);
515
516 pci_read_config_dword(pdev, I5100_NRECMEMB, &dw2);
517 cas = i5100_nrecmemb_cas(dw2);
518 ras = i5100_nrecmemb_ras(dw2);
519
520 /* FIXME: not really sure if this is what merr is...
521 */
522 if (!merr)
523 msg = i5100_err_msg(ferr);
524 else
525 msg = i5100_err_msg(nerr);
526
527 i5100_handle_ue(mci, chan, bank, rank, syndrome, cas, ras, msg);
528 }
529
530 pci_write_config_dword(pdev, I5100_VALIDLOG, dw);
531 }
532
533 static void i5100_check_error(struct mem_ctl_info *mci)
534 {
535 struct i5100_priv *priv = mci->pvt_info;
536 u32 dw, dw2;
537
538 pci_read_config_dword(priv->mc, I5100_FERR_NF_MEM, &dw);
539 if (i5100_ferr_nf_mem_any(dw)) {
540
541 pci_read_config_dword(priv->mc, I5100_NERR_NF_MEM, &dw2);
542
543 i5100_read_log(mci, i5100_ferr_nf_mem_chan_indx(dw),
544 i5100_ferr_nf_mem_any(dw),
545 i5100_nerr_nf_mem_any(dw2));
546
547 pci_write_config_dword(priv->mc, I5100_NERR_NF_MEM, dw2);
548 }
549 pci_write_config_dword(priv->mc, I5100_FERR_NF_MEM, dw);
550 }
551
552 /* The i5100 chipset will scrub the entire memory once, then
553 * set a done bit. Continuous scrubbing is achieved by enqueing
554 * delayed work to a workqueue, checking every few minutes if
555 * the scrubbing has completed and if so reinitiating it.
556 */
557
558 static void i5100_refresh_scrubbing(struct work_struct *work)
559 {
560 struct delayed_work *i5100_scrubbing = container_of(work,
561 struct delayed_work,
562 work);
563 struct i5100_priv *priv = container_of(i5100_scrubbing,
564 struct i5100_priv,
565 i5100_scrubbing);
566 u32 dw;
567
568 pci_read_config_dword(priv->mc, I5100_MC, &dw);
569
570 if (priv->scrub_enable) {
571
572 pci_read_config_dword(priv->mc, I5100_MC, &dw);
573
574 if (i5100_mc_scrbdone(dw)) {
575 dw |= I5100_MC_SCRBEN_MASK;
576 pci_write_config_dword(priv->mc, I5100_MC, dw);
577 pci_read_config_dword(priv->mc, I5100_MC, &dw);
578 }
579
580 schedule_delayed_work(&(priv->i5100_scrubbing),
581 I5100_SCRUB_REFRESH_RATE);
582 }
583 }
584 /*
585 * The bandwidth is based on experimentation, feel free to refine it.
586 */
587 static int i5100_set_scrub_rate(struct mem_ctl_info *mci, u32 bandwidth)
588 {
589 struct i5100_priv *priv = mci->pvt_info;
590 u32 dw;
591
592 pci_read_config_dword(priv->mc, I5100_MC, &dw);
593 if (bandwidth) {
594 priv->scrub_enable = 1;
595 dw |= I5100_MC_SCRBEN_MASK;
596 schedule_delayed_work(&(priv->i5100_scrubbing),
597 I5100_SCRUB_REFRESH_RATE);
598 } else {
599 priv->scrub_enable = 0;
600 dw &= ~I5100_MC_SCRBEN_MASK;
601 cancel_delayed_work(&(priv->i5100_scrubbing));
602 }
603 pci_write_config_dword(priv->mc, I5100_MC, dw);
604
605 pci_read_config_dword(priv->mc, I5100_MC, &dw);
606
607 bandwidth = 5900000 * i5100_mc_scrben(dw);
608
609 return bandwidth;
610 }
611
612 static int i5100_get_scrub_rate(struct mem_ctl_info *mci)
613 {
614 struct i5100_priv *priv = mci->pvt_info;
615 u32 dw;
616
617 pci_read_config_dword(priv->mc, I5100_MC, &dw);
618
619 return 5900000 * i5100_mc_scrben(dw);
620 }
621
622 static struct pci_dev *pci_get_device_func(unsigned vendor,
623 unsigned device,
624 unsigned func)
625 {
626 struct pci_dev *ret = NULL;
627
628 while (1) {
629 ret = pci_get_device(vendor, device, ret);
630
631 if (!ret)
632 break;
633
634 if (PCI_FUNC(ret->devfn) == func)
635 break;
636 }
637
638 return ret;
639 }
640
641 static unsigned long __devinit i5100_npages(struct mem_ctl_info *mci,
642 int csrow)
643 {
644 struct i5100_priv *priv = mci->pvt_info;
645 const unsigned chan_rank = i5100_csrow_to_rank(mci, csrow);
646 const unsigned chan = i5100_csrow_to_chan(mci, csrow);
647 unsigned addr_lines;
648
649 /* dimm present? */
650 if (!priv->mtr[chan][chan_rank].present)
651 return 0ULL;
652
653 addr_lines =
654 I5100_DIMM_ADDR_LINES +
655 priv->mtr[chan][chan_rank].numcol +
656 priv->mtr[chan][chan_rank].numrow +
657 priv->mtr[chan][chan_rank].numbank;
658
659 return (unsigned long)
660 ((unsigned long long) (1ULL << addr_lines) / PAGE_SIZE);
661 }
662
663 static void __devinit i5100_init_mtr(struct mem_ctl_info *mci)
664 {
665 struct i5100_priv *priv = mci->pvt_info;
666 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
667 int i;
668
669 for (i = 0; i < I5100_CHANNELS; i++) {
670 int j;
671 struct pci_dev *pdev = mms[i];
672
673 for (j = 0; j < I5100_MAX_RANKS_PER_CHAN; j++) {
674 const unsigned addr =
675 (j < 4) ? I5100_MTR_0 + j * 2 :
676 I5100_MTR_4 + (j - 4) * 2;
677 u16 w;
678
679 pci_read_config_word(pdev, addr, &w);
680
681 priv->mtr[i][j].present = i5100_mtr_present(w);
682 priv->mtr[i][j].ethrottle = i5100_mtr_ethrottle(w);
683 priv->mtr[i][j].width = 4 + 4 * i5100_mtr_width(w);
684 priv->mtr[i][j].numbank = 2 + i5100_mtr_numbank(w);
685 priv->mtr[i][j].numrow = 13 + i5100_mtr_numrow(w);
686 priv->mtr[i][j].numcol = 10 + i5100_mtr_numcol(w);
687 }
688 }
689 }
690
691 /*
692 * FIXME: make this into a real i2c adapter (so that dimm-decode
693 * will work)?
694 */
695 static int i5100_read_spd_byte(const struct mem_ctl_info *mci,
696 u8 ch, u8 slot, u8 addr, u8 *byte)
697 {
698 struct i5100_priv *priv = mci->pvt_info;
699 u16 w;
700 unsigned long et;
701
702 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
703 if (i5100_spddata_busy(w))
704 return -1;
705
706 pci_write_config_dword(priv->mc, I5100_SPDCMD,
707 i5100_spdcmd_create(0xa, 1, ch * 4 + slot, addr,
708 0, 0));
709
710 /* wait up to 100ms */
711 et = jiffies + HZ / 10;
712 udelay(100);
713 while (1) {
714 pci_read_config_word(priv->mc, I5100_SPDDATA, &w);
715 if (!i5100_spddata_busy(w))
716 break;
717 udelay(100);
718 }
719
720 if (!i5100_spddata_rdo(w) || i5100_spddata_sbe(w))
721 return -1;
722
723 *byte = i5100_spddata_data(w);
724
725 return 0;
726 }
727
728 /*
729 * fill dimm chip select map
730 *
731 * FIXME:
732 * o not the only way to may chip selects to dimm slots
733 * o investigate if there is some way to obtain this map from the bios
734 */
735 static void __devinit i5100_init_dimm_csmap(struct mem_ctl_info *mci)
736 {
737 struct i5100_priv *priv = mci->pvt_info;
738 int i;
739
740 for (i = 0; i < I5100_MAX_DIMM_SLOTS_PER_CHAN; i++) {
741 int j;
742
743 for (j = 0; j < I5100_MAX_RANKS_PER_DIMM; j++)
744 priv->dimm_csmap[i][j] = -1; /* default NC */
745 }
746
747 /* only 2 chip selects per slot... */
748 if (priv->ranksperchan == 4) {
749 priv->dimm_csmap[0][0] = 0;
750 priv->dimm_csmap[0][1] = 3;
751 priv->dimm_csmap[1][0] = 1;
752 priv->dimm_csmap[1][1] = 2;
753 priv->dimm_csmap[2][0] = 2;
754 priv->dimm_csmap[3][0] = 3;
755 } else {
756 priv->dimm_csmap[0][0] = 0;
757 priv->dimm_csmap[0][1] = 1;
758 priv->dimm_csmap[1][0] = 2;
759 priv->dimm_csmap[1][1] = 3;
760 priv->dimm_csmap[2][0] = 4;
761 priv->dimm_csmap[2][1] = 5;
762 }
763 }
764
765 static void __devinit i5100_init_dimm_layout(struct pci_dev *pdev,
766 struct mem_ctl_info *mci)
767 {
768 struct i5100_priv *priv = mci->pvt_info;
769 int i;
770
771 for (i = 0; i < I5100_CHANNELS; i++) {
772 int j;
773
774 for (j = 0; j < I5100_MAX_DIMM_SLOTS_PER_CHAN; j++) {
775 u8 rank;
776
777 if (i5100_read_spd_byte(mci, i, j, 5, &rank) < 0)
778 priv->dimm_numrank[i][j] = 0;
779 else
780 priv->dimm_numrank[i][j] = (rank & 3) + 1;
781 }
782 }
783
784 i5100_init_dimm_csmap(mci);
785 }
786
787 static void __devinit i5100_init_interleaving(struct pci_dev *pdev,
788 struct mem_ctl_info *mci)
789 {
790 u16 w;
791 u32 dw;
792 struct i5100_priv *priv = mci->pvt_info;
793 struct pci_dev *mms[2] = { priv->ch0mm, priv->ch1mm };
794 int i;
795
796 pci_read_config_word(pdev, I5100_TOLM, &w);
797 priv->tolm = (u64) i5100_tolm_tolm(w) * 256 * 1024 * 1024;
798
799 pci_read_config_word(pdev, I5100_MIR0, &w);
800 priv->mir[0].limit = (u64) i5100_mir_limit(w) << 28;
801 priv->mir[0].way[1] = i5100_mir_way1(w);
802 priv->mir[0].way[0] = i5100_mir_way0(w);
803
804 pci_read_config_word(pdev, I5100_MIR1, &w);
805 priv->mir[1].limit = (u64) i5100_mir_limit(w) << 28;
806 priv->mir[1].way[1] = i5100_mir_way1(w);
807 priv->mir[1].way[0] = i5100_mir_way0(w);
808
809 pci_read_config_word(pdev, I5100_AMIR_0, &w);
810 priv->amir[0] = w;
811 pci_read_config_word(pdev, I5100_AMIR_1, &w);
812 priv->amir[1] = w;
813
814 for (i = 0; i < I5100_CHANNELS; i++) {
815 int j;
816
817 for (j = 0; j < 5; j++) {
818 int k;
819
820 pci_read_config_dword(mms[i], I5100_DMIR + j * 4, &dw);
821
822 priv->dmir[i][j].limit =
823 (u64) i5100_dmir_limit(dw) << 28;
824 for (k = 0; k < I5100_MAX_RANKS_PER_DIMM; k++)
825 priv->dmir[i][j].rank[k] =
826 i5100_dmir_rank(dw, k);
827 }
828 }
829
830 i5100_init_mtr(mci);
831 }
832
833 static void __devinit i5100_init_csrows(struct mem_ctl_info *mci)
834 {
835 int i;
836 struct i5100_priv *priv = mci->pvt_info;
837
838 for (i = 0; i < mci->tot_dimms; i++) {
839 struct dimm_info *dimm;
840 const unsigned long npages = i5100_npages(mci, i);
841 const unsigned chan = i5100_csrow_to_chan(mci, i);
842 const unsigned rank = i5100_csrow_to_rank(mci, i);
843
844 if (!npages)
845 continue;
846
847 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers,
848 chan, rank, 0);
849
850 dimm->nr_pages = npages;
851 if (npages) {
852 dimm->grain = 32;
853 dimm->dtype = (priv->mtr[chan][rank].width == 4) ?
854 DEV_X4 : DEV_X8;
855 dimm->mtype = MEM_RDDR2;
856 dimm->edac_mode = EDAC_SECDED;
857 snprintf(dimm->label, sizeof(dimm->label),
858 "DIMM%u",
859 i5100_rank_to_slot(mci, chan, rank));
860 }
861
862 debugf2("dimm channel %d, rank %d, size %ld\n",
863 chan, rank, (long)PAGES_TO_MiB(npages));
864 }
865 }
866
867 static int __devinit i5100_init_one(struct pci_dev *pdev,
868 const struct pci_device_id *id)
869 {
870 int rc;
871 struct mem_ctl_info *mci;
872 struct edac_mc_layer layers[2];
873 struct i5100_priv *priv;
874 struct pci_dev *ch0mm, *ch1mm;
875 int ret = 0;
876 u32 dw;
877 int ranksperch;
878
879 if (PCI_FUNC(pdev->devfn) != 1)
880 return -ENODEV;
881
882 rc = pci_enable_device(pdev);
883 if (rc < 0) {
884 ret = rc;
885 goto bail;
886 }
887
888 /* ECC enabled? */
889 pci_read_config_dword(pdev, I5100_MC, &dw);
890 if (!i5100_mc_errdeten(dw)) {
891 printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
892 ret = -ENODEV;
893 goto bail_pdev;
894 }
895
896 /* figure out how many ranks, from strapped state of 48GB_Mode input */
897 pci_read_config_dword(pdev, I5100_MS, &dw);
898 ranksperch = !!(dw & (1 << 8)) * 2 + 4;
899
900 /* enable error reporting... */
901 pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
902 dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
903 pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
904
905 /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
906 ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
907 PCI_DEVICE_ID_INTEL_5100_21, 0);
908 if (!ch0mm) {
909 ret = -ENODEV;
910 goto bail_pdev;
911 }
912
913 rc = pci_enable_device(ch0mm);
914 if (rc < 0) {
915 ret = rc;
916 goto bail_ch0;
917 }
918
919 /* device 22, func 0, Channel 1 Memory Map, Error Flag/Mask, etc... */
920 ch1mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
921 PCI_DEVICE_ID_INTEL_5100_22, 0);
922 if (!ch1mm) {
923 ret = -ENODEV;
924 goto bail_disable_ch0;
925 }
926
927 rc = pci_enable_device(ch1mm);
928 if (rc < 0) {
929 ret = rc;
930 goto bail_ch1;
931 }
932
933 layers[0].type = EDAC_MC_LAYER_CHANNEL;
934 layers[0].size = 2;
935 layers[0].is_virt_csrow = false;
936 layers[1].type = EDAC_MC_LAYER_SLOT;
937 layers[1].size = ranksperch;
938 layers[1].is_virt_csrow = true;
939 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
940 sizeof(*priv));
941 if (!mci) {
942 ret = -ENOMEM;
943 goto bail_disable_ch1;
944 }
945
946 mci->dev = &pdev->dev;
947
948 priv = mci->pvt_info;
949 priv->ranksperchan = ranksperch;
950 priv->mc = pdev;
951 priv->ch0mm = ch0mm;
952 priv->ch1mm = ch1mm;
953
954 INIT_DELAYED_WORK(&(priv->i5100_scrubbing), i5100_refresh_scrubbing);
955
956 /* If scrubbing was already enabled by the bios, start maintaining it */
957 pci_read_config_dword(pdev, I5100_MC, &dw);
958 if (i5100_mc_scrben(dw)) {
959 priv->scrub_enable = 1;
960 schedule_delayed_work(&(priv->i5100_scrubbing),
961 I5100_SCRUB_REFRESH_RATE);
962 }
963
964 i5100_init_dimm_layout(pdev, mci);
965 i5100_init_interleaving(pdev, mci);
966
967 mci->mtype_cap = MEM_FLAG_FB_DDR2;
968 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
969 mci->edac_cap = EDAC_FLAG_SECDED;
970 mci->mod_name = "i5100_edac.c";
971 mci->mod_ver = "not versioned";
972 mci->ctl_name = "i5100";
973 mci->dev_name = pci_name(pdev);
974 mci->ctl_page_to_phys = NULL;
975
976 mci->edac_check = i5100_check_error;
977 mci->set_sdram_scrub_rate = i5100_set_scrub_rate;
978 mci->get_sdram_scrub_rate = i5100_get_scrub_rate;
979
980 i5100_init_csrows(mci);
981
982 /* this strange construction seems to be in every driver, dunno why */
983 switch (edac_op_state) {
984 case EDAC_OPSTATE_POLL:
985 case EDAC_OPSTATE_NMI:
986 break;
987 default:
988 edac_op_state = EDAC_OPSTATE_POLL;
989 break;
990 }
991
992 if (edac_mc_add_mc(mci)) {
993 ret = -ENODEV;
994 goto bail_scrub;
995 }
996
997 return ret;
998
999 bail_scrub:
1000 priv->scrub_enable = 0;
1001 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1002 edac_mc_free(mci);
1003
1004 bail_disable_ch1:
1005 pci_disable_device(ch1mm);
1006
1007 bail_ch1:
1008 pci_dev_put(ch1mm);
1009
1010 bail_disable_ch0:
1011 pci_disable_device(ch0mm);
1012
1013 bail_ch0:
1014 pci_dev_put(ch0mm);
1015
1016 bail_pdev:
1017 pci_disable_device(pdev);
1018
1019 bail:
1020 return ret;
1021 }
1022
1023 static void __devexit i5100_remove_one(struct pci_dev *pdev)
1024 {
1025 struct mem_ctl_info *mci;
1026 struct i5100_priv *priv;
1027
1028 mci = edac_mc_del_mc(&pdev->dev);
1029
1030 if (!mci)
1031 return;
1032
1033 priv = mci->pvt_info;
1034
1035 priv->scrub_enable = 0;
1036 cancel_delayed_work_sync(&(priv->i5100_scrubbing));
1037
1038 pci_disable_device(pdev);
1039 pci_disable_device(priv->ch0mm);
1040 pci_disable_device(priv->ch1mm);
1041 pci_dev_put(priv->ch0mm);
1042 pci_dev_put(priv->ch1mm);
1043
1044 edac_mc_free(mci);
1045 }
1046
1047 static DEFINE_PCI_DEVICE_TABLE(i5100_pci_tbl) = {
1048 /* Device 16, Function 0, Channel 0 Memory Map, Error Flag/Mask, ... */
1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5100_16) },
1050 { 0, }
1051 };
1052 MODULE_DEVICE_TABLE(pci, i5100_pci_tbl);
1053
1054 static struct pci_driver i5100_driver = {
1055 .name = KBUILD_BASENAME,
1056 .probe = i5100_init_one,
1057 .remove = __devexit_p(i5100_remove_one),
1058 .id_table = i5100_pci_tbl,
1059 };
1060
1061 static int __init i5100_init(void)
1062 {
1063 int pci_rc;
1064
1065 pci_rc = pci_register_driver(&i5100_driver);
1066
1067 return (pci_rc < 0) ? pci_rc : 0;
1068 }
1069
1070 static void __exit i5100_exit(void)
1071 {
1072 pci_unregister_driver(&i5100_driver);
1073 }
1074
1075 module_init(i5100_init);
1076 module_exit(i5100_exit);
1077
1078 MODULE_LICENSE("GPL");
1079 MODULE_AUTHOR
1080 ("Arthur Jones <ajones@riverbed.com>");
1081 MODULE_DESCRIPTION("MC Driver for Intel I5100 memory controllers");
Linux 2.6 libata-dev (mirror)