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manual update from upstream:
[linux-2.6/libata-dev.git] / drivers / scsi / sata_mv.c
blob46dbdee79f77af8d51ecbe334323bea22c2f641c
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 *
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 */
22
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/blkdev.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/device.h>
33 #include "scsi.h"
34 #include <scsi/scsi_host.h>
35 #include <linux/libata.h>
36 #include <asm/io.h>
37
38 #define DRV_NAME "sata_mv"
39 #define DRV_VERSION "0.25"
40
41 enum {
42 /* BAR's are enumerated in terms of pci_resource_start() terms */
43 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
44 MV_IO_BAR = 2, /* offset 0x18: IO space */
45 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46
47 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
48 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
49
50 MV_PCI_REG_BASE = 0,
51 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
52 MV_SATAHC0_REG_BASE = 0x20000,
53
54 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
55 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
56 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
57 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
58
59 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
60
61 MV_MAX_Q_DEPTH = 32,
62 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
63
64 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
65 * CRPB needs alignment on a 256B boundary. Size == 256B
66 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
67 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
68 */
69 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
70 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
71 MV_MAX_SG_CT = 176,
72 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
73 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
74
75 /* Our DMA boundary is determined by an ePRD being unable to handle
76 * anything larger than 64KB
77 */
78 MV_DMA_BOUNDARY = 0xffffU,
79
80 MV_PORTS_PER_HC = 4,
81 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
82 MV_PORT_HC_SHIFT = 2,
83 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
84 MV_PORT_MASK = 3,
85
86 /* Host Flags */
87 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
88 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
89 MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */
90 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
92 MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE |
93 MV_FLAG_GLBL_SFT_RST),
94
95 chip_504x = 0,
96 chip_508x = 1,
97 chip_604x = 2,
98 chip_608x = 3,
99
100 CRQB_FLAG_READ = (1 << 0),
101 CRQB_TAG_SHIFT = 1,
102 CRQB_CMD_ADDR_SHIFT = 8,
103 CRQB_CMD_CS = (0x2 << 11),
104 CRQB_CMD_LAST = (1 << 15),
105
106 CRPB_FLAG_STATUS_SHIFT = 8,
107
108 EPRD_FLAG_END_OF_TBL = (1 << 31),
109
110 /* PCI interface registers */
111
112 PCI_COMMAND_OFS = 0xc00,
113
114 PCI_MAIN_CMD_STS_OFS = 0xd30,
115 STOP_PCI_MASTER = (1 << 2),
116 PCI_MASTER_EMPTY = (1 << 3),
117 GLOB_SFT_RST = (1 << 4),
118
119 PCI_IRQ_CAUSE_OFS = 0x1d58,
120 PCI_IRQ_MASK_OFS = 0x1d5c,
121 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
122
123 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
124 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
125 PORT0_ERR = (1 << 0), /* shift by port # */
126 PORT0_DONE = (1 << 1), /* shift by port # */
127 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
128 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
129 PCI_ERR = (1 << 18),
130 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
131 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
132 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
133 GPIO_INT = (1 << 22),
134 SELF_INT = (1 << 23),
135 TWSI_INT = (1 << 24),
136 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
137 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
138 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
139 HC_MAIN_RSVD),
140
141 /* SATAHC registers */
142 HC_CFG_OFS = 0,
143
144 HC_IRQ_CAUSE_OFS = 0x14,
145 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
146 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
147 DEV_IRQ = (1 << 8), /* shift by port # */
148
149 /* Shadow block registers */
150 SHD_BLK_OFS = 0x100,
151 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
152
153 /* SATA registers */
154 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
155 SATA_ACTIVE_OFS = 0x350,
156
157 /* Port registers */
158 EDMA_CFG_OFS = 0,
159 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
160 EDMA_CFG_NCQ = (1 << 5),
161 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
162 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
163 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
164
165 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
166 EDMA_ERR_IRQ_MASK_OFS = 0xc,
167 EDMA_ERR_D_PAR = (1 << 0),
168 EDMA_ERR_PRD_PAR = (1 << 1),
169 EDMA_ERR_DEV = (1 << 2),
170 EDMA_ERR_DEV_DCON = (1 << 3),
171 EDMA_ERR_DEV_CON = (1 << 4),
172 EDMA_ERR_SERR = (1 << 5),
173 EDMA_ERR_SELF_DIS = (1 << 7),
174 EDMA_ERR_BIST_ASYNC = (1 << 8),
175 EDMA_ERR_CRBQ_PAR = (1 << 9),
176 EDMA_ERR_CRPB_PAR = (1 << 10),
177 EDMA_ERR_INTRL_PAR = (1 << 11),
178 EDMA_ERR_IORDY = (1 << 12),
179 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
180 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
181 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
182 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
183 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
184 EDMA_ERR_TRANS_PROTO = (1 << 31),
185 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
186 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
187 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
188 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
189 EDMA_ERR_LNK_DATA_RX |
190 EDMA_ERR_LNK_DATA_TX |
191 EDMA_ERR_TRANS_PROTO),
192
193 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
194 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
195 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
196
197 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
198 EDMA_REQ_Q_PTR_SHIFT = 5,
199
200 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
201 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
202 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
203 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
204 EDMA_RSP_Q_PTR_SHIFT = 3,
205
206 EDMA_CMD_OFS = 0x28,
207 EDMA_EN = (1 << 0),
208 EDMA_DS = (1 << 1),
209 ATA_RST = (1 << 2),
210
211 /* Host private flags (hp_flags) */
212 MV_HP_FLAG_MSI = (1 << 0),
213
214 /* Port private flags (pp_flags) */
215 MV_PP_FLAG_EDMA_EN = (1 << 0),
216 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
217 };
218
219 /* Command ReQuest Block: 32B */
220 struct mv_crqb {
221 u32 sg_addr;
222 u32 sg_addr_hi;
223 u16 ctrl_flags;
224 u16 ata_cmd[11];
225 };
226
227 /* Command ResPonse Block: 8B */
228 struct mv_crpb {
229 u16 id;
230 u16 flags;
231 u32 tmstmp;
232 };
233
234 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
235 struct mv_sg {
236 u32 addr;
237 u32 flags_size;
238 u32 addr_hi;
239 u32 reserved;
240 };
241
242 struct mv_port_priv {
243 struct mv_crqb *crqb;
244 dma_addr_t crqb_dma;
245 struct mv_crpb *crpb;
246 dma_addr_t crpb_dma;
247 struct mv_sg *sg_tbl;
248 dma_addr_t sg_tbl_dma;
249
250 unsigned req_producer; /* cp of req_in_ptr */
251 unsigned rsp_consumer; /* cp of rsp_out_ptr */
252 u32 pp_flags;
253 };
254
255 struct mv_host_priv {
256 u32 hp_flags;
257 };
258
259 static void mv_irq_clear(struct ata_port *ap);
260 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
261 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
262 static void mv_phy_reset(struct ata_port *ap);
263 static void mv_host_stop(struct ata_host_set *host_set);
264 static int mv_port_start(struct ata_port *ap);
265 static void mv_port_stop(struct ata_port *ap);
266 static void mv_qc_prep(struct ata_queued_cmd *qc);
267 static int mv_qc_issue(struct ata_queued_cmd *qc);
268 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
269 struct pt_regs *regs);
270 static void mv_eng_timeout(struct ata_port *ap);
271 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
272
273 static Scsi_Host_Template mv_sht = {
274 .module = THIS_MODULE,
275 .name = DRV_NAME,
276 .ioctl = ata_scsi_ioctl,
277 .queuecommand = ata_scsi_queuecmd,
278 .eh_strategy_handler = ata_scsi_error,
279 .can_queue = MV_USE_Q_DEPTH,
280 .this_id = ATA_SHT_THIS_ID,
281 .sg_tablesize = MV_MAX_SG_CT,
282 .max_sectors = ATA_MAX_SECTORS,
283 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
284 .emulated = ATA_SHT_EMULATED,
285 .use_clustering = ATA_SHT_USE_CLUSTERING,
286 .proc_name = DRV_NAME,
287 .dma_boundary = MV_DMA_BOUNDARY,
288 .slave_configure = ata_scsi_slave_config,
289 .bios_param = ata_std_bios_param,
290 .ordered_flush = 1,
291 };
292
293 static const struct ata_port_operations mv_ops = {
294 .port_disable = ata_port_disable,
295
296 .tf_load = ata_tf_load,
297 .tf_read = ata_tf_read,
298 .check_status = ata_check_status,
299 .exec_command = ata_exec_command,
300 .dev_select = ata_std_dev_select,
301
302 .phy_reset = mv_phy_reset,
303
304 .qc_prep = mv_qc_prep,
305 .qc_issue = mv_qc_issue,
306
307 .eng_timeout = mv_eng_timeout,
308
309 .irq_handler = mv_interrupt,
310 .irq_clear = mv_irq_clear,
311
312 .scr_read = mv_scr_read,
313 .scr_write = mv_scr_write,
314
315 .port_start = mv_port_start,
316 .port_stop = mv_port_stop,
317 .host_stop = mv_host_stop,
318 };
319
320 static struct ata_port_info mv_port_info[] = {
321 { /* chip_504x */
322 .sht = &mv_sht,
323 .host_flags = MV_COMMON_FLAGS,
324 .pio_mask = 0x1f, /* pio0-4 */
325 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
326 .port_ops = &mv_ops,
327 },
328 { /* chip_508x */
329 .sht = &mv_sht,
330 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
331 .pio_mask = 0x1f, /* pio0-4 */
332 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
333 .port_ops = &mv_ops,
334 },
335 { /* chip_604x */
336 .sht = &mv_sht,
337 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
338 .pio_mask = 0x1f, /* pio0-4 */
339 .udma_mask = 0x7f, /* udma0-6 */
340 .port_ops = &mv_ops,
341 },
342 { /* chip_608x */
343 .sht = &mv_sht,
344 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
345 MV_FLAG_DUAL_HC),
346 .pio_mask = 0x1f, /* pio0-4 */
347 .udma_mask = 0x7f, /* udma0-6 */
348 .port_ops = &mv_ops,
349 },
350 };
351
352 static struct pci_device_id mv_pci_tbl[] = {
353 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
354 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
355 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x},
356 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
357
358 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
359 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
360 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
361 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
362 {} /* terminate list */
363 };
364
365 static struct pci_driver mv_pci_driver = {
366 .name = DRV_NAME,
367 .id_table = mv_pci_tbl,
368 .probe = mv_init_one,
369 .remove = ata_pci_remove_one,
370 };
371
372 /*
373 * Functions
374 */
375
376 static inline void writelfl(unsigned long data, void __iomem *addr)
377 {
378 writel(data, addr);
379 (void) readl(addr); /* flush to avoid PCI posted write */
380 }
381
382 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
383 {
384 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
385 }
386
387 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
388 {
389 return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) +
390 MV_SATAHC_ARBTR_REG_SZ +
391 ((port & MV_PORT_MASK) * MV_PORT_REG_SZ));
392 }
393
394 static inline void __iomem *mv_ap_base(struct ata_port *ap)
395 {
396 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
397 }
398
399 static inline int mv_get_hc_count(unsigned long hp_flags)
400 {
401 return ((hp_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
402 }
403
404 static void mv_irq_clear(struct ata_port *ap)
405 {
406 }
407
408 /**
409 * mv_start_dma - Enable eDMA engine
410 * @base: port base address
411 * @pp: port private data
412 *
413 * Verify the local cache of the eDMA state is accurate with an
414 * assert.
415 *
416 * LOCKING:
417 * Inherited from caller.
418 */
419 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
420 {
421 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
422 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
423 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
424 }
425 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
426 }
427
428 /**
429 * mv_stop_dma - Disable eDMA engine
430 * @ap: ATA channel to manipulate
431 *
432 * Verify the local cache of the eDMA state is accurate with an
433 * assert.
434 *
435 * LOCKING:
436 * Inherited from caller.
437 */
438 static void mv_stop_dma(struct ata_port *ap)
439 {
440 void __iomem *port_mmio = mv_ap_base(ap);
441 struct mv_port_priv *pp = ap->private_data;
442 u32 reg;
443 int i;
444
445 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
446 /* Disable EDMA if active. The disable bit auto clears.
447 */
448 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
449 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
450 } else {
451 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
452 }
453
454 /* now properly wait for the eDMA to stop */
455 for (i = 1000; i > 0; i--) {
456 reg = readl(port_mmio + EDMA_CMD_OFS);
457 if (!(EDMA_EN & reg)) {
458 break;
459 }
460 udelay(100);
461 }
462
463 if (EDMA_EN & reg) {
464 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
465 /* FIXME: Consider doing a reset here to recover */
466 }
467 }
468
469 #ifdef ATA_DEBUG
470 static void mv_dump_mem(void __iomem *start, unsigned bytes)
471 {
472 int b, w;
473 for (b = 0; b < bytes; ) {
474 DPRINTK("%p: ", start + b);
475 for (w = 0; b < bytes && w < 4; w++) {
476 printk("%08x ",readl(start + b));
477 b += sizeof(u32);
478 }
479 printk("\n");
480 }
481 }
482 #endif
483
484 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
485 {
486 #ifdef ATA_DEBUG
487 int b, w;
488 u32 dw;
489 for (b = 0; b < bytes; ) {
490 DPRINTK("%02x: ", b);
491 for (w = 0; b < bytes && w < 4; w++) {
492 (void) pci_read_config_dword(pdev,b,&dw);
493 printk("%08x ",dw);
494 b += sizeof(u32);
495 }
496 printk("\n");
497 }
498 #endif
499 }
500 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
501 struct pci_dev *pdev)
502 {
503 #ifdef ATA_DEBUG
504 void __iomem *hc_base = mv_hc_base(mmio_base,
505 port >> MV_PORT_HC_SHIFT);
506 void __iomem *port_base;
507 int start_port, num_ports, p, start_hc, num_hcs, hc;
508
509 if (0 > port) {
510 start_hc = start_port = 0;
511 num_ports = 8; /* shld be benign for 4 port devs */
512 num_hcs = 2;
513 } else {
514 start_hc = port >> MV_PORT_HC_SHIFT;
515 start_port = port;
516 num_ports = num_hcs = 1;
517 }
518 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
519 num_ports > 1 ? num_ports - 1 : start_port);
520
521 if (NULL != pdev) {
522 DPRINTK("PCI config space regs:\n");
523 mv_dump_pci_cfg(pdev, 0x68);
524 }
525 DPRINTK("PCI regs:\n");
526 mv_dump_mem(mmio_base+0xc00, 0x3c);
527 mv_dump_mem(mmio_base+0xd00, 0x34);
528 mv_dump_mem(mmio_base+0xf00, 0x4);
529 mv_dump_mem(mmio_base+0x1d00, 0x6c);
530 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
531 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
532 DPRINTK("HC regs (HC %i):\n", hc);
533 mv_dump_mem(hc_base, 0x1c);
534 }
535 for (p = start_port; p < start_port + num_ports; p++) {
536 port_base = mv_port_base(mmio_base, p);
537 DPRINTK("EDMA regs (port %i):\n",p);
538 mv_dump_mem(port_base, 0x54);
539 DPRINTK("SATA regs (port %i):\n",p);
540 mv_dump_mem(port_base+0x300, 0x60);
541 }
542 #endif
543 }
544
545 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
546 {
547 unsigned int ofs;
548
549 switch (sc_reg_in) {
550 case SCR_STATUS:
551 case SCR_CONTROL:
552 case SCR_ERROR:
553 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
554 break;
555 case SCR_ACTIVE:
556 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
557 break;
558 default:
559 ofs = 0xffffffffU;
560 break;
561 }
562 return ofs;
563 }
564
565 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
566 {
567 unsigned int ofs = mv_scr_offset(sc_reg_in);
568
569 if (0xffffffffU != ofs) {
570 return readl(mv_ap_base(ap) + ofs);
571 } else {
572 return (u32) ofs;
573 }
574 }
575
576 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
577 {
578 unsigned int ofs = mv_scr_offset(sc_reg_in);
579
580 if (0xffffffffU != ofs) {
581 writelfl(val, mv_ap_base(ap) + ofs);
582 }
583 }
584
585 /**
586 * mv_global_soft_reset - Perform the 6xxx global soft reset
587 * @mmio_base: base address of the HBA
588 *
589 * This routine only applies to 6xxx parts.
590 *
591 * LOCKING:
592 * Inherited from caller.
593 */
594 static int mv_global_soft_reset(void __iomem *mmio_base)
595 {
596 void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS;
597 int i, rc = 0;
598 u32 t;
599
600 /* Following procedure defined in PCI "main command and status
601 * register" table.
602 */
603 t = readl(reg);
604 writel(t | STOP_PCI_MASTER, reg);
605
606 for (i = 0; i < 1000; i++) {
607 udelay(1);
608 t = readl(reg);
609 if (PCI_MASTER_EMPTY & t) {
610 break;
611 }
612 }
613 if (!(PCI_MASTER_EMPTY & t)) {
614 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
615 rc = 1;
616 goto done;
617 }
618
619 /* set reset */
620 i = 5;
621 do {
622 writel(t | GLOB_SFT_RST, reg);
623 t = readl(reg);
624 udelay(1);
625 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
626
627 if (!(GLOB_SFT_RST & t)) {
628 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
629 rc = 1;
630 goto done;
631 }
632
633 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
634 i = 5;
635 do {
636 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
637 t = readl(reg);
638 udelay(1);
639 } while ((GLOB_SFT_RST & t) && (i-- > 0));
640
641 if (GLOB_SFT_RST & t) {
642 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
643 rc = 1;
644 }
645 done:
646 return rc;
647 }
648
649 /**
650 * mv_host_stop - Host specific cleanup/stop routine.
651 * @host_set: host data structure
652 *
653 * Disable ints, cleanup host memory, call general purpose
654 * host_stop.
655 *
656 * LOCKING:
657 * Inherited from caller.
658 */
659 static void mv_host_stop(struct ata_host_set *host_set)
660 {
661 struct mv_host_priv *hpriv = host_set->private_data;
662 struct pci_dev *pdev = to_pci_dev(host_set->dev);
663
664 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
665 pci_disable_msi(pdev);
666 } else {
667 pci_intx(pdev, 0);
668 }
669 kfree(hpriv);
670 ata_host_stop(host_set);
671 }
672
673 /**
674 * mv_port_start - Port specific init/start routine.
675 * @ap: ATA channel to manipulate
676 *
677 * Allocate and point to DMA memory, init port private memory,
678 * zero indices.
679 *
680 * LOCKING:
681 * Inherited from caller.
682 */
683 static int mv_port_start(struct ata_port *ap)
684 {
685 struct device *dev = ap->host_set->dev;
686 struct mv_port_priv *pp;
687 void __iomem *port_mmio = mv_ap_base(ap);
688 void *mem;
689 dma_addr_t mem_dma;
690
691 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
692 if (!pp) {
693 return -ENOMEM;
694 }
695 memset(pp, 0, sizeof(*pp));
696
697 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
698 GFP_KERNEL);
699 if (!mem) {
700 kfree(pp);
701 return -ENOMEM;
702 }
703 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
704
705 /* First item in chunk of DMA memory:
706 * 32-slot command request table (CRQB), 32 bytes each in size
707 */
708 pp->crqb = mem;
709 pp->crqb_dma = mem_dma;
710 mem += MV_CRQB_Q_SZ;
711 mem_dma += MV_CRQB_Q_SZ;
712
713 /* Second item:
714 * 32-slot command response table (CRPB), 8 bytes each in size
715 */
716 pp->crpb = mem;
717 pp->crpb_dma = mem_dma;
718 mem += MV_CRPB_Q_SZ;
719 mem_dma += MV_CRPB_Q_SZ;
720
721 /* Third item:
722 * Table of scatter-gather descriptors (ePRD), 16 bytes each
723 */
724 pp->sg_tbl = mem;
725 pp->sg_tbl_dma = mem_dma;
726
727 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
728 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
729
730 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
731 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
732 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
733
734 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
735 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
736
737 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
738 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
739 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
740
741 pp->req_producer = pp->rsp_consumer = 0;
742
743 /* Don't turn on EDMA here...do it before DMA commands only. Else
744 * we'll be unable to send non-data, PIO, etc due to restricted access
745 * to shadow regs.
746 */
747 ap->private_data = pp;
748 return 0;
749 }
750
751 /**
752 * mv_port_stop - Port specific cleanup/stop routine.
753 * @ap: ATA channel to manipulate
754 *
755 * Stop DMA, cleanup port memory.
756 *
757 * LOCKING:
758 * This routine uses the host_set lock to protect the DMA stop.
759 */
760 static void mv_port_stop(struct ata_port *ap)
761 {
762 struct device *dev = ap->host_set->dev;
763 struct mv_port_priv *pp = ap->private_data;
764 unsigned long flags;
765
766 spin_lock_irqsave(&ap->host_set->lock, flags);
767 mv_stop_dma(ap);
768 spin_unlock_irqrestore(&ap->host_set->lock, flags);
769
770 ap->private_data = NULL;
771 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
772 kfree(pp);
773 }
774
775 /**
776 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
777 * @qc: queued command whose SG list to source from
778 *
779 * Populate the SG list and mark the last entry.
780 *
781 * LOCKING:
782 * Inherited from caller.
783 */
784 static void mv_fill_sg(struct ata_queued_cmd *qc)
785 {
786 struct mv_port_priv *pp = qc->ap->private_data;
787 unsigned int i;
788
789 for (i = 0; i < qc->n_elem; i++) {
790 u32 sg_len;
791 dma_addr_t addr;
792
793 addr = sg_dma_address(&qc->sg[i]);
794 sg_len = sg_dma_len(&qc->sg[i]);
795
796 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
797 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
798 assert(0 == (sg_len & ~MV_DMA_BOUNDARY));
799 pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len);
800 }
801 if (0 < qc->n_elem) {
802 pp->sg_tbl[qc->n_elem - 1].flags_size |=
803 cpu_to_le32(EPRD_FLAG_END_OF_TBL);
804 }
805 }
806
807 static inline unsigned mv_inc_q_index(unsigned *index)
808 {
809 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
810 return *index;
811 }
812
813 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
814 {
815 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
816 (last ? CRQB_CMD_LAST : 0);
817 }
818
819 /**
820 * mv_qc_prep - Host specific command preparation.
821 * @qc: queued command to prepare
822 *
823 * This routine simply redirects to the general purpose routine
824 * if command is not DMA. Else, it handles prep of the CRQB
825 * (command request block), does some sanity checking, and calls
826 * the SG load routine.
827 *
828 * LOCKING:
829 * Inherited from caller.
830 */
831 static void mv_qc_prep(struct ata_queued_cmd *qc)
832 {
833 struct ata_port *ap = qc->ap;
834 struct mv_port_priv *pp = ap->private_data;
835 u16 *cw;
836 struct ata_taskfile *tf;
837 u16 flags = 0;
838
839 if (ATA_PROT_DMA != qc->tf.protocol) {
840 return;
841 }
842
843 /* the req producer index should be the same as we remember it */
844 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
845 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
846 pp->req_producer);
847
848 /* Fill in command request block
849 */
850 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
851 flags |= CRQB_FLAG_READ;
852 }
853 assert(MV_MAX_Q_DEPTH > qc->tag);
854 flags |= qc->tag << CRQB_TAG_SHIFT;
855
856 pp->crqb[pp->req_producer].sg_addr =
857 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
858 pp->crqb[pp->req_producer].sg_addr_hi =
859 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
860 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
861
862 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
863 tf = &qc->tf;
864
865 /* Sadly, the CRQB cannot accomodate all registers--there are
866 * only 11 bytes...so we must pick and choose required
867 * registers based on the command. So, we drop feature and
868 * hob_feature for [RW] DMA commands, but they are needed for
869 * NCQ. NCQ will drop hob_nsect.
870 */
871 switch (tf->command) {
872 case ATA_CMD_READ:
873 case ATA_CMD_READ_EXT:
874 case ATA_CMD_WRITE:
875 case ATA_CMD_WRITE_EXT:
876 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
877 break;
878 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
879 case ATA_CMD_FPDMA_READ:
880 case ATA_CMD_FPDMA_WRITE:
881 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
882 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
883 break;
884 #endif /* FIXME: remove this line when NCQ added */
885 default:
886 /* The only other commands EDMA supports in non-queued and
887 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
888 * of which are defined/used by Linux. If we get here, this
889 * driver needs work.
890 *
891 * FIXME: modify libata to give qc_prep a return value and
892 * return error here.
893 */
894 BUG_ON(tf->command);
895 break;
896 }
897 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
898 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
899 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
900 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
901 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
902 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
903 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
904 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
905 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
906
907 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
908 return;
909 }
910 mv_fill_sg(qc);
911 }
912
913 /**
914 * mv_qc_issue - Initiate a command to the host
915 * @qc: queued command to start
916 *
917 * This routine simply redirects to the general purpose routine
918 * if command is not DMA. Else, it sanity checks our local
919 * caches of the request producer/consumer indices then enables
920 * DMA and bumps the request producer index.
921 *
922 * LOCKING:
923 * Inherited from caller.
924 */
925 static int mv_qc_issue(struct ata_queued_cmd *qc)
926 {
927 void __iomem *port_mmio = mv_ap_base(qc->ap);
928 struct mv_port_priv *pp = qc->ap->private_data;
929 u32 in_ptr;
930
931 if (ATA_PROT_DMA != qc->tf.protocol) {
932 /* We're about to send a non-EDMA capable command to the
933 * port. Turn off EDMA so there won't be problems accessing
934 * shadow block, etc registers.
935 */
936 mv_stop_dma(qc->ap);
937 return ata_qc_issue_prot(qc);
938 }
939
940 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
941
942 /* the req producer index should be the same as we remember it */
943 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
944 pp->req_producer);
945 /* until we do queuing, the queue should be empty at this point */
946 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
947 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
948 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
949
950 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
951
952 mv_start_dma(port_mmio, pp);
953
954 /* and write the request in pointer to kick the EDMA to life */
955 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
956 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
957 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
958
959 return 0;
960 }
961
962 /**
963 * mv_get_crpb_status - get status from most recently completed cmd
964 * @ap: ATA channel to manipulate
965 *
966 * This routine is for use when the port is in DMA mode, when it
967 * will be using the CRPB (command response block) method of
968 * returning command completion information. We assert indices
969 * are good, grab status, and bump the response consumer index to
970 * prove that we're up to date.
971 *
972 * LOCKING:
973 * Inherited from caller.
974 */
975 static u8 mv_get_crpb_status(struct ata_port *ap)
976 {
977 void __iomem *port_mmio = mv_ap_base(ap);
978 struct mv_port_priv *pp = ap->private_data;
979 u32 out_ptr;
980
981 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
982
983 /* the response consumer index should be the same as we remember it */
984 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
985 pp->rsp_consumer);
986
987 /* increment our consumer index... */
988 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
989
990 /* and, until we do NCQ, there should only be 1 CRPB waiting */
991 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
992 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
993 pp->rsp_consumer);
994
995 /* write out our inc'd consumer index so EDMA knows we're caught up */
996 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
997 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
998 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
999
1000 /* Return ATA status register for completed CRPB */
1001 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1002 }
1003
1004 /**
1005 * mv_err_intr - Handle error interrupts on the port
1006 * @ap: ATA channel to manipulate
1007 *
1008 * In most cases, just clear the interrupt and move on. However,
1009 * some cases require an eDMA reset, which is done right before
1010 * the COMRESET in mv_phy_reset(). The SERR case requires a
1011 * clear of pending errors in the SATA SERROR register. Finally,
1012 * if the port disabled DMA, update our cached copy to match.
1013 *
1014 * LOCKING:
1015 * Inherited from caller.
1016 */
1017 static void mv_err_intr(struct ata_port *ap)
1018 {
1019 void __iomem *port_mmio = mv_ap_base(ap);
1020 u32 edma_err_cause, serr = 0;
1021
1022 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1023
1024 if (EDMA_ERR_SERR & edma_err_cause) {
1025 serr = scr_read(ap, SCR_ERROR);
1026 scr_write_flush(ap, SCR_ERROR, serr);
1027 }
1028 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1029 struct mv_port_priv *pp = ap->private_data;
1030 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1031 }
1032 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1033 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1034
1035 /* Clear EDMA now that SERR cleanup done */
1036 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1037
1038 /* check for fatal here and recover if needed */
1039 if (EDMA_ERR_FATAL & edma_err_cause) {
1040 mv_phy_reset(ap);
1041 }
1042 }
1043
1044 /**
1045 * mv_host_intr - Handle all interrupts on the given host controller
1046 * @host_set: host specific structure
1047 * @relevant: port error bits relevant to this host controller
1048 * @hc: which host controller we're to look at
1049 *
1050 * Read then write clear the HC interrupt status then walk each
1051 * port connected to the HC and see if it needs servicing. Port
1052 * success ints are reported in the HC interrupt status reg, the
1053 * port error ints are reported in the higher level main
1054 * interrupt status register and thus are passed in via the
1055 * 'relevant' argument.
1056 *
1057 * LOCKING:
1058 * Inherited from caller.
1059 */
1060 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1061 unsigned int hc)
1062 {
1063 void __iomem *mmio = host_set->mmio_base;
1064 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1065 struct ata_port *ap;
1066 struct ata_queued_cmd *qc;
1067 u32 hc_irq_cause;
1068 int shift, port, port0, hard_port, handled;
1069 unsigned int err_mask;
1070 u8 ata_status = 0;
1071
1072 if (hc == 0) {
1073 port0 = 0;
1074 } else {
1075 port0 = MV_PORTS_PER_HC;
1076 }
1077
1078 /* we'll need the HC success int register in most cases */
1079 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1080 if (hc_irq_cause) {
1081 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1082 }
1083
1084 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1085 hc,relevant,hc_irq_cause);
1086
1087 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1088 ap = host_set->ports[port];
1089 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1090 handled = 0; /* ensure ata_status is set if handled++ */
1091
1092 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1093 /* new CRPB on the queue; just one at a time until NCQ
1094 */
1095 ata_status = mv_get_crpb_status(ap);
1096 handled++;
1097 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1098 /* received ATA IRQ; read the status reg to clear INTRQ
1099 */
1100 ata_status = readb((void __iomem *)
1101 ap->ioaddr.status_addr);
1102 handled++;
1103 }
1104
1105 err_mask = ac_err_mask(ata_status);
1106
1107 shift = port << 1; /* (port * 2) */
1108 if (port >= MV_PORTS_PER_HC) {
1109 shift++; /* skip bit 8 in the HC Main IRQ reg */
1110 }
1111 if ((PORT0_ERR << shift) & relevant) {
1112 mv_err_intr(ap);
1113 err_mask |= AC_ERR_OTHER;
1114 handled++;
1115 }
1116
1117 if (handled && ap) {
1118 qc = ata_qc_from_tag(ap, ap->active_tag);
1119 if (NULL != qc) {
1120 VPRINTK("port %u IRQ found for qc, "
1121 "ata_status 0x%x\n", port,ata_status);
1122 /* mark qc status appropriately */
1123 ata_qc_complete(qc, err_mask);
1124 }
1125 }
1126 }
1127 VPRINTK("EXIT\n");
1128 }
1129
1130 /**
1131 * mv_interrupt -
1132 * @irq: unused
1133 * @dev_instance: private data; in this case the host structure
1134 * @regs: unused
1135 *
1136 * Read the read only register to determine if any host
1137 * controllers have pending interrupts. If so, call lower level
1138 * routine to handle. Also check for PCI errors which are only
1139 * reported here.
1140 *
1141 * LOCKING:
1142 * This routine holds the host_set lock while processing pending
1143 * interrupts.
1144 */
1145 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1146 struct pt_regs *regs)
1147 {
1148 struct ata_host_set *host_set = dev_instance;
1149 unsigned int hc, handled = 0, n_hcs;
1150 void __iomem *mmio = host_set->mmio_base;
1151 u32 irq_stat;
1152
1153 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1154
1155 /* check the cases where we either have nothing pending or have read
1156 * a bogus register value which can indicate HW removal or PCI fault
1157 */
1158 if (!irq_stat || (0xffffffffU == irq_stat)) {
1159 return IRQ_NONE;
1160 }
1161
1162 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1163 spin_lock(&host_set->lock);
1164
1165 for (hc = 0; hc < n_hcs; hc++) {
1166 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1167 if (relevant) {
1168 mv_host_intr(host_set, relevant, hc);
1169 handled++;
1170 }
1171 }
1172 if (PCI_ERR & irq_stat) {
1173 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1174 readl(mmio + PCI_IRQ_CAUSE_OFS));
1175
1176 DPRINTK("All regs @ PCI error\n");
1177 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1178
1179 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1180 handled++;
1181 }
1182 spin_unlock(&host_set->lock);
1183
1184 return IRQ_RETVAL(handled);
1185 }
1186
1187 /**
1188 * mv_phy_reset - Perform eDMA reset followed by COMRESET
1189 * @ap: ATA channel to manipulate
1190 *
1191 * Part of this is taken from __sata_phy_reset and modified to
1192 * not sleep since this routine gets called from interrupt level.
1193 *
1194 * LOCKING:
1195 * Inherited from caller. This is coded to safe to call at
1196 * interrupt level, i.e. it does not sleep.
1197 */
1198 static void mv_phy_reset(struct ata_port *ap)
1199 {
1200 void __iomem *port_mmio = mv_ap_base(ap);
1201 struct ata_taskfile tf;
1202 struct ata_device *dev = &ap->device[0];
1203 unsigned long timeout;
1204
1205 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1206
1207 mv_stop_dma(ap);
1208
1209 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1210 udelay(25); /* allow reset propagation */
1211
1212 /* Spec never mentions clearing the bit. Marvell's driver does
1213 * clear the bit, however.
1214 */
1215 writelfl(0, port_mmio + EDMA_CMD_OFS);
1216
1217 VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1218 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1219 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1220
1221 /* proceed to init communications via the scr_control reg */
1222 scr_write_flush(ap, SCR_CONTROL, 0x301);
1223 mdelay(1);
1224 scr_write_flush(ap, SCR_CONTROL, 0x300);
1225 timeout = jiffies + (HZ * 1);
1226 do {
1227 mdelay(10);
1228 if ((scr_read(ap, SCR_STATUS) & 0xf) != 1)
1229 break;
1230 } while (time_before(jiffies, timeout));
1231
1232 VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1233 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1234 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1235
1236 if (sata_dev_present(ap)) {
1237 ata_port_probe(ap);
1238 } else {
1239 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1240 ap->id, scr_read(ap, SCR_STATUS));
1241 ata_port_disable(ap);
1242 return;
1243 }
1244 ap->cbl = ATA_CBL_SATA;
1245
1246 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1247 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1248 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1249 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1250
1251 dev->class = ata_dev_classify(&tf);
1252 if (!ata_dev_present(dev)) {
1253 VPRINTK("Port disabled post-sig: No device present.\n");
1254 ata_port_disable(ap);
1255 }
1256 VPRINTK("EXIT\n");
1257 }
1258
1259 /**
1260 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1261 * @ap: ATA channel to manipulate
1262 *
1263 * Intent is to clear all pending error conditions, reset the
1264 * chip/bus, fail the command, and move on.
1265 *
1266 * LOCKING:
1267 * This routine holds the host_set lock while failing the command.
1268 */
1269 static void mv_eng_timeout(struct ata_port *ap)
1270 {
1271 struct ata_queued_cmd *qc;
1272 unsigned long flags;
1273
1274 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1275 DPRINTK("All regs @ start of eng_timeout\n");
1276 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1277 to_pci_dev(ap->host_set->dev));
1278
1279 qc = ata_qc_from_tag(ap, ap->active_tag);
1280 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1281 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1282 &qc->scsicmd->cmnd);
1283
1284 mv_err_intr(ap);
1285 mv_phy_reset(ap);
1286
1287 if (!qc) {
1288 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1289 ap->id);
1290 } else {
1291 /* hack alert! We cannot use the supplied completion
1292 * function from inside the ->eh_strategy_handler() thread.
1293 * libata is the only user of ->eh_strategy_handler() in
1294 * any kernel, so the default scsi_done() assumes it is
1295 * not being called from the SCSI EH.
1296 */
1297 spin_lock_irqsave(&ap->host_set->lock, flags);
1298 qc->scsidone = scsi_finish_command;
1299 ata_qc_complete(qc, AC_ERR_OTHER);
1300 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1301 }
1302 }
1303
1304 /**
1305 * mv_port_init - Perform some early initialization on a single port.
1306 * @port: libata data structure storing shadow register addresses
1307 * @port_mmio: base address of the port
1308 *
1309 * Initialize shadow register mmio addresses, clear outstanding
1310 * interrupts on the port, and unmask interrupts for the future
1311 * start of the port.
1312 *
1313 * LOCKING:
1314 * Inherited from caller.
1315 */
1316 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1317 {
1318 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1319 unsigned serr_ofs;
1320
1321 /* PIO related setup
1322 */
1323 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1324 port->error_addr =
1325 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1326 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1327 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1328 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1329 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1330 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1331 port->status_addr =
1332 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1333 /* special case: control/altstatus doesn't have ATA_REG_ address */
1334 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1335
1336 /* unused: */
1337 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1338
1339 /* Clear any currently outstanding port interrupt conditions */
1340 serr_ofs = mv_scr_offset(SCR_ERROR);
1341 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1342 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1343
1344 /* unmask all EDMA error interrupts */
1345 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1346
1347 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1348 readl(port_mmio + EDMA_CFG_OFS),
1349 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1350 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1351 }
1352
1353 /**
1354 * mv_host_init - Perform some early initialization of the host.
1355 * @probe_ent: early data struct representing the host
1356 *
1357 * If possible, do an early global reset of the host. Then do
1358 * our port init and clear/unmask all/relevant host interrupts.
1359 *
1360 * LOCKING:
1361 * Inherited from caller.
1362 */
1363 static int mv_host_init(struct ata_probe_ent *probe_ent)
1364 {
1365 int rc = 0, n_hc, port, hc;
1366 void __iomem *mmio = probe_ent->mmio_base;
1367 void __iomem *port_mmio;
1368
1369 if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) &&
1370 mv_global_soft_reset(probe_ent->mmio_base)) {
1371 rc = 1;
1372 goto done;
1373 }
1374
1375 n_hc = mv_get_hc_count(probe_ent->host_flags);
1376 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
1377
1378 for (port = 0; port < probe_ent->n_ports; port++) {
1379 port_mmio = mv_port_base(mmio, port);
1380 mv_port_init(&probe_ent->port[port], port_mmio);
1381 }
1382
1383 for (hc = 0; hc < n_hc; hc++) {
1384 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1385
1386 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
1387 "(before clear)=0x%08x\n", hc,
1388 readl(hc_mmio + HC_CFG_OFS),
1389 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
1390
1391 /* Clear any currently outstanding hc interrupt conditions */
1392 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
1393 }
1394
1395 /* Clear any currently outstanding host interrupt conditions */
1396 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1397
1398 /* and unmask interrupt generation for host regs */
1399 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
1400 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
1401
1402 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1403 "PCI int cause/mask=0x%08x/0x%08x\n",
1404 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
1405 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
1406 readl(mmio + PCI_IRQ_CAUSE_OFS),
1407 readl(mmio + PCI_IRQ_MASK_OFS));
1408 done:
1409 return rc;
1410 }
1411
1412 /**
1413 * mv_print_info - Dump key info to kernel log for perusal.
1414 * @probe_ent: early data struct representing the host
1415 *
1416 * FIXME: complete this.
1417 *
1418 * LOCKING:
1419 * Inherited from caller.
1420 */
1421 static void mv_print_info(struct ata_probe_ent *probe_ent)
1422 {
1423 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1424 struct mv_host_priv *hpriv = probe_ent->private_data;
1425 u8 rev_id, scc;
1426 const char *scc_s;
1427
1428 /* Use this to determine the HW stepping of the chip so we know
1429 * what errata to workaround
1430 */
1431 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1432
1433 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
1434 if (scc == 0)
1435 scc_s = "SCSI";
1436 else if (scc == 0x01)
1437 scc_s = "RAID";
1438 else
1439 scc_s = "unknown";
1440
1441 dev_printk(KERN_INFO, &pdev->dev,
1442 "%u slots %u ports %s mode IRQ via %s\n",
1443 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
1444 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
1445 }
1446
1447 /**
1448 * mv_init_one - handle a positive probe of a Marvell host
1449 * @pdev: PCI device found
1450 * @ent: PCI device ID entry for the matched host
1451 *
1452 * LOCKING:
1453 * Inherited from caller.
1454 */
1455 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1456 {
1457 static int printed_version = 0;
1458 struct ata_probe_ent *probe_ent = NULL;
1459 struct mv_host_priv *hpriv;
1460 unsigned int board_idx = (unsigned int)ent->driver_data;
1461 void __iomem *mmio_base;
1462 int pci_dev_busy = 0, rc;
1463
1464 if (!printed_version++)
1465 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
1466
1467 rc = pci_enable_device(pdev);
1468 if (rc) {
1469 return rc;
1470 }
1471
1472 rc = pci_request_regions(pdev, DRV_NAME);
1473 if (rc) {
1474 pci_dev_busy = 1;
1475 goto err_out;
1476 }
1477
1478 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1479 if (probe_ent == NULL) {
1480 rc = -ENOMEM;
1481 goto err_out_regions;
1482 }
1483
1484 memset(probe_ent, 0, sizeof(*probe_ent));
1485 probe_ent->dev = pci_dev_to_dev(pdev);
1486 INIT_LIST_HEAD(&probe_ent->node);
1487
1488 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
1489 if (mmio_base == NULL) {
1490 rc = -ENOMEM;
1491 goto err_out_free_ent;
1492 }
1493
1494 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1495 if (!hpriv) {
1496 rc = -ENOMEM;
1497 goto err_out_iounmap;
1498 }
1499 memset(hpriv, 0, sizeof(*hpriv));
1500
1501 probe_ent->sht = mv_port_info[board_idx].sht;
1502 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
1503 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
1504 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
1505 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
1506
1507 probe_ent->irq = pdev->irq;
1508 probe_ent->irq_flags = SA_SHIRQ;
1509 probe_ent->mmio_base = mmio_base;
1510 probe_ent->private_data = hpriv;
1511
1512 /* initialize adapter */
1513 rc = mv_host_init(probe_ent);
1514 if (rc) {
1515 goto err_out_hpriv;
1516 }
1517
1518 /* Enable interrupts */
1519 if (pci_enable_msi(pdev) == 0) {
1520 hpriv->hp_flags |= MV_HP_FLAG_MSI;
1521 } else {
1522 pci_intx(pdev, 1);
1523 }
1524
1525 mv_dump_pci_cfg(pdev, 0x68);
1526 mv_print_info(probe_ent);
1527
1528 if (ata_device_add(probe_ent) == 0) {
1529 rc = -ENODEV; /* No devices discovered */
1530 goto err_out_dev_add;
1531 }
1532
1533 kfree(probe_ent);
1534 return 0;
1535
1536 err_out_dev_add:
1537 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
1538 pci_disable_msi(pdev);
1539 } else {
1540 pci_intx(pdev, 0);
1541 }
1542 err_out_hpriv:
1543 kfree(hpriv);
1544 err_out_iounmap:
1545 pci_iounmap(pdev, mmio_base);
1546 err_out_free_ent:
1547 kfree(probe_ent);
1548 err_out_regions:
1549 pci_release_regions(pdev);
1550 err_out:
1551 if (!pci_dev_busy) {
1552 pci_disable_device(pdev);
1553 }
1554
1555 return rc;
1556 }
1557
1558 static int __init mv_init(void)
1559 {
1560 return pci_module_init(&mv_pci_driver);
1561 }
1562
1563 static void __exit mv_exit(void)
1564 {
1565 pci_unregister_driver(&mv_pci_driver);
1566 }
1567
1568 MODULE_AUTHOR("Brett Russ");
1569 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
1570 MODULE_LICENSE("GPL");
1571 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
1572 MODULE_VERSION(DRV_VERSION);
1573
1574 module_init(mv_init);
1575 module_exit(mv_exit);
Linux 2.6 libata-dev (mirror)