1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "3.0.12-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
62 [board_X540
] = &ixgbe_X540_info
,
65 /* ixgbe_pci_tbl - PCI Device ID Table
67 * Wildcard entries (PCI_ANY_ID) should come last
68 * Last entry must be all 0s
70 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
71 * Class, Class Mask, private data (not used) }
73 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
74 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
76 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
78 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
80 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
82 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
84 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
86 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
88 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
90 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
92 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
94 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
96 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
98 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
100 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
102 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
104 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
106 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
108 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
110 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
112 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
114 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
116 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_X540T
),
119 /* required last entry */
122 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
124 #ifdef CONFIG_IXGBE_DCA
125 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
127 static struct notifier_block dca_notifier
= {
128 .notifier_call
= ixgbe_notify_dca
,
134 #ifdef CONFIG_PCI_IOV
135 static unsigned int max_vfs
;
136 module_param(max_vfs
, uint
, 0);
137 MODULE_PARM_DESC(max_vfs
,
138 "Maximum number of virtual functions to allocate per physical function");
139 #endif /* CONFIG_PCI_IOV */
141 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
142 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
143 MODULE_LICENSE("GPL");
144 MODULE_VERSION(DRV_VERSION
);
146 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
148 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
150 struct ixgbe_hw
*hw
= &adapter
->hw
;
155 #ifdef CONFIG_PCI_IOV
156 /* disable iov and allow time for transactions to clear */
157 pci_disable_sriov(adapter
->pdev
);
160 /* turn off device IOV mode */
161 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
162 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
163 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
164 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
165 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
166 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
168 /* set default pool back to 0 */
169 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
170 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
171 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
173 /* take a breather then clean up driver data */
176 kfree(adapter
->vfinfo
);
177 adapter
->vfinfo
= NULL
;
179 adapter
->num_vfs
= 0;
180 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
183 struct ixgbe_reg_info
{
188 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
190 /* General Registers */
191 {IXGBE_CTRL
, "CTRL"},
192 {IXGBE_STATUS
, "STATUS"},
193 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
195 /* Interrupt Registers */
196 {IXGBE_EICR
, "EICR"},
199 {IXGBE_SRRCTL(0), "SRRCTL"},
200 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
201 {IXGBE_RDLEN(0), "RDLEN"},
202 {IXGBE_RDH(0), "RDH"},
203 {IXGBE_RDT(0), "RDT"},
204 {IXGBE_RXDCTL(0), "RXDCTL"},
205 {IXGBE_RDBAL(0), "RDBAL"},
206 {IXGBE_RDBAH(0), "RDBAH"},
209 {IXGBE_TDBAL(0), "TDBAL"},
210 {IXGBE_TDBAH(0), "TDBAH"},
211 {IXGBE_TDLEN(0), "TDLEN"},
212 {IXGBE_TDH(0), "TDH"},
213 {IXGBE_TDT(0), "TDT"},
214 {IXGBE_TXDCTL(0), "TXDCTL"},
216 /* List Terminator */
222 * ixgbe_regdump - register printout routine
224 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
230 switch (reginfo
->ofs
) {
231 case IXGBE_SRRCTL(0):
232 for (i
= 0; i
< 64; i
++)
233 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
235 case IXGBE_DCA_RXCTRL(0):
236 for (i
= 0; i
< 64; i
++)
237 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
240 for (i
= 0; i
< 64; i
++)
241 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
244 for (i
= 0; i
< 64; i
++)
245 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
248 for (i
= 0; i
< 64; i
++)
249 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
251 case IXGBE_RXDCTL(0):
252 for (i
= 0; i
< 64; i
++)
253 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
256 for (i
= 0; i
< 64; i
++)
257 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
260 for (i
= 0; i
< 64; i
++)
261 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
264 for (i
= 0; i
< 64; i
++)
265 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
268 for (i
= 0; i
< 64; i
++)
269 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
272 for (i
= 0; i
< 64; i
++)
273 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
276 for (i
= 0; i
< 64; i
++)
277 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
280 for (i
= 0; i
< 64; i
++)
281 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
283 case IXGBE_TXDCTL(0):
284 for (i
= 0; i
< 64; i
++)
285 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
288 pr_info("%-15s %08x\n", reginfo
->name
,
289 IXGBE_READ_REG(hw
, reginfo
->ofs
));
293 for (i
= 0; i
< 8; i
++) {
294 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
295 pr_err("%-15s", rname
);
296 for (j
= 0; j
< 8; j
++)
297 pr_cont(" %08x", regs
[i
*8+j
]);
304 * ixgbe_dump - Print registers, tx-rings and rx-rings
306 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
308 struct net_device
*netdev
= adapter
->netdev
;
309 struct ixgbe_hw
*hw
= &adapter
->hw
;
310 struct ixgbe_reg_info
*reginfo
;
312 struct ixgbe_ring
*tx_ring
;
313 struct ixgbe_tx_buffer
*tx_buffer_info
;
314 union ixgbe_adv_tx_desc
*tx_desc
;
315 struct my_u0
{ u64 a
; u64 b
; } *u0
;
316 struct ixgbe_ring
*rx_ring
;
317 union ixgbe_adv_rx_desc
*rx_desc
;
318 struct ixgbe_rx_buffer
*rx_buffer_info
;
322 if (!netif_msg_hw(adapter
))
325 /* Print netdevice Info */
327 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
328 pr_info("Device Name state "
329 "trans_start last_rx\n");
330 pr_info("%-15s %016lX %016lX %016lX\n",
337 /* Print Registers */
338 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
339 pr_info(" Register Name Value\n");
340 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
341 reginfo
->name
; reginfo
++) {
342 ixgbe_regdump(hw
, reginfo
);
345 /* Print TX Ring Summary */
346 if (!netdev
|| !netif_running(netdev
))
349 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
350 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
351 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
352 tx_ring
= adapter
->tx_ring
[n
];
354 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
355 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
356 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
357 (u64
)tx_buffer_info
->dma
,
358 tx_buffer_info
->length
,
359 tx_buffer_info
->next_to_watch
,
360 (u64
)tx_buffer_info
->time_stamp
);
364 if (!netif_msg_tx_done(adapter
))
365 goto rx_ring_summary
;
367 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
369 /* Transmit Descriptor Formats
371 * Advanced Transmit Descriptor
372 * +--------------------------------------------------------------+
373 * 0 | Buffer Address [63:0] |
374 * +--------------------------------------------------------------+
375 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
376 * +--------------------------------------------------------------+
377 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
380 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
381 tx_ring
= adapter
->tx_ring
[n
];
382 pr_info("------------------------------------\n");
383 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
384 pr_info("------------------------------------\n");
385 pr_info("T [desc] [address 63:0 ] "
386 "[PlPOIdStDDt Ln] [bi->dma ] "
387 "leng ntw timestamp bi->skb\n");
389 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
390 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
391 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
392 u0
= (struct my_u0
*)tx_desc
;
393 pr_info("T [0x%03X] %016llX %016llX %016llX"
394 " %04X %3X %016llX %p", i
,
397 (u64
)tx_buffer_info
->dma
,
398 tx_buffer_info
->length
,
399 tx_buffer_info
->next_to_watch
,
400 (u64
)tx_buffer_info
->time_stamp
,
401 tx_buffer_info
->skb
);
402 if (i
== tx_ring
->next_to_use
&&
403 i
== tx_ring
->next_to_clean
)
405 else if (i
== tx_ring
->next_to_use
)
407 else if (i
== tx_ring
->next_to_clean
)
412 if (netif_msg_pktdata(adapter
) &&
413 tx_buffer_info
->dma
!= 0)
414 print_hex_dump(KERN_INFO
, "",
415 DUMP_PREFIX_ADDRESS
, 16, 1,
416 phys_to_virt(tx_buffer_info
->dma
),
417 tx_buffer_info
->length
, true);
421 /* Print RX Rings Summary */
423 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
424 pr_info("Queue [NTU] [NTC]\n");
425 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
426 rx_ring
= adapter
->rx_ring
[n
];
427 pr_info("%5d %5X %5X\n",
428 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
432 if (!netif_msg_rx_status(adapter
))
435 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
437 /* Advanced Receive Descriptor (Read) Format
439 * +-----------------------------------------------------+
440 * 0 | Packet Buffer Address [63:1] |A0/NSE|
441 * +----------------------------------------------+------+
442 * 8 | Header Buffer Address [63:1] | DD |
443 * +-----------------------------------------------------+
446 * Advanced Receive Descriptor (Write-Back) Format
448 * 63 48 47 32 31 30 21 20 16 15 4 3 0
449 * +------------------------------------------------------+
450 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
451 * | Checksum Ident | | | | Type | Type |
452 * +------------------------------------------------------+
453 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
454 * +------------------------------------------------------+
455 * 63 48 47 32 31 20 19 0
457 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
458 rx_ring
= adapter
->rx_ring
[n
];
459 pr_info("------------------------------------\n");
460 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
461 pr_info("------------------------------------\n");
462 pr_info("R [desc] [ PktBuf A0] "
463 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
464 "<-- Adv Rx Read format\n");
465 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
466 "[vl er S cks ln] ---------------- [bi->skb] "
467 "<-- Adv Rx Write-Back format\n");
469 for (i
= 0; i
< rx_ring
->count
; i
++) {
470 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
471 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
472 u0
= (struct my_u0
*)rx_desc
;
473 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
474 if (staterr
& IXGBE_RXD_STAT_DD
) {
475 /* Descriptor Done */
476 pr_info("RWB[0x%03X] %016llX "
477 "%016llX ---------------- %p", i
,
480 rx_buffer_info
->skb
);
482 pr_info("R [0x%03X] %016llX "
483 "%016llX %016llX %p", i
,
486 (u64
)rx_buffer_info
->dma
,
487 rx_buffer_info
->skb
);
489 if (netif_msg_pktdata(adapter
)) {
490 print_hex_dump(KERN_INFO
, "",
491 DUMP_PREFIX_ADDRESS
, 16, 1,
492 phys_to_virt(rx_buffer_info
->dma
),
493 rx_ring
->rx_buf_len
, true);
495 if (rx_ring
->rx_buf_len
496 < IXGBE_RXBUFFER_2048
)
497 print_hex_dump(KERN_INFO
, "",
498 DUMP_PREFIX_ADDRESS
, 16, 1,
500 rx_buffer_info
->page_dma
+
501 rx_buffer_info
->page_offset
507 if (i
== rx_ring
->next_to_use
)
509 else if (i
== rx_ring
->next_to_clean
)
521 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
525 /* Let firmware take over control of h/w */
526 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
527 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
528 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
531 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
535 /* Let firmware know the driver has taken over */
536 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
537 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
538 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
542 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
543 * @adapter: pointer to adapter struct
544 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
545 * @queue: queue to map the corresponding interrupt to
546 * @msix_vector: the vector to map to the corresponding queue
549 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
550 u8 queue
, u8 msix_vector
)
553 struct ixgbe_hw
*hw
= &adapter
->hw
;
554 switch (hw
->mac
.type
) {
555 case ixgbe_mac_82598EB
:
556 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
559 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
560 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
561 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
562 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
563 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
565 case ixgbe_mac_82599EB
:
567 if (direction
== -1) {
569 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
570 index
= ((queue
& 1) * 8);
571 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
572 ivar
&= ~(0xFF << index
);
573 ivar
|= (msix_vector
<< index
);
574 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
577 /* tx or rx causes */
578 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
579 index
= ((16 * (queue
& 1)) + (8 * direction
));
580 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
581 ivar
&= ~(0xFF << index
);
582 ivar
|= (msix_vector
<< index
);
583 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
591 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
596 switch (adapter
->hw
.mac
.type
) {
597 case ixgbe_mac_82598EB
:
598 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
599 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
601 case ixgbe_mac_82599EB
:
603 mask
= (qmask
& 0xFFFFFFFF);
604 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
605 mask
= (qmask
>> 32);
606 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
613 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*tx_ring
,
614 struct ixgbe_tx_buffer
*tx_buffer_info
)
616 if (tx_buffer_info
->dma
) {
617 if (tx_buffer_info
->mapped_as_page
)
618 dma_unmap_page(tx_ring
->dev
,
620 tx_buffer_info
->length
,
623 dma_unmap_single(tx_ring
->dev
,
625 tx_buffer_info
->length
,
627 tx_buffer_info
->dma
= 0;
629 if (tx_buffer_info
->skb
) {
630 dev_kfree_skb_any(tx_buffer_info
->skb
);
631 tx_buffer_info
->skb
= NULL
;
633 tx_buffer_info
->time_stamp
= 0;
634 /* tx_buffer_info must be completely set up in the transmit path */
638 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
639 * @adapter: driver private struct
640 * @index: reg idx of queue to query (0-127)
642 * Helper function to determine the traffic index for a paticular
645 * Returns : a tc index for use in range 0-7, or 0-3
647 u8
ixgbe_dcb_txq_to_tc(struct ixgbe_adapter
*adapter
, u8 reg_idx
)
650 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
652 /* if DCB is not enabled the queues have no TC */
653 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
656 /* check valid range */
657 if (reg_idx
>= adapter
->hw
.mac
.max_tx_queues
)
660 switch (adapter
->hw
.mac
.type
) {
661 case ixgbe_mac_82598EB
:
665 if (dcb_i
!= 4 && dcb_i
!= 8)
668 /* if VMDq is enabled the lowest order bits determine TC */
669 if (adapter
->flags
& (IXGBE_FLAG_SRIOV_ENABLED
|
670 IXGBE_FLAG_VMDQ_ENABLED
)) {
671 tc
= reg_idx
& (dcb_i
- 1);
676 * Convert the reg_idx into the correct TC. This bitmask
677 * targets the last full 32 ring traffic class and assigns
678 * it a value of 1. From there the rest of the rings are
679 * based on shifting the mask further up to include the
680 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
681 * will only ever be 8 or 4 and that reg_idx will never
682 * be greater then 128. The code without the power of 2
683 * optimizations would be:
684 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
686 tc
= ((reg_idx
& 0X1F) + 0x20) * dcb_i
;
687 tc
>>= 9 - (reg_idx
>> 5);
693 static void ixgbe_update_xoff_received(struct ixgbe_adapter
*adapter
)
695 struct ixgbe_hw
*hw
= &adapter
->hw
;
696 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
701 if ((hw
->fc
.current_mode
== ixgbe_fc_full
) ||
702 (hw
->fc
.current_mode
== ixgbe_fc_rx_pause
)) {
703 switch (hw
->mac
.type
) {
704 case ixgbe_mac_82598EB
:
705 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
708 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
710 hwstats
->lxoffrxc
+= data
;
712 /* refill credits (no tx hang) if we received xoff */
716 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
717 clear_bit(__IXGBE_HANG_CHECK_ARMED
,
718 &adapter
->tx_ring
[i
]->state
);
720 } else if (!(adapter
->dcb_cfg
.pfc_mode_enable
))
723 /* update stats for each tc, only valid with PFC enabled */
724 for (i
= 0; i
< MAX_TX_PACKET_BUFFERS
; i
++) {
725 switch (hw
->mac
.type
) {
726 case ixgbe_mac_82598EB
:
727 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
730 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
732 hwstats
->pxoffrxc
[i
] += xoff
[i
];
735 /* disarm tx queues that have received xoff frames */
736 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
737 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
738 u32 tc
= ixgbe_dcb_txq_to_tc(adapter
, tx_ring
->reg_idx
);
741 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
745 static u64
ixgbe_get_tx_completed(struct ixgbe_ring
*ring
)
747 return ring
->tx_stats
.completed
;
750 static u64
ixgbe_get_tx_pending(struct ixgbe_ring
*ring
)
752 struct ixgbe_adapter
*adapter
= netdev_priv(ring
->netdev
);
753 struct ixgbe_hw
*hw
= &adapter
->hw
;
755 u32 head
= IXGBE_READ_REG(hw
, IXGBE_TDH(ring
->reg_idx
));
756 u32 tail
= IXGBE_READ_REG(hw
, IXGBE_TDT(ring
->reg_idx
));
759 return (head
< tail
) ?
760 tail
- head
: (tail
+ ring
->count
- head
);
765 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring
*tx_ring
)
767 u32 tx_done
= ixgbe_get_tx_completed(tx_ring
);
768 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
769 u32 tx_pending
= ixgbe_get_tx_pending(tx_ring
);
772 clear_check_for_tx_hang(tx_ring
);
775 * Check for a hung queue, but be thorough. This verifies
776 * that a transmit has been completed since the previous
777 * check AND there is at least one packet pending. The
778 * ARMED bit is set to indicate a potential hang. The
779 * bit is cleared if a pause frame is received to remove
780 * false hang detection due to PFC or 802.3x frames. By
781 * requiring this to fail twice we avoid races with
782 * pfc clearing the ARMED bit and conditions where we
783 * run the check_tx_hang logic with a transmit completion
784 * pending but without time to complete it yet.
786 if ((tx_done_old
== tx_done
) && tx_pending
) {
787 /* make sure it is true for two checks in a row */
788 ret
= test_and_set_bit(__IXGBE_HANG_CHECK_ARMED
,
791 /* update completed stats and continue */
792 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
793 /* reset the countdown */
794 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
800 #define IXGBE_MAX_TXD_PWR 14
801 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
803 /* Tx Descriptors needed, worst case */
804 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
805 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
806 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
807 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
809 static void ixgbe_tx_timeout(struct net_device
*netdev
);
812 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
813 * @q_vector: structure containing interrupt and ring information
814 * @tx_ring: tx ring to clean
816 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
817 struct ixgbe_ring
*tx_ring
)
819 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
820 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
821 struct ixgbe_tx_buffer
*tx_buffer_info
;
822 unsigned int total_bytes
= 0, total_packets
= 0;
823 u16 i
, eop
, count
= 0;
825 i
= tx_ring
->next_to_clean
;
826 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
827 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
829 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
830 (count
< tx_ring
->work_limit
)) {
831 bool cleaned
= false;
832 rmb(); /* read buffer_info after eop_desc */
833 for ( ; !cleaned
; count
++) {
834 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
835 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
837 tx_desc
->wb
.status
= 0;
838 cleaned
= (i
== eop
);
841 if (i
== tx_ring
->count
)
844 if (cleaned
&& tx_buffer_info
->skb
) {
845 total_bytes
+= tx_buffer_info
->bytecount
;
846 total_packets
+= tx_buffer_info
->gso_segs
;
849 ixgbe_unmap_and_free_tx_resource(tx_ring
,
853 tx_ring
->tx_stats
.completed
++;
854 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
855 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
858 tx_ring
->next_to_clean
= i
;
859 tx_ring
->total_bytes
+= total_bytes
;
860 tx_ring
->total_packets
+= total_packets
;
861 u64_stats_update_begin(&tx_ring
->syncp
);
862 tx_ring
->stats
.packets
+= total_packets
;
863 tx_ring
->stats
.bytes
+= total_bytes
;
864 u64_stats_update_end(&tx_ring
->syncp
);
866 if (check_for_tx_hang(tx_ring
) && ixgbe_check_tx_hang(tx_ring
)) {
867 /* schedule immediate reset if we believe we hung */
868 struct ixgbe_hw
*hw
= &adapter
->hw
;
869 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
870 e_err(drv
, "Detected Tx Unit Hang\n"
872 " TDH, TDT <%x>, <%x>\n"
873 " next_to_use <%x>\n"
874 " next_to_clean <%x>\n"
875 "tx_buffer_info[next_to_clean]\n"
876 " time_stamp <%lx>\n"
878 tx_ring
->queue_index
,
879 IXGBE_READ_REG(hw
, IXGBE_TDH(tx_ring
->reg_idx
)),
880 IXGBE_READ_REG(hw
, IXGBE_TDT(tx_ring
->reg_idx
)),
881 tx_ring
->next_to_use
, eop
,
882 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
884 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
887 "tx hang %d detected on queue %d, resetting adapter\n",
888 adapter
->tx_timeout_count
+ 1, tx_ring
->queue_index
);
890 /* schedule immediate reset if we believe we hung */
891 ixgbe_tx_timeout(adapter
->netdev
);
893 /* the adapter is about to reset, no point in enabling stuff */
897 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
898 if (unlikely(count
&& netif_carrier_ok(tx_ring
->netdev
) &&
899 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
900 /* Make sure that anybody stopping the queue after this
901 * sees the new next_to_clean.
904 if (__netif_subqueue_stopped(tx_ring
->netdev
, tx_ring
->queue_index
) &&
905 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
906 netif_wake_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
907 ++tx_ring
->tx_stats
.restart_queue
;
911 return count
< tx_ring
->work_limit
;
914 #ifdef CONFIG_IXGBE_DCA
915 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
916 struct ixgbe_ring
*rx_ring
,
919 struct ixgbe_hw
*hw
= &adapter
->hw
;
921 u8 reg_idx
= rx_ring
->reg_idx
;
923 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
));
924 switch (hw
->mac
.type
) {
925 case ixgbe_mac_82598EB
:
926 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
927 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
929 case ixgbe_mac_82599EB
:
931 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
932 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
933 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
938 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
939 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
940 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
941 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
942 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
943 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
), rxctrl
);
946 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
947 struct ixgbe_ring
*tx_ring
,
950 struct ixgbe_hw
*hw
= &adapter
->hw
;
952 u8 reg_idx
= tx_ring
->reg_idx
;
954 switch (hw
->mac
.type
) {
955 case ixgbe_mac_82598EB
:
956 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
));
957 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
958 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
959 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
960 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
961 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
), txctrl
);
963 case ixgbe_mac_82599EB
:
965 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
));
966 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
967 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
968 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
969 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
970 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
971 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
), txctrl
);
978 static void ixgbe_update_dca(struct ixgbe_q_vector
*q_vector
)
980 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
985 if (q_vector
->cpu
== cpu
)
988 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
989 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
990 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[r_idx
], cpu
);
991 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
995 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
996 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
997 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[r_idx
], cpu
);
998 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1002 q_vector
->cpu
= cpu
;
1007 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
1012 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1015 /* always use CB2 mode, difference is masked in the CB driver */
1016 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
1018 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
1019 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1023 for (i
= 0; i
< num_q_vectors
; i
++) {
1024 adapter
->q_vector
[i
]->cpu
= -1;
1025 ixgbe_update_dca(adapter
->q_vector
[i
]);
1029 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
1031 struct ixgbe_adapter
*adapter
= dev_get_drvdata(dev
);
1032 unsigned long event
= *(unsigned long *)data
;
1034 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1038 case DCA_PROVIDER_ADD
:
1039 /* if we're already enabled, don't do it again */
1040 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1042 if (dca_add_requester(dev
) == 0) {
1043 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
1044 ixgbe_setup_dca(adapter
);
1047 /* Fall Through since DCA is disabled. */
1048 case DCA_PROVIDER_REMOVE
:
1049 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
1050 dca_remove_requester(dev
);
1051 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
1052 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
1060 #endif /* CONFIG_IXGBE_DCA */
1062 * ixgbe_receive_skb - Send a completed packet up the stack
1063 * @adapter: board private structure
1064 * @skb: packet to send up
1065 * @status: hardware indication of status of receive
1066 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1067 * @rx_desc: rx descriptor
1069 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
1070 struct sk_buff
*skb
, u8 status
,
1071 struct ixgbe_ring
*ring
,
1072 union ixgbe_adv_rx_desc
*rx_desc
)
1074 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1075 struct napi_struct
*napi
= &q_vector
->napi
;
1076 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
1077 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
1079 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
1080 __vlan_hwaccel_put_tag(skb
, tag
);
1082 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
1083 napi_gro_receive(napi
, skb
);
1089 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1090 * @adapter: address of board private structure
1091 * @status_err: hardware indication of status of receive
1092 * @skb: skb currently being received and modified
1094 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
1095 union ixgbe_adv_rx_desc
*rx_desc
,
1096 struct sk_buff
*skb
)
1098 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1100 skb_checksum_none_assert(skb
);
1102 /* Rx csum disabled */
1103 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
1106 /* if IP and error */
1107 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
1108 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
1109 adapter
->hw_csum_rx_error
++;
1113 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
1116 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1117 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1120 * 82599 errata, UDP frames with a 0 checksum can be marked as
1123 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1124 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1127 adapter
->hw_csum_rx_error
++;
1131 /* It must be a TCP or UDP packet with a valid checksum */
1132 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1135 static inline void ixgbe_release_rx_desc(struct ixgbe_ring
*rx_ring
, u32 val
)
1138 * Force memory writes to complete before letting h/w
1139 * know there are new descriptors to fetch. (Only
1140 * applicable for weak-ordered memory model archs,
1144 writel(val
, rx_ring
->tail
);
1148 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1149 * @rx_ring: ring to place buffers on
1150 * @cleaned_count: number of buffers to replace
1152 void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*rx_ring
, u16 cleaned_count
)
1154 union ixgbe_adv_rx_desc
*rx_desc
;
1155 struct ixgbe_rx_buffer
*bi
;
1156 struct sk_buff
*skb
;
1157 u16 i
= rx_ring
->next_to_use
;
1159 /* do nothing if no valid netdev defined */
1160 if (!rx_ring
->netdev
)
1163 while (cleaned_count
--) {
1164 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1165 bi
= &rx_ring
->rx_buffer_info
[i
];
1169 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1170 rx_ring
->rx_buf_len
);
1172 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1175 /* initialize queue mapping */
1176 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1181 bi
->dma
= dma_map_single(rx_ring
->dev
,
1183 rx_ring
->rx_buf_len
,
1185 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
1186 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1192 if (ring_is_ps_enabled(rx_ring
)) {
1194 bi
->page
= netdev_alloc_page(rx_ring
->netdev
);
1196 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1201 if (!bi
->page_dma
) {
1202 /* use a half page if we're re-using */
1203 bi
->page_offset
^= PAGE_SIZE
/ 2;
1204 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
1209 if (dma_mapping_error(rx_ring
->dev
,
1211 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1217 /* Refresh the desc even if buffer_addrs didn't change
1218 * because each write-back erases this info. */
1219 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1220 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1222 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1223 rx_desc
->read
.hdr_addr
= 0;
1227 if (i
== rx_ring
->count
)
1232 if (rx_ring
->next_to_use
!= i
) {
1233 rx_ring
->next_to_use
= i
;
1234 ixgbe_release_rx_desc(rx_ring
, i
);
1238 static inline u16
ixgbe_get_hlen(union ixgbe_adv_rx_desc
*rx_desc
)
1240 /* HW will not DMA in data larger than the given buffer, even if it
1241 * parses the (NFS, of course) header to be larger. In that case, it
1242 * fills the header buffer and spills the rest into the page.
1244 u16 hdr_info
= le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
);
1245 u16 hlen
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1246 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1247 if (hlen
> IXGBE_RX_HDR_SIZE
)
1248 hlen
= IXGBE_RX_HDR_SIZE
;
1253 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1254 * @skb: pointer to the last skb in the rsc queue
1256 * This function changes a queue full of hw rsc buffers into a completed
1257 * packet. It uses the ->prev pointers to find the first packet and then
1258 * turns it into the frag list owner.
1260 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
1262 unsigned int frag_list_size
= 0;
1263 unsigned int skb_cnt
= 1;
1266 struct sk_buff
*prev
= skb
->prev
;
1267 frag_list_size
+= skb
->len
;
1273 skb_shinfo(skb
)->frag_list
= skb
->next
;
1275 skb
->len
+= frag_list_size
;
1276 skb
->data_len
+= frag_list_size
;
1277 skb
->truesize
+= frag_list_size
;
1278 IXGBE_RSC_CB(skb
)->skb_cnt
= skb_cnt
;
1283 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc
*rx_desc
)
1285 return !!(le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1286 IXGBE_RXDADV_RSCCNT_MASK
);
1289 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1290 struct ixgbe_ring
*rx_ring
,
1291 int *work_done
, int work_to_do
)
1293 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1294 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1295 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1296 struct sk_buff
*skb
;
1297 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1298 const int current_node
= numa_node_id();
1301 #endif /* IXGBE_FCOE */
1304 u16 cleaned_count
= 0;
1305 bool pkt_is_rsc
= false;
1307 i
= rx_ring
->next_to_clean
;
1308 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1309 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1311 while (staterr
& IXGBE_RXD_STAT_DD
) {
1314 rmb(); /* read descriptor and rx_buffer_info after status DD */
1316 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1318 skb
= rx_buffer_info
->skb
;
1319 rx_buffer_info
->skb
= NULL
;
1320 prefetch(skb
->data
);
1322 if (ring_is_rsc_enabled(rx_ring
))
1323 pkt_is_rsc
= ixgbe_get_rsc_state(rx_desc
);
1325 /* if this is a skb from previous receive DMA will be 0 */
1326 if (rx_buffer_info
->dma
) {
1329 !(staterr
& IXGBE_RXD_STAT_EOP
) &&
1332 * When HWRSC is enabled, delay unmapping
1333 * of the first packet. It carries the
1334 * header information, HW may still
1335 * access the header after the writeback.
1336 * Only unmap it when EOP is reached
1338 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1339 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1341 dma_unmap_single(rx_ring
->dev
,
1342 rx_buffer_info
->dma
,
1343 rx_ring
->rx_buf_len
,
1346 rx_buffer_info
->dma
= 0;
1348 if (ring_is_ps_enabled(rx_ring
)) {
1349 hlen
= ixgbe_get_hlen(rx_desc
);
1350 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1352 hlen
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1357 /* assume packet split since header is unmapped */
1358 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1362 dma_unmap_page(rx_ring
->dev
,
1363 rx_buffer_info
->page_dma
,
1366 rx_buffer_info
->page_dma
= 0;
1367 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1368 rx_buffer_info
->page
,
1369 rx_buffer_info
->page_offset
,
1372 if ((page_count(rx_buffer_info
->page
) == 1) &&
1373 (page_to_nid(rx_buffer_info
->page
) == current_node
))
1374 get_page(rx_buffer_info
->page
);
1376 rx_buffer_info
->page
= NULL
;
1378 skb
->len
+= upper_len
;
1379 skb
->data_len
+= upper_len
;
1380 skb
->truesize
+= upper_len
;
1384 if (i
== rx_ring
->count
)
1387 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1392 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1393 IXGBE_RXDADV_NEXTP_SHIFT
;
1394 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1396 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1399 if (!(staterr
& IXGBE_RXD_STAT_EOP
)) {
1400 if (ring_is_ps_enabled(rx_ring
)) {
1401 rx_buffer_info
->skb
= next_buffer
->skb
;
1402 rx_buffer_info
->dma
= next_buffer
->dma
;
1403 next_buffer
->skb
= skb
;
1404 next_buffer
->dma
= 0;
1406 skb
->next
= next_buffer
->skb
;
1407 skb
->next
->prev
= skb
;
1409 rx_ring
->rx_stats
.non_eop_descs
++;
1414 skb
= ixgbe_transform_rsc_queue(skb
);
1415 /* if we got here without RSC the packet is invalid */
1417 __pskb_trim(skb
, 0);
1418 rx_buffer_info
->skb
= skb
;
1423 if (ring_is_rsc_enabled(rx_ring
)) {
1424 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1425 dma_unmap_single(rx_ring
->dev
,
1426 IXGBE_RSC_CB(skb
)->dma
,
1427 rx_ring
->rx_buf_len
,
1429 IXGBE_RSC_CB(skb
)->dma
= 0;
1430 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1434 if (ring_is_ps_enabled(rx_ring
))
1435 rx_ring
->rx_stats
.rsc_count
+=
1436 skb_shinfo(skb
)->nr_frags
;
1438 rx_ring
->rx_stats
.rsc_count
+=
1439 IXGBE_RSC_CB(skb
)->skb_cnt
;
1440 rx_ring
->rx_stats
.rsc_flush
++;
1443 /* ERR_MASK will only have valid bits if EOP set */
1444 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1445 /* trim packet back to size 0 and recycle it */
1446 __pskb_trim(skb
, 0);
1447 rx_buffer_info
->skb
= skb
;
1451 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1453 /* probably a little skewed due to removing CRC */
1454 total_rx_bytes
+= skb
->len
;
1457 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1459 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1460 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1461 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1465 #endif /* IXGBE_FCOE */
1466 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1469 rx_desc
->wb
.upper
.status_error
= 0;
1472 if (*work_done
>= work_to_do
)
1475 /* return some buffers to hardware, one at a time is too slow */
1476 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1477 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1481 /* use prefetched values */
1483 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1486 rx_ring
->next_to_clean
= i
;
1487 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1490 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1493 /* include DDPed FCoE data */
1494 if (ddp_bytes
> 0) {
1497 mss
= rx_ring
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1498 sizeof(struct fc_frame_header
) -
1499 sizeof(struct fcoe_crc_eof
);
1502 total_rx_bytes
+= ddp_bytes
;
1503 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1505 #endif /* IXGBE_FCOE */
1507 rx_ring
->total_packets
+= total_rx_packets
;
1508 rx_ring
->total_bytes
+= total_rx_bytes
;
1509 u64_stats_update_begin(&rx_ring
->syncp
);
1510 rx_ring
->stats
.packets
+= total_rx_packets
;
1511 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1512 u64_stats_update_end(&rx_ring
->syncp
);
1515 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1517 * ixgbe_configure_msix - Configure MSI-X hardware
1518 * @adapter: board private structure
1520 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1523 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1525 struct ixgbe_q_vector
*q_vector
;
1526 int i
, q_vectors
, v_idx
, r_idx
;
1529 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1532 * Populate the IVAR table and set the ITR values to the
1533 * corresponding register.
1535 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1536 q_vector
= adapter
->q_vector
[v_idx
];
1537 /* XXX for_each_set_bit(...) */
1538 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1539 adapter
->num_rx_queues
);
1541 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1542 u8 reg_idx
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1543 ixgbe_set_ivar(adapter
, 0, reg_idx
, v_idx
);
1544 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1545 adapter
->num_rx_queues
,
1548 r_idx
= find_first_bit(q_vector
->txr_idx
,
1549 adapter
->num_tx_queues
);
1551 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1552 u8 reg_idx
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1553 ixgbe_set_ivar(adapter
, 1, reg_idx
, v_idx
);
1554 r_idx
= find_next_bit(q_vector
->txr_idx
,
1555 adapter
->num_tx_queues
,
1559 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1561 q_vector
->eitr
= adapter
->tx_eitr_param
;
1562 else if (q_vector
->rxr_count
)
1564 q_vector
->eitr
= adapter
->rx_eitr_param
;
1566 ixgbe_write_eitr(q_vector
);
1567 /* If Flow Director is enabled, set interrupt affinity */
1568 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
1569 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
1571 * Allocate the affinity_hint cpumask, assign the mask
1572 * for this vector, and set our affinity_hint for
1575 if (!alloc_cpumask_var(&q_vector
->affinity_mask
,
1578 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
1579 irq_set_affinity_hint(adapter
->msix_entries
[v_idx
].vector
,
1580 q_vector
->affinity_mask
);
1584 switch (adapter
->hw
.mac
.type
) {
1585 case ixgbe_mac_82598EB
:
1586 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1589 case ixgbe_mac_82599EB
:
1590 case ixgbe_mac_X540
:
1591 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1597 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1599 /* set up to autoclear timer, and the vectors */
1600 mask
= IXGBE_EIMS_ENABLE_MASK
;
1601 if (adapter
->num_vfs
)
1602 mask
&= ~(IXGBE_EIMS_OTHER
|
1603 IXGBE_EIMS_MAILBOX
|
1606 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1607 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1610 enum latency_range
{
1614 latency_invalid
= 255
1618 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1619 * @adapter: pointer to adapter
1620 * @eitr: eitr setting (ints per sec) to give last timeslice
1621 * @itr_setting: current throttle rate in ints/second
1622 * @packets: the number of packets during this measurement interval
1623 * @bytes: the number of bytes during this measurement interval
1625 * Stores a new ITR value based on packets and byte
1626 * counts during the last interrupt. The advantage of per interrupt
1627 * computation is faster updates and more accurate ITR for the current
1628 * traffic pattern. Constants in this function were computed
1629 * based on theoretical maximum wire speed and thresholds were set based
1630 * on testing data as well as attempting to minimize response time
1631 * while increasing bulk throughput.
1632 * this functionality is controlled by the InterruptThrottleRate module
1633 * parameter (see ixgbe_param.c)
1635 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1636 u32 eitr
, u8 itr_setting
,
1637 int packets
, int bytes
)
1639 unsigned int retval
= itr_setting
;
1644 goto update_itr_done
;
1647 /* simple throttlerate management
1648 * 0-20MB/s lowest (100000 ints/s)
1649 * 20-100MB/s low (20000 ints/s)
1650 * 100-1249MB/s bulk (8000 ints/s)
1652 /* what was last interrupt timeslice? */
1653 timepassed_us
= 1000000/eitr
;
1654 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1656 switch (itr_setting
) {
1657 case lowest_latency
:
1658 if (bytes_perint
> adapter
->eitr_low
)
1659 retval
= low_latency
;
1662 if (bytes_perint
> adapter
->eitr_high
)
1663 retval
= bulk_latency
;
1664 else if (bytes_perint
<= adapter
->eitr_low
)
1665 retval
= lowest_latency
;
1668 if (bytes_perint
<= adapter
->eitr_high
)
1669 retval
= low_latency
;
1678 * ixgbe_write_eitr - write EITR register in hardware specific way
1679 * @q_vector: structure containing interrupt and ring information
1681 * This function is made to be called by ethtool and by the driver
1682 * when it needs to update EITR registers at runtime. Hardware
1683 * specific quirks/differences are taken care of here.
1685 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1687 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1688 struct ixgbe_hw
*hw
= &adapter
->hw
;
1689 int v_idx
= q_vector
->v_idx
;
1690 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1692 switch (adapter
->hw
.mac
.type
) {
1693 case ixgbe_mac_82598EB
:
1694 /* must write high and low 16 bits to reset counter */
1695 itr_reg
|= (itr_reg
<< 16);
1697 case ixgbe_mac_82599EB
:
1698 case ixgbe_mac_X540
:
1700 * 82599 and X540 can support a value of zero, so allow it for
1701 * max interrupt rate, but there is an errata where it can
1702 * not be zero with RSC
1705 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1709 * set the WDIS bit to not clear the timer bits and cause an
1710 * immediate assertion of the interrupt
1712 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1717 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1720 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1722 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1725 u8 current_itr
, ret_itr
;
1727 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1728 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1729 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[r_idx
];
1730 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1732 tx_ring
->total_packets
,
1733 tx_ring
->total_bytes
);
1734 /* if the result for this queue would decrease interrupt
1735 * rate for this vector then use that result */
1736 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1737 q_vector
->tx_itr
- 1 : ret_itr
);
1738 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1742 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1743 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1744 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[r_idx
];
1745 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1747 rx_ring
->total_packets
,
1748 rx_ring
->total_bytes
);
1749 /* if the result for this queue would decrease interrupt
1750 * rate for this vector then use that result */
1751 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1752 q_vector
->rx_itr
- 1 : ret_itr
);
1753 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1757 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1759 switch (current_itr
) {
1760 /* counts and packets in update_itr are dependent on these numbers */
1761 case lowest_latency
:
1765 new_itr
= 20000; /* aka hwitr = ~200 */
1773 if (new_itr
!= q_vector
->eitr
) {
1774 /* do an exponential smoothing */
1775 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
1777 /* save the algorithm value here, not the smoothed one */
1778 q_vector
->eitr
= new_itr
;
1780 ixgbe_write_eitr(q_vector
);
1785 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1786 * @work: pointer to work_struct containing our data
1788 static void ixgbe_check_overtemp_task(struct work_struct
*work
)
1790 struct ixgbe_adapter
*adapter
= container_of(work
,
1791 struct ixgbe_adapter
,
1792 check_overtemp_task
);
1793 struct ixgbe_hw
*hw
= &adapter
->hw
;
1794 u32 eicr
= adapter
->interrupt_event
;
1796 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
))
1799 switch (hw
->device_id
) {
1800 case IXGBE_DEV_ID_82599_T3_LOM
: {
1802 bool link_up
= false;
1804 if (hw
->mac
.ops
.check_link
)
1805 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1807 if (((eicr
& IXGBE_EICR_GPI_SDP0
) && (!link_up
)) ||
1808 (eicr
& IXGBE_EICR_LSC
))
1809 /* Check if this is due to overtemp */
1810 if (hw
->phy
.ops
.check_overtemp(hw
) == IXGBE_ERR_OVERTEMP
)
1815 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1820 "Network adapter has been stopped because it has over heated. "
1821 "Restart the computer. If the problem persists, "
1822 "power off the system and replace the adapter\n");
1823 /* write to clear the interrupt */
1824 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP0
);
1827 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1829 struct ixgbe_hw
*hw
= &adapter
->hw
;
1831 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1832 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1833 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1834 /* write to clear the interrupt */
1835 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1839 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1841 struct ixgbe_hw
*hw
= &adapter
->hw
;
1843 if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1844 /* Clear the interrupt */
1845 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1846 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1847 schedule_work(&adapter
->sfp_config_module_task
);
1850 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1851 /* Clear the interrupt */
1852 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1853 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1854 schedule_work(&adapter
->multispeed_fiber_task
);
1858 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1860 struct ixgbe_hw
*hw
= &adapter
->hw
;
1863 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1864 adapter
->link_check_timeout
= jiffies
;
1865 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1866 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1867 IXGBE_WRITE_FLUSH(hw
);
1868 schedule_work(&adapter
->watchdog_task
);
1872 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1874 struct net_device
*netdev
= data
;
1875 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1876 struct ixgbe_hw
*hw
= &adapter
->hw
;
1880 * Workaround for Silicon errata. Use clear-by-write instead
1881 * of clear-by-read. Reading with EICS will return the
1882 * interrupt causes without clearing, which later be done
1883 * with the write to EICR.
1885 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1886 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1888 if (eicr
& IXGBE_EICR_LSC
)
1889 ixgbe_check_lsc(adapter
);
1891 if (eicr
& IXGBE_EICR_MAILBOX
)
1892 ixgbe_msg_task(adapter
);
1894 switch (hw
->mac
.type
) {
1895 case ixgbe_mac_82599EB
:
1896 case ixgbe_mac_X540
:
1897 /* Handle Flow Director Full threshold interrupt */
1898 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1900 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1901 /* Disable transmits before FDIR Re-initialization */
1902 netif_tx_stop_all_queues(netdev
);
1903 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1904 struct ixgbe_ring
*tx_ring
=
1905 adapter
->tx_ring
[i
];
1906 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE
,
1908 schedule_work(&adapter
->fdir_reinit_task
);
1911 ixgbe_check_sfp_event(adapter
, eicr
);
1912 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1913 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
1914 adapter
->interrupt_event
= eicr
;
1915 schedule_work(&adapter
->check_overtemp_task
);
1922 ixgbe_check_fan_failure(adapter
, eicr
);
1924 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1925 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1930 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1934 struct ixgbe_hw
*hw
= &adapter
->hw
;
1936 switch (hw
->mac
.type
) {
1937 case ixgbe_mac_82598EB
:
1938 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1939 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, mask
);
1941 case ixgbe_mac_82599EB
:
1942 case ixgbe_mac_X540
:
1943 mask
= (qmask
& 0xFFFFFFFF);
1945 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(0), mask
);
1946 mask
= (qmask
>> 32);
1948 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(1), mask
);
1953 /* skip the flush */
1956 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1960 struct ixgbe_hw
*hw
= &adapter
->hw
;
1962 switch (hw
->mac
.type
) {
1963 case ixgbe_mac_82598EB
:
1964 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1965 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, mask
);
1967 case ixgbe_mac_82599EB
:
1968 case ixgbe_mac_X540
:
1969 mask
= (qmask
& 0xFFFFFFFF);
1971 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(0), mask
);
1972 mask
= (qmask
>> 32);
1974 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(1), mask
);
1979 /* skip the flush */
1982 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1984 struct ixgbe_q_vector
*q_vector
= data
;
1985 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1986 struct ixgbe_ring
*tx_ring
;
1989 if (!q_vector
->txr_count
)
1992 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1993 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1994 tx_ring
= adapter
->tx_ring
[r_idx
];
1995 tx_ring
->total_bytes
= 0;
1996 tx_ring
->total_packets
= 0;
1997 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2001 /* EIAM disabled interrupts (on this vector) for us */
2002 napi_schedule(&q_vector
->napi
);
2008 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2010 * @data: pointer to our q_vector struct for this interrupt vector
2012 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
2014 struct ixgbe_q_vector
*q_vector
= data
;
2015 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2016 struct ixgbe_ring
*rx_ring
;
2020 #ifdef CONFIG_IXGBE_DCA
2021 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2022 ixgbe_update_dca(q_vector
);
2025 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2026 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2027 rx_ring
= adapter
->rx_ring
[r_idx
];
2028 rx_ring
->total_bytes
= 0;
2029 rx_ring
->total_packets
= 0;
2030 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2034 if (!q_vector
->rxr_count
)
2037 /* EIAM disabled interrupts (on this vector) for us */
2038 napi_schedule(&q_vector
->napi
);
2043 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
2045 struct ixgbe_q_vector
*q_vector
= data
;
2046 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2047 struct ixgbe_ring
*ring
;
2051 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
2054 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2055 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2056 ring
= adapter
->tx_ring
[r_idx
];
2057 ring
->total_bytes
= 0;
2058 ring
->total_packets
= 0;
2059 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2063 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2064 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2065 ring
= adapter
->rx_ring
[r_idx
];
2066 ring
->total_bytes
= 0;
2067 ring
->total_packets
= 0;
2068 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2072 /* EIAM disabled interrupts (on this vector) for us */
2073 napi_schedule(&q_vector
->napi
);
2079 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2080 * @napi: napi struct with our devices info in it
2081 * @budget: amount of work driver is allowed to do this pass, in packets
2083 * This function is optimized for cleaning one queue only on a single
2086 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
2088 struct ixgbe_q_vector
*q_vector
=
2089 container_of(napi
, struct ixgbe_q_vector
, napi
);
2090 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2091 struct ixgbe_ring
*rx_ring
= NULL
;
2095 #ifdef CONFIG_IXGBE_DCA
2096 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2097 ixgbe_update_dca(q_vector
);
2100 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2101 rx_ring
= adapter
->rx_ring
[r_idx
];
2103 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
2105 /* If all Rx work done, exit the polling mode */
2106 if (work_done
< budget
) {
2107 napi_complete(napi
);
2108 if (adapter
->rx_itr_setting
& 1)
2109 ixgbe_set_itr_msix(q_vector
);
2110 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2111 ixgbe_irq_enable_queues(adapter
,
2112 ((u64
)1 << q_vector
->v_idx
));
2119 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2120 * @napi: napi struct with our devices info in it
2121 * @budget: amount of work driver is allowed to do this pass, in packets
2123 * This function will clean more than one rx queue associated with a
2126 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
2128 struct ixgbe_q_vector
*q_vector
=
2129 container_of(napi
, struct ixgbe_q_vector
, napi
);
2130 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2131 struct ixgbe_ring
*ring
= NULL
;
2132 int work_done
= 0, i
;
2134 bool tx_clean_complete
= true;
2136 #ifdef CONFIG_IXGBE_DCA
2137 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2138 ixgbe_update_dca(q_vector
);
2141 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2142 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2143 ring
= adapter
->tx_ring
[r_idx
];
2144 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
2145 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2149 /* attempt to distribute budget to each queue fairly, but don't allow
2150 * the budget to go below 1 because we'll exit polling */
2151 budget
/= (q_vector
->rxr_count
?: 1);
2152 budget
= max(budget
, 1);
2153 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2154 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2155 ring
= adapter
->rx_ring
[r_idx
];
2156 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
2157 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2161 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2162 ring
= adapter
->rx_ring
[r_idx
];
2163 /* If all Rx work done, exit the polling mode */
2164 if (work_done
< budget
) {
2165 napi_complete(napi
);
2166 if (adapter
->rx_itr_setting
& 1)
2167 ixgbe_set_itr_msix(q_vector
);
2168 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2169 ixgbe_irq_enable_queues(adapter
,
2170 ((u64
)1 << q_vector
->v_idx
));
2178 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2179 * @napi: napi struct with our devices info in it
2180 * @budget: amount of work driver is allowed to do this pass, in packets
2182 * This function is optimized for cleaning one queue only on a single
2185 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2187 struct ixgbe_q_vector
*q_vector
=
2188 container_of(napi
, struct ixgbe_q_vector
, napi
);
2189 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2190 struct ixgbe_ring
*tx_ring
= NULL
;
2194 #ifdef CONFIG_IXGBE_DCA
2195 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2196 ixgbe_update_dca(q_vector
);
2199 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2200 tx_ring
= adapter
->tx_ring
[r_idx
];
2202 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2205 /* If all Tx work done, exit the polling mode */
2206 if (work_done
< budget
) {
2207 napi_complete(napi
);
2208 if (adapter
->tx_itr_setting
& 1)
2209 ixgbe_set_itr_msix(q_vector
);
2210 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2211 ixgbe_irq_enable_queues(adapter
,
2212 ((u64
)1 << q_vector
->v_idx
));
2218 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2221 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2222 struct ixgbe_ring
*rx_ring
= a
->rx_ring
[r_idx
];
2224 set_bit(r_idx
, q_vector
->rxr_idx
);
2225 q_vector
->rxr_count
++;
2226 rx_ring
->q_vector
= q_vector
;
2229 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2232 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2233 struct ixgbe_ring
*tx_ring
= a
->tx_ring
[t_idx
];
2235 set_bit(t_idx
, q_vector
->txr_idx
);
2236 q_vector
->txr_count
++;
2237 tx_ring
->q_vector
= q_vector
;
2241 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2242 * @adapter: board private structure to initialize
2244 * This function maps descriptor rings to the queue-specific vectors
2245 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2246 * one vector per ring/queue, but on a constrained vector budget, we
2247 * group the rings as "efficiently" as possible. You would add new
2248 * mapping configurations in here.
2250 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
)
2254 int rxr_idx
= 0, txr_idx
= 0;
2255 int rxr_remaining
= adapter
->num_rx_queues
;
2256 int txr_remaining
= adapter
->num_tx_queues
;
2261 /* No mapping required if MSI-X is disabled. */
2262 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2265 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2268 * The ideal configuration...
2269 * We have enough vectors to map one per queue.
2271 if (q_vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2272 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2273 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2275 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2276 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2282 * If we don't have enough vectors for a 1-to-1
2283 * mapping, we'll have to group them so there are
2284 * multiple queues per vector.
2286 /* Re-adjusting *qpv takes care of the remainder. */
2287 for (i
= v_start
; i
< q_vectors
; i
++) {
2288 rqpv
= DIV_ROUND_UP(rxr_remaining
, q_vectors
- i
);
2289 for (j
= 0; j
< rqpv
; j
++) {
2290 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2294 tqpv
= DIV_ROUND_UP(txr_remaining
, q_vectors
- i
);
2295 for (j
= 0; j
< tqpv
; j
++) {
2296 map_vector_to_txq(adapter
, i
, txr_idx
);
2306 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2307 * @adapter: board private structure
2309 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2310 * interrupts from the kernel.
2312 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2314 struct net_device
*netdev
= adapter
->netdev
;
2315 irqreturn_t (*handler
)(int, void *);
2316 int i
, vector
, q_vectors
, err
;
2319 /* Decrement for Other and TCP Timer vectors */
2320 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2322 err
= ixgbe_map_rings_to_vectors(adapter
);
2326 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2327 ? &ixgbe_msix_clean_many : \
2328 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2329 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2331 for (vector
= 0; vector
< q_vectors
; vector
++) {
2332 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[vector
];
2333 handler
= SET_HANDLER(q_vector
);
2335 if (handler
== &ixgbe_msix_clean_rx
) {
2336 sprintf(q_vector
->name
, "%s-%s-%d",
2337 netdev
->name
, "rx", ri
++);
2338 } else if (handler
== &ixgbe_msix_clean_tx
) {
2339 sprintf(q_vector
->name
, "%s-%s-%d",
2340 netdev
->name
, "tx", ti
++);
2341 } else if (handler
== &ixgbe_msix_clean_many
) {
2342 sprintf(q_vector
->name
, "%s-%s-%d",
2343 netdev
->name
, "TxRx", ri
++);
2346 /* skip this unused q_vector */
2349 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2350 handler
, 0, q_vector
->name
,
2353 e_err(probe
, "request_irq failed for MSIX interrupt "
2354 "Error: %d\n", err
);
2355 goto free_queue_irqs
;
2359 sprintf(adapter
->lsc_int_name
, "%s:lsc", netdev
->name
);
2360 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2361 ixgbe_msix_lsc
, 0, adapter
->lsc_int_name
, netdev
);
2363 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2364 goto free_queue_irqs
;
2370 for (i
= vector
- 1; i
>= 0; i
--)
2371 free_irq(adapter
->msix_entries
[--vector
].vector
,
2372 adapter
->q_vector
[i
]);
2373 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2374 pci_disable_msix(adapter
->pdev
);
2375 kfree(adapter
->msix_entries
);
2376 adapter
->msix_entries
= NULL
;
2380 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2382 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2383 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2384 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2385 u32 new_itr
= q_vector
->eitr
;
2388 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2390 tx_ring
->total_packets
,
2391 tx_ring
->total_bytes
);
2392 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2394 rx_ring
->total_packets
,
2395 rx_ring
->total_bytes
);
2397 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2399 switch (current_itr
) {
2400 /* counts and packets in update_itr are dependent on these numbers */
2401 case lowest_latency
:
2405 new_itr
= 20000; /* aka hwitr = ~200 */
2414 if (new_itr
!= q_vector
->eitr
) {
2415 /* do an exponential smoothing */
2416 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
2418 /* save the algorithm value here */
2419 q_vector
->eitr
= new_itr
;
2421 ixgbe_write_eitr(q_vector
);
2426 * ixgbe_irq_enable - Enable default interrupt generation settings
2427 * @adapter: board private structure
2429 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
2434 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2435 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2436 mask
|= IXGBE_EIMS_GPI_SDP0
;
2437 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2438 mask
|= IXGBE_EIMS_GPI_SDP1
;
2439 switch (adapter
->hw
.mac
.type
) {
2440 case ixgbe_mac_82599EB
:
2441 case ixgbe_mac_X540
:
2442 mask
|= IXGBE_EIMS_ECC
;
2443 mask
|= IXGBE_EIMS_GPI_SDP1
;
2444 mask
|= IXGBE_EIMS_GPI_SDP2
;
2445 if (adapter
->num_vfs
)
2446 mask
|= IXGBE_EIMS_MAILBOX
;
2451 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2452 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2453 mask
|= IXGBE_EIMS_FLOW_DIR
;
2455 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2457 ixgbe_irq_enable_queues(adapter
, ~0);
2459 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2461 if (adapter
->num_vfs
> 32) {
2462 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2463 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2468 * ixgbe_intr - legacy mode Interrupt Handler
2469 * @irq: interrupt number
2470 * @data: pointer to a network interface device structure
2472 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2474 struct net_device
*netdev
= data
;
2475 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2476 struct ixgbe_hw
*hw
= &adapter
->hw
;
2477 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2481 * Workaround for silicon errata on 82598. Mask the interrupts
2482 * before the read of EICR.
2484 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2486 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2487 * therefore no explict interrupt disable is necessary */
2488 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2491 * shared interrupt alert!
2492 * make sure interrupts are enabled because the read will
2493 * have disabled interrupts due to EIAM
2494 * finish the workaround of silicon errata on 82598. Unmask
2495 * the interrupt that we masked before the EICR read.
2497 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2498 ixgbe_irq_enable(adapter
, true, true);
2499 return IRQ_NONE
; /* Not our interrupt */
2502 if (eicr
& IXGBE_EICR_LSC
)
2503 ixgbe_check_lsc(adapter
);
2505 switch (hw
->mac
.type
) {
2506 case ixgbe_mac_82599EB
:
2507 case ixgbe_mac_X540
:
2508 ixgbe_check_sfp_event(adapter
, eicr
);
2509 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2510 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
2511 adapter
->interrupt_event
= eicr
;
2512 schedule_work(&adapter
->check_overtemp_task
);
2519 ixgbe_check_fan_failure(adapter
, eicr
);
2521 if (napi_schedule_prep(&(q_vector
->napi
))) {
2522 adapter
->tx_ring
[0]->total_packets
= 0;
2523 adapter
->tx_ring
[0]->total_bytes
= 0;
2524 adapter
->rx_ring
[0]->total_packets
= 0;
2525 adapter
->rx_ring
[0]->total_bytes
= 0;
2526 /* would disable interrupts here but EIAM disabled it */
2527 __napi_schedule(&(q_vector
->napi
));
2531 * re-enable link(maybe) and non-queue interrupts, no flush.
2532 * ixgbe_poll will re-enable the queue interrupts
2535 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2536 ixgbe_irq_enable(adapter
, false, false);
2541 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2543 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2545 for (i
= 0; i
< q_vectors
; i
++) {
2546 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2547 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2548 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2549 q_vector
->rxr_count
= 0;
2550 q_vector
->txr_count
= 0;
2555 * ixgbe_request_irq - initialize interrupts
2556 * @adapter: board private structure
2558 * Attempts to configure interrupts using the best available
2559 * capabilities of the hardware and kernel.
2561 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2563 struct net_device
*netdev
= adapter
->netdev
;
2566 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2567 err
= ixgbe_request_msix_irqs(adapter
);
2568 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2569 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2570 netdev
->name
, netdev
);
2572 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2573 netdev
->name
, netdev
);
2577 e_err(probe
, "request_irq failed, Error %d\n", err
);
2582 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2584 struct net_device
*netdev
= adapter
->netdev
;
2586 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2589 q_vectors
= adapter
->num_msix_vectors
;
2592 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2595 for (; i
>= 0; i
--) {
2596 free_irq(adapter
->msix_entries
[i
].vector
,
2597 adapter
->q_vector
[i
]);
2600 ixgbe_reset_q_vectors(adapter
);
2602 free_irq(adapter
->pdev
->irq
, netdev
);
2607 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2608 * @adapter: board private structure
2610 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2612 switch (adapter
->hw
.mac
.type
) {
2613 case ixgbe_mac_82598EB
:
2614 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2616 case ixgbe_mac_82599EB
:
2617 case ixgbe_mac_X540
:
2618 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2619 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2620 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2621 if (adapter
->num_vfs
> 32)
2622 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2627 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2628 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2630 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2631 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2633 synchronize_irq(adapter
->pdev
->irq
);
2638 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2641 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2643 struct ixgbe_hw
*hw
= &adapter
->hw
;
2645 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2646 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2648 ixgbe_set_ivar(adapter
, 0, 0, 0);
2649 ixgbe_set_ivar(adapter
, 1, 0, 0);
2651 map_vector_to_rxq(adapter
, 0, 0);
2652 map_vector_to_txq(adapter
, 0, 0);
2654 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2658 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2659 * @adapter: board private structure
2660 * @ring: structure containing ring specific data
2662 * Configure the Tx descriptor ring after a reset.
2664 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2665 struct ixgbe_ring
*ring
)
2667 struct ixgbe_hw
*hw
= &adapter
->hw
;
2668 u64 tdba
= ring
->dma
;
2671 u8 reg_idx
= ring
->reg_idx
;
2673 /* disable queue to avoid issues while updating state */
2674 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2675 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2676 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2677 IXGBE_WRITE_FLUSH(hw
);
2679 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2680 (tdba
& DMA_BIT_MASK(32)));
2681 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2682 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2683 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2684 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2685 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2686 ring
->tail
= hw
->hw_addr
+ IXGBE_TDT(reg_idx
);
2688 /* configure fetching thresholds */
2689 if (adapter
->rx_itr_setting
== 0) {
2690 /* cannot set wthresh when itr==0 */
2691 txdctl
&= ~0x007F0000;
2693 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2694 txdctl
|= (8 << 16);
2696 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2697 /* PThresh workaround for Tx hang with DFP enabled. */
2701 /* reinitialize flowdirector state */
2702 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
2703 adapter
->atr_sample_rate
) {
2704 ring
->atr_sample_rate
= adapter
->atr_sample_rate
;
2705 ring
->atr_count
= 0;
2706 set_bit(__IXGBE_TX_FDIR_INIT_DONE
, &ring
->state
);
2708 ring
->atr_sample_rate
= 0;
2711 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &ring
->state
);
2714 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2715 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2717 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2718 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2719 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2722 /* poll to verify queue is enabled */
2725 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2726 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2728 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2731 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2733 struct ixgbe_hw
*hw
= &adapter
->hw
;
2737 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2740 /* disable the arbiter while setting MTQC */
2741 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2742 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2743 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2745 /* set transmit pool layout */
2746 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2747 switch (adapter
->flags
& mask
) {
2749 case (IXGBE_FLAG_SRIOV_ENABLED
):
2750 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2751 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2754 case (IXGBE_FLAG_DCB_ENABLED
):
2755 /* We enable 8 traffic classes, DCB only */
2756 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2757 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2761 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2765 /* re-enable the arbiter */
2766 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2767 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2771 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2772 * @adapter: board private structure
2774 * Configure the Tx unit of the MAC after a reset.
2776 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2778 struct ixgbe_hw
*hw
= &adapter
->hw
;
2782 ixgbe_setup_mtqc(adapter
);
2784 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2785 /* DMATXCTL.EN must be before Tx queues are enabled */
2786 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2787 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2788 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2791 /* Setup the HW Tx Head and Tail descriptor pointers */
2792 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2793 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2796 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2798 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2799 struct ixgbe_ring
*rx_ring
)
2802 u8 reg_idx
= rx_ring
->reg_idx
;
2804 switch (adapter
->hw
.mac
.type
) {
2805 case ixgbe_mac_82598EB
: {
2806 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2807 const int mask
= feature
[RING_F_RSS
].mask
;
2808 reg_idx
= reg_idx
& mask
;
2811 case ixgbe_mac_82599EB
:
2812 case ixgbe_mac_X540
:
2817 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
));
2819 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2820 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2821 if (adapter
->num_vfs
)
2822 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2824 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2825 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2827 if (ring_is_ps_enabled(rx_ring
)) {
2828 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2829 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2831 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2833 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2835 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2836 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2837 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2840 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
), srrctl
);
2843 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2845 struct ixgbe_hw
*hw
= &adapter
->hw
;
2846 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2847 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2848 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2849 u32 mrqc
= 0, reta
= 0;
2854 /* Fill out hash function seeds */
2855 for (i
= 0; i
< 10; i
++)
2856 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2858 /* Fill out redirection table */
2859 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2860 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2862 /* reta = 4-byte sliding window of
2863 * 0x00..(indices-1)(indices-1)00..etc. */
2864 reta
= (reta
<< 8) | (j
* 0x11);
2866 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2869 /* Disable indicating checksum in descriptor, enables RSS hash */
2870 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2871 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2872 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2874 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
2875 mask
= adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
;
2877 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2878 #ifdef CONFIG_IXGBE_DCB
2879 | IXGBE_FLAG_DCB_ENABLED
2881 | IXGBE_FLAG_SRIOV_ENABLED
2885 case (IXGBE_FLAG_RSS_ENABLED
):
2886 mrqc
= IXGBE_MRQC_RSSEN
;
2888 case (IXGBE_FLAG_SRIOV_ENABLED
):
2889 mrqc
= IXGBE_MRQC_VMDQEN
;
2891 #ifdef CONFIG_IXGBE_DCB
2892 case (IXGBE_FLAG_DCB_ENABLED
):
2893 mrqc
= IXGBE_MRQC_RT8TCEN
;
2895 #endif /* CONFIG_IXGBE_DCB */
2900 /* Perform hash on these packet types */
2901 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2902 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2903 | IXGBE_MRQC_RSS_FIELD_IPV6
2904 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2906 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2910 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2911 * @adapter: address of board private structure
2912 * @ring: structure containing ring specific data
2914 void ixgbe_clear_rscctl(struct ixgbe_adapter
*adapter
,
2915 struct ixgbe_ring
*ring
)
2917 struct ixgbe_hw
*hw
= &adapter
->hw
;
2919 u8 reg_idx
= ring
->reg_idx
;
2921 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2922 rscctrl
&= ~IXGBE_RSCCTL_RSCEN
;
2923 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2927 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2928 * @adapter: address of board private structure
2929 * @index: index of ring to set
2931 void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
2932 struct ixgbe_ring
*ring
)
2934 struct ixgbe_hw
*hw
= &adapter
->hw
;
2937 u8 reg_idx
= ring
->reg_idx
;
2939 if (!ring_is_rsc_enabled(ring
))
2942 rx_buf_len
= ring
->rx_buf_len
;
2943 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
2944 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2946 * we must limit the number of descriptors so that the
2947 * total size of max desc * buf_len is not greater
2950 if (ring_is_ps_enabled(ring
)) {
2951 #if (MAX_SKB_FRAGS > 16)
2952 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2953 #elif (MAX_SKB_FRAGS > 8)
2954 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2955 #elif (MAX_SKB_FRAGS > 4)
2956 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2958 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2961 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2962 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2963 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2964 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2966 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2968 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
2972 * ixgbe_set_uta - Set unicast filter table address
2973 * @adapter: board private structure
2975 * The unicast table address is a register array of 32-bit registers.
2976 * The table is meant to be used in a way similar to how the MTA is used
2977 * however due to certain limitations in the hardware it is necessary to
2978 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2979 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2981 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
2983 struct ixgbe_hw
*hw
= &adapter
->hw
;
2986 /* The UTA table only exists on 82599 hardware and newer */
2987 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
2990 /* we only need to do this if VMDq is enabled */
2991 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
2994 for (i
= 0; i
< 128; i
++)
2995 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
2998 #define IXGBE_MAX_RX_DESC_POLL 10
2999 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
3000 struct ixgbe_ring
*ring
)
3002 struct ixgbe_hw
*hw
= &adapter
->hw
;
3003 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
3005 u8 reg_idx
= ring
->reg_idx
;
3007 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3008 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
3009 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
3014 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3015 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
3018 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
3019 "the polling period\n", reg_idx
);
3023 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
3024 struct ixgbe_ring
*ring
)
3026 struct ixgbe_hw
*hw
= &adapter
->hw
;
3027 u64 rdba
= ring
->dma
;
3029 u8 reg_idx
= ring
->reg_idx
;
3031 /* disable queue to avoid issues while updating state */
3032 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3033 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
),
3034 rxdctl
& ~IXGBE_RXDCTL_ENABLE
);
3035 IXGBE_WRITE_FLUSH(hw
);
3037 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
3038 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
3039 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
3040 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
3041 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
3042 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
3043 ring
->tail
= hw
->hw_addr
+ IXGBE_RDT(reg_idx
);
3045 ixgbe_configure_srrctl(adapter
, ring
);
3046 ixgbe_configure_rscctl(adapter
, ring
);
3048 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3050 * enable cache line friendly hardware writes:
3051 * PTHRESH=32 descriptors (half the internal cache),
3052 * this also removes ugly rx_no_buffer_count increment
3053 * HTHRESH=4 descriptors (to minimize latency on fetch)
3054 * WTHRESH=8 burst writeback up to two cache lines
3056 rxdctl
&= ~0x3FFFFF;
3060 /* enable receive descriptor ring */
3061 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3062 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3064 ixgbe_rx_desc_queue_enable(adapter
, ring
);
3065 ixgbe_alloc_rx_buffers(ring
, IXGBE_DESC_UNUSED(ring
));
3068 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
3070 struct ixgbe_hw
*hw
= &adapter
->hw
;
3073 /* PSRTYPE must be initialized in non 82598 adapters */
3074 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
3075 IXGBE_PSRTYPE_UDPHDR
|
3076 IXGBE_PSRTYPE_IPV4HDR
|
3077 IXGBE_PSRTYPE_L2HDR
|
3078 IXGBE_PSRTYPE_IPV6HDR
;
3080 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3083 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
3084 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
3086 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
3087 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
3091 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
3093 struct ixgbe_hw
*hw
= &adapter
->hw
;
3096 u32 reg_offset
, vf_shift
;
3099 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3102 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
3103 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
3104 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
3105 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
3107 vf_shift
= adapter
->num_vfs
% 32;
3108 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
3110 /* Enable only the PF's pool for Tx/Rx */
3111 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
3112 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
3113 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
3114 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
3115 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3117 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3118 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
3121 * Set up VF register offsets for selected VT Mode,
3122 * i.e. 32 or 64 VFs for SR-IOV
3124 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3125 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
3126 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
3127 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3129 /* enable Tx loopback for VF/PF communication */
3130 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3133 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
3135 struct ixgbe_hw
*hw
= &adapter
->hw
;
3136 struct net_device
*netdev
= adapter
->netdev
;
3137 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3139 struct ixgbe_ring
*rx_ring
;
3143 /* Decide whether to use packet split mode or not */
3144 /* Do not use packet split if we're in SR-IOV Mode */
3145 if (!adapter
->num_vfs
)
3146 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
3148 /* Set the RX buffer length according to the mode */
3149 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
3150 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
3152 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
3153 (netdev
->mtu
<= ETH_DATA_LEN
))
3154 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3156 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
3160 /* adjust max frame to be able to do baby jumbo for FCoE */
3161 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
3162 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3163 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3165 #endif /* IXGBE_FCOE */
3166 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3167 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3168 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3169 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3171 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3174 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3175 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3176 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
3177 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3180 * Setup the HW Rx Head and Tail Descriptor Pointers and
3181 * the Base and Length of the Rx Descriptor Ring
3183 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3184 rx_ring
= adapter
->rx_ring
[i
];
3185 rx_ring
->rx_buf_len
= rx_buf_len
;
3187 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
3188 set_ring_ps_enabled(rx_ring
);
3190 clear_ring_ps_enabled(rx_ring
);
3192 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
3193 set_ring_rsc_enabled(rx_ring
);
3195 clear_ring_rsc_enabled(rx_ring
);
3198 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
3199 struct ixgbe_ring_feature
*f
;
3200 f
= &adapter
->ring_feature
[RING_F_FCOE
];
3201 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
3202 clear_ring_ps_enabled(rx_ring
);
3203 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
3204 rx_ring
->rx_buf_len
=
3205 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3206 } else if (!ring_is_rsc_enabled(rx_ring
) &&
3207 !ring_is_ps_enabled(rx_ring
)) {
3208 rx_ring
->rx_buf_len
=
3209 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3212 #endif /* IXGBE_FCOE */
3216 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
3218 struct ixgbe_hw
*hw
= &adapter
->hw
;
3219 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
3221 switch (hw
->mac
.type
) {
3222 case ixgbe_mac_82598EB
:
3224 * For VMDq support of different descriptor types or
3225 * buffer sizes through the use of multiple SRRCTL
3226 * registers, RDRXCTL.MVMEN must be set to 1
3228 * also, the manual doesn't mention it clearly but DCA hints
3229 * will only use queue 0's tags unless this bit is set. Side
3230 * effects of setting this bit are only that SRRCTL must be
3231 * fully programmed [0..15]
3233 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
3235 case ixgbe_mac_82599EB
:
3236 case ixgbe_mac_X540
:
3237 /* Disable RSC for ACK packets */
3238 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
3239 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
3240 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
3241 /* hardware requires some bits to be set by default */
3242 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
3243 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
3246 /* We should do nothing since we don't know this hardware */
3250 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3254 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3255 * @adapter: board private structure
3257 * Configure the Rx unit of the MAC after a reset.
3259 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3261 struct ixgbe_hw
*hw
= &adapter
->hw
;
3265 /* disable receives while setting up the descriptors */
3266 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3267 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3269 ixgbe_setup_psrtype(adapter
);
3270 ixgbe_setup_rdrxctl(adapter
);
3272 /* Program registers for the distribution of queues */
3273 ixgbe_setup_mrqc(adapter
);
3275 ixgbe_set_uta(adapter
);
3277 /* set_rx_buffer_len must be called before ring initialization */
3278 ixgbe_set_rx_buffer_len(adapter
);
3281 * Setup the HW Rx Head and Tail Descriptor Pointers and
3282 * the Base and Length of the Rx Descriptor Ring
3284 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3285 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3287 /* disable drop enable for 82598 parts */
3288 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3289 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3291 /* enable all receives */
3292 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3293 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3296 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3298 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3299 struct ixgbe_hw
*hw
= &adapter
->hw
;
3300 int pool_ndx
= adapter
->num_vfs
;
3302 /* add VID to filter table */
3303 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3304 set_bit(vid
, adapter
->active_vlans
);
3307 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3309 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3310 struct ixgbe_hw
*hw
= &adapter
->hw
;
3311 int pool_ndx
= adapter
->num_vfs
;
3313 /* remove VID from filter table */
3314 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3315 clear_bit(vid
, adapter
->active_vlans
);
3319 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3320 * @adapter: driver data
3322 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3324 struct ixgbe_hw
*hw
= &adapter
->hw
;
3327 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3328 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3329 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3333 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3334 * @adapter: driver data
3336 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3338 struct ixgbe_hw
*hw
= &adapter
->hw
;
3341 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3342 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3343 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3344 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3348 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3349 * @adapter: driver data
3351 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3353 struct ixgbe_hw
*hw
= &adapter
->hw
;
3357 switch (hw
->mac
.type
) {
3358 case ixgbe_mac_82598EB
:
3359 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3360 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3361 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3363 case ixgbe_mac_82599EB
:
3364 case ixgbe_mac_X540
:
3365 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3366 j
= adapter
->rx_ring
[i
]->reg_idx
;
3367 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3368 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3369 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3378 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3379 * @adapter: driver data
3381 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3383 struct ixgbe_hw
*hw
= &adapter
->hw
;
3387 switch (hw
->mac
.type
) {
3388 case ixgbe_mac_82598EB
:
3389 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3390 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3391 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3393 case ixgbe_mac_82599EB
:
3394 case ixgbe_mac_X540
:
3395 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3396 j
= adapter
->rx_ring
[i
]->reg_idx
;
3397 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3398 vlnctrl
|= IXGBE_RXDCTL_VME
;
3399 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3407 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3411 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3413 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3414 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3418 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3419 * @netdev: network interface device structure
3421 * Writes unicast address list to the RAR table.
3422 * Returns: -ENOMEM on failure/insufficient address space
3423 * 0 on no addresses written
3424 * X on writing X addresses to the RAR table
3426 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3428 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3429 struct ixgbe_hw
*hw
= &adapter
->hw
;
3430 unsigned int vfn
= adapter
->num_vfs
;
3431 unsigned int rar_entries
= hw
->mac
.num_rar_entries
- (vfn
+ 1);
3434 /* return ENOMEM indicating insufficient memory for addresses */
3435 if (netdev_uc_count(netdev
) > rar_entries
)
3438 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3439 struct netdev_hw_addr
*ha
;
3440 /* return error if we do not support writing to RAR table */
3441 if (!hw
->mac
.ops
.set_rar
)
3444 netdev_for_each_uc_addr(ha
, netdev
) {
3447 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3452 /* write the addresses in reverse order to avoid write combining */
3453 for (; rar_entries
> 0 ; rar_entries
--)
3454 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3460 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3461 * @netdev: network interface device structure
3463 * The set_rx_method entry point is called whenever the unicast/multicast
3464 * address list or the network interface flags are updated. This routine is
3465 * responsible for configuring the hardware for proper unicast, multicast and
3468 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3470 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3471 struct ixgbe_hw
*hw
= &adapter
->hw
;
3472 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3475 /* Check for Promiscuous and All Multicast modes */
3477 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3479 /* set all bits that we expect to always be set */
3480 fctrl
|= IXGBE_FCTRL_BAM
;
3481 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3482 fctrl
|= IXGBE_FCTRL_PMCF
;
3484 /* clear the bits we are changing the status of */
3485 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3487 if (netdev
->flags
& IFF_PROMISC
) {
3488 hw
->addr_ctrl
.user_set_promisc
= true;
3489 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3490 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3491 /* don't hardware filter vlans in promisc mode */
3492 ixgbe_vlan_filter_disable(adapter
);
3494 if (netdev
->flags
& IFF_ALLMULTI
) {
3495 fctrl
|= IXGBE_FCTRL_MPE
;
3496 vmolr
|= IXGBE_VMOLR_MPE
;
3499 * Write addresses to the MTA, if the attempt fails
3500 * then we should just turn on promiscous mode so
3501 * that we can at least receive multicast traffic
3503 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3504 vmolr
|= IXGBE_VMOLR_ROMPE
;
3506 ixgbe_vlan_filter_enable(adapter
);
3507 hw
->addr_ctrl
.user_set_promisc
= false;
3509 * Write addresses to available RAR registers, if there is not
3510 * sufficient space to store all the addresses then enable
3511 * unicast promiscous mode
3513 count
= ixgbe_write_uc_addr_list(netdev
);
3515 fctrl
|= IXGBE_FCTRL_UPE
;
3516 vmolr
|= IXGBE_VMOLR_ROPE
;
3520 if (adapter
->num_vfs
) {
3521 ixgbe_restore_vf_multicasts(adapter
);
3522 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3523 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3525 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3528 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3530 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3531 ixgbe_vlan_strip_enable(adapter
);
3533 ixgbe_vlan_strip_disable(adapter
);
3536 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3539 struct ixgbe_q_vector
*q_vector
;
3540 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3542 /* legacy and MSI only use one vector */
3543 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3546 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3547 struct napi_struct
*napi
;
3548 q_vector
= adapter
->q_vector
[q_idx
];
3549 napi
= &q_vector
->napi
;
3550 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3551 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3552 if (q_vector
->txr_count
== 1)
3553 napi
->poll
= &ixgbe_clean_txonly
;
3554 else if (q_vector
->rxr_count
== 1)
3555 napi
->poll
= &ixgbe_clean_rxonly
;
3563 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3566 struct ixgbe_q_vector
*q_vector
;
3567 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3569 /* legacy and MSI only use one vector */
3570 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3573 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3574 q_vector
= adapter
->q_vector
[q_idx
];
3575 napi_disable(&q_vector
->napi
);
3579 #ifdef CONFIG_IXGBE_DCB
3581 * ixgbe_configure_dcb - Configure DCB hardware
3582 * @adapter: ixgbe adapter struct
3584 * This is called by the driver on open to configure the DCB hardware.
3585 * This is also called by the gennetlink interface when reconfiguring
3588 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3590 struct ixgbe_hw
*hw
= &adapter
->hw
;
3591 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3593 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3594 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3595 netif_set_gso_max_size(adapter
->netdev
, 65536);
3599 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3600 netif_set_gso_max_size(adapter
->netdev
, 32768);
3603 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3604 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3607 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3609 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3612 /* Enable VLAN tag insert/strip */
3613 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3615 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3617 /* reconfigure the hardware */
3618 ixgbe_dcb_hw_config(hw
, &adapter
->dcb_cfg
);
3622 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3624 struct net_device
*netdev
= adapter
->netdev
;
3625 struct ixgbe_hw
*hw
= &adapter
->hw
;
3628 #ifdef CONFIG_IXGBE_DCB
3629 ixgbe_configure_dcb(adapter
);
3632 ixgbe_set_rx_mode(netdev
);
3633 ixgbe_restore_vlan(adapter
);
3636 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3637 ixgbe_configure_fcoe(adapter
);
3639 #endif /* IXGBE_FCOE */
3640 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3641 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3642 adapter
->tx_ring
[i
]->atr_sample_rate
=
3643 adapter
->atr_sample_rate
;
3644 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3645 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3646 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3648 ixgbe_configure_virtualization(adapter
);
3650 ixgbe_configure_tx(adapter
);
3651 ixgbe_configure_rx(adapter
);
3654 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3656 switch (hw
->phy
.type
) {
3657 case ixgbe_phy_sfp_avago
:
3658 case ixgbe_phy_sfp_ftl
:
3659 case ixgbe_phy_sfp_intel
:
3660 case ixgbe_phy_sfp_unknown
:
3661 case ixgbe_phy_sfp_passive_tyco
:
3662 case ixgbe_phy_sfp_passive_unknown
:
3663 case ixgbe_phy_sfp_active_unknown
:
3664 case ixgbe_phy_sfp_ftl_active
:
3672 * ixgbe_sfp_link_config - set up SFP+ link
3673 * @adapter: pointer to private adapter struct
3675 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3677 struct ixgbe_hw
*hw
= &adapter
->hw
;
3679 if (hw
->phy
.multispeed_fiber
) {
3681 * In multispeed fiber setups, the device may not have
3682 * had a physical connection when the driver loaded.
3683 * If that's the case, the initial link configuration
3684 * couldn't get the MAC into 10G or 1G mode, so we'll
3685 * never have a link status change interrupt fire.
3686 * We need to try and force an autonegotiation
3687 * session, then bring up link.
3689 hw
->mac
.ops
.setup_sfp(hw
);
3690 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
3691 schedule_work(&adapter
->multispeed_fiber_task
);
3694 * Direct Attach Cu and non-multispeed fiber modules
3695 * still need to be configured properly prior to
3698 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
3699 schedule_work(&adapter
->sfp_config_module_task
);
3704 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3705 * @hw: pointer to private hardware struct
3707 * Returns 0 on success, negative on failure
3709 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3712 bool negotiation
, link_up
= false;
3713 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3715 if (hw
->mac
.ops
.check_link
)
3716 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3721 if (hw
->mac
.ops
.get_link_capabilities
)
3722 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3727 if (hw
->mac
.ops
.setup_link
)
3728 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3733 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3735 struct ixgbe_hw
*hw
= &adapter
->hw
;
3738 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3739 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3741 gpie
|= IXGBE_GPIE_EIAME
;
3743 * use EIAM to auto-mask when MSI-X interrupt is asserted
3744 * this saves a register write for every interrupt
3746 switch (hw
->mac
.type
) {
3747 case ixgbe_mac_82598EB
:
3748 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3750 case ixgbe_mac_82599EB
:
3751 case ixgbe_mac_X540
:
3753 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3754 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3758 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3759 * specifically only auto mask tx and rx interrupts */
3760 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3763 /* XXX: to interrupt immediately for EICS writes, enable this */
3764 /* gpie |= IXGBE_GPIE_EIMEN; */
3766 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3767 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3768 gpie
|= IXGBE_GPIE_VTMODE_64
;
3771 /* Enable fan failure interrupt */
3772 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3773 gpie
|= IXGBE_SDP1_GPIEN
;
3775 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3776 gpie
|= IXGBE_SDP1_GPIEN
;
3777 gpie
|= IXGBE_SDP2_GPIEN
;
3779 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3782 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3784 struct ixgbe_hw
*hw
= &adapter
->hw
;
3788 ixgbe_get_hw_control(adapter
);
3789 ixgbe_setup_gpie(adapter
);
3791 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3792 ixgbe_configure_msix(adapter
);
3794 ixgbe_configure_msi_and_legacy(adapter
);
3796 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3797 if (hw
->mac
.ops
.enable_tx_laser
&&
3798 ((hw
->phy
.multispeed_fiber
) ||
3799 ((hw
->phy
.type
== ixgbe_media_type_fiber
) &&
3800 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
3801 hw
->mac
.ops
.enable_tx_laser(hw
);
3803 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3804 ixgbe_napi_enable_all(adapter
);
3806 if (ixgbe_is_sfp(hw
)) {
3807 ixgbe_sfp_link_config(adapter
);
3809 err
= ixgbe_non_sfp_link_config(hw
);
3811 e_err(probe
, "link_config FAILED %d\n", err
);
3814 /* clear any pending interrupts, may auto mask */
3815 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3816 ixgbe_irq_enable(adapter
, true, true);
3819 * If this adapter has a fan, check to see if we had a failure
3820 * before we enabled the interrupt.
3822 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3823 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3824 if (esdp
& IXGBE_ESDP_SDP1
)
3825 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3829 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3830 * arrived before interrupts were enabled but after probe. Such
3831 * devices wouldn't have their type identified yet. We need to
3832 * kick off the SFP+ module setup first, then try to bring up link.
3833 * If we're not hot-pluggable SFP+, we just need to configure link
3836 if (hw
->phy
.type
== ixgbe_phy_unknown
)
3837 schedule_work(&adapter
->sfp_config_module_task
);
3839 /* enable transmits */
3840 netif_tx_start_all_queues(adapter
->netdev
);
3842 /* bring the link up in the watchdog, this could race with our first
3843 * link up interrupt but shouldn't be a problem */
3844 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3845 adapter
->link_check_timeout
= jiffies
;
3846 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3848 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3849 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3850 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3851 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3856 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3858 WARN_ON(in_interrupt());
3859 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3861 ixgbe_down(adapter
);
3863 * If SR-IOV enabled then wait a bit before bringing the adapter
3864 * back up to give the VFs time to respond to the reset. The
3865 * two second wait is based upon the watchdog timer cycle in
3868 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3871 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3874 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3876 /* hardware has been reset, we need to reload some things */
3877 ixgbe_configure(adapter
);
3879 return ixgbe_up_complete(adapter
);
3882 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3884 struct ixgbe_hw
*hw
= &adapter
->hw
;
3887 err
= hw
->mac
.ops
.init_hw(hw
);
3890 case IXGBE_ERR_SFP_NOT_PRESENT
:
3892 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3893 e_dev_err("master disable timed out\n");
3895 case IXGBE_ERR_EEPROM_VERSION
:
3896 /* We are running on a pre-production device, log a warning */
3897 e_dev_warn("This device is a pre-production adapter/LOM. "
3898 "Please be aware there may be issuesassociated with "
3899 "your hardware. If you are experiencing problems "
3900 "please contact your Intel or hardware "
3901 "representative who provided you with this "
3905 e_dev_err("Hardware Error: %d\n", err
);
3908 /* reprogram the RAR[0] in case user changed it. */
3909 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3914 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3915 * @rx_ring: ring to free buffers from
3917 static void ixgbe_clean_rx_ring(struct ixgbe_ring
*rx_ring
)
3919 struct device
*dev
= rx_ring
->dev
;
3923 /* ring already cleared, nothing to do */
3924 if (!rx_ring
->rx_buffer_info
)
3927 /* Free all the Rx ring sk_buffs */
3928 for (i
= 0; i
< rx_ring
->count
; i
++) {
3929 struct ixgbe_rx_buffer
*rx_buffer_info
;
3931 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3932 if (rx_buffer_info
->dma
) {
3933 dma_unmap_single(rx_ring
->dev
, rx_buffer_info
->dma
,
3934 rx_ring
->rx_buf_len
,
3936 rx_buffer_info
->dma
= 0;
3938 if (rx_buffer_info
->skb
) {
3939 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3940 rx_buffer_info
->skb
= NULL
;
3942 struct sk_buff
*this = skb
;
3943 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3944 dma_unmap_single(dev
,
3945 IXGBE_RSC_CB(this)->dma
,
3946 rx_ring
->rx_buf_len
,
3948 IXGBE_RSC_CB(this)->dma
= 0;
3949 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3952 dev_kfree_skb(this);
3955 if (!rx_buffer_info
->page
)
3957 if (rx_buffer_info
->page_dma
) {
3958 dma_unmap_page(dev
, rx_buffer_info
->page_dma
,
3959 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3960 rx_buffer_info
->page_dma
= 0;
3962 put_page(rx_buffer_info
->page
);
3963 rx_buffer_info
->page
= NULL
;
3964 rx_buffer_info
->page_offset
= 0;
3967 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3968 memset(rx_ring
->rx_buffer_info
, 0, size
);
3970 /* Zero out the descriptor ring */
3971 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3973 rx_ring
->next_to_clean
= 0;
3974 rx_ring
->next_to_use
= 0;
3978 * ixgbe_clean_tx_ring - Free Tx Buffers
3979 * @tx_ring: ring to be cleaned
3981 static void ixgbe_clean_tx_ring(struct ixgbe_ring
*tx_ring
)
3983 struct ixgbe_tx_buffer
*tx_buffer_info
;
3987 /* ring already cleared, nothing to do */
3988 if (!tx_ring
->tx_buffer_info
)
3991 /* Free all the Tx ring sk_buffs */
3992 for (i
= 0; i
< tx_ring
->count
; i
++) {
3993 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3994 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
3997 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3998 memset(tx_ring
->tx_buffer_info
, 0, size
);
4000 /* Zero out the descriptor ring */
4001 memset(tx_ring
->desc
, 0, tx_ring
->size
);
4003 tx_ring
->next_to_use
= 0;
4004 tx_ring
->next_to_clean
= 0;
4008 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4009 * @adapter: board private structure
4011 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
4015 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4016 ixgbe_clean_rx_ring(adapter
->rx_ring
[i
]);
4020 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4021 * @adapter: board private structure
4023 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
4027 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4028 ixgbe_clean_tx_ring(adapter
->tx_ring
[i
]);
4031 void ixgbe_down(struct ixgbe_adapter
*adapter
)
4033 struct net_device
*netdev
= adapter
->netdev
;
4034 struct ixgbe_hw
*hw
= &adapter
->hw
;
4038 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4040 /* signal that we are down to the interrupt handler */
4041 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4043 /* disable receive for all VFs and wait one second */
4044 if (adapter
->num_vfs
) {
4045 /* ping all the active vfs to let them know we are going down */
4046 ixgbe_ping_all_vfs(adapter
);
4048 /* Disable all VFTE/VFRE TX/RX */
4049 ixgbe_disable_tx_rx(adapter
);
4051 /* Mark all the VFs as inactive */
4052 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
4053 adapter
->vfinfo
[i
].clear_to_send
= 0;
4056 /* disable receives */
4057 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
4058 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
4060 IXGBE_WRITE_FLUSH(hw
);
4063 netif_tx_stop_all_queues(netdev
);
4065 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4066 del_timer_sync(&adapter
->sfp_timer
);
4067 del_timer_sync(&adapter
->watchdog_timer
);
4068 cancel_work_sync(&adapter
->watchdog_task
);
4070 netif_carrier_off(netdev
);
4071 netif_tx_disable(netdev
);
4073 ixgbe_irq_disable(adapter
);
4075 ixgbe_napi_disable_all(adapter
);
4077 /* Cleanup the affinity_hint CPU mask memory and callback */
4078 for (i
= 0; i
< num_q_vectors
; i
++) {
4079 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
4080 /* clear the affinity_mask in the IRQ descriptor */
4081 irq_set_affinity_hint(adapter
->msix_entries
[i
]. vector
, NULL
);
4082 /* release the CPU mask memory */
4083 free_cpumask_var(q_vector
->affinity_mask
);
4086 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4087 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
4088 cancel_work_sync(&adapter
->fdir_reinit_task
);
4090 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
4091 cancel_work_sync(&adapter
->check_overtemp_task
);
4093 /* disable transmits in the hardware now that interrupts are off */
4094 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4095 u8 reg_idx
= adapter
->tx_ring
[i
]->reg_idx
;
4096 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
4097 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
4098 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
4100 /* Disable the Tx DMA engine on 82599 */
4101 switch (hw
->mac
.type
) {
4102 case ixgbe_mac_82599EB
:
4103 case ixgbe_mac_X540
:
4104 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
4105 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
4106 ~IXGBE_DMATXCTL_TE
));
4112 /* clear n-tuple filters that are cached */
4113 ethtool_ntuple_flush(netdev
);
4115 if (!pci_channel_offline(adapter
->pdev
))
4116 ixgbe_reset(adapter
);
4118 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4119 if (hw
->mac
.ops
.disable_tx_laser
&&
4120 ((hw
->phy
.multispeed_fiber
) ||
4121 ((hw
->phy
.type
== ixgbe_media_type_fiber
) &&
4122 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
4123 hw
->mac
.ops
.disable_tx_laser(hw
);
4125 ixgbe_clean_all_tx_rings(adapter
);
4126 ixgbe_clean_all_rx_rings(adapter
);
4128 #ifdef CONFIG_IXGBE_DCA
4129 /* since we reset the hardware DCA settings were cleared */
4130 ixgbe_setup_dca(adapter
);
4135 * ixgbe_poll - NAPI Rx polling callback
4136 * @napi: structure for representing this polling device
4137 * @budget: how many packets driver is allowed to clean
4139 * This function is used for legacy and MSI, NAPI mode
4141 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
4143 struct ixgbe_q_vector
*q_vector
=
4144 container_of(napi
, struct ixgbe_q_vector
, napi
);
4145 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
4146 int tx_clean_complete
, work_done
= 0;
4148 #ifdef CONFIG_IXGBE_DCA
4149 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
4150 ixgbe_update_dca(q_vector
);
4153 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
4154 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
4156 if (!tx_clean_complete
)
4159 /* If budget not fully consumed, exit the polling mode */
4160 if (work_done
< budget
) {
4161 napi_complete(napi
);
4162 if (adapter
->rx_itr_setting
& 1)
4163 ixgbe_set_itr(adapter
);
4164 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
4165 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
4171 * ixgbe_tx_timeout - Respond to a Tx Hang
4172 * @netdev: network interface device structure
4174 static void ixgbe_tx_timeout(struct net_device
*netdev
)
4176 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4178 adapter
->tx_timeout_count
++;
4180 /* Do the reset outside of interrupt context */
4181 schedule_work(&adapter
->reset_task
);
4184 static void ixgbe_reset_task(struct work_struct
*work
)
4186 struct ixgbe_adapter
*adapter
;
4187 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
4189 /* If we're already down or resetting, just bail */
4190 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
4191 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
4194 ixgbe_dump(adapter
);
4195 netdev_err(adapter
->netdev
, "Reset adapter\n");
4196 ixgbe_reinit_locked(adapter
);
4199 #ifdef CONFIG_IXGBE_DCB
4200 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
4203 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
4205 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
4209 adapter
->num_rx_queues
= f
->indices
;
4210 adapter
->num_tx_queues
= f
->indices
;
4218 * ixgbe_set_rss_queues: Allocate queues for RSS
4219 * @adapter: board private structure to initialize
4221 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4222 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4225 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4228 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4230 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4232 adapter
->num_rx_queues
= f
->indices
;
4233 adapter
->num_tx_queues
= f
->indices
;
4243 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4244 * @adapter: board private structure to initialize
4246 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4247 * to the original CPU that initiated the Tx session. This runs in addition
4248 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4249 * Rx load across CPUs using RSS.
4252 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4255 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4257 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4260 /* Flow Director must have RSS enabled */
4261 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4262 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4263 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
4264 adapter
->num_tx_queues
= f_fdir
->indices
;
4265 adapter
->num_rx_queues
= f_fdir
->indices
;
4268 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4269 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4276 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4277 * @adapter: board private structure to initialize
4279 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4280 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4281 * rx queues out of the max number of rx queues, instead, it is used as the
4282 * index of the first rx queue used by FCoE.
4285 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4288 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4290 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4291 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4292 adapter
->num_rx_queues
= 1;
4293 adapter
->num_tx_queues
= 1;
4294 #ifdef CONFIG_IXGBE_DCB
4295 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4296 e_info(probe
, "FCoE enabled with DCB\n");
4297 ixgbe_set_dcb_queues(adapter
);
4300 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4301 e_info(probe
, "FCoE enabled with RSS\n");
4302 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4303 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4304 ixgbe_set_fdir_queues(adapter
);
4306 ixgbe_set_rss_queues(adapter
);
4308 /* adding FCoE rx rings to the end */
4309 f
->mask
= adapter
->num_rx_queues
;
4310 adapter
->num_rx_queues
+= f
->indices
;
4311 adapter
->num_tx_queues
+= f
->indices
;
4319 #endif /* IXGBE_FCOE */
4321 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4322 * @adapter: board private structure to initialize
4324 * IOV doesn't actually use anything, so just NAK the
4325 * request for now and let the other queue routines
4326 * figure out what to do.
4328 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4334 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4335 * @adapter: board private structure to initialize
4337 * This is the top level queue allocation routine. The order here is very
4338 * important, starting with the "most" number of features turned on at once,
4339 * and ending with the smallest set of features. This way large combinations
4340 * can be allocated if they're turned on, and smaller combinations are the
4341 * fallthrough conditions.
4344 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4346 /* Start with base case */
4347 adapter
->num_rx_queues
= 1;
4348 adapter
->num_tx_queues
= 1;
4349 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4350 adapter
->num_rx_queues_per_pool
= 1;
4352 if (ixgbe_set_sriov_queues(adapter
))
4356 if (ixgbe_set_fcoe_queues(adapter
))
4359 #endif /* IXGBE_FCOE */
4360 #ifdef CONFIG_IXGBE_DCB
4361 if (ixgbe_set_dcb_queues(adapter
))
4365 if (ixgbe_set_fdir_queues(adapter
))
4368 if (ixgbe_set_rss_queues(adapter
))
4371 /* fallback to base case */
4372 adapter
->num_rx_queues
= 1;
4373 adapter
->num_tx_queues
= 1;
4376 /* Notify the stack of the (possibly) reduced queue counts. */
4377 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4378 return netif_set_real_num_rx_queues(adapter
->netdev
,
4379 adapter
->num_rx_queues
);
4382 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4385 int err
, vector_threshold
;
4387 /* We'll want at least 3 (vector_threshold):
4390 * 3) Other (Link Status Change, etc.)
4391 * 4) TCP Timer (optional)
4393 vector_threshold
= MIN_MSIX_COUNT
;
4395 /* The more we get, the more we will assign to Tx/Rx Cleanup
4396 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4397 * Right now, we simply care about how many we'll get; we'll
4398 * set them up later while requesting irq's.
4400 while (vectors
>= vector_threshold
) {
4401 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4403 if (!err
) /* Success in acquiring all requested vectors. */
4406 vectors
= 0; /* Nasty failure, quit now */
4407 else /* err == number of vectors we should try again with */
4411 if (vectors
< vector_threshold
) {
4412 /* Can't allocate enough MSI-X interrupts? Oh well.
4413 * This just means we'll go with either a single MSI
4414 * vector or fall back to legacy interrupts.
4416 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4417 "Unable to allocate MSI-X interrupts\n");
4418 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4419 kfree(adapter
->msix_entries
);
4420 adapter
->msix_entries
= NULL
;
4422 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4424 * Adjust for only the vectors we'll use, which is minimum
4425 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4426 * vectors we were allocated.
4428 adapter
->num_msix_vectors
= min(vectors
,
4429 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4434 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4435 * @adapter: board private structure to initialize
4437 * Cache the descriptor ring offsets for RSS to the assigned rings.
4440 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4444 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
4447 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4448 adapter
->rx_ring
[i
]->reg_idx
= i
;
4449 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4450 adapter
->tx_ring
[i
]->reg_idx
= i
;
4455 #ifdef CONFIG_IXGBE_DCB
4457 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4458 * @adapter: board private structure to initialize
4460 * Cache the descriptor ring offsets for DCB to the assigned rings.
4463 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4467 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
4469 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
4472 /* the number of queues is assumed to be symmetric */
4473 switch (adapter
->hw
.mac
.type
) {
4474 case ixgbe_mac_82598EB
:
4475 for (i
= 0; i
< dcb_i
; i
++) {
4476 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
4477 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
4481 case ixgbe_mac_82599EB
:
4482 case ixgbe_mac_X540
:
4485 * Tx TC0 starts at: descriptor queue 0
4486 * Tx TC1 starts at: descriptor queue 32
4487 * Tx TC2 starts at: descriptor queue 64
4488 * Tx TC3 starts at: descriptor queue 80
4489 * Tx TC4 starts at: descriptor queue 96
4490 * Tx TC5 starts at: descriptor queue 104
4491 * Tx TC6 starts at: descriptor queue 112
4492 * Tx TC7 starts at: descriptor queue 120
4494 * Rx TC0-TC7 are offset by 16 queues each
4496 for (i
= 0; i
< 3; i
++) {
4497 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
4498 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4500 for ( ; i
< 5; i
++) {
4501 adapter
->tx_ring
[i
]->reg_idx
= ((i
+ 2) << 4);
4502 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4504 for ( ; i
< dcb_i
; i
++) {
4505 adapter
->tx_ring
[i
]->reg_idx
= ((i
+ 8) << 3);
4506 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4509 } else if (dcb_i
== 4) {
4511 * Tx TC0 starts at: descriptor queue 0
4512 * Tx TC1 starts at: descriptor queue 64
4513 * Tx TC2 starts at: descriptor queue 96
4514 * Tx TC3 starts at: descriptor queue 112
4516 * Rx TC0-TC3 are offset by 32 queues each
4518 adapter
->tx_ring
[0]->reg_idx
= 0;
4519 adapter
->tx_ring
[1]->reg_idx
= 64;
4520 adapter
->tx_ring
[2]->reg_idx
= 96;
4521 adapter
->tx_ring
[3]->reg_idx
= 112;
4522 for (i
= 0 ; i
< dcb_i
; i
++)
4523 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
4535 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4536 * @adapter: board private structure to initialize
4538 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4541 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4546 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4547 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4548 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4549 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4550 adapter
->rx_ring
[i
]->reg_idx
= i
;
4551 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4552 adapter
->tx_ring
[i
]->reg_idx
= i
;
4561 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4562 * @adapter: board private structure to initialize
4564 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4567 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4569 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4571 u8 fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4573 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4576 #ifdef CONFIG_IXGBE_DCB
4577 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4578 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
4580 ixgbe_cache_ring_dcb(adapter
);
4581 /* find out queues in TC for FCoE */
4582 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4583 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4585 * In 82599, the number of Tx queues for each traffic
4586 * class for both 8-TC and 4-TC modes are:
4587 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4588 * 8 TCs: 32 32 16 16 8 8 8 8
4589 * 4 TCs: 64 64 32 32
4590 * We have max 8 queues for FCoE, where 8 the is
4591 * FCoE redirection table size. If TC for FCoE is
4592 * less than or equal to TC3, we have enough queues
4593 * to add max of 8 queues for FCoE, so we start FCoE
4594 * Tx queue from the next one, i.e., reg_idx + 1.
4595 * If TC for FCoE is above TC3, implying 8 TC mode,
4596 * and we need 8 for FCoE, we have to take all queues
4597 * in that traffic class for FCoE.
4599 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
4602 #endif /* CONFIG_IXGBE_DCB */
4603 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4604 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4605 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4606 ixgbe_cache_ring_fdir(adapter
);
4608 ixgbe_cache_ring_rss(adapter
);
4610 fcoe_rx_i
= f
->mask
;
4611 fcoe_tx_i
= f
->mask
;
4613 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4614 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4615 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4620 #endif /* IXGBE_FCOE */
4622 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4623 * @adapter: board private structure to initialize
4625 * SR-IOV doesn't use any descriptor rings but changes the default if
4626 * no other mapping is used.
4629 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4631 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4632 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4633 if (adapter
->num_vfs
)
4640 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4641 * @adapter: board private structure to initialize
4643 * Once we know the feature-set enabled for the device, we'll cache
4644 * the register offset the descriptor ring is assigned to.
4646 * Note, the order the various feature calls is important. It must start with
4647 * the "most" features enabled at the same time, then trickle down to the
4648 * least amount of features turned on at once.
4650 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4652 /* start with default case */
4653 adapter
->rx_ring
[0]->reg_idx
= 0;
4654 adapter
->tx_ring
[0]->reg_idx
= 0;
4656 if (ixgbe_cache_ring_sriov(adapter
))
4660 if (ixgbe_cache_ring_fcoe(adapter
))
4663 #endif /* IXGBE_FCOE */
4664 #ifdef CONFIG_IXGBE_DCB
4665 if (ixgbe_cache_ring_dcb(adapter
))
4669 if (ixgbe_cache_ring_fdir(adapter
))
4672 if (ixgbe_cache_ring_rss(adapter
))
4677 * ixgbe_alloc_queues - Allocate memory for all rings
4678 * @adapter: board private structure to initialize
4680 * We allocate one ring per queue at run-time since we don't know the
4681 * number of queues at compile-time. The polling_netdev array is
4682 * intended for Multiqueue, but should work fine with a single queue.
4684 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4686 int rx
= 0, tx
= 0, nid
= adapter
->node
;
4688 if (nid
< 0 || !node_online(nid
))
4689 nid
= first_online_node
;
4691 for (; tx
< adapter
->num_tx_queues
; tx
++) {
4692 struct ixgbe_ring
*ring
;
4694 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4696 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4698 goto err_allocation
;
4699 ring
->count
= adapter
->tx_ring_count
;
4700 ring
->queue_index
= tx
;
4701 ring
->numa_node
= nid
;
4702 ring
->dev
= &adapter
->pdev
->dev
;
4703 ring
->netdev
= adapter
->netdev
;
4705 adapter
->tx_ring
[tx
] = ring
;
4708 for (; rx
< adapter
->num_rx_queues
; rx
++) {
4709 struct ixgbe_ring
*ring
;
4711 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4713 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4715 goto err_allocation
;
4716 ring
->count
= adapter
->rx_ring_count
;
4717 ring
->queue_index
= rx
;
4718 ring
->numa_node
= nid
;
4719 ring
->dev
= &adapter
->pdev
->dev
;
4720 ring
->netdev
= adapter
->netdev
;
4722 adapter
->rx_ring
[rx
] = ring
;
4725 ixgbe_cache_ring_register(adapter
);
4731 kfree(adapter
->tx_ring
[--tx
]);
4734 kfree(adapter
->rx_ring
[--rx
]);
4739 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4740 * @adapter: board private structure to initialize
4742 * Attempt to configure the interrupts using the best available
4743 * capabilities of the hardware and the kernel.
4745 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4747 struct ixgbe_hw
*hw
= &adapter
->hw
;
4749 int vector
, v_budget
;
4752 * It's easy to be greedy for MSI-X vectors, but it really
4753 * doesn't do us much good if we have a lot more vectors
4754 * than CPU's. So let's be conservative and only ask for
4755 * (roughly) the same number of vectors as there are CPU's.
4757 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4758 (int)num_online_cpus()) + NON_Q_VECTORS
;
4761 * At the same time, hardware can only support a maximum of
4762 * hw.mac->max_msix_vectors vectors. With features
4763 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4764 * descriptor queues supported by our device. Thus, we cap it off in
4765 * those rare cases where the cpu count also exceeds our vector limit.
4767 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4769 /* A failure in MSI-X entry allocation isn't fatal, but it does
4770 * mean we disable MSI-X capabilities of the adapter. */
4771 adapter
->msix_entries
= kcalloc(v_budget
,
4772 sizeof(struct msix_entry
), GFP_KERNEL
);
4773 if (adapter
->msix_entries
) {
4774 for (vector
= 0; vector
< v_budget
; vector
++)
4775 adapter
->msix_entries
[vector
].entry
= vector
;
4777 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4779 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4783 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4784 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4785 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4786 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4787 adapter
->atr_sample_rate
= 0;
4788 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4789 ixgbe_disable_sriov(adapter
);
4791 err
= ixgbe_set_num_queues(adapter
);
4795 err
= pci_enable_msi(adapter
->pdev
);
4797 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4799 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4800 "Unable to allocate MSI interrupt, "
4801 "falling back to legacy. Error: %d\n", err
);
4811 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4812 * @adapter: board private structure to initialize
4814 * We allocate one q_vector per queue interrupt. If allocation fails we
4817 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4819 int q_idx
, num_q_vectors
;
4820 struct ixgbe_q_vector
*q_vector
;
4822 int (*poll
)(struct napi_struct
*, int);
4824 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4825 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4826 napi_vectors
= adapter
->num_rx_queues
;
4827 poll
= &ixgbe_clean_rxtx_many
;
4834 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4835 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4836 GFP_KERNEL
, adapter
->node
);
4838 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4842 q_vector
->adapter
= adapter
;
4843 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4844 q_vector
->eitr
= adapter
->tx_eitr_param
;
4846 q_vector
->eitr
= adapter
->rx_eitr_param
;
4847 q_vector
->v_idx
= q_idx
;
4848 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4849 adapter
->q_vector
[q_idx
] = q_vector
;
4857 q_vector
= adapter
->q_vector
[q_idx
];
4858 netif_napi_del(&q_vector
->napi
);
4860 adapter
->q_vector
[q_idx
] = NULL
;
4866 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4867 * @adapter: board private structure to initialize
4869 * This function frees the memory allocated to the q_vectors. In addition if
4870 * NAPI is enabled it will delete any references to the NAPI struct prior
4871 * to freeing the q_vector.
4873 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4875 int q_idx
, num_q_vectors
;
4877 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4878 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4882 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4883 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4884 adapter
->q_vector
[q_idx
] = NULL
;
4885 netif_napi_del(&q_vector
->napi
);
4890 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4892 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4893 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4894 pci_disable_msix(adapter
->pdev
);
4895 kfree(adapter
->msix_entries
);
4896 adapter
->msix_entries
= NULL
;
4897 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4898 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4899 pci_disable_msi(adapter
->pdev
);
4904 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4905 * @adapter: board private structure to initialize
4907 * We determine which interrupt scheme to use based on...
4908 * - Kernel support (MSI, MSI-X)
4909 * - which can be user-defined (via MODULE_PARAM)
4910 * - Hardware queue count (num_*_queues)
4911 * - defined by miscellaneous hardware support/features (RSS, etc.)
4913 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4917 /* Number of supported queues */
4918 err
= ixgbe_set_num_queues(adapter
);
4922 err
= ixgbe_set_interrupt_capability(adapter
);
4924 e_dev_err("Unable to setup interrupt capabilities\n");
4925 goto err_set_interrupt
;
4928 err
= ixgbe_alloc_q_vectors(adapter
);
4930 e_dev_err("Unable to allocate memory for queue vectors\n");
4931 goto err_alloc_q_vectors
;
4934 err
= ixgbe_alloc_queues(adapter
);
4936 e_dev_err("Unable to allocate memory for queues\n");
4937 goto err_alloc_queues
;
4940 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4941 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
4942 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4944 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4949 ixgbe_free_q_vectors(adapter
);
4950 err_alloc_q_vectors
:
4951 ixgbe_reset_interrupt_capability(adapter
);
4956 static void ring_free_rcu(struct rcu_head
*head
)
4958 kfree(container_of(head
, struct ixgbe_ring
, rcu
));
4962 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4963 * @adapter: board private structure to clear interrupt scheme on
4965 * We go through and clear interrupt specific resources and reset the structure
4966 * to pre-load conditions
4968 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4972 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4973 kfree(adapter
->tx_ring
[i
]);
4974 adapter
->tx_ring
[i
] = NULL
;
4976 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4977 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4979 /* ixgbe_get_stats64() might access this ring, we must wait
4980 * a grace period before freeing it.
4982 call_rcu(&ring
->rcu
, ring_free_rcu
);
4983 adapter
->rx_ring
[i
] = NULL
;
4986 ixgbe_free_q_vectors(adapter
);
4987 ixgbe_reset_interrupt_capability(adapter
);
4991 * ixgbe_sfp_timer - worker thread to find a missing module
4992 * @data: pointer to our adapter struct
4994 static void ixgbe_sfp_timer(unsigned long data
)
4996 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4999 * Do the sfp_timer outside of interrupt context due to the
5000 * delays that sfp+ detection requires
5002 schedule_work(&adapter
->sfp_task
);
5006 * ixgbe_sfp_task - worker thread to find a missing module
5007 * @work: pointer to work_struct containing our data
5009 static void ixgbe_sfp_task(struct work_struct
*work
)
5011 struct ixgbe_adapter
*adapter
= container_of(work
,
5012 struct ixgbe_adapter
,
5014 struct ixgbe_hw
*hw
= &adapter
->hw
;
5016 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
5017 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
5018 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
5019 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
5021 ret
= hw
->phy
.ops
.reset(hw
);
5022 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5023 e_dev_err("failed to initialize because an unsupported "
5024 "SFP+ module type was detected.\n");
5025 e_dev_err("Reload the driver after installing a "
5026 "supported module.\n");
5027 unregister_netdev(adapter
->netdev
);
5029 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
5031 /* don't need this routine any more */
5032 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
5036 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
5037 mod_timer(&adapter
->sfp_timer
,
5038 round_jiffies(jiffies
+ (2 * HZ
)));
5042 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5043 * @adapter: board private structure to initialize
5045 * ixgbe_sw_init initializes the Adapter private data structure.
5046 * Fields are initialized based on PCI device information and
5047 * OS network device settings (MTU size).
5049 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
5051 struct ixgbe_hw
*hw
= &adapter
->hw
;
5052 struct pci_dev
*pdev
= adapter
->pdev
;
5053 struct net_device
*dev
= adapter
->netdev
;
5055 #ifdef CONFIG_IXGBE_DCB
5057 struct tc_configuration
*tc
;
5059 int max_frame
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5061 /* PCI config space info */
5063 hw
->vendor_id
= pdev
->vendor
;
5064 hw
->device_id
= pdev
->device
;
5065 hw
->revision_id
= pdev
->revision
;
5066 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
5067 hw
->subsystem_device_id
= pdev
->subsystem_device
;
5069 /* Set capability flags */
5070 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
5071 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
5072 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
5073 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
5074 switch (hw
->mac
.type
) {
5075 case ixgbe_mac_82598EB
:
5076 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
5077 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
5078 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
5080 case ixgbe_mac_82599EB
:
5081 case ixgbe_mac_X540
:
5082 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
5083 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
5084 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
5085 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
5086 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
5087 if (dev
->features
& NETIF_F_NTUPLE
) {
5088 /* Flow Director perfect filter enabled */
5089 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
5090 adapter
->atr_sample_rate
= 0;
5091 spin_lock_init(&adapter
->fdir_perfect_lock
);
5093 /* Flow Director hash filters enabled */
5094 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
5095 adapter
->atr_sample_rate
= 20;
5097 adapter
->ring_feature
[RING_F_FDIR
].indices
=
5098 IXGBE_MAX_FDIR_INDICES
;
5099 adapter
->fdir_pballoc
= 0;
5101 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
5102 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
5103 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
5104 #ifdef CONFIG_IXGBE_DCB
5105 /* Default traffic class to use for FCoE */
5106 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
5107 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
5109 #endif /* IXGBE_FCOE */
5115 #ifdef CONFIG_IXGBE_DCB
5116 /* Configure DCB traffic classes */
5117 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
5118 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
5119 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
5120 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5121 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
5122 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5123 tc
->dcb_pfc
= pfc_disabled
;
5125 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
5126 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
5127 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
5128 adapter
->dcb_cfg
.pfc_mode_enable
= false;
5129 adapter
->dcb_cfg
.round_robin_enable
= false;
5130 adapter
->dcb_set_bitmap
= 0x00;
5131 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
5132 adapter
->ring_feature
[RING_F_DCB
].indices
);
5136 /* default flow control settings */
5137 hw
->fc
.requested_mode
= ixgbe_fc_full
;
5138 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
5140 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
5142 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5143 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5144 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
5145 hw
->fc
.send_xon
= true;
5146 hw
->fc
.disable_fc_autoneg
= false;
5148 /* enable itr by default in dynamic mode */
5149 adapter
->rx_itr_setting
= 1;
5150 adapter
->rx_eitr_param
= 20000;
5151 adapter
->tx_itr_setting
= 1;
5152 adapter
->tx_eitr_param
= 10000;
5154 /* set defaults for eitr in MegaBytes */
5155 adapter
->eitr_low
= 10;
5156 adapter
->eitr_high
= 20;
5158 /* set default ring sizes */
5159 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
5160 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
5162 /* initialize eeprom parameters */
5163 if (ixgbe_init_eeprom_params_generic(hw
)) {
5164 e_dev_err("EEPROM initialization failed\n");
5168 /* enable rx csum by default */
5169 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
5171 /* get assigned NUMA node */
5172 adapter
->node
= dev_to_node(&pdev
->dev
);
5174 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5180 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5181 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5183 * Return 0 on success, negative on failure
5185 int ixgbe_setup_tx_resources(struct ixgbe_ring
*tx_ring
)
5187 struct device
*dev
= tx_ring
->dev
;
5190 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
5191 tx_ring
->tx_buffer_info
= vzalloc_node(size
, tx_ring
->numa_node
);
5192 if (!tx_ring
->tx_buffer_info
)
5193 tx_ring
->tx_buffer_info
= vzalloc(size
);
5194 if (!tx_ring
->tx_buffer_info
)
5197 /* round up to nearest 4K */
5198 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
5199 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
5201 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
5202 &tx_ring
->dma
, GFP_KERNEL
);
5206 tx_ring
->next_to_use
= 0;
5207 tx_ring
->next_to_clean
= 0;
5208 tx_ring
->work_limit
= tx_ring
->count
;
5212 vfree(tx_ring
->tx_buffer_info
);
5213 tx_ring
->tx_buffer_info
= NULL
;
5214 dev_err(dev
, "Unable to allocate memory for the Tx descriptor ring\n");
5219 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5220 * @adapter: board private structure
5222 * If this function returns with an error, then it's possible one or
5223 * more of the rings is populated (while the rest are not). It is the
5224 * callers duty to clean those orphaned rings.
5226 * Return 0 on success, negative on failure
5228 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5232 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5233 err
= ixgbe_setup_tx_resources(adapter
->tx_ring
[i
]);
5236 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5244 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5245 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5247 * Returns 0 on success, negative on failure
5249 int ixgbe_setup_rx_resources(struct ixgbe_ring
*rx_ring
)
5251 struct device
*dev
= rx_ring
->dev
;
5254 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5255 rx_ring
->rx_buffer_info
= vzalloc_node(size
, rx_ring
->numa_node
);
5256 if (!rx_ring
->rx_buffer_info
)
5257 rx_ring
->rx_buffer_info
= vzalloc(size
);
5258 if (!rx_ring
->rx_buffer_info
)
5261 /* Round up to nearest 4K */
5262 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5263 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5265 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
5266 &rx_ring
->dma
, GFP_KERNEL
);
5271 rx_ring
->next_to_clean
= 0;
5272 rx_ring
->next_to_use
= 0;
5276 vfree(rx_ring
->rx_buffer_info
);
5277 rx_ring
->rx_buffer_info
= NULL
;
5278 dev_err(dev
, "Unable to allocate memory for the Rx descriptor ring\n");
5283 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5284 * @adapter: board private structure
5286 * If this function returns with an error, then it's possible one or
5287 * more of the rings is populated (while the rest are not). It is the
5288 * callers duty to clean those orphaned rings.
5290 * Return 0 on success, negative on failure
5292 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5296 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5297 err
= ixgbe_setup_rx_resources(adapter
->rx_ring
[i
]);
5300 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5308 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5309 * @tx_ring: Tx descriptor ring for a specific queue
5311 * Free all transmit software resources
5313 void ixgbe_free_tx_resources(struct ixgbe_ring
*tx_ring
)
5315 ixgbe_clean_tx_ring(tx_ring
);
5317 vfree(tx_ring
->tx_buffer_info
);
5318 tx_ring
->tx_buffer_info
= NULL
;
5320 /* if not set, then don't free */
5324 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
5325 tx_ring
->desc
, tx_ring
->dma
);
5327 tx_ring
->desc
= NULL
;
5331 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5332 * @adapter: board private structure
5334 * Free all transmit software resources
5336 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5340 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5341 if (adapter
->tx_ring
[i
]->desc
)
5342 ixgbe_free_tx_resources(adapter
->tx_ring
[i
]);
5346 * ixgbe_free_rx_resources - Free Rx Resources
5347 * @rx_ring: ring to clean the resources from
5349 * Free all receive software resources
5351 void ixgbe_free_rx_resources(struct ixgbe_ring
*rx_ring
)
5353 ixgbe_clean_rx_ring(rx_ring
);
5355 vfree(rx_ring
->rx_buffer_info
);
5356 rx_ring
->rx_buffer_info
= NULL
;
5358 /* if not set, then don't free */
5362 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
5363 rx_ring
->desc
, rx_ring
->dma
);
5365 rx_ring
->desc
= NULL
;
5369 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5370 * @adapter: board private structure
5372 * Free all receive software resources
5374 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5378 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5379 if (adapter
->rx_ring
[i
]->desc
)
5380 ixgbe_free_rx_resources(adapter
->rx_ring
[i
]);
5384 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5385 * @netdev: network interface device structure
5386 * @new_mtu: new value for maximum frame size
5388 * Returns 0 on success, negative on failure
5390 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5392 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5393 struct ixgbe_hw
*hw
= &adapter
->hw
;
5394 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5396 /* MTU < 68 is an error and causes problems on some kernels */
5397 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5400 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5401 /* must set new MTU before calling down or up */
5402 netdev
->mtu
= new_mtu
;
5404 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5405 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5407 if (netif_running(netdev
))
5408 ixgbe_reinit_locked(adapter
);
5414 * ixgbe_open - Called when a network interface is made active
5415 * @netdev: network interface device structure
5417 * Returns 0 on success, negative value on failure
5419 * The open entry point is called when a network interface is made
5420 * active by the system (IFF_UP). At this point all resources needed
5421 * for transmit and receive operations are allocated, the interrupt
5422 * handler is registered with the OS, the watchdog timer is started,
5423 * and the stack is notified that the interface is ready.
5425 static int ixgbe_open(struct net_device
*netdev
)
5427 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5430 /* disallow open during test */
5431 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5434 netif_carrier_off(netdev
);
5436 /* allocate transmit descriptors */
5437 err
= ixgbe_setup_all_tx_resources(adapter
);
5441 /* allocate receive descriptors */
5442 err
= ixgbe_setup_all_rx_resources(adapter
);
5446 ixgbe_configure(adapter
);
5448 err
= ixgbe_request_irq(adapter
);
5452 err
= ixgbe_up_complete(adapter
);
5456 netif_tx_start_all_queues(netdev
);
5461 ixgbe_release_hw_control(adapter
);
5462 ixgbe_free_irq(adapter
);
5465 ixgbe_free_all_rx_resources(adapter
);
5467 ixgbe_free_all_tx_resources(adapter
);
5468 ixgbe_reset(adapter
);
5474 * ixgbe_close - Disables a network interface
5475 * @netdev: network interface device structure
5477 * Returns 0, this is not allowed to fail
5479 * The close entry point is called when an interface is de-activated
5480 * by the OS. The hardware is still under the drivers control, but
5481 * needs to be disabled. A global MAC reset is issued to stop the
5482 * hardware, and all transmit and receive resources are freed.
5484 static int ixgbe_close(struct net_device
*netdev
)
5486 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5488 ixgbe_down(adapter
);
5489 ixgbe_free_irq(adapter
);
5491 ixgbe_free_all_tx_resources(adapter
);
5492 ixgbe_free_all_rx_resources(adapter
);
5494 ixgbe_release_hw_control(adapter
);
5500 static int ixgbe_resume(struct pci_dev
*pdev
)
5502 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5503 struct net_device
*netdev
= adapter
->netdev
;
5506 pci_set_power_state(pdev
, PCI_D0
);
5507 pci_restore_state(pdev
);
5509 * pci_restore_state clears dev->state_saved so call
5510 * pci_save_state to restore it.
5512 pci_save_state(pdev
);
5514 err
= pci_enable_device_mem(pdev
);
5516 e_dev_err("Cannot enable PCI device from suspend\n");
5519 pci_set_master(pdev
);
5521 pci_wake_from_d3(pdev
, false);
5523 err
= ixgbe_init_interrupt_scheme(adapter
);
5525 e_dev_err("Cannot initialize interrupts for device\n");
5529 ixgbe_reset(adapter
);
5531 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5533 if (netif_running(netdev
)) {
5534 err
= ixgbe_open(netdev
);
5539 netif_device_attach(netdev
);
5543 #endif /* CONFIG_PM */
5545 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5547 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5548 struct net_device
*netdev
= adapter
->netdev
;
5549 struct ixgbe_hw
*hw
= &adapter
->hw
;
5551 u32 wufc
= adapter
->wol
;
5556 netif_device_detach(netdev
);
5558 if (netif_running(netdev
)) {
5559 ixgbe_down(adapter
);
5560 ixgbe_free_irq(adapter
);
5561 ixgbe_free_all_tx_resources(adapter
);
5562 ixgbe_free_all_rx_resources(adapter
);
5565 ixgbe_clear_interrupt_scheme(adapter
);
5568 retval
= pci_save_state(pdev
);
5574 ixgbe_set_rx_mode(netdev
);
5576 /* turn on all-multi mode if wake on multicast is enabled */
5577 if (wufc
& IXGBE_WUFC_MC
) {
5578 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5579 fctrl
|= IXGBE_FCTRL_MPE
;
5580 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5583 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5584 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5585 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5587 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5589 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5590 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5593 switch (hw
->mac
.type
) {
5594 case ixgbe_mac_82598EB
:
5595 pci_wake_from_d3(pdev
, false);
5597 case ixgbe_mac_82599EB
:
5598 case ixgbe_mac_X540
:
5599 pci_wake_from_d3(pdev
, !!wufc
);
5605 *enable_wake
= !!wufc
;
5607 ixgbe_release_hw_control(adapter
);
5609 pci_disable_device(pdev
);
5615 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5620 retval
= __ixgbe_shutdown(pdev
, &wake
);
5625 pci_prepare_to_sleep(pdev
);
5627 pci_wake_from_d3(pdev
, false);
5628 pci_set_power_state(pdev
, PCI_D3hot
);
5633 #endif /* CONFIG_PM */
5635 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5639 __ixgbe_shutdown(pdev
, &wake
);
5641 if (system_state
== SYSTEM_POWER_OFF
) {
5642 pci_wake_from_d3(pdev
, wake
);
5643 pci_set_power_state(pdev
, PCI_D3hot
);
5648 * ixgbe_update_stats - Update the board statistics counters.
5649 * @adapter: board private structure
5651 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5653 struct net_device
*netdev
= adapter
->netdev
;
5654 struct ixgbe_hw
*hw
= &adapter
->hw
;
5655 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5657 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5658 u64 non_eop_descs
= 0, restart_queue
= 0, tx_busy
= 0;
5659 u64 alloc_rx_page_failed
= 0, alloc_rx_buff_failed
= 0;
5660 u64 bytes
= 0, packets
= 0;
5662 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5663 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5666 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5669 for (i
= 0; i
< 16; i
++)
5670 adapter
->hw_rx_no_dma_resources
+=
5671 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5672 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5673 rsc_count
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_count
;
5674 rsc_flush
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_flush
;
5676 adapter
->rsc_total_count
= rsc_count
;
5677 adapter
->rsc_total_flush
= rsc_flush
;
5680 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5681 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[i
];
5682 non_eop_descs
+= rx_ring
->rx_stats
.non_eop_descs
;
5683 alloc_rx_page_failed
+= rx_ring
->rx_stats
.alloc_rx_page_failed
;
5684 alloc_rx_buff_failed
+= rx_ring
->rx_stats
.alloc_rx_buff_failed
;
5685 bytes
+= rx_ring
->stats
.bytes
;
5686 packets
+= rx_ring
->stats
.packets
;
5688 adapter
->non_eop_descs
= non_eop_descs
;
5689 adapter
->alloc_rx_page_failed
= alloc_rx_page_failed
;
5690 adapter
->alloc_rx_buff_failed
= alloc_rx_buff_failed
;
5691 netdev
->stats
.rx_bytes
= bytes
;
5692 netdev
->stats
.rx_packets
= packets
;
5696 /* gather some stats to the adapter struct that are per queue */
5697 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5698 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5699 restart_queue
+= tx_ring
->tx_stats
.restart_queue
;
5700 tx_busy
+= tx_ring
->tx_stats
.tx_busy
;
5701 bytes
+= tx_ring
->stats
.bytes
;
5702 packets
+= tx_ring
->stats
.packets
;
5704 adapter
->restart_queue
= restart_queue
;
5705 adapter
->tx_busy
= tx_busy
;
5706 netdev
->stats
.tx_bytes
= bytes
;
5707 netdev
->stats
.tx_packets
= packets
;
5709 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5710 for (i
= 0; i
< 8; i
++) {
5711 /* for packet buffers not used, the register should read 0 */
5712 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5714 hwstats
->mpc
[i
] += mpc
;
5715 total_mpc
+= hwstats
->mpc
[i
];
5716 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5717 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5718 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5719 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5720 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5721 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5722 switch (hw
->mac
.type
) {
5723 case ixgbe_mac_82598EB
:
5724 hwstats
->pxonrxc
[i
] +=
5725 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5727 case ixgbe_mac_82599EB
:
5728 case ixgbe_mac_X540
:
5729 hwstats
->pxonrxc
[i
] +=
5730 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5735 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5736 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5738 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5739 /* work around hardware counting issue */
5740 hwstats
->gprc
-= missed_rx
;
5742 ixgbe_update_xoff_received(adapter
);
5744 /* 82598 hardware only has a 32 bit counter in the high register */
5745 switch (hw
->mac
.type
) {
5746 case ixgbe_mac_82598EB
:
5747 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5748 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5749 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5750 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5752 case ixgbe_mac_82599EB
:
5753 case ixgbe_mac_X540
:
5754 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5755 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
5756 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5757 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
5758 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5759 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5760 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5761 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5762 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5764 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5765 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5766 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5767 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5768 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5769 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5770 #endif /* IXGBE_FCOE */
5775 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5776 hwstats
->bprc
+= bprc
;
5777 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5778 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5779 hwstats
->mprc
-= bprc
;
5780 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5781 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5782 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5783 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5784 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5785 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5786 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5787 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5788 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5789 hwstats
->lxontxc
+= lxon
;
5790 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5791 hwstats
->lxofftxc
+= lxoff
;
5792 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5793 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5794 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5796 * 82598 errata - tx of flow control packets is included in tx counters
5798 xon_off_tot
= lxon
+ lxoff
;
5799 hwstats
->gptc
-= xon_off_tot
;
5800 hwstats
->mptc
-= xon_off_tot
;
5801 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5802 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5803 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5804 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5805 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5806 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5807 hwstats
->ptc64
-= xon_off_tot
;
5808 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5809 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5810 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5811 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5812 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5813 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5815 /* Fill out the OS statistics structure */
5816 netdev
->stats
.multicast
= hwstats
->mprc
;
5819 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5820 netdev
->stats
.rx_dropped
= 0;
5821 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5822 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5823 netdev
->stats
.rx_missed_errors
= total_mpc
;
5827 * ixgbe_watchdog - Timer Call-back
5828 * @data: pointer to adapter cast into an unsigned long
5830 static void ixgbe_watchdog(unsigned long data
)
5832 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5833 struct ixgbe_hw
*hw
= &adapter
->hw
;
5838 * Do the watchdog outside of interrupt context due to the lovely
5839 * delays that some of the newer hardware requires
5842 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5843 goto watchdog_short_circuit
;
5845 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5847 * for legacy and MSI interrupts don't set any bits
5848 * that are enabled for EIAM, because this operation
5849 * would set *both* EIMS and EICS for any bit in EIAM
5851 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5852 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5853 goto watchdog_reschedule
;
5856 /* get one bit for every active tx/rx interrupt vector */
5857 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5858 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5859 if (qv
->rxr_count
|| qv
->txr_count
)
5860 eics
|= ((u64
)1 << i
);
5863 /* Cause software interrupt to ensure rx rings are cleaned */
5864 ixgbe_irq_rearm_queues(adapter
, eics
);
5866 watchdog_reschedule
:
5867 /* Reset the timer */
5868 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5870 watchdog_short_circuit
:
5871 schedule_work(&adapter
->watchdog_task
);
5875 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5876 * @work: pointer to work_struct containing our data
5878 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5880 struct ixgbe_adapter
*adapter
= container_of(work
,
5881 struct ixgbe_adapter
,
5882 multispeed_fiber_task
);
5883 struct ixgbe_hw
*hw
= &adapter
->hw
;
5887 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5888 autoneg
= hw
->phy
.autoneg_advertised
;
5889 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5890 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5891 hw
->mac
.autotry_restart
= false;
5892 if (hw
->mac
.ops
.setup_link
)
5893 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5894 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5895 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5899 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5900 * @work: pointer to work_struct containing our data
5902 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5904 struct ixgbe_adapter
*adapter
= container_of(work
,
5905 struct ixgbe_adapter
,
5906 sfp_config_module_task
);
5907 struct ixgbe_hw
*hw
= &adapter
->hw
;
5910 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5912 /* Time for electrical oscillations to settle down */
5914 err
= hw
->phy
.ops
.identify_sfp(hw
);
5916 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5917 e_dev_err("failed to initialize because an unsupported SFP+ "
5918 "module type was detected.\n");
5919 e_dev_err("Reload the driver after installing a supported "
5921 unregister_netdev(adapter
->netdev
);
5924 hw
->mac
.ops
.setup_sfp(hw
);
5926 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5927 /* This will also work for DA Twinax connections */
5928 schedule_work(&adapter
->multispeed_fiber_task
);
5929 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5933 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5934 * @work: pointer to work_struct containing our data
5936 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5938 struct ixgbe_adapter
*adapter
= container_of(work
,
5939 struct ixgbe_adapter
,
5941 struct ixgbe_hw
*hw
= &adapter
->hw
;
5944 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5945 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5946 set_bit(__IXGBE_TX_FDIR_INIT_DONE
,
5947 &(adapter
->tx_ring
[i
]->state
));
5949 e_err(probe
, "failed to finish FDIR re-initialization, "
5950 "ignored adding FDIR ATR filters\n");
5952 /* Done FDIR Re-initialization, enable transmits */
5953 netif_tx_start_all_queues(adapter
->netdev
);
5956 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5959 * ixgbe_watchdog_task - worker thread to bring link up
5960 * @work: pointer to work_struct containing our data
5962 static void ixgbe_watchdog_task(struct work_struct
*work
)
5964 struct ixgbe_adapter
*adapter
= container_of(work
,
5965 struct ixgbe_adapter
,
5967 struct net_device
*netdev
= adapter
->netdev
;
5968 struct ixgbe_hw
*hw
= &adapter
->hw
;
5972 struct ixgbe_ring
*tx_ring
;
5973 int some_tx_pending
= 0;
5975 mutex_lock(&ixgbe_watchdog_lock
);
5977 link_up
= adapter
->link_up
;
5978 link_speed
= adapter
->link_speed
;
5980 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5981 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5984 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5985 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5986 hw
->mac
.ops
.fc_enable(hw
, i
);
5988 hw
->mac
.ops
.fc_enable(hw
, 0);
5991 hw
->mac
.ops
.fc_enable(hw
, 0);
5996 time_after(jiffies
, (adapter
->link_check_timeout
+
5997 IXGBE_TRY_LINK_TIMEOUT
))) {
5998 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5999 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
6001 adapter
->link_up
= link_up
;
6002 adapter
->link_speed
= link_speed
;
6006 if (!netif_carrier_ok(netdev
)) {
6007 bool flow_rx
, flow_tx
;
6009 switch (hw
->mac
.type
) {
6010 case ixgbe_mac_82598EB
: {
6011 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
6012 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
6013 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
6014 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
6017 case ixgbe_mac_82599EB
:
6018 case ixgbe_mac_X540
: {
6019 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
6020 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
6021 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
6022 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
6031 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
6032 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
6034 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
6035 "1 Gbps" : "unknown speed")),
6036 ((flow_rx
&& flow_tx
) ? "RX/TX" :
6038 (flow_tx
? "TX" : "None"))));
6040 netif_carrier_on(netdev
);
6042 /* Force detection of hung controller */
6043 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6044 tx_ring
= adapter
->tx_ring
[i
];
6045 set_check_for_tx_hang(tx_ring
);
6049 adapter
->link_up
= false;
6050 adapter
->link_speed
= 0;
6051 if (netif_carrier_ok(netdev
)) {
6052 e_info(drv
, "NIC Link is Down\n");
6053 netif_carrier_off(netdev
);
6057 if (!netif_carrier_ok(netdev
)) {
6058 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6059 tx_ring
= adapter
->tx_ring
[i
];
6060 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
6061 some_tx_pending
= 1;
6066 if (some_tx_pending
) {
6067 /* We've lost link, so the controller stops DMA,
6068 * but we've got queued Tx work that's never going
6069 * to get done, so reset controller to flush Tx.
6070 * (Do the reset outside of interrupt context).
6072 schedule_work(&adapter
->reset_task
);
6076 ixgbe_update_stats(adapter
);
6077 mutex_unlock(&ixgbe_watchdog_lock
);
6080 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
6081 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
6082 u32 tx_flags
, u8
*hdr_len
, __be16 protocol
)
6084 struct ixgbe_adv_tx_context_desc
*context_desc
;
6087 struct ixgbe_tx_buffer
*tx_buffer_info
;
6088 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
6089 u32 mss_l4len_idx
, l4len
;
6091 if (skb_is_gso(skb
)) {
6092 if (skb_header_cloned(skb
)) {
6093 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
6097 l4len
= tcp_hdrlen(skb
);
6100 if (protocol
== htons(ETH_P_IP
)) {
6101 struct iphdr
*iph
= ip_hdr(skb
);
6104 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6108 } else if (skb_is_gso_v6(skb
)) {
6109 ipv6_hdr(skb
)->payload_len
= 0;
6110 tcp_hdr(skb
)->check
=
6111 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
6112 &ipv6_hdr(skb
)->daddr
,
6116 i
= tx_ring
->next_to_use
;
6118 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6119 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6121 /* VLAN MACLEN IPLEN */
6122 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6124 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6125 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
6126 IXGBE_ADVTXD_MACLEN_SHIFT
);
6127 *hdr_len
+= skb_network_offset(skb
);
6129 (skb_transport_header(skb
) - skb_network_header(skb
));
6131 (skb_transport_header(skb
) - skb_network_header(skb
));
6132 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6133 context_desc
->seqnum_seed
= 0;
6135 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6136 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
6137 IXGBE_ADVTXD_DTYP_CTXT
);
6139 if (protocol
== htons(ETH_P_IP
))
6140 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6141 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6142 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6146 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
6147 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
6148 /* use index 1 for TSO */
6149 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6150 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
6152 tx_buffer_info
->time_stamp
= jiffies
;
6153 tx_buffer_info
->next_to_watch
= i
;
6156 if (i
== tx_ring
->count
)
6158 tx_ring
->next_to_use
= i
;
6165 static u32
ixgbe_psum(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6171 case cpu_to_be16(ETH_P_IP
):
6172 rtn
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6173 switch (ip_hdr(skb
)->protocol
) {
6175 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6178 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6182 case cpu_to_be16(ETH_P_IPV6
):
6183 /* XXX what about other V6 headers?? */
6184 switch (ipv6_hdr(skb
)->nexthdr
) {
6186 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6189 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6194 if (unlikely(net_ratelimit()))
6195 e_warn(probe
, "partial checksum but proto=%x!\n",
6203 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
6204 struct ixgbe_ring
*tx_ring
,
6205 struct sk_buff
*skb
, u32 tx_flags
,
6208 struct ixgbe_adv_tx_context_desc
*context_desc
;
6210 struct ixgbe_tx_buffer
*tx_buffer_info
;
6211 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
6213 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
6214 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
6215 i
= tx_ring
->next_to_use
;
6216 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6217 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6219 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6221 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6222 vlan_macip_lens
|= (skb_network_offset(skb
) <<
6223 IXGBE_ADVTXD_MACLEN_SHIFT
);
6224 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6225 vlan_macip_lens
|= (skb_transport_header(skb
) -
6226 skb_network_header(skb
));
6228 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6229 context_desc
->seqnum_seed
= 0;
6231 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
6232 IXGBE_ADVTXD_DTYP_CTXT
);
6234 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6235 type_tucmd_mlhl
|= ixgbe_psum(adapter
, skb
, protocol
);
6237 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6238 /* use index zero for tx checksum offload */
6239 context_desc
->mss_l4len_idx
= 0;
6241 tx_buffer_info
->time_stamp
= jiffies
;
6242 tx_buffer_info
->next_to_watch
= i
;
6245 if (i
== tx_ring
->count
)
6247 tx_ring
->next_to_use
= i
;
6255 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
6256 struct ixgbe_ring
*tx_ring
,
6257 struct sk_buff
*skb
, u32 tx_flags
,
6258 unsigned int first
, const u8 hdr_len
)
6260 struct device
*dev
= tx_ring
->dev
;
6261 struct ixgbe_tx_buffer
*tx_buffer_info
;
6263 unsigned int total
= skb
->len
;
6264 unsigned int offset
= 0, size
, count
= 0, i
;
6265 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
6267 unsigned int bytecount
= skb
->len
;
6270 i
= tx_ring
->next_to_use
;
6272 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6273 /* excluding fcoe_crc_eof for FCoE */
6274 total
-= sizeof(struct fcoe_crc_eof
);
6276 len
= min(skb_headlen(skb
), total
);
6278 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6279 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6281 tx_buffer_info
->length
= size
;
6282 tx_buffer_info
->mapped_as_page
= false;
6283 tx_buffer_info
->dma
= dma_map_single(dev
,
6285 size
, DMA_TO_DEVICE
);
6286 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6288 tx_buffer_info
->time_stamp
= jiffies
;
6289 tx_buffer_info
->next_to_watch
= i
;
6298 if (i
== tx_ring
->count
)
6303 for (f
= 0; f
< nr_frags
; f
++) {
6304 struct skb_frag_struct
*frag
;
6306 frag
= &skb_shinfo(skb
)->frags
[f
];
6307 len
= min((unsigned int)frag
->size
, total
);
6308 offset
= frag
->page_offset
;
6312 if (i
== tx_ring
->count
)
6315 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6316 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6318 tx_buffer_info
->length
= size
;
6319 tx_buffer_info
->dma
= dma_map_page(dev
,
6323 tx_buffer_info
->mapped_as_page
= true;
6324 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6326 tx_buffer_info
->time_stamp
= jiffies
;
6327 tx_buffer_info
->next_to_watch
= i
;
6338 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6339 gso_segs
= skb_shinfo(skb
)->gso_segs
;
6341 /* adjust for FCoE Sequence Offload */
6342 else if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6343 gso_segs
= DIV_ROUND_UP(skb
->len
- hdr_len
,
6344 skb_shinfo(skb
)->gso_size
);
6345 #endif /* IXGBE_FCOE */
6346 bytecount
+= (gso_segs
- 1) * hdr_len
;
6348 /* multiply data chunks by size of headers */
6349 tx_ring
->tx_buffer_info
[i
].bytecount
= bytecount
;
6350 tx_ring
->tx_buffer_info
[i
].gso_segs
= gso_segs
;
6351 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6352 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6357 e_dev_err("TX DMA map failed\n");
6359 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6360 tx_buffer_info
->dma
= 0;
6361 tx_buffer_info
->time_stamp
= 0;
6362 tx_buffer_info
->next_to_watch
= 0;
6366 /* clear timestamp and dma mappings for remaining portion of packet */
6369 i
+= tx_ring
->count
;
6371 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6372 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
6378 static void ixgbe_tx_queue(struct ixgbe_ring
*tx_ring
,
6379 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6381 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6382 struct ixgbe_tx_buffer
*tx_buffer_info
;
6383 u32 olinfo_status
= 0, cmd_type_len
= 0;
6385 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6387 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6389 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6391 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6392 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6394 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6395 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6397 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6398 IXGBE_ADVTXD_POPTS_SHIFT
;
6400 /* use index 1 context for tso */
6401 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6402 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6403 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6404 IXGBE_ADVTXD_POPTS_SHIFT
;
6406 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6407 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6408 IXGBE_ADVTXD_POPTS_SHIFT
;
6410 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6411 olinfo_status
|= IXGBE_ADVTXD_CC
;
6412 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6413 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6414 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6417 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6419 i
= tx_ring
->next_to_use
;
6421 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6422 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6423 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6424 tx_desc
->read
.cmd_type_len
=
6425 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6426 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6428 if (i
== tx_ring
->count
)
6432 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6435 * Force memory writes to complete before letting h/w
6436 * know there are new descriptors to fetch. (Only
6437 * applicable for weak-ordered memory model archs,
6442 tx_ring
->next_to_use
= i
;
6443 writel(i
, tx_ring
->tail
);
6446 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6447 u8 queue
, u32 tx_flags
, __be16 protocol
)
6449 struct ixgbe_atr_input atr_input
;
6450 struct iphdr
*iph
= ip_hdr(skb
);
6451 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
6455 /* Right now, we support IPv4 w/ TCP only */
6456 if (protocol
!= htons(ETH_P_IP
) ||
6457 iph
->protocol
!= IPPROTO_TCP
)
6460 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
6462 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
6463 IXGBE_TX_FLAGS_VLAN_SHIFT
;
6467 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
6468 ixgbe_atr_set_src_port_82599(&atr_input
, th
->dest
);
6469 ixgbe_atr_set_dst_port_82599(&atr_input
, th
->source
);
6470 ixgbe_atr_set_flex_byte_82599(&atr_input
, eth
->h_proto
);
6471 ixgbe_atr_set_l4type_82599(&atr_input
, IXGBE_ATR_L4TYPE_TCP
);
6472 /* src and dst are inverted, think how the receiver sees them */
6473 ixgbe_atr_set_src_ipv4_82599(&atr_input
, iph
->daddr
);
6474 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, iph
->saddr
);
6476 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6477 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
6480 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6482 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6483 /* Herbert's original patch had:
6484 * smp_mb__after_netif_stop_queue();
6485 * but since that doesn't exist yet, just open code it. */
6488 /* We need to check again in a case another CPU has just
6489 * made room available. */
6490 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6493 /* A reprieve! - use start_queue because it doesn't call schedule */
6494 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6495 ++tx_ring
->tx_stats
.restart_queue
;
6499 static int ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6501 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6503 return __ixgbe_maybe_stop_tx(tx_ring
, size
);
6506 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6508 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6509 int txq
= smp_processor_id();
6513 protocol
= vlan_get_protocol(skb
);
6515 if ((protocol
== htons(ETH_P_FCOE
)) ||
6516 (protocol
== htons(ETH_P_FIP
))) {
6517 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
6518 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6519 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6521 #ifdef CONFIG_IXGBE_DCB
6522 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6523 txq
= adapter
->fcoe
.up
;
6530 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6531 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6532 txq
-= dev
->real_num_tx_queues
;
6536 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6537 if (skb
->priority
== TC_PRIO_CONTROL
)
6538 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
6540 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
6545 return skb_tx_hash(dev
, skb
);
6548 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
,
6549 struct ixgbe_adapter
*adapter
,
6550 struct ixgbe_ring
*tx_ring
)
6552 struct net_device
*netdev
= tx_ring
->netdev
;
6553 struct netdev_queue
*txq
;
6555 unsigned int tx_flags
= 0;
6562 protocol
= vlan_get_protocol(skb
);
6564 if (vlan_tx_tag_present(skb
)) {
6565 tx_flags
|= vlan_tx_tag_get(skb
);
6566 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6567 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6568 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6570 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6571 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6572 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6573 skb
->priority
!= TC_PRIO_CONTROL
) {
6574 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6575 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6576 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6580 /* for FCoE with DCB, we force the priority to what
6581 * was specified by the switch */
6582 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6583 (protocol
== htons(ETH_P_FCOE
) ||
6584 protocol
== htons(ETH_P_FIP
))) {
6585 #ifdef CONFIG_IXGBE_DCB
6586 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6587 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6588 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6589 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
6590 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6593 /* flag for FCoE offloads */
6594 if (protocol
== htons(ETH_P_FCOE
))
6595 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6599 /* four things can cause us to need a context descriptor */
6600 if (skb_is_gso(skb
) ||
6601 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6602 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6603 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6606 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6607 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6608 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6610 if (ixgbe_maybe_stop_tx(tx_ring
, count
)) {
6611 tx_ring
->tx_stats
.tx_busy
++;
6612 return NETDEV_TX_BUSY
;
6615 first
= tx_ring
->next_to_use
;
6616 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6618 /* setup tx offload for FCoE */
6619 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6621 dev_kfree_skb_any(skb
);
6622 return NETDEV_TX_OK
;
6625 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6626 #endif /* IXGBE_FCOE */
6628 if (protocol
== htons(ETH_P_IP
))
6629 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6630 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
,
6633 dev_kfree_skb_any(skb
);
6634 return NETDEV_TX_OK
;
6638 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6639 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
,
6641 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6642 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6645 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
, hdr_len
);
6647 /* add the ATR filter if ATR is on */
6648 if (tx_ring
->atr_sample_rate
) {
6649 ++tx_ring
->atr_count
;
6650 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
6651 test_bit(__IXGBE_TX_FDIR_INIT_DONE
,
6653 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
6654 tx_flags
, protocol
);
6655 tx_ring
->atr_count
= 0;
6658 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
6659 txq
->tx_bytes
+= skb
->len
;
6661 ixgbe_tx_queue(tx_ring
, tx_flags
, count
, skb
->len
, hdr_len
);
6662 ixgbe_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
6665 dev_kfree_skb_any(skb
);
6666 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6667 tx_ring
->next_to_use
= first
;
6670 return NETDEV_TX_OK
;
6673 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6675 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6676 struct ixgbe_ring
*tx_ring
;
6678 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6679 return ixgbe_xmit_frame_ring(skb
, adapter
, tx_ring
);
6683 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6684 * @netdev: network interface device structure
6685 * @p: pointer to an address structure
6687 * Returns 0 on success, negative on failure
6689 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6691 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6692 struct ixgbe_hw
*hw
= &adapter
->hw
;
6693 struct sockaddr
*addr
= p
;
6695 if (!is_valid_ether_addr(addr
->sa_data
))
6696 return -EADDRNOTAVAIL
;
6698 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6699 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6701 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6708 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6710 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6711 struct ixgbe_hw
*hw
= &adapter
->hw
;
6715 if (prtad
!= hw
->phy
.mdio
.prtad
)
6717 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6723 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6724 u16 addr
, u16 value
)
6726 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6727 struct ixgbe_hw
*hw
= &adapter
->hw
;
6729 if (prtad
!= hw
->phy
.mdio
.prtad
)
6731 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6734 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6736 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6738 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6742 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6744 * @netdev: network interface device structure
6746 * Returns non-zero on failure
6748 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6751 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6752 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6754 if (is_valid_ether_addr(mac
->san_addr
)) {
6756 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6763 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6765 * @netdev: network interface device structure
6767 * Returns non-zero on failure
6769 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6772 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6773 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6775 if (is_valid_ether_addr(mac
->san_addr
)) {
6777 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6783 #ifdef CONFIG_NET_POLL_CONTROLLER
6785 * Polling 'interrupt' - used by things like netconsole to send skbs
6786 * without having to re-enable interrupts. It's not called while
6787 * the interrupt routine is executing.
6789 static void ixgbe_netpoll(struct net_device
*netdev
)
6791 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6794 /* if interface is down do nothing */
6795 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6798 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6799 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6800 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6801 for (i
= 0; i
< num_q_vectors
; i
++) {
6802 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6803 ixgbe_msix_clean_many(0, q_vector
);
6806 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6808 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6812 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
6813 struct rtnl_link_stats64
*stats
)
6815 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6818 /* accurate rx/tx bytes/packets stats */
6819 dev_txq_stats_fold(netdev
, stats
);
6821 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
6822 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->rx_ring
[i
]);
6828 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
6829 packets
= ring
->stats
.packets
;
6830 bytes
= ring
->stats
.bytes
;
6831 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
6832 stats
->rx_packets
+= packets
;
6833 stats
->rx_bytes
+= bytes
;
6837 /* following stats updated by ixgbe_watchdog_task() */
6838 stats
->multicast
= netdev
->stats
.multicast
;
6839 stats
->rx_errors
= netdev
->stats
.rx_errors
;
6840 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
6841 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
6842 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
6847 static const struct net_device_ops ixgbe_netdev_ops
= {
6848 .ndo_open
= ixgbe_open
,
6849 .ndo_stop
= ixgbe_close
,
6850 .ndo_start_xmit
= ixgbe_xmit_frame
,
6851 .ndo_select_queue
= ixgbe_select_queue
,
6852 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
6853 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
6854 .ndo_validate_addr
= eth_validate_addr
,
6855 .ndo_set_mac_address
= ixgbe_set_mac
,
6856 .ndo_change_mtu
= ixgbe_change_mtu
,
6857 .ndo_tx_timeout
= ixgbe_tx_timeout
,
6858 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
6859 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
6860 .ndo_do_ioctl
= ixgbe_ioctl
,
6861 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
6862 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
6863 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
6864 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
6865 .ndo_get_stats64
= ixgbe_get_stats64
,
6866 #ifdef CONFIG_NET_POLL_CONTROLLER
6867 .ndo_poll_controller
= ixgbe_netpoll
,
6870 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
6871 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
6872 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
6873 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
6874 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
6875 #endif /* IXGBE_FCOE */
6878 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
6879 const struct ixgbe_info
*ii
)
6881 #ifdef CONFIG_PCI_IOV
6882 struct ixgbe_hw
*hw
= &adapter
->hw
;
6885 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
6888 /* The 82599 supports up to 64 VFs per physical function
6889 * but this implementation limits allocation to 63 so that
6890 * basic networking resources are still available to the
6893 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
6894 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
6895 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
6897 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
6900 /* If call to enable VFs succeeded then allocate memory
6901 * for per VF control structures.
6904 kcalloc(adapter
->num_vfs
,
6905 sizeof(struct vf_data_storage
), GFP_KERNEL
);
6906 if (adapter
->vfinfo
) {
6907 /* Now that we're sure SR-IOV is enabled
6908 * and memory allocated set up the mailbox parameters
6910 ixgbe_init_mbx_params_pf(hw
);
6911 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
6912 sizeof(hw
->mbx
.ops
));
6914 /* Disable RSC when in SR-IOV mode */
6915 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
6916 IXGBE_FLAG2_RSC_ENABLED
);
6921 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
6922 "SRIOV disabled\n");
6923 pci_disable_sriov(adapter
->pdev
);
6926 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6927 adapter
->num_vfs
= 0;
6928 #endif /* CONFIG_PCI_IOV */
6932 * ixgbe_probe - Device Initialization Routine
6933 * @pdev: PCI device information struct
6934 * @ent: entry in ixgbe_pci_tbl
6936 * Returns 0 on success, negative on failure
6938 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6939 * The OS initialization, configuring of the adapter private structure,
6940 * and a hardware reset occur.
6942 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6943 const struct pci_device_id
*ent
)
6945 struct net_device
*netdev
;
6946 struct ixgbe_adapter
*adapter
= NULL
;
6947 struct ixgbe_hw
*hw
;
6948 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6949 static int cards_found
;
6950 int i
, err
, pci_using_dac
;
6951 unsigned int indices
= num_possible_cpus();
6957 /* Catch broken hardware that put the wrong VF device ID in
6958 * the PCIe SR-IOV capability.
6960 if (pdev
->is_virtfn
) {
6961 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
6962 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
6966 err
= pci_enable_device_mem(pdev
);
6970 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
6971 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
6974 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
6976 err
= dma_set_coherent_mask(&pdev
->dev
,
6980 "No usable DMA configuration, aborting\n");
6987 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6988 IORESOURCE_MEM
), ixgbe_driver_name
);
6991 "pci_request_selected_regions failed 0x%x\n", err
);
6995 pci_enable_pcie_error_reporting(pdev
);
6997 pci_set_master(pdev
);
6998 pci_save_state(pdev
);
7000 if (ii
->mac
== ixgbe_mac_82598EB
)
7001 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
7003 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
7005 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
7007 indices
+= min_t(unsigned int, num_possible_cpus(),
7008 IXGBE_MAX_FCOE_INDICES
);
7010 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
7013 goto err_alloc_etherdev
;
7016 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
7018 adapter
= netdev_priv(netdev
);
7019 pci_set_drvdata(pdev
, adapter
);
7021 adapter
->netdev
= netdev
;
7022 adapter
->pdev
= pdev
;
7025 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
7027 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
7028 pci_resource_len(pdev
, 0));
7034 for (i
= 1; i
<= 5; i
++) {
7035 if (pci_resource_len(pdev
, i
) == 0)
7039 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
7040 ixgbe_set_ethtool_ops(netdev
);
7041 netdev
->watchdog_timeo
= 5 * HZ
;
7042 strcpy(netdev
->name
, pci_name(pdev
));
7044 adapter
->bd_number
= cards_found
;
7047 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
7048 hw
->mac
.type
= ii
->mac
;
7051 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
7052 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
7053 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7054 if (!(eec
& (1 << 8)))
7055 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
7058 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
7059 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
7060 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7061 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
7062 hw
->phy
.mdio
.mmds
= 0;
7063 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
7064 hw
->phy
.mdio
.dev
= netdev
;
7065 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
7066 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
7068 /* set up this timer and work struct before calling get_invariants
7069 * which might start the timer
7071 init_timer(&adapter
->sfp_timer
);
7072 adapter
->sfp_timer
.function
= ixgbe_sfp_timer
;
7073 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
7075 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
7077 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
7078 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
7080 /* a new SFP+ module arrival, called from GPI SDP2 context */
7081 INIT_WORK(&adapter
->sfp_config_module_task
,
7082 ixgbe_sfp_config_module_task
);
7084 ii
->get_invariants(hw
);
7086 /* setup the private structure */
7087 err
= ixgbe_sw_init(adapter
);
7091 /* Make it possible the adapter to be woken up via WOL */
7092 switch (adapter
->hw
.mac
.type
) {
7093 case ixgbe_mac_82599EB
:
7094 case ixgbe_mac_X540
:
7095 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7102 * If there is a fan on this device and it has failed log the
7105 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
7106 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
7107 if (esdp
& IXGBE_ESDP_SDP1
)
7108 e_crit(probe
, "Fan has stopped, replace the adapter\n");
7111 /* reset_hw fills in the perm_addr as well */
7112 hw
->phy
.reset_if_overtemp
= true;
7113 err
= hw
->mac
.ops
.reset_hw(hw
);
7114 hw
->phy
.reset_if_overtemp
= false;
7115 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
7116 hw
->mac
.type
== ixgbe_mac_82598EB
) {
7118 * Start a kernel thread to watch for a module to arrive.
7119 * Only do this for 82598, since 82599 will generate
7120 * interrupts on module arrival.
7122 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7123 mod_timer(&adapter
->sfp_timer
,
7124 round_jiffies(jiffies
+ (2 * HZ
)));
7126 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
7127 e_dev_err("failed to initialize because an unsupported SFP+ "
7128 "module type was detected.\n");
7129 e_dev_err("Reload the driver after installing a supported "
7133 e_dev_err("HW Init failed: %d\n", err
);
7137 ixgbe_probe_vf(adapter
, ii
);
7139 netdev
->features
= NETIF_F_SG
|
7141 NETIF_F_HW_VLAN_TX
|
7142 NETIF_F_HW_VLAN_RX
|
7143 NETIF_F_HW_VLAN_FILTER
;
7145 netdev
->features
|= NETIF_F_IPV6_CSUM
;
7146 netdev
->features
|= NETIF_F_TSO
;
7147 netdev
->features
|= NETIF_F_TSO6
;
7148 netdev
->features
|= NETIF_F_GRO
;
7150 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
7151 netdev
->features
|= NETIF_F_SCTP_CSUM
;
7153 netdev
->vlan_features
|= NETIF_F_TSO
;
7154 netdev
->vlan_features
|= NETIF_F_TSO6
;
7155 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
7156 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
7157 netdev
->vlan_features
|= NETIF_F_SG
;
7159 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7160 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
7161 IXGBE_FLAG_DCB_ENABLED
);
7162 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
7163 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
7165 #ifdef CONFIG_IXGBE_DCB
7166 netdev
->dcbnl_ops
= &dcbnl_ops
;
7170 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7171 if (hw
->mac
.ops
.get_device_caps
) {
7172 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
7173 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
7174 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
7177 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7178 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
7179 netdev
->vlan_features
|= NETIF_F_FSO
;
7180 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
7182 #endif /* IXGBE_FCOE */
7183 if (pci_using_dac
) {
7184 netdev
->features
|= NETIF_F_HIGHDMA
;
7185 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
7188 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
7189 netdev
->features
|= NETIF_F_LRO
;
7191 /* make sure the EEPROM is good */
7192 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
7193 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7198 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7199 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7201 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
7202 e_dev_err("invalid MAC address\n");
7207 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7208 if (hw
->mac
.ops
.disable_tx_laser
&&
7209 ((hw
->phy
.multispeed_fiber
) ||
7210 ((hw
->phy
.type
== ixgbe_media_type_fiber
) &&
7211 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
7212 hw
->mac
.ops
.disable_tx_laser(hw
);
7214 init_timer(&adapter
->watchdog_timer
);
7215 adapter
->watchdog_timer
.function
= ixgbe_watchdog
;
7216 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
7218 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
7219 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
7221 err
= ixgbe_init_interrupt_scheme(adapter
);
7225 switch (pdev
->device
) {
7226 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
7227 /* All except this subdevice support WOL */
7228 if (pdev
->subsystem_device
==
7229 IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
) {
7233 case IXGBE_DEV_ID_82599_KX4
:
7234 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7235 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7241 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
7243 /* pick up the PCI bus settings for reporting later */
7244 hw
->mac
.ops
.get_bus_info(hw
);
7246 /* print bus type/speed/width info */
7247 e_dev_info("(PCI Express:%s:%s) %pM\n",
7248 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0Gb/s" :
7249 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5Gb/s" :
7251 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
7252 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
7253 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
7256 ixgbe_read_pba_num_generic(hw
, &part_num
);
7257 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
7258 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
7259 "PBA No: %06x-%03x\n",
7260 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
7261 (part_num
>> 8), (part_num
& 0xff));
7263 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
7264 hw
->mac
.type
, hw
->phy
.type
,
7265 (part_num
>> 8), (part_num
& 0xff));
7267 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
7268 e_dev_warn("PCI-Express bandwidth available for this card is "
7269 "not sufficient for optimal performance.\n");
7270 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7274 /* save off EEPROM version number */
7275 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
7277 /* reset the hardware with the new settings */
7278 err
= hw
->mac
.ops
.start_hw(hw
);
7280 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7281 /* We are running on a pre-production device, log a warning */
7282 e_dev_warn("This device is a pre-production adapter/LOM. "
7283 "Please be aware there may be issues associated "
7284 "with your hardware. If you are experiencing "
7285 "problems please contact your Intel or hardware "
7286 "representative who provided you with this "
7289 strcpy(netdev
->name
, "eth%d");
7290 err
= register_netdev(netdev
);
7294 /* carrier off reporting is important to ethtool even BEFORE open */
7295 netif_carrier_off(netdev
);
7297 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7298 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7299 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
7301 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
7302 INIT_WORK(&adapter
->check_overtemp_task
,
7303 ixgbe_check_overtemp_task
);
7304 #ifdef CONFIG_IXGBE_DCA
7305 if (dca_add_requester(&pdev
->dev
) == 0) {
7306 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7307 ixgbe_setup_dca(adapter
);
7310 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7311 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7312 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7313 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7316 /* add san mac addr to netdev */
7317 ixgbe_add_sanmac_netdev(netdev
);
7319 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7324 ixgbe_release_hw_control(adapter
);
7325 ixgbe_clear_interrupt_scheme(adapter
);
7328 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7329 ixgbe_disable_sriov(adapter
);
7330 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7331 del_timer_sync(&adapter
->sfp_timer
);
7332 cancel_work_sync(&adapter
->sfp_task
);
7333 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7334 cancel_work_sync(&adapter
->sfp_config_module_task
);
7335 iounmap(hw
->hw_addr
);
7337 free_netdev(netdev
);
7339 pci_release_selected_regions(pdev
,
7340 pci_select_bars(pdev
, IORESOURCE_MEM
));
7343 pci_disable_device(pdev
);
7348 * ixgbe_remove - Device Removal Routine
7349 * @pdev: PCI device information struct
7351 * ixgbe_remove is called by the PCI subsystem to alert the driver
7352 * that it should release a PCI device. The could be caused by a
7353 * Hot-Plug event, or because the driver is going to be removed from
7356 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7358 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7359 struct net_device
*netdev
= adapter
->netdev
;
7361 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7362 /* clear the module not found bit to make sure the worker won't
7365 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
7366 del_timer_sync(&adapter
->watchdog_timer
);
7368 del_timer_sync(&adapter
->sfp_timer
);
7369 cancel_work_sync(&adapter
->watchdog_task
);
7370 cancel_work_sync(&adapter
->sfp_task
);
7371 cancel_work_sync(&adapter
->multispeed_fiber_task
);
7372 cancel_work_sync(&adapter
->sfp_config_module_task
);
7373 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
7374 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
7375 cancel_work_sync(&adapter
->fdir_reinit_task
);
7376 flush_scheduled_work();
7378 #ifdef CONFIG_IXGBE_DCA
7379 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7380 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7381 dca_remove_requester(&pdev
->dev
);
7382 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7387 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7388 ixgbe_cleanup_fcoe(adapter
);
7390 #endif /* IXGBE_FCOE */
7392 /* remove the added san mac */
7393 ixgbe_del_sanmac_netdev(netdev
);
7395 if (netdev
->reg_state
== NETREG_REGISTERED
)
7396 unregister_netdev(netdev
);
7398 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7399 ixgbe_disable_sriov(adapter
);
7401 ixgbe_clear_interrupt_scheme(adapter
);
7403 ixgbe_release_hw_control(adapter
);
7405 iounmap(adapter
->hw
.hw_addr
);
7406 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7409 e_dev_info("complete\n");
7411 free_netdev(netdev
);
7413 pci_disable_pcie_error_reporting(pdev
);
7415 pci_disable_device(pdev
);
7419 * ixgbe_io_error_detected - called when PCI error is detected
7420 * @pdev: Pointer to PCI device
7421 * @state: The current pci connection state
7423 * This function is called after a PCI bus error affecting
7424 * this device has been detected.
7426 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7427 pci_channel_state_t state
)
7429 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7430 struct net_device
*netdev
= adapter
->netdev
;
7432 netif_device_detach(netdev
);
7434 if (state
== pci_channel_io_perm_failure
)
7435 return PCI_ERS_RESULT_DISCONNECT
;
7437 if (netif_running(netdev
))
7438 ixgbe_down(adapter
);
7439 pci_disable_device(pdev
);
7441 /* Request a slot reset. */
7442 return PCI_ERS_RESULT_NEED_RESET
;
7446 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7447 * @pdev: Pointer to PCI device
7449 * Restart the card from scratch, as if from a cold-boot.
7451 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7453 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7454 pci_ers_result_t result
;
7457 if (pci_enable_device_mem(pdev
)) {
7458 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7459 result
= PCI_ERS_RESULT_DISCONNECT
;
7461 pci_set_master(pdev
);
7462 pci_restore_state(pdev
);
7463 pci_save_state(pdev
);
7465 pci_wake_from_d3(pdev
, false);
7467 ixgbe_reset(adapter
);
7468 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7469 result
= PCI_ERS_RESULT_RECOVERED
;
7472 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7474 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7475 "failed 0x%0x\n", err
);
7476 /* non-fatal, continue */
7483 * ixgbe_io_resume - called when traffic can start flowing again.
7484 * @pdev: Pointer to PCI device
7486 * This callback is called when the error recovery driver tells us that
7487 * its OK to resume normal operation.
7489 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7491 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7492 struct net_device
*netdev
= adapter
->netdev
;
7494 if (netif_running(netdev
)) {
7495 if (ixgbe_up(adapter
)) {
7496 e_info(probe
, "ixgbe_up failed after reset\n");
7501 netif_device_attach(netdev
);
7504 static struct pci_error_handlers ixgbe_err_handler
= {
7505 .error_detected
= ixgbe_io_error_detected
,
7506 .slot_reset
= ixgbe_io_slot_reset
,
7507 .resume
= ixgbe_io_resume
,
7510 static struct pci_driver ixgbe_driver
= {
7511 .name
= ixgbe_driver_name
,
7512 .id_table
= ixgbe_pci_tbl
,
7513 .probe
= ixgbe_probe
,
7514 .remove
= __devexit_p(ixgbe_remove
),
7516 .suspend
= ixgbe_suspend
,
7517 .resume
= ixgbe_resume
,
7519 .shutdown
= ixgbe_shutdown
,
7520 .err_handler
= &ixgbe_err_handler
7524 * ixgbe_init_module - Driver Registration Routine
7526 * ixgbe_init_module is the first routine called when the driver is
7527 * loaded. All it does is register with the PCI subsystem.
7529 static int __init
ixgbe_init_module(void)
7532 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
7533 pr_info("%s\n", ixgbe_copyright
);
7535 #ifdef CONFIG_IXGBE_DCA
7536 dca_register_notify(&dca_notifier
);
7539 ret
= pci_register_driver(&ixgbe_driver
);
7543 module_init(ixgbe_init_module
);
7546 * ixgbe_exit_module - Driver Exit Cleanup Routine
7548 * ixgbe_exit_module is called just before the driver is removed
7551 static void __exit
ixgbe_exit_module(void)
7553 #ifdef CONFIG_IXGBE_DCA
7554 dca_unregister_notify(&dca_notifier
);
7556 pci_unregister_driver(&ixgbe_driver
);
7557 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7560 #ifdef CONFIG_IXGBE_DCA
7561 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7566 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7567 __ixgbe_notify_dca
);
7569 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7572 #endif /* CONFIG_IXGBE_DCA */
7575 * ixgbe_get_hw_dev return device
7576 * used by hardware layer to print debugging information
7578 struct net_device
*ixgbe_get_hw_dev(struct ixgbe_hw
*hw
)
7580 struct ixgbe_adapter
*adapter
= hw
->back
;
7581 return adapter
->netdev
;
7584 module_exit(ixgbe_exit_module
);