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drm/i915: clarify gen2 pageflip cmd
[linux-2.6/libata-dev.git] / drivers / gpu / drm / i915 / intel_display.c
blob4247a7b1823b4296f2ba7b690040b4da9131de8a
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_update_watermarks(struct drm_device *dev);
48 static void intel_increase_pllclock(struct drm_crtc *crtc);
49 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
50
51 typedef struct {
52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
61 } intel_clock_t;
62
63 typedef struct {
64 int min, max;
65 } intel_range_t;
66
67 typedef struct {
68 int dot_limit;
69 int p2_slow, p2_fast;
70 } intel_p2_t;
71
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t;
74 struct intel_limit {
75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *, intel_clock_t *);
79 };
80
81 /* FDI */
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
84 static bool
85 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
88 static bool
89 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
92
93 static bool
94 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
97 static bool
98 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
101
102 static inline u32 /* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device *dev)
104 {
105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
110 }
111
112 static const intel_limit_t intel_limits_i8xx_dvo = {
113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
123 .find_pll = intel_find_best_PLL,
124 };
125
126 static const intel_limit_t intel_limits_i8xx_lvds = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
137 .find_pll = intel_find_best_PLL,
138 };
139
140 static const intel_limit_t intel_limits_i9xx_sdvo = {
141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i9xx_lvds = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168
169 static const intel_limit_t intel_limits_g4x_sdvo = {
170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
181 },
182 .find_pll = intel_g4x_find_best_PLL,
183 };
184
185 static const intel_limit_t intel_limits_g4x_hdmi = {
186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
196 .find_pll = intel_g4x_find_best_PLL,
197 };
198
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
210 },
211 .find_pll = intel_g4x_find_best_PLL,
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
225 },
226 .find_pll = intel_g4x_find_best_PLL,
227 };
228
229 static const intel_limit_t intel_limits_g4x_display_port = {
230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
239 .p2_slow = 10, .p2_fast = 10 },
240 .find_pll = intel_find_pll_g4x_dp,
241 };
242
243 static const intel_limit_t intel_limits_pineview_sdvo = {
244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
246 /* Pineview's Ncounter is a ring counter */
247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
249 /* Pineview only has one combined m divider, which we treat as m2. */
250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
256 .find_pll = intel_find_best_PLL,
257 };
258
259 static const intel_limit_t intel_limits_pineview_lvds = {
260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
270 .find_pll = intel_find_best_PLL,
271 };
272
273 /* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
278 static const intel_limit_t intel_limits_ironlake_dac = {
279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
289 .find_pll = intel_g4x_find_best_PLL,
290 };
291
292 static const intel_limit_t intel_limits_ironlake_single_lvds = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
303 .find_pll = intel_g4x_find_best_PLL,
304 };
305
306 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
329 .p1 = { .min = 2, .max = 8 },
330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
332 .find_pll = intel_g4x_find_best_PLL,
333 };
334
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
343 .p1 = { .min = 2, .max = 6 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
346 .find_pll = intel_g4x_find_best_PLL,
347 };
348
349 static const intel_limit_t intel_limits_ironlake_display_port = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
359 .p2_slow = 10, .p2_fast = 10 },
360 .find_pll = intel_find_pll_ironlake_dp,
361 };
362
363 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
365 {
366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368 const intel_limit_t *limit;
369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
374 if (refclk == 100000)
375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
379 if (refclk == 100000)
380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
387 else
388 limit = &intel_limits_ironlake_dac;
389
390 return limit;
391 }
392
393 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394 {
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
403 limit = &intel_limits_g4x_dual_channel_lvds;
404 else
405 /* LVDS with dual channel */
406 limit = &intel_limits_g4x_single_channel_lvds;
407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
409 limit = &intel_limits_g4x_hdmi;
410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
411 limit = &intel_limits_g4x_sdvo;
412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
413 limit = &intel_limits_g4x_display_port;
414 } else /* The option is for other outputs */
415 limit = &intel_limits_i9xx_sdvo;
416
417 return limit;
418 }
419
420 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
421 {
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
425 if (HAS_PCH_SPLIT(dev))
426 limit = intel_ironlake_limit(crtc, refclk);
427 else if (IS_G4X(dev)) {
428 limit = intel_g4x_limit(crtc);
429 } else if (IS_PINEVIEW(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_pineview_lvds;
432 else
433 limit = &intel_limits_pineview_sdvo;
434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
441 limit = &intel_limits_i8xx_lvds;
442 else
443 limit = &intel_limits_i8xx_dvo;
444 }
445 return limit;
446 }
447
448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
449 static void pineview_clock(int refclk, intel_clock_t *clock)
450 {
451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455 }
456
457 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458 {
459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
461 return;
462 }
463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467 }
468
469 /**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
472 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
473 {
474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
483 }
484
485 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
486 /**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
491 static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
494 {
495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
496 INTELPllInvalid("p1 out of range\n");
497 if (clock->p < limit->p.min || limit->p.max < clock->p)
498 INTELPllInvalid("p out of range\n");
499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
500 INTELPllInvalid("m2 out of range\n");
501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
502 INTELPllInvalid("m1 out of range\n");
503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
504 INTELPllInvalid("m1 <= m2\n");
505 if (clock->m < limit->m.min || limit->m.max < clock->m)
506 INTELPllInvalid("m out of range\n");
507 if (clock->n < limit->n.min || limit->n.max < clock->n)
508 INTELPllInvalid("n out of range\n");
509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
510 INTELPllInvalid("vco out of range\n");
511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
515 INTELPllInvalid("dot out of range\n");
516
517 return true;
518 }
519
520 static bool
521 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
524
525 {
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
529 int err = target;
530
531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
532 (I915_READ(LVDS)) != 0) {
533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
551 memset(best_clock, 0, sizeof(*best_clock));
552
553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
564 int this_err;
565
566 intel_clock(dev, refclk, &clock);
567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
569 continue;
570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585 }
586
587 static bool
588 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
591 {
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
602 int lvds_reg;
603
604 if (HAS_PCH_SPLIT(dev))
605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
622 /* based on hardware requirement, prefer smaller n to precision */
623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
624 /* based on hardware requirement, prefere larger m1,m2 */
625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
633 intel_clock(dev, refclk, &clock);
634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
636 continue;
637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
640
641 this_err = abs(clock.dot - target);
642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
652 return found;
653 }
654
655 static bool
656 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
659 {
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
662
663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679 }
680
681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
682 static bool
683 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
686 {
687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
707 }
708
709 /**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
718 {
719 struct drm_i915_private *dev_priv = dev->dev_private;
720 int pipestat_reg = PIPESTAT(pipe);
721
722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
738 /* Wait for vblank interrupt bit to set */
739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
742 DRM_DEBUG_KMS("vblank wait timed out\n");
743 }
744
745 /*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
760 *
761 */
762 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
763 {
764 struct drm_i915_private *dev_priv = dev->dev_private;
765
766 if (INTEL_INFO(dev)->gen >= 4) {
767 int reg = PIPECONF(pipe);
768
769 /* Wait for the Pipe State to go off */
770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
775 int reg = PIPEDSL(pipe);
776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
780 last_line = I915_READ(reg) & DSL_LINEMASK;
781 mdelay(5);
782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
787 }
788
789 static const char *state_string(bool enabled)
790 {
791 return enabled ? "on" : "off";
792 }
793
794 /* Only for pre-ILK configs */
795 static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797 {
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808 }
809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
812 /* For ILK+ */
813 static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815 {
816 int reg;
817 u32 val;
818 bool cur_state;
819
820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839 }
840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845 {
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856 }
857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862 {
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873 }
874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890 }
891
892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894 {
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901 }
902
903 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905 {
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
909 bool locked = true;
910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
929 pipe_name(pipe));
930 }
931
932 void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
934 {
935 int reg;
936 u32 val;
937 bool cur_state;
938
939 reg = PIPECONF(pipe);
940 val = I915_READ(reg);
941 cur_state = !!(val & PIPECONF_ENABLE);
942 WARN(cur_state != state,
943 "pipe %c assertion failure (expected %s, current %s)\n",
944 pipe_name(pipe), state_string(state), state_string(cur_state));
945 }
946
947 static void assert_plane(struct drm_i915_private *dev_priv,
948 enum plane plane, bool state)
949 {
950 int reg;
951 u32 val;
952 bool cur_state;
953
954 reg = DSPCNTR(plane);
955 val = I915_READ(reg);
956 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
957 WARN(cur_state != state,
958 "plane %c assertion failure (expected %s, current %s)\n",
959 plane_name(plane), state_string(state), state_string(cur_state));
960 }
961
962 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
963 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
964
965 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
966 enum pipe pipe)
967 {
968 int reg, i;
969 u32 val;
970 int cur_pipe;
971
972 /* Planes are fixed to pipes on ILK+ */
973 if (HAS_PCH_SPLIT(dev_priv->dev)) {
974 reg = DSPCNTR(pipe);
975 val = I915_READ(reg);
976 WARN((val & DISPLAY_PLANE_ENABLE),
977 "plane %c assertion failure, should be disabled but not\n",
978 plane_name(pipe));
979 return;
980 }
981
982 /* Need to check both planes against the pipe */
983 for (i = 0; i < 2; i++) {
984 reg = DSPCNTR(i);
985 val = I915_READ(reg);
986 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
987 DISPPLANE_SEL_PIPE_SHIFT;
988 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
989 "plane %c assertion failure, should be off on pipe %c but is still active\n",
990 plane_name(i), pipe_name(pipe));
991 }
992 }
993
994 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
995 {
996 u32 val;
997 bool enabled;
998
999 val = I915_READ(PCH_DREF_CONTROL);
1000 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1001 DREF_SUPERSPREAD_SOURCE_MASK));
1002 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1003 }
1004
1005 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1006 enum pipe pipe)
1007 {
1008 int reg;
1009 u32 val;
1010 bool enabled;
1011
1012 reg = TRANSCONF(pipe);
1013 val = I915_READ(reg);
1014 enabled = !!(val & TRANS_ENABLE);
1015 WARN(enabled,
1016 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1017 pipe_name(pipe));
1018 }
1019
1020 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe, u32 port_sel, u32 val)
1022 {
1023 if ((val & DP_PORT_EN) == 0)
1024 return false;
1025
1026 if (HAS_PCH_CPT(dev_priv->dev)) {
1027 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1028 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1029 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1030 return false;
1031 } else {
1032 if ((val & DP_PIPE_MASK) != (pipe << 30))
1033 return false;
1034 }
1035 return true;
1036 }
1037
1038 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1039 enum pipe pipe, u32 val)
1040 {
1041 if ((val & PORT_ENABLE) == 0)
1042 return false;
1043
1044 if (HAS_PCH_CPT(dev_priv->dev)) {
1045 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1046 return false;
1047 } else {
1048 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1049 return false;
1050 }
1051 return true;
1052 }
1053
1054 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1055 enum pipe pipe, u32 val)
1056 {
1057 if ((val & LVDS_PORT_EN) == 0)
1058 return false;
1059
1060 if (HAS_PCH_CPT(dev_priv->dev)) {
1061 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1062 return false;
1063 } else {
1064 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1065 return false;
1066 }
1067 return true;
1068 }
1069
1070 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, u32 val)
1072 {
1073 if ((val & ADPA_DAC_ENABLE) == 0)
1074 return false;
1075 if (HAS_PCH_CPT(dev_priv->dev)) {
1076 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1077 return false;
1078 } else {
1079 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1080 return false;
1081 }
1082 return true;
1083 }
1084
1085 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, int reg, u32 port_sel)
1087 {
1088 u32 val = I915_READ(reg);
1089 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1090 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1091 reg, pipe_name(pipe));
1092 }
1093
1094 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1095 enum pipe pipe, int reg)
1096 {
1097 u32 val = I915_READ(reg);
1098 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
1099 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1100 reg, pipe_name(pipe));
1101 }
1102
1103 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105 {
1106 int reg;
1107 u32 val;
1108
1109 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1110 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1111 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1112
1113 reg = PCH_ADPA;
1114 val = I915_READ(reg);
1115 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
1116 "PCH VGA enabled on transcoder %c, should be disabled\n",
1117 pipe_name(pipe));
1118
1119 reg = PCH_LVDS;
1120 val = I915_READ(reg);
1121 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
1122 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1123 pipe_name(pipe));
1124
1125 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1126 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1127 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1128 }
1129
1130 /**
1131 * intel_enable_pll - enable a PLL
1132 * @dev_priv: i915 private structure
1133 * @pipe: pipe PLL to enable
1134 *
1135 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1136 * make sure the PLL reg is writable first though, since the panel write
1137 * protect mechanism may be enabled.
1138 *
1139 * Note! This is for pre-ILK only.
1140 */
1141 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1142 {
1143 int reg;
1144 u32 val;
1145
1146 /* No really, not for ILK+ */
1147 BUG_ON(dev_priv->info->gen >= 5);
1148
1149 /* PLL is protected by panel, make sure we can write it */
1150 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1151 assert_panel_unlocked(dev_priv, pipe);
1152
1153 reg = DPLL(pipe);
1154 val = I915_READ(reg);
1155 val |= DPLL_VCO_ENABLE;
1156
1157 /* We do this three times for luck */
1158 I915_WRITE(reg, val);
1159 POSTING_READ(reg);
1160 udelay(150); /* wait for warmup */
1161 I915_WRITE(reg, val);
1162 POSTING_READ(reg);
1163 udelay(150); /* wait for warmup */
1164 I915_WRITE(reg, val);
1165 POSTING_READ(reg);
1166 udelay(150); /* wait for warmup */
1167 }
1168
1169 /**
1170 * intel_disable_pll - disable a PLL
1171 * @dev_priv: i915 private structure
1172 * @pipe: pipe PLL to disable
1173 *
1174 * Disable the PLL for @pipe, making sure the pipe is off first.
1175 *
1176 * Note! This is for pre-ILK only.
1177 */
1178 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1179 {
1180 int reg;
1181 u32 val;
1182
1183 /* Don't disable pipe A or pipe A PLLs if needed */
1184 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1185 return;
1186
1187 /* Make sure the pipe isn't still relying on us */
1188 assert_pipe_disabled(dev_priv, pipe);
1189
1190 reg = DPLL(pipe);
1191 val = I915_READ(reg);
1192 val &= ~DPLL_VCO_ENABLE;
1193 I915_WRITE(reg, val);
1194 POSTING_READ(reg);
1195 }
1196
1197 /**
1198 * intel_enable_pch_pll - enable PCH PLL
1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe PLL to enable
1201 *
1202 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1203 * drives the transcoder clock.
1204 */
1205 static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207 {
1208 int reg;
1209 u32 val;
1210
1211 if (pipe > 1)
1212 return;
1213
1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* PCH refclock must be enabled first */
1218 assert_pch_refclk_enabled(dev_priv);
1219
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val |= DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1224 POSTING_READ(reg);
1225 udelay(200);
1226 }
1227
1228 static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230 {
1231 int reg;
1232 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1233 pll_sel = TRANSC_DPLL_ENABLE;
1234
1235 if (pipe > 1)
1236 return;
1237
1238 /* PCH only available on ILK+ */
1239 BUG_ON(dev_priv->info->gen < 5);
1240
1241 /* Make sure transcoder isn't still depending on us */
1242 assert_transcoder_disabled(dev_priv, pipe);
1243
1244 if (pipe == 0)
1245 pll_sel |= TRANSC_DPLLA_SEL;
1246 else if (pipe == 1)
1247 pll_sel |= TRANSC_DPLLB_SEL;
1248
1249
1250 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1251 return;
1252
1253 reg = PCH_DPLL(pipe);
1254 val = I915_READ(reg);
1255 val &= ~DPLL_VCO_ENABLE;
1256 I915_WRITE(reg, val);
1257 POSTING_READ(reg);
1258 udelay(200);
1259 }
1260
1261 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
1263 {
1264 int reg;
1265 u32 val;
1266
1267 /* PCH only available on ILK+ */
1268 BUG_ON(dev_priv->info->gen < 5);
1269
1270 /* Make sure PCH DPLL is enabled */
1271 assert_pch_pll_enabled(dev_priv, pipe);
1272
1273 /* FDI must be feeding us bits for PCH ports */
1274 assert_fdi_tx_enabled(dev_priv, pipe);
1275 assert_fdi_rx_enabled(dev_priv, pipe);
1276
1277 reg = TRANSCONF(pipe);
1278 val = I915_READ(reg);
1279
1280 if (HAS_PCH_IBX(dev_priv->dev)) {
1281 /*
1282 * make the BPC in transcoder be consistent with
1283 * that in pipeconf reg.
1284 */
1285 val &= ~PIPE_BPC_MASK;
1286 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1287 }
1288 I915_WRITE(reg, val | TRANS_ENABLE);
1289 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1290 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1291 }
1292
1293 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1294 enum pipe pipe)
1295 {
1296 int reg;
1297 u32 val;
1298
1299 /* FDI relies on the transcoder */
1300 assert_fdi_tx_disabled(dev_priv, pipe);
1301 assert_fdi_rx_disabled(dev_priv, pipe);
1302
1303 /* Ports must be off as well */
1304 assert_pch_ports_disabled(dev_priv, pipe);
1305
1306 reg = TRANSCONF(pipe);
1307 val = I915_READ(reg);
1308 val &= ~TRANS_ENABLE;
1309 I915_WRITE(reg, val);
1310 /* wait for PCH transcoder off, transcoder state */
1311 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1312 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1313 }
1314
1315 /**
1316 * intel_enable_pipe - enable a pipe, asserting requirements
1317 * @dev_priv: i915 private structure
1318 * @pipe: pipe to enable
1319 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1320 *
1321 * Enable @pipe, making sure that various hardware specific requirements
1322 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1323 *
1324 * @pipe should be %PIPE_A or %PIPE_B.
1325 *
1326 * Will wait until the pipe is actually running (i.e. first vblank) before
1327 * returning.
1328 */
1329 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1330 bool pch_port)
1331 {
1332 int reg;
1333 u32 val;
1334
1335 /*
1336 * A pipe without a PLL won't actually be able to drive bits from
1337 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1338 * need the check.
1339 */
1340 if (!HAS_PCH_SPLIT(dev_priv->dev))
1341 assert_pll_enabled(dev_priv, pipe);
1342 else {
1343 if (pch_port) {
1344 /* if driving the PCH, we need FDI enabled */
1345 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1346 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1347 }
1348 /* FIXME: assert CPU port conditions for SNB+ */
1349 }
1350
1351 reg = PIPECONF(pipe);
1352 val = I915_READ(reg);
1353 if (val & PIPECONF_ENABLE)
1354 return;
1355
1356 I915_WRITE(reg, val | PIPECONF_ENABLE);
1357 intel_wait_for_vblank(dev_priv->dev, pipe);
1358 }
1359
1360 /**
1361 * intel_disable_pipe - disable a pipe, asserting requirements
1362 * @dev_priv: i915 private structure
1363 * @pipe: pipe to disable
1364 *
1365 * Disable @pipe, making sure that various hardware specific requirements
1366 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1367 *
1368 * @pipe should be %PIPE_A or %PIPE_B.
1369 *
1370 * Will wait until the pipe has shut down before returning.
1371 */
1372 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1373 enum pipe pipe)
1374 {
1375 int reg;
1376 u32 val;
1377
1378 /*
1379 * Make sure planes won't keep trying to pump pixels to us,
1380 * or we might hang the display.
1381 */
1382 assert_planes_disabled(dev_priv, pipe);
1383
1384 /* Don't disable pipe A or pipe A PLLs if needed */
1385 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1386 return;
1387
1388 reg = PIPECONF(pipe);
1389 val = I915_READ(reg);
1390 if ((val & PIPECONF_ENABLE) == 0)
1391 return;
1392
1393 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1394 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1395 }
1396
1397 /*
1398 * Plane regs are double buffered, going from enabled->disabled needs a
1399 * trigger in order to latch. The display address reg provides this.
1400 */
1401 static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1402 enum plane plane)
1403 {
1404 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1405 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1406 }
1407
1408 /**
1409 * intel_enable_plane - enable a display plane on a given pipe
1410 * @dev_priv: i915 private structure
1411 * @plane: plane to enable
1412 * @pipe: pipe being fed
1413 *
1414 * Enable @plane on @pipe, making sure that @pipe is running first.
1415 */
1416 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1417 enum plane plane, enum pipe pipe)
1418 {
1419 int reg;
1420 u32 val;
1421
1422 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1423 assert_pipe_enabled(dev_priv, pipe);
1424
1425 reg = DSPCNTR(plane);
1426 val = I915_READ(reg);
1427 if (val & DISPLAY_PLANE_ENABLE)
1428 return;
1429
1430 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1431 intel_flush_display_plane(dev_priv, plane);
1432 intel_wait_for_vblank(dev_priv->dev, pipe);
1433 }
1434
1435 /**
1436 * intel_disable_plane - disable a display plane
1437 * @dev_priv: i915 private structure
1438 * @plane: plane to disable
1439 * @pipe: pipe consuming the data
1440 *
1441 * Disable @plane; should be an independent operation.
1442 */
1443 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1444 enum plane plane, enum pipe pipe)
1445 {
1446 int reg;
1447 u32 val;
1448
1449 reg = DSPCNTR(plane);
1450 val = I915_READ(reg);
1451 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1452 return;
1453
1454 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1455 intel_flush_display_plane(dev_priv, plane);
1456 intel_wait_for_vblank(dev_priv->dev, pipe);
1457 }
1458
1459 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1460 enum pipe pipe, int reg, u32 port_sel)
1461 {
1462 u32 val = I915_READ(reg);
1463 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1464 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1465 I915_WRITE(reg, val & ~DP_PORT_EN);
1466 }
1467 }
1468
1469 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1470 enum pipe pipe, int reg)
1471 {
1472 u32 val = I915_READ(reg);
1473 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
1474 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1475 reg, pipe);
1476 I915_WRITE(reg, val & ~PORT_ENABLE);
1477 }
1478 }
1479
1480 /* Disable any ports connected to this transcoder */
1481 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1482 enum pipe pipe)
1483 {
1484 u32 reg, val;
1485
1486 val = I915_READ(PCH_PP_CONTROL);
1487 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1488
1489 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1490 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1491 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1492
1493 reg = PCH_ADPA;
1494 val = I915_READ(reg);
1495 if (adpa_pipe_enabled(dev_priv, val, pipe))
1496 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1497
1498 reg = PCH_LVDS;
1499 val = I915_READ(reg);
1500 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1501 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1502 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1503 POSTING_READ(reg);
1504 udelay(100);
1505 }
1506
1507 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1508 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1509 disable_pch_hdmi(dev_priv, pipe, HDMID);
1510 }
1511
1512 static void i8xx_disable_fbc(struct drm_device *dev)
1513 {
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515 u32 fbc_ctl;
1516
1517 /* Disable compression */
1518 fbc_ctl = I915_READ(FBC_CONTROL);
1519 if ((fbc_ctl & FBC_CTL_EN) == 0)
1520 return;
1521
1522 fbc_ctl &= ~FBC_CTL_EN;
1523 I915_WRITE(FBC_CONTROL, fbc_ctl);
1524
1525 /* Wait for compressing bit to clear */
1526 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1527 DRM_DEBUG_KMS("FBC idle timed out\n");
1528 return;
1529 }
1530
1531 DRM_DEBUG_KMS("disabled FBC\n");
1532 }
1533
1534 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1535 {
1536 struct drm_device *dev = crtc->dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 struct drm_framebuffer *fb = crtc->fb;
1539 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1540 struct drm_i915_gem_object *obj = intel_fb->obj;
1541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1542 int cfb_pitch;
1543 int plane, i;
1544 u32 fbc_ctl, fbc_ctl2;
1545
1546 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1547 if (fb->pitches[0] < cfb_pitch)
1548 cfb_pitch = fb->pitches[0];
1549
1550 /* FBC_CTL wants 64B units */
1551 cfb_pitch = (cfb_pitch / 64) - 1;
1552 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1553
1554 /* Clear old tags */
1555 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1556 I915_WRITE(FBC_TAG + (i * 4), 0);
1557
1558 /* Set it up... */
1559 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1560 fbc_ctl2 |= plane;
1561 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1562 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1563
1564 /* enable it... */
1565 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1566 if (IS_I945GM(dev))
1567 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1568 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1569 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1570 fbc_ctl |= obj->fence_reg;
1571 I915_WRITE(FBC_CONTROL, fbc_ctl);
1572
1573 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1574 cfb_pitch, crtc->y, intel_crtc->plane);
1575 }
1576
1577 static bool i8xx_fbc_enabled(struct drm_device *dev)
1578 {
1579 struct drm_i915_private *dev_priv = dev->dev_private;
1580
1581 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1582 }
1583
1584 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1585 {
1586 struct drm_device *dev = crtc->dev;
1587 struct drm_i915_private *dev_priv = dev->dev_private;
1588 struct drm_framebuffer *fb = crtc->fb;
1589 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1590 struct drm_i915_gem_object *obj = intel_fb->obj;
1591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1592 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1593 unsigned long stall_watermark = 200;
1594 u32 dpfc_ctl;
1595
1596 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1597 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
1598 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1599
1600 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1601 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1602 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1603 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1604
1605 /* enable it... */
1606 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1607
1608 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1609 }
1610
1611 static void g4x_disable_fbc(struct drm_device *dev)
1612 {
1613 struct drm_i915_private *dev_priv = dev->dev_private;
1614 u32 dpfc_ctl;
1615
1616 /* Disable compression */
1617 dpfc_ctl = I915_READ(DPFC_CONTROL);
1618 if (dpfc_ctl & DPFC_CTL_EN) {
1619 dpfc_ctl &= ~DPFC_CTL_EN;
1620 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1621
1622 DRM_DEBUG_KMS("disabled FBC\n");
1623 }
1624 }
1625
1626 static bool g4x_fbc_enabled(struct drm_device *dev)
1627 {
1628 struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1631 }
1632
1633 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1634 {
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1636 u32 blt_ecoskpd;
1637
1638 /* Make sure blitter notifies FBC of writes */
1639 gen6_gt_force_wake_get(dev_priv);
1640 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1641 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1642 GEN6_BLITTER_LOCK_SHIFT;
1643 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1644 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1645 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1646 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1647 GEN6_BLITTER_LOCK_SHIFT);
1648 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1649 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1650 gen6_gt_force_wake_put(dev_priv);
1651 }
1652
1653 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1654 {
1655 struct drm_device *dev = crtc->dev;
1656 struct drm_i915_private *dev_priv = dev->dev_private;
1657 struct drm_framebuffer *fb = crtc->fb;
1658 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1659 struct drm_i915_gem_object *obj = intel_fb->obj;
1660 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1661 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1662 unsigned long stall_watermark = 200;
1663 u32 dpfc_ctl;
1664
1665 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1666 dpfc_ctl &= DPFC_RESERVED;
1667 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1668 /* Set persistent mode for front-buffer rendering, ala X. */
1669 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
1670 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
1671 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1672
1673 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1674 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1675 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1676 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1677 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1678 /* enable it... */
1679 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1680
1681 if (IS_GEN6(dev)) {
1682 I915_WRITE(SNB_DPFC_CTL_SA,
1683 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
1684 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1685 sandybridge_blit_fbc_update(dev);
1686 }
1687
1688 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1689 }
1690
1691 static void ironlake_disable_fbc(struct drm_device *dev)
1692 {
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1694 u32 dpfc_ctl;
1695
1696 /* Disable compression */
1697 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1698 if (dpfc_ctl & DPFC_CTL_EN) {
1699 dpfc_ctl &= ~DPFC_CTL_EN;
1700 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1701
1702 DRM_DEBUG_KMS("disabled FBC\n");
1703 }
1704 }
1705
1706 static bool ironlake_fbc_enabled(struct drm_device *dev)
1707 {
1708 struct drm_i915_private *dev_priv = dev->dev_private;
1709
1710 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1711 }
1712
1713 bool intel_fbc_enabled(struct drm_device *dev)
1714 {
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716
1717 if (!dev_priv->display.fbc_enabled)
1718 return false;
1719
1720 return dev_priv->display.fbc_enabled(dev);
1721 }
1722
1723 static void intel_fbc_work_fn(struct work_struct *__work)
1724 {
1725 struct intel_fbc_work *work =
1726 container_of(to_delayed_work(__work),
1727 struct intel_fbc_work, work);
1728 struct drm_device *dev = work->crtc->dev;
1729 struct drm_i915_private *dev_priv = dev->dev_private;
1730
1731 mutex_lock(&dev->struct_mutex);
1732 if (work == dev_priv->fbc_work) {
1733 /* Double check that we haven't switched fb without cancelling
1734 * the prior work.
1735 */
1736 if (work->crtc->fb == work->fb) {
1737 dev_priv->display.enable_fbc(work->crtc,
1738 work->interval);
1739
1740 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1741 dev_priv->cfb_fb = work->crtc->fb->base.id;
1742 dev_priv->cfb_y = work->crtc->y;
1743 }
1744
1745 dev_priv->fbc_work = NULL;
1746 }
1747 mutex_unlock(&dev->struct_mutex);
1748
1749 kfree(work);
1750 }
1751
1752 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1753 {
1754 if (dev_priv->fbc_work == NULL)
1755 return;
1756
1757 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1758
1759 /* Synchronisation is provided by struct_mutex and checking of
1760 * dev_priv->fbc_work, so we can perform the cancellation
1761 * entirely asynchronously.
1762 */
1763 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1764 /* tasklet was killed before being run, clean up */
1765 kfree(dev_priv->fbc_work);
1766
1767 /* Mark the work as no longer wanted so that if it does
1768 * wake-up (because the work was already running and waiting
1769 * for our mutex), it will discover that is no longer
1770 * necessary to run.
1771 */
1772 dev_priv->fbc_work = NULL;
1773 }
1774
1775 static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1776 {
1777 struct intel_fbc_work *work;
1778 struct drm_device *dev = crtc->dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780
1781 if (!dev_priv->display.enable_fbc)
1782 return;
1783
1784 intel_cancel_fbc_work(dev_priv);
1785
1786 work = kzalloc(sizeof *work, GFP_KERNEL);
1787 if (work == NULL) {
1788 dev_priv->display.enable_fbc(crtc, interval);
1789 return;
1790 }
1791
1792 work->crtc = crtc;
1793 work->fb = crtc->fb;
1794 work->interval = interval;
1795 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1796
1797 dev_priv->fbc_work = work;
1798
1799 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1800
1801 /* Delay the actual enabling to let pageflipping cease and the
1802 * display to settle before starting the compression. Note that
1803 * this delay also serves a second purpose: it allows for a
1804 * vblank to pass after disabling the FBC before we attempt
1805 * to modify the control registers.
1806 *
1807 * A more complicated solution would involve tracking vblanks
1808 * following the termination of the page-flipping sequence
1809 * and indeed performing the enable as a co-routine and not
1810 * waiting synchronously upon the vblank.
1811 */
1812 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
1813 }
1814
1815 void intel_disable_fbc(struct drm_device *dev)
1816 {
1817 struct drm_i915_private *dev_priv = dev->dev_private;
1818
1819 intel_cancel_fbc_work(dev_priv);
1820
1821 if (!dev_priv->display.disable_fbc)
1822 return;
1823
1824 dev_priv->display.disable_fbc(dev);
1825 dev_priv->cfb_plane = -1;
1826 }
1827
1828 /**
1829 * intel_update_fbc - enable/disable FBC as needed
1830 * @dev: the drm_device
1831 *
1832 * Set up the framebuffer compression hardware at mode set time. We
1833 * enable it if possible:
1834 * - plane A only (on pre-965)
1835 * - no pixel mulitply/line duplication
1836 * - no alpha buffer discard
1837 * - no dual wide
1838 * - framebuffer <= 2048 in width, 1536 in height
1839 *
1840 * We can't assume that any compression will take place (worst case),
1841 * so the compressed buffer has to be the same size as the uncompressed
1842 * one. It also must reside (along with the line length buffer) in
1843 * stolen memory.
1844 *
1845 * We need to enable/disable FBC on a global basis.
1846 */
1847 static void intel_update_fbc(struct drm_device *dev)
1848 {
1849 struct drm_i915_private *dev_priv = dev->dev_private;
1850 struct drm_crtc *crtc = NULL, *tmp_crtc;
1851 struct intel_crtc *intel_crtc;
1852 struct drm_framebuffer *fb;
1853 struct intel_framebuffer *intel_fb;
1854 struct drm_i915_gem_object *obj;
1855 int enable_fbc;
1856
1857 DRM_DEBUG_KMS("\n");
1858
1859 if (!i915_powersave)
1860 return;
1861
1862 if (!I915_HAS_FBC(dev))
1863 return;
1864
1865 /*
1866 * If FBC is already on, we just have to verify that we can
1867 * keep it that way...
1868 * Need to disable if:
1869 * - more than one pipe is active
1870 * - changing FBC params (stride, fence, mode)
1871 * - new fb is too large to fit in compressed buffer
1872 * - going to an unsupported config (interlace, pixel multiply, etc.)
1873 */
1874 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1875 if (tmp_crtc->enabled && tmp_crtc->fb) {
1876 if (crtc) {
1877 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1878 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1879 goto out_disable;
1880 }
1881 crtc = tmp_crtc;
1882 }
1883 }
1884
1885 if (!crtc || crtc->fb == NULL) {
1886 DRM_DEBUG_KMS("no output, disabling\n");
1887 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1888 goto out_disable;
1889 }
1890
1891 intel_crtc = to_intel_crtc(crtc);
1892 fb = crtc->fb;
1893 intel_fb = to_intel_framebuffer(fb);
1894 obj = intel_fb->obj;
1895
1896 enable_fbc = i915_enable_fbc;
1897 if (enable_fbc < 0) {
1898 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1899 enable_fbc = 1;
1900 if (INTEL_INFO(dev)->gen <= 5)
1901 enable_fbc = 0;
1902 }
1903 if (!enable_fbc) {
1904 DRM_DEBUG_KMS("fbc disabled per module param\n");
1905 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1906 goto out_disable;
1907 }
1908 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1909 DRM_DEBUG_KMS("framebuffer too large, disabling "
1910 "compression\n");
1911 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1912 goto out_disable;
1913 }
1914 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1915 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1916 DRM_DEBUG_KMS("mode incompatible with compression, "
1917 "disabling\n");
1918 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1919 goto out_disable;
1920 }
1921 if ((crtc->mode.hdisplay > 2048) ||
1922 (crtc->mode.vdisplay > 1536)) {
1923 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1924 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1925 goto out_disable;
1926 }
1927 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1928 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1929 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1930 goto out_disable;
1931 }
1932
1933 /* The use of a CPU fence is mandatory in order to detect writes
1934 * by the CPU to the scanout and trigger updates to the FBC.
1935 */
1936 if (obj->tiling_mode != I915_TILING_X ||
1937 obj->fence_reg == I915_FENCE_REG_NONE) {
1938 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1939 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1940 goto out_disable;
1941 }
1942
1943 /* If the kernel debugger is active, always disable compression */
1944 if (in_dbg_master())
1945 goto out_disable;
1946
1947 /* If the scanout has not changed, don't modify the FBC settings.
1948 * Note that we make the fundamental assumption that the fb->obj
1949 * cannot be unpinned (and have its GTT offset and fence revoked)
1950 * without first being decoupled from the scanout and FBC disabled.
1951 */
1952 if (dev_priv->cfb_plane == intel_crtc->plane &&
1953 dev_priv->cfb_fb == fb->base.id &&
1954 dev_priv->cfb_y == crtc->y)
1955 return;
1956
1957 if (intel_fbc_enabled(dev)) {
1958 /* We update FBC along two paths, after changing fb/crtc
1959 * configuration (modeswitching) and after page-flipping
1960 * finishes. For the latter, we know that not only did
1961 * we disable the FBC at the start of the page-flip
1962 * sequence, but also more than one vblank has passed.
1963 *
1964 * For the former case of modeswitching, it is possible
1965 * to switch between two FBC valid configurations
1966 * instantaneously so we do need to disable the FBC
1967 * before we can modify its control registers. We also
1968 * have to wait for the next vblank for that to take
1969 * effect. However, since we delay enabling FBC we can
1970 * assume that a vblank has passed since disabling and
1971 * that we can safely alter the registers in the deferred
1972 * callback.
1973 *
1974 * In the scenario that we go from a valid to invalid
1975 * and then back to valid FBC configuration we have
1976 * no strict enforcement that a vblank occurred since
1977 * disabling the FBC. However, along all current pipe
1978 * disabling paths we do need to wait for a vblank at
1979 * some point. And we wait before enabling FBC anyway.
1980 */
1981 DRM_DEBUG_KMS("disabling active FBC for update\n");
1982 intel_disable_fbc(dev);
1983 }
1984
1985 intel_enable_fbc(crtc, 500);
1986 return;
1987
1988 out_disable:
1989 /* Multiple disables should be harmless */
1990 if (intel_fbc_enabled(dev)) {
1991 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1992 intel_disable_fbc(dev);
1993 }
1994 }
1995
1996 int
1997 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1998 struct drm_i915_gem_object *obj,
1999 struct intel_ring_buffer *pipelined)
2000 {
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 u32 alignment;
2003 int ret;
2004
2005 switch (obj->tiling_mode) {
2006 case I915_TILING_NONE:
2007 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2008 alignment = 128 * 1024;
2009 else if (INTEL_INFO(dev)->gen >= 4)
2010 alignment = 4 * 1024;
2011 else
2012 alignment = 64 * 1024;
2013 break;
2014 case I915_TILING_X:
2015 /* pin() will align the object as required by fence */
2016 alignment = 0;
2017 break;
2018 case I915_TILING_Y:
2019 /* FIXME: Is this true? */
2020 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2021 return -EINVAL;
2022 default:
2023 BUG();
2024 }
2025
2026 dev_priv->mm.interruptible = false;
2027 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2028 if (ret)
2029 goto err_interruptible;
2030
2031 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2032 * fence, whereas 965+ only requires a fence if using
2033 * framebuffer compression. For simplicity, we always install
2034 * a fence as the cost is not that onerous.
2035 */
2036 if (obj->tiling_mode != I915_TILING_NONE) {
2037 ret = i915_gem_object_get_fence(obj, pipelined);
2038 if (ret)
2039 goto err_unpin;
2040 }
2041
2042 dev_priv->mm.interruptible = true;
2043 return 0;
2044
2045 err_unpin:
2046 i915_gem_object_unpin(obj);
2047 err_interruptible:
2048 dev_priv->mm.interruptible = true;
2049 return ret;
2050 }
2051
2052 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2053 int x, int y)
2054 {
2055 struct drm_device *dev = crtc->dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2058 struct intel_framebuffer *intel_fb;
2059 struct drm_i915_gem_object *obj;
2060 int plane = intel_crtc->plane;
2061 unsigned long Start, Offset;
2062 u32 dspcntr;
2063 u32 reg;
2064
2065 switch (plane) {
2066 case 0:
2067 case 1:
2068 break;
2069 default:
2070 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2071 return -EINVAL;
2072 }
2073
2074 intel_fb = to_intel_framebuffer(fb);
2075 obj = intel_fb->obj;
2076
2077 reg = DSPCNTR(plane);
2078 dspcntr = I915_READ(reg);
2079 /* Mask out pixel format bits in case we change it */
2080 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2081 switch (fb->bits_per_pixel) {
2082 case 8:
2083 dspcntr |= DISPPLANE_8BPP;
2084 break;
2085 case 16:
2086 if (fb->depth == 15)
2087 dspcntr |= DISPPLANE_15_16BPP;
2088 else
2089 dspcntr |= DISPPLANE_16BPP;
2090 break;
2091 case 24:
2092 case 32:
2093 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2094 break;
2095 default:
2096 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2097 return -EINVAL;
2098 }
2099 if (INTEL_INFO(dev)->gen >= 4) {
2100 if (obj->tiling_mode != I915_TILING_NONE)
2101 dspcntr |= DISPPLANE_TILED;
2102 else
2103 dspcntr &= ~DISPPLANE_TILED;
2104 }
2105
2106 I915_WRITE(reg, dspcntr);
2107
2108 Start = obj->gtt_offset;
2109 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2110
2111 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2112 Start, Offset, x, y, fb->pitches[0]);
2113 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2114 if (INTEL_INFO(dev)->gen >= 4) {
2115 I915_WRITE(DSPSURF(plane), Start);
2116 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2117 I915_WRITE(DSPADDR(plane), Offset);
2118 } else
2119 I915_WRITE(DSPADDR(plane), Start + Offset);
2120 POSTING_READ(reg);
2121
2122 return 0;
2123 }
2124
2125 static int ironlake_update_plane(struct drm_crtc *crtc,
2126 struct drm_framebuffer *fb, int x, int y)
2127 {
2128 struct drm_device *dev = crtc->dev;
2129 struct drm_i915_private *dev_priv = dev->dev_private;
2130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2131 struct intel_framebuffer *intel_fb;
2132 struct drm_i915_gem_object *obj;
2133 int plane = intel_crtc->plane;
2134 unsigned long Start, Offset;
2135 u32 dspcntr;
2136 u32 reg;
2137
2138 switch (plane) {
2139 case 0:
2140 case 1:
2141 case 2:
2142 break;
2143 default:
2144 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2145 return -EINVAL;
2146 }
2147
2148 intel_fb = to_intel_framebuffer(fb);
2149 obj = intel_fb->obj;
2150
2151 reg = DSPCNTR(plane);
2152 dspcntr = I915_READ(reg);
2153 /* Mask out pixel format bits in case we change it */
2154 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2155 switch (fb->bits_per_pixel) {
2156 case 8:
2157 dspcntr |= DISPPLANE_8BPP;
2158 break;
2159 case 16:
2160 if (fb->depth != 16)
2161 return -EINVAL;
2162
2163 dspcntr |= DISPPLANE_16BPP;
2164 break;
2165 case 24:
2166 case 32:
2167 if (fb->depth == 24)
2168 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2169 else if (fb->depth == 30)
2170 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2171 else
2172 return -EINVAL;
2173 break;
2174 default:
2175 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2176 return -EINVAL;
2177 }
2178
2179 if (obj->tiling_mode != I915_TILING_NONE)
2180 dspcntr |= DISPPLANE_TILED;
2181 else
2182 dspcntr &= ~DISPPLANE_TILED;
2183
2184 /* must disable */
2185 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2186
2187 I915_WRITE(reg, dspcntr);
2188
2189 Start = obj->gtt_offset;
2190 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2191
2192 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2193 Start, Offset, x, y, fb->pitches[0]);
2194 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2195 I915_WRITE(DSPSURF(plane), Start);
2196 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2197 I915_WRITE(DSPADDR(plane), Offset);
2198 POSTING_READ(reg);
2199
2200 return 0;
2201 }
2202
2203 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2204 static int
2205 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2206 int x, int y, enum mode_set_atomic state)
2207 {
2208 struct drm_device *dev = crtc->dev;
2209 struct drm_i915_private *dev_priv = dev->dev_private;
2210 int ret;
2211
2212 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2213 if (ret)
2214 return ret;
2215
2216 intel_update_fbc(dev);
2217 intel_increase_pllclock(crtc);
2218
2219 return 0;
2220 }
2221
2222 static int
2223 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2224 struct drm_framebuffer *old_fb)
2225 {
2226 struct drm_device *dev = crtc->dev;
2227 struct drm_i915_master_private *master_priv;
2228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2229 int ret;
2230
2231 /* no fb bound */
2232 if (!crtc->fb) {
2233 DRM_ERROR("No FB bound\n");
2234 return 0;
2235 }
2236
2237 switch (intel_crtc->plane) {
2238 case 0:
2239 case 1:
2240 break;
2241 case 2:
2242 if (IS_IVYBRIDGE(dev))
2243 break;
2244 /* fall through otherwise */
2245 default:
2246 DRM_ERROR("no plane for crtc\n");
2247 return -EINVAL;
2248 }
2249
2250 mutex_lock(&dev->struct_mutex);
2251 ret = intel_pin_and_fence_fb_obj(dev,
2252 to_intel_framebuffer(crtc->fb)->obj,
2253 NULL);
2254 if (ret != 0) {
2255 mutex_unlock(&dev->struct_mutex);
2256 DRM_ERROR("pin & fence failed\n");
2257 return ret;
2258 }
2259
2260 if (old_fb) {
2261 struct drm_i915_private *dev_priv = dev->dev_private;
2262 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2263
2264 wait_event(dev_priv->pending_flip_queue,
2265 atomic_read(&dev_priv->mm.wedged) ||
2266 atomic_read(&obj->pending_flip) == 0);
2267
2268 /* Big Hammer, we also need to ensure that any pending
2269 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2270 * current scanout is retired before unpinning the old
2271 * framebuffer.
2272 *
2273 * This should only fail upon a hung GPU, in which case we
2274 * can safely continue.
2275 */
2276 ret = i915_gem_object_finish_gpu(obj);
2277 (void) ret;
2278 }
2279
2280 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2281 LEAVE_ATOMIC_MODE_SET);
2282 if (ret) {
2283 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2284 mutex_unlock(&dev->struct_mutex);
2285 DRM_ERROR("failed to update base address\n");
2286 return ret;
2287 }
2288
2289 if (old_fb) {
2290 intel_wait_for_vblank(dev, intel_crtc->pipe);
2291 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
2292 }
2293
2294 mutex_unlock(&dev->struct_mutex);
2295
2296 if (!dev->primary->master)
2297 return 0;
2298
2299 master_priv = dev->primary->master->driver_priv;
2300 if (!master_priv->sarea_priv)
2301 return 0;
2302
2303 if (intel_crtc->pipe) {
2304 master_priv->sarea_priv->pipeB_x = x;
2305 master_priv->sarea_priv->pipeB_y = y;
2306 } else {
2307 master_priv->sarea_priv->pipeA_x = x;
2308 master_priv->sarea_priv->pipeA_y = y;
2309 }
2310
2311 return 0;
2312 }
2313
2314 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2315 {
2316 struct drm_device *dev = crtc->dev;
2317 struct drm_i915_private *dev_priv = dev->dev_private;
2318 u32 dpa_ctl;
2319
2320 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2321 dpa_ctl = I915_READ(DP_A);
2322 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2323
2324 if (clock < 200000) {
2325 u32 temp;
2326 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2327 /* workaround for 160Mhz:
2328 1) program 0x4600c bits 15:0 = 0x8124
2329 2) program 0x46010 bit 0 = 1
2330 3) program 0x46034 bit 24 = 1
2331 4) program 0x64000 bit 14 = 1
2332 */
2333 temp = I915_READ(0x4600c);
2334 temp &= 0xffff0000;
2335 I915_WRITE(0x4600c, temp | 0x8124);
2336
2337 temp = I915_READ(0x46010);
2338 I915_WRITE(0x46010, temp | 1);
2339
2340 temp = I915_READ(0x46034);
2341 I915_WRITE(0x46034, temp | (1 << 24));
2342 } else {
2343 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2344 }
2345 I915_WRITE(DP_A, dpa_ctl);
2346
2347 POSTING_READ(DP_A);
2348 udelay(500);
2349 }
2350
2351 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2352 {
2353 struct drm_device *dev = crtc->dev;
2354 struct drm_i915_private *dev_priv = dev->dev_private;
2355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2356 int pipe = intel_crtc->pipe;
2357 u32 reg, temp;
2358
2359 /* enable normal train */
2360 reg = FDI_TX_CTL(pipe);
2361 temp = I915_READ(reg);
2362 if (IS_IVYBRIDGE(dev)) {
2363 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2364 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2365 } else {
2366 temp &= ~FDI_LINK_TRAIN_NONE;
2367 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2368 }
2369 I915_WRITE(reg, temp);
2370
2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
2373 if (HAS_PCH_CPT(dev)) {
2374 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2375 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2376 } else {
2377 temp &= ~FDI_LINK_TRAIN_NONE;
2378 temp |= FDI_LINK_TRAIN_NONE;
2379 }
2380 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2381
2382 /* wait one idle pattern time */
2383 POSTING_READ(reg);
2384 udelay(1000);
2385
2386 /* IVB wants error correction enabled */
2387 if (IS_IVYBRIDGE(dev))
2388 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2389 FDI_FE_ERRC_ENABLE);
2390 }
2391
2392 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2393 {
2394 struct drm_i915_private *dev_priv = dev->dev_private;
2395 u32 flags = I915_READ(SOUTH_CHICKEN1);
2396
2397 flags |= FDI_PHASE_SYNC_OVR(pipe);
2398 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2399 flags |= FDI_PHASE_SYNC_EN(pipe);
2400 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2401 POSTING_READ(SOUTH_CHICKEN1);
2402 }
2403
2404 /* The FDI link training functions for ILK/Ibexpeak. */
2405 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2406 {
2407 struct drm_device *dev = crtc->dev;
2408 struct drm_i915_private *dev_priv = dev->dev_private;
2409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2410 int pipe = intel_crtc->pipe;
2411 int plane = intel_crtc->plane;
2412 u32 reg, temp, tries;
2413
2414 /* FDI needs bits from pipe & plane first */
2415 assert_pipe_enabled(dev_priv, pipe);
2416 assert_plane_enabled(dev_priv, plane);
2417
2418 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2419 for train result */
2420 reg = FDI_RX_IMR(pipe);
2421 temp = I915_READ(reg);
2422 temp &= ~FDI_RX_SYMBOL_LOCK;
2423 temp &= ~FDI_RX_BIT_LOCK;
2424 I915_WRITE(reg, temp);
2425 I915_READ(reg);
2426 udelay(150);
2427
2428 /* enable CPU FDI TX and PCH FDI RX */
2429 reg = FDI_TX_CTL(pipe);
2430 temp = I915_READ(reg);
2431 temp &= ~(7 << 19);
2432 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_1;
2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2436
2437 reg = FDI_RX_CTL(pipe);
2438 temp = I915_READ(reg);
2439 temp &= ~FDI_LINK_TRAIN_NONE;
2440 temp |= FDI_LINK_TRAIN_PATTERN_1;
2441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2442
2443 POSTING_READ(reg);
2444 udelay(150);
2445
2446 /* Ironlake workaround, enable clock pointer after FDI enable*/
2447 if (HAS_PCH_IBX(dev)) {
2448 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2449 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2450 FDI_RX_PHASE_SYNC_POINTER_EN);
2451 }
2452
2453 reg = FDI_RX_IIR(pipe);
2454 for (tries = 0; tries < 5; tries++) {
2455 temp = I915_READ(reg);
2456 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2457
2458 if ((temp & FDI_RX_BIT_LOCK)) {
2459 DRM_DEBUG_KMS("FDI train 1 done.\n");
2460 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2461 break;
2462 }
2463 }
2464 if (tries == 5)
2465 DRM_ERROR("FDI train 1 fail!\n");
2466
2467 /* Train 2 */
2468 reg = FDI_TX_CTL(pipe);
2469 temp = I915_READ(reg);
2470 temp &= ~FDI_LINK_TRAIN_NONE;
2471 temp |= FDI_LINK_TRAIN_PATTERN_2;
2472 I915_WRITE(reg, temp);
2473
2474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
2476 temp &= ~FDI_LINK_TRAIN_NONE;
2477 temp |= FDI_LINK_TRAIN_PATTERN_2;
2478 I915_WRITE(reg, temp);
2479
2480 POSTING_READ(reg);
2481 udelay(150);
2482
2483 reg = FDI_RX_IIR(pipe);
2484 for (tries = 0; tries < 5; tries++) {
2485 temp = I915_READ(reg);
2486 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2487
2488 if (temp & FDI_RX_SYMBOL_LOCK) {
2489 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2490 DRM_DEBUG_KMS("FDI train 2 done.\n");
2491 break;
2492 }
2493 }
2494 if (tries == 5)
2495 DRM_ERROR("FDI train 2 fail!\n");
2496
2497 DRM_DEBUG_KMS("FDI train done\n");
2498
2499 }
2500
2501 static const int snb_b_fdi_train_param[] = {
2502 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2503 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2504 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2505 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2506 };
2507
2508 /* The FDI link training functions for SNB/Cougarpoint. */
2509 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2510 {
2511 struct drm_device *dev = crtc->dev;
2512 struct drm_i915_private *dev_priv = dev->dev_private;
2513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2514 int pipe = intel_crtc->pipe;
2515 u32 reg, temp, i;
2516
2517 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2518 for train result */
2519 reg = FDI_RX_IMR(pipe);
2520 temp = I915_READ(reg);
2521 temp &= ~FDI_RX_SYMBOL_LOCK;
2522 temp &= ~FDI_RX_BIT_LOCK;
2523 I915_WRITE(reg, temp);
2524
2525 POSTING_READ(reg);
2526 udelay(150);
2527
2528 /* enable CPU FDI TX and PCH FDI RX */
2529 reg = FDI_TX_CTL(pipe);
2530 temp = I915_READ(reg);
2531 temp &= ~(7 << 19);
2532 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2533 temp &= ~FDI_LINK_TRAIN_NONE;
2534 temp |= FDI_LINK_TRAIN_PATTERN_1;
2535 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536 /* SNB-B */
2537 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2538 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2539
2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
2552 udelay(150);
2553
2554 if (HAS_PCH_CPT(dev))
2555 cpt_phase_pointer_enable(dev, pipe);
2556
2557 for (i = 0; i < 4; i++) {
2558 reg = FDI_TX_CTL(pipe);
2559 temp = I915_READ(reg);
2560 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2561 temp |= snb_b_fdi_train_param[i];
2562 I915_WRITE(reg, temp);
2563
2564 POSTING_READ(reg);
2565 udelay(500);
2566
2567 reg = FDI_RX_IIR(pipe);
2568 temp = I915_READ(reg);
2569 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2570
2571 if (temp & FDI_RX_BIT_LOCK) {
2572 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2573 DRM_DEBUG_KMS("FDI train 1 done.\n");
2574 break;
2575 }
2576 }
2577 if (i == 4)
2578 DRM_ERROR("FDI train 1 fail!\n");
2579
2580 /* Train 2 */
2581 reg = FDI_TX_CTL(pipe);
2582 temp = I915_READ(reg);
2583 temp &= ~FDI_LINK_TRAIN_NONE;
2584 temp |= FDI_LINK_TRAIN_PATTERN_2;
2585 if (IS_GEN6(dev)) {
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 /* SNB-B */
2588 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2589 }
2590 I915_WRITE(reg, temp);
2591
2592 reg = FDI_RX_CTL(pipe);
2593 temp = I915_READ(reg);
2594 if (HAS_PCH_CPT(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2597 } else {
2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_2;
2600 }
2601 I915_WRITE(reg, temp);
2602
2603 POSTING_READ(reg);
2604 udelay(150);
2605
2606 for (i = 0; i < 4; i++) {
2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
2614 udelay(500);
2615
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619
2620 if (temp & FDI_RX_SYMBOL_LOCK) {
2621 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2622 DRM_DEBUG_KMS("FDI train 2 done.\n");
2623 break;
2624 }
2625 }
2626 if (i == 4)
2627 DRM_ERROR("FDI train 2 fail!\n");
2628
2629 DRM_DEBUG_KMS("FDI train done.\n");
2630 }
2631
2632 /* Manual link training for Ivy Bridge A0 parts */
2633 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2634 {
2635 struct drm_device *dev = crtc->dev;
2636 struct drm_i915_private *dev_priv = dev->dev_private;
2637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2638 int pipe = intel_crtc->pipe;
2639 u32 reg, temp, i;
2640
2641 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2642 for train result */
2643 reg = FDI_RX_IMR(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_RX_SYMBOL_LOCK;
2646 temp &= ~FDI_RX_BIT_LOCK;
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(150);
2651
2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~(7 << 19);
2656 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2661 temp |= FDI_COMPOSITE_SYNC;
2662 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2663
2664 reg = FDI_RX_CTL(pipe);
2665 temp = I915_READ(reg);
2666 temp &= ~FDI_LINK_TRAIN_AUTO;
2667 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2668 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2669 temp |= FDI_COMPOSITE_SYNC;
2670 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2671
2672 POSTING_READ(reg);
2673 udelay(150);
2674
2675 if (HAS_PCH_CPT(dev))
2676 cpt_phase_pointer_enable(dev, pipe);
2677
2678 for (i = 0; i < 4; i++) {
2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682 temp |= snb_b_fdi_train_param[i];
2683 I915_WRITE(reg, temp);
2684
2685 POSTING_READ(reg);
2686 udelay(500);
2687
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691
2692 if (temp & FDI_RX_BIT_LOCK ||
2693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2695 DRM_DEBUG_KMS("FDI train 1 done.\n");
2696 break;
2697 }
2698 }
2699 if (i == 4)
2700 DRM_ERROR("FDI train 1 fail!\n");
2701
2702 /* Train 2 */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709 I915_WRITE(reg, temp);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715 I915_WRITE(reg, temp);
2716
2717 POSTING_READ(reg);
2718 udelay(150);
2719
2720 for (i = 0; i < 4; i++) {
2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= snb_b_fdi_train_param[i];
2725 I915_WRITE(reg, temp);
2726
2727 POSTING_READ(reg);
2728 udelay(500);
2729
2730 reg = FDI_RX_IIR(pipe);
2731 temp = I915_READ(reg);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2733
2734 if (temp & FDI_RX_SYMBOL_LOCK) {
2735 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2736 DRM_DEBUG_KMS("FDI train 2 done.\n");
2737 break;
2738 }
2739 }
2740 if (i == 4)
2741 DRM_ERROR("FDI train 2 fail!\n");
2742
2743 DRM_DEBUG_KMS("FDI train done.\n");
2744 }
2745
2746 static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2747 {
2748 struct drm_device *dev = crtc->dev;
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2751 int pipe = intel_crtc->pipe;
2752 u32 reg, temp;
2753
2754 /* Write the TU size bits so error detection works */
2755 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2756 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2757
2758 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2759 reg = FDI_RX_CTL(pipe);
2760 temp = I915_READ(reg);
2761 temp &= ~((0x7 << 19) | (0x7 << 16));
2762 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2763 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2764 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2765
2766 POSTING_READ(reg);
2767 udelay(200);
2768
2769 /* Switch from Rawclk to PCDclk */
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp | FDI_PCDCLK);
2772
2773 POSTING_READ(reg);
2774 udelay(200);
2775
2776 /* Enable CPU FDI TX PLL, always on for Ironlake */
2777 reg = FDI_TX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2780 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2781
2782 POSTING_READ(reg);
2783 udelay(100);
2784 }
2785 }
2786
2787 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2788 {
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 u32 flags = I915_READ(SOUTH_CHICKEN1);
2791
2792 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2794 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2795 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2796 POSTING_READ(SOUTH_CHICKEN1);
2797 }
2798 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2799 {
2800 struct drm_device *dev = crtc->dev;
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2803 int pipe = intel_crtc->pipe;
2804 u32 reg, temp;
2805
2806 /* disable CPU FDI tx and PCH FDI rx */
2807 reg = FDI_TX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2810 POSTING_READ(reg);
2811
2812 reg = FDI_RX_CTL(pipe);
2813 temp = I915_READ(reg);
2814 temp &= ~(0x7 << 16);
2815 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2816 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2817
2818 POSTING_READ(reg);
2819 udelay(100);
2820
2821 /* Ironlake workaround, disable clock pointer after downing FDI */
2822 if (HAS_PCH_IBX(dev)) {
2823 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2824 I915_WRITE(FDI_RX_CHICKEN(pipe),
2825 I915_READ(FDI_RX_CHICKEN(pipe) &
2826 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2827 } else if (HAS_PCH_CPT(dev)) {
2828 cpt_phase_pointer_disable(dev, pipe);
2829 }
2830
2831 /* still set train pattern 1 */
2832 reg = FDI_TX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 temp &= ~FDI_LINK_TRAIN_NONE;
2835 temp |= FDI_LINK_TRAIN_PATTERN_1;
2836 I915_WRITE(reg, temp);
2837
2838 reg = FDI_RX_CTL(pipe);
2839 temp = I915_READ(reg);
2840 if (HAS_PCH_CPT(dev)) {
2841 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2842 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2843 } else {
2844 temp &= ~FDI_LINK_TRAIN_NONE;
2845 temp |= FDI_LINK_TRAIN_PATTERN_1;
2846 }
2847 /* BPC in FDI rx is consistent with that in PIPECONF */
2848 temp &= ~(0x07 << 16);
2849 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2850 I915_WRITE(reg, temp);
2851
2852 POSTING_READ(reg);
2853 udelay(100);
2854 }
2855
2856 /*
2857 * When we disable a pipe, we need to clear any pending scanline wait events
2858 * to avoid hanging the ring, which we assume we are waiting on.
2859 */
2860 static void intel_clear_scanline_wait(struct drm_device *dev)
2861 {
2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 struct intel_ring_buffer *ring;
2864 u32 tmp;
2865
2866 if (IS_GEN2(dev))
2867 /* Can't break the hang on i8xx */
2868 return;
2869
2870 ring = LP_RING(dev_priv);
2871 tmp = I915_READ_CTL(ring);
2872 if (tmp & RING_WAIT)
2873 I915_WRITE_CTL(ring, tmp);
2874 }
2875
2876 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2877 {
2878 struct drm_i915_gem_object *obj;
2879 struct drm_i915_private *dev_priv;
2880
2881 if (crtc->fb == NULL)
2882 return;
2883
2884 obj = to_intel_framebuffer(crtc->fb)->obj;
2885 dev_priv = crtc->dev->dev_private;
2886 wait_event(dev_priv->pending_flip_queue,
2887 atomic_read(&obj->pending_flip) == 0);
2888 }
2889
2890 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2891 {
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_mode_config *mode_config = &dev->mode_config;
2894 struct intel_encoder *encoder;
2895
2896 /*
2897 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2898 * must be driven by its own crtc; no sharing is possible.
2899 */
2900 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2901 if (encoder->base.crtc != crtc)
2902 continue;
2903
2904 switch (encoder->type) {
2905 case INTEL_OUTPUT_EDP:
2906 if (!intel_encoder_is_pch_edp(&encoder->base))
2907 return false;
2908 continue;
2909 }
2910 }
2911
2912 return true;
2913 }
2914
2915 /*
2916 * Enable PCH resources required for PCH ports:
2917 * - PCH PLLs
2918 * - FDI training & RX/TX
2919 * - update transcoder timings
2920 * - DP transcoding bits
2921 * - transcoder
2922 */
2923 static void ironlake_pch_enable(struct drm_crtc *crtc)
2924 {
2925 struct drm_device *dev = crtc->dev;
2926 struct drm_i915_private *dev_priv = dev->dev_private;
2927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2928 int pipe = intel_crtc->pipe;
2929 u32 reg, temp, transc_sel;
2930
2931 /* For PCH output, training FDI link */
2932 dev_priv->display.fdi_link_train(crtc);
2933
2934 intel_enable_pch_pll(dev_priv, pipe);
2935
2936 if (HAS_PCH_CPT(dev)) {
2937 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2938 TRANSC_DPLLB_SEL;
2939
2940 /* Be sure PCH DPLL SEL is set */
2941 temp = I915_READ(PCH_DPLL_SEL);
2942 if (pipe == 0) {
2943 temp &= ~(TRANSA_DPLLB_SEL);
2944 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2945 } else if (pipe == 1) {
2946 temp &= ~(TRANSB_DPLLB_SEL);
2947 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2948 } else if (pipe == 2) {
2949 temp &= ~(TRANSC_DPLLB_SEL);
2950 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
2951 }
2952 I915_WRITE(PCH_DPLL_SEL, temp);
2953 }
2954
2955 /* set transcoder timing, panel must allow it */
2956 assert_panel_unlocked(dev_priv, pipe);
2957 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2958 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2959 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2960
2961 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2962 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2963 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2964
2965 intel_fdi_normal_train(crtc);
2966
2967 /* For PCH DP, enable TRANS_DP_CTL */
2968 if (HAS_PCH_CPT(dev) &&
2969 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2970 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2971 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
2972 reg = TRANS_DP_CTL(pipe);
2973 temp = I915_READ(reg);
2974 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2975 TRANS_DP_SYNC_MASK |
2976 TRANS_DP_BPC_MASK);
2977 temp |= (TRANS_DP_OUTPUT_ENABLE |
2978 TRANS_DP_ENH_FRAMING);
2979 temp |= bpc << 9; /* same format but at 11:9 */
2980
2981 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2982 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2983 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2984 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2985
2986 switch (intel_trans_dp_port_sel(crtc)) {
2987 case PCH_DP_B:
2988 temp |= TRANS_DP_PORT_SEL_B;
2989 break;
2990 case PCH_DP_C:
2991 temp |= TRANS_DP_PORT_SEL_C;
2992 break;
2993 case PCH_DP_D:
2994 temp |= TRANS_DP_PORT_SEL_D;
2995 break;
2996 default:
2997 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2998 temp |= TRANS_DP_PORT_SEL_B;
2999 break;
3000 }
3001
3002 I915_WRITE(reg, temp);
3003 }
3004
3005 intel_enable_transcoder(dev_priv, pipe);
3006 }
3007
3008 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3009 {
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3012 u32 temp;
3013
3014 temp = I915_READ(dslreg);
3015 udelay(500);
3016 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3017 /* Without this, mode sets may fail silently on FDI */
3018 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3019 udelay(250);
3020 I915_WRITE(tc2reg, 0);
3021 if (wait_for(I915_READ(dslreg) != temp, 5))
3022 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3023 }
3024 }
3025
3026 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3027 {
3028 struct drm_device *dev = crtc->dev;
3029 struct drm_i915_private *dev_priv = dev->dev_private;
3030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3031 int pipe = intel_crtc->pipe;
3032 int plane = intel_crtc->plane;
3033 u32 temp;
3034 bool is_pch_port;
3035
3036 if (intel_crtc->active)
3037 return;
3038
3039 intel_crtc->active = true;
3040 intel_update_watermarks(dev);
3041
3042 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3043 temp = I915_READ(PCH_LVDS);
3044 if ((temp & LVDS_PORT_EN) == 0)
3045 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3046 }
3047
3048 is_pch_port = intel_crtc_driving_pch(crtc);
3049
3050 if (is_pch_port)
3051 ironlake_fdi_pll_enable(crtc);
3052 else
3053 ironlake_fdi_disable(crtc);
3054
3055 /* Enable panel fitting for LVDS */
3056 if (dev_priv->pch_pf_size &&
3057 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3058 /* Force use of hard-coded filter coefficients
3059 * as some pre-programmed values are broken,
3060 * e.g. x201.
3061 */
3062 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3063 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3064 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3065 }
3066
3067 /*
3068 * On ILK+ LUT must be loaded before the pipe is running but with
3069 * clocks enabled
3070 */
3071 intel_crtc_load_lut(crtc);
3072
3073 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3074 intel_enable_plane(dev_priv, plane, pipe);
3075
3076 if (is_pch_port)
3077 ironlake_pch_enable(crtc);
3078
3079 mutex_lock(&dev->struct_mutex);
3080 intel_update_fbc(dev);
3081 mutex_unlock(&dev->struct_mutex);
3082
3083 intel_crtc_update_cursor(crtc, true);
3084 }
3085
3086 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3087 {
3088 struct drm_device *dev = crtc->dev;
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3091 int pipe = intel_crtc->pipe;
3092 int plane = intel_crtc->plane;
3093 u32 reg, temp;
3094
3095 if (!intel_crtc->active)
3096 return;
3097
3098 intel_crtc_wait_for_pending_flips(crtc);
3099 drm_vblank_off(dev, pipe);
3100 intel_crtc_update_cursor(crtc, false);
3101
3102 intel_disable_plane(dev_priv, plane, pipe);
3103
3104 if (dev_priv->cfb_plane == plane)
3105 intel_disable_fbc(dev);
3106
3107 intel_disable_pipe(dev_priv, pipe);
3108
3109 /* Disable PF */
3110 I915_WRITE(PF_CTL(pipe), 0);
3111 I915_WRITE(PF_WIN_SZ(pipe), 0);
3112
3113 ironlake_fdi_disable(crtc);
3114
3115 /* This is a horrible layering violation; we should be doing this in
3116 * the connector/encoder ->prepare instead, but we don't always have
3117 * enough information there about the config to know whether it will
3118 * actually be necessary or just cause undesired flicker.
3119 */
3120 intel_disable_pch_ports(dev_priv, pipe);
3121
3122 intel_disable_transcoder(dev_priv, pipe);
3123
3124 if (HAS_PCH_CPT(dev)) {
3125 /* disable TRANS_DP_CTL */
3126 reg = TRANS_DP_CTL(pipe);
3127 temp = I915_READ(reg);
3128 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3129 temp |= TRANS_DP_PORT_SEL_NONE;
3130 I915_WRITE(reg, temp);
3131
3132 /* disable DPLL_SEL */
3133 temp = I915_READ(PCH_DPLL_SEL);
3134 switch (pipe) {
3135 case 0:
3136 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3137 break;
3138 case 1:
3139 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3140 break;
3141 case 2:
3142 /* C shares PLL A or B */
3143 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3144 break;
3145 default:
3146 BUG(); /* wtf */
3147 }
3148 I915_WRITE(PCH_DPLL_SEL, temp);
3149 }
3150
3151 /* disable PCH DPLL */
3152 if (!intel_crtc->no_pll)
3153 intel_disable_pch_pll(dev_priv, pipe);
3154
3155 /* Switch from PCDclk to Rawclk */
3156 reg = FDI_RX_CTL(pipe);
3157 temp = I915_READ(reg);
3158 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3159
3160 /* Disable CPU FDI TX PLL */
3161 reg = FDI_TX_CTL(pipe);
3162 temp = I915_READ(reg);
3163 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3164
3165 POSTING_READ(reg);
3166 udelay(100);
3167
3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3171
3172 /* Wait for the clocks to turn off. */
3173 POSTING_READ(reg);
3174 udelay(100);
3175
3176 intel_crtc->active = false;
3177 intel_update_watermarks(dev);
3178
3179 mutex_lock(&dev->struct_mutex);
3180 intel_update_fbc(dev);
3181 intel_clear_scanline_wait(dev);
3182 mutex_unlock(&dev->struct_mutex);
3183 }
3184
3185 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3186 {
3187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3188 int pipe = intel_crtc->pipe;
3189 int plane = intel_crtc->plane;
3190
3191 /* XXX: When our outputs are all unaware of DPMS modes other than off
3192 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3193 */
3194 switch (mode) {
3195 case DRM_MODE_DPMS_ON:
3196 case DRM_MODE_DPMS_STANDBY:
3197 case DRM_MODE_DPMS_SUSPEND:
3198 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3199 ironlake_crtc_enable(crtc);
3200 break;
3201
3202 case DRM_MODE_DPMS_OFF:
3203 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3204 ironlake_crtc_disable(crtc);
3205 break;
3206 }
3207 }
3208
3209 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3210 {
3211 if (!enable && intel_crtc->overlay) {
3212 struct drm_device *dev = intel_crtc->base.dev;
3213 struct drm_i915_private *dev_priv = dev->dev_private;
3214
3215 mutex_lock(&dev->struct_mutex);
3216 dev_priv->mm.interruptible = false;
3217 (void) intel_overlay_switch_off(intel_crtc->overlay);
3218 dev_priv->mm.interruptible = true;
3219 mutex_unlock(&dev->struct_mutex);
3220 }
3221
3222 /* Let userspace switch the overlay on again. In most cases userspace
3223 * has to recompute where to put it anyway.
3224 */
3225 }
3226
3227 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3228 {
3229 struct drm_device *dev = crtc->dev;
3230 struct drm_i915_private *dev_priv = dev->dev_private;
3231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3232 int pipe = intel_crtc->pipe;
3233 int plane = intel_crtc->plane;
3234
3235 if (intel_crtc->active)
3236 return;
3237
3238 intel_crtc->active = true;
3239 intel_update_watermarks(dev);
3240
3241 intel_enable_pll(dev_priv, pipe);
3242 intel_enable_pipe(dev_priv, pipe, false);
3243 intel_enable_plane(dev_priv, plane, pipe);
3244
3245 intel_crtc_load_lut(crtc);
3246 intel_update_fbc(dev);
3247
3248 /* Give the overlay scaler a chance to enable if it's on this pipe */
3249 intel_crtc_dpms_overlay(intel_crtc, true);
3250 intel_crtc_update_cursor(crtc, true);
3251 }
3252
3253 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3254 {
3255 struct drm_device *dev = crtc->dev;
3256 struct drm_i915_private *dev_priv = dev->dev_private;
3257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3258 int pipe = intel_crtc->pipe;
3259 int plane = intel_crtc->plane;
3260
3261 if (!intel_crtc->active)
3262 return;
3263
3264 /* Give the overlay scaler a chance to disable if it's on this pipe */
3265 intel_crtc_wait_for_pending_flips(crtc);
3266 drm_vblank_off(dev, pipe);
3267 intel_crtc_dpms_overlay(intel_crtc, false);
3268 intel_crtc_update_cursor(crtc, false);
3269
3270 if (dev_priv->cfb_plane == plane)
3271 intel_disable_fbc(dev);
3272
3273 intel_disable_plane(dev_priv, plane, pipe);
3274 intel_disable_pipe(dev_priv, pipe);
3275 intel_disable_pll(dev_priv, pipe);
3276
3277 intel_crtc->active = false;
3278 intel_update_fbc(dev);
3279 intel_update_watermarks(dev);
3280 intel_clear_scanline_wait(dev);
3281 }
3282
3283 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3284 {
3285 /* XXX: When our outputs are all unaware of DPMS modes other than off
3286 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3287 */
3288 switch (mode) {
3289 case DRM_MODE_DPMS_ON:
3290 case DRM_MODE_DPMS_STANDBY:
3291 case DRM_MODE_DPMS_SUSPEND:
3292 i9xx_crtc_enable(crtc);
3293 break;
3294 case DRM_MODE_DPMS_OFF:
3295 i9xx_crtc_disable(crtc);
3296 break;
3297 }
3298 }
3299
3300 /**
3301 * Sets the power management mode of the pipe and plane.
3302 */
3303 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3304 {
3305 struct drm_device *dev = crtc->dev;
3306 struct drm_i915_private *dev_priv = dev->dev_private;
3307 struct drm_i915_master_private *master_priv;
3308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3309 int pipe = intel_crtc->pipe;
3310 bool enabled;
3311
3312 if (intel_crtc->dpms_mode == mode)
3313 return;
3314
3315 intel_crtc->dpms_mode = mode;
3316
3317 dev_priv->display.dpms(crtc, mode);
3318
3319 if (!dev->primary->master)
3320 return;
3321
3322 master_priv = dev->primary->master->driver_priv;
3323 if (!master_priv->sarea_priv)
3324 return;
3325
3326 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3327
3328 switch (pipe) {
3329 case 0:
3330 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3331 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3332 break;
3333 case 1:
3334 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3335 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3336 break;
3337 default:
3338 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3339 break;
3340 }
3341 }
3342
3343 static void intel_crtc_disable(struct drm_crtc *crtc)
3344 {
3345 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3346 struct drm_device *dev = crtc->dev;
3347
3348 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3349 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3350 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3351
3352 if (crtc->fb) {
3353 mutex_lock(&dev->struct_mutex);
3354 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3355 mutex_unlock(&dev->struct_mutex);
3356 }
3357 }
3358
3359 /* Prepare for a mode set.
3360 *
3361 * Note we could be a lot smarter here. We need to figure out which outputs
3362 * will be enabled, which disabled (in short, how the config will changes)
3363 * and perform the minimum necessary steps to accomplish that, e.g. updating
3364 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3365 * panel fitting is in the proper state, etc.
3366 */
3367 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
3368 {
3369 i9xx_crtc_disable(crtc);
3370 }
3371
3372 static void i9xx_crtc_commit(struct drm_crtc *crtc)
3373 {
3374 i9xx_crtc_enable(crtc);
3375 }
3376
3377 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3378 {
3379 ironlake_crtc_disable(crtc);
3380 }
3381
3382 static void ironlake_crtc_commit(struct drm_crtc *crtc)
3383 {
3384 ironlake_crtc_enable(crtc);
3385 }
3386
3387 void intel_encoder_prepare(struct drm_encoder *encoder)
3388 {
3389 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3390 /* lvds has its own version of prepare see intel_lvds_prepare */
3391 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3392 }
3393
3394 void intel_encoder_commit(struct drm_encoder *encoder)
3395 {
3396 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3397 struct drm_device *dev = encoder->dev;
3398 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3399 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3400
3401 /* lvds has its own version of commit see intel_lvds_commit */
3402 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3403
3404 if (HAS_PCH_CPT(dev))
3405 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3406 }
3407
3408 void intel_encoder_destroy(struct drm_encoder *encoder)
3409 {
3410 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3411
3412 drm_encoder_cleanup(encoder);
3413 kfree(intel_encoder);
3414 }
3415
3416 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3417 struct drm_display_mode *mode,
3418 struct drm_display_mode *adjusted_mode)
3419 {
3420 struct drm_device *dev = crtc->dev;
3421
3422 if (HAS_PCH_SPLIT(dev)) {
3423 /* FDI link clock is fixed at 2.7G */
3424 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3425 return false;
3426 }
3427
3428 /* XXX some encoders set the crtcinfo, others don't.
3429 * Obviously we need some form of conflict resolution here...
3430 */
3431 if (adjusted_mode->crtc_htotal == 0)
3432 drm_mode_set_crtcinfo(adjusted_mode, 0);
3433
3434 return true;
3435 }
3436
3437 static int i945_get_display_clock_speed(struct drm_device *dev)
3438 {
3439 return 400000;
3440 }
3441
3442 static int i915_get_display_clock_speed(struct drm_device *dev)
3443 {
3444 return 333000;
3445 }
3446
3447 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3448 {
3449 return 200000;
3450 }
3451
3452 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3453 {
3454 u16 gcfgc = 0;
3455
3456 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3457
3458 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3459 return 133000;
3460 else {
3461 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3462 case GC_DISPLAY_CLOCK_333_MHZ:
3463 return 333000;
3464 default:
3465 case GC_DISPLAY_CLOCK_190_200_MHZ:
3466 return 190000;
3467 }
3468 }
3469 }
3470
3471 static int i865_get_display_clock_speed(struct drm_device *dev)
3472 {
3473 return 266000;
3474 }
3475
3476 static int i855_get_display_clock_speed(struct drm_device *dev)
3477 {
3478 u16 hpllcc = 0;
3479 /* Assume that the hardware is in the high speed state. This
3480 * should be the default.
3481 */
3482 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3483 case GC_CLOCK_133_200:
3484 case GC_CLOCK_100_200:
3485 return 200000;
3486 case GC_CLOCK_166_250:
3487 return 250000;
3488 case GC_CLOCK_100_133:
3489 return 133000;
3490 }
3491
3492 /* Shouldn't happen */
3493 return 0;
3494 }
3495
3496 static int i830_get_display_clock_speed(struct drm_device *dev)
3497 {
3498 return 133000;
3499 }
3500
3501 struct fdi_m_n {
3502 u32 tu;
3503 u32 gmch_m;
3504 u32 gmch_n;
3505 u32 link_m;
3506 u32 link_n;
3507 };
3508
3509 static void
3510 fdi_reduce_ratio(u32 *num, u32 *den)
3511 {
3512 while (*num > 0xffffff || *den > 0xffffff) {
3513 *num >>= 1;
3514 *den >>= 1;
3515 }
3516 }
3517
3518 static void
3519 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3520 int link_clock, struct fdi_m_n *m_n)
3521 {
3522 m_n->tu = 64; /* default size */
3523
3524 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3525 m_n->gmch_m = bits_per_pixel * pixel_clock;
3526 m_n->gmch_n = link_clock * nlanes * 8;
3527 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3528
3529 m_n->link_m = pixel_clock;
3530 m_n->link_n = link_clock;
3531 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3532 }
3533
3534
3535 struct intel_watermark_params {
3536 unsigned long fifo_size;
3537 unsigned long max_wm;
3538 unsigned long default_wm;
3539 unsigned long guard_size;
3540 unsigned long cacheline_size;
3541 };
3542
3543 /* Pineview has different values for various configs */
3544 static const struct intel_watermark_params pineview_display_wm = {
3545 PINEVIEW_DISPLAY_FIFO,
3546 PINEVIEW_MAX_WM,
3547 PINEVIEW_DFT_WM,
3548 PINEVIEW_GUARD_WM,
3549 PINEVIEW_FIFO_LINE_SIZE
3550 };
3551 static const struct intel_watermark_params pineview_display_hplloff_wm = {
3552 PINEVIEW_DISPLAY_FIFO,
3553 PINEVIEW_MAX_WM,
3554 PINEVIEW_DFT_HPLLOFF_WM,
3555 PINEVIEW_GUARD_WM,
3556 PINEVIEW_FIFO_LINE_SIZE
3557 };
3558 static const struct intel_watermark_params pineview_cursor_wm = {
3559 PINEVIEW_CURSOR_FIFO,
3560 PINEVIEW_CURSOR_MAX_WM,
3561 PINEVIEW_CURSOR_DFT_WM,
3562 PINEVIEW_CURSOR_GUARD_WM,
3563 PINEVIEW_FIFO_LINE_SIZE,
3564 };
3565 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
3566 PINEVIEW_CURSOR_FIFO,
3567 PINEVIEW_CURSOR_MAX_WM,
3568 PINEVIEW_CURSOR_DFT_WM,
3569 PINEVIEW_CURSOR_GUARD_WM,
3570 PINEVIEW_FIFO_LINE_SIZE
3571 };
3572 static const struct intel_watermark_params g4x_wm_info = {
3573 G4X_FIFO_SIZE,
3574 G4X_MAX_WM,
3575 G4X_MAX_WM,
3576 2,
3577 G4X_FIFO_LINE_SIZE,
3578 };
3579 static const struct intel_watermark_params g4x_cursor_wm_info = {
3580 I965_CURSOR_FIFO,
3581 I965_CURSOR_MAX_WM,
3582 I965_CURSOR_DFT_WM,
3583 2,
3584 G4X_FIFO_LINE_SIZE,
3585 };
3586 static const struct intel_watermark_params i965_cursor_wm_info = {
3587 I965_CURSOR_FIFO,
3588 I965_CURSOR_MAX_WM,
3589 I965_CURSOR_DFT_WM,
3590 2,
3591 I915_FIFO_LINE_SIZE,
3592 };
3593 static const struct intel_watermark_params i945_wm_info = {
3594 I945_FIFO_SIZE,
3595 I915_MAX_WM,
3596 1,
3597 2,
3598 I915_FIFO_LINE_SIZE
3599 };
3600 static const struct intel_watermark_params i915_wm_info = {
3601 I915_FIFO_SIZE,
3602 I915_MAX_WM,
3603 1,
3604 2,
3605 I915_FIFO_LINE_SIZE
3606 };
3607 static const struct intel_watermark_params i855_wm_info = {
3608 I855GM_FIFO_SIZE,
3609 I915_MAX_WM,
3610 1,
3611 2,
3612 I830_FIFO_LINE_SIZE
3613 };
3614 static const struct intel_watermark_params i830_wm_info = {
3615 I830_FIFO_SIZE,
3616 I915_MAX_WM,
3617 1,
3618 2,
3619 I830_FIFO_LINE_SIZE
3620 };
3621
3622 static const struct intel_watermark_params ironlake_display_wm_info = {
3623 ILK_DISPLAY_FIFO,
3624 ILK_DISPLAY_MAXWM,
3625 ILK_DISPLAY_DFTWM,
3626 2,
3627 ILK_FIFO_LINE_SIZE
3628 };
3629 static const struct intel_watermark_params ironlake_cursor_wm_info = {
3630 ILK_CURSOR_FIFO,
3631 ILK_CURSOR_MAXWM,
3632 ILK_CURSOR_DFTWM,
3633 2,
3634 ILK_FIFO_LINE_SIZE
3635 };
3636 static const struct intel_watermark_params ironlake_display_srwm_info = {
3637 ILK_DISPLAY_SR_FIFO,
3638 ILK_DISPLAY_MAX_SRWM,
3639 ILK_DISPLAY_DFT_SRWM,
3640 2,
3641 ILK_FIFO_LINE_SIZE
3642 };
3643 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
3644 ILK_CURSOR_SR_FIFO,
3645 ILK_CURSOR_MAX_SRWM,
3646 ILK_CURSOR_DFT_SRWM,
3647 2,
3648 ILK_FIFO_LINE_SIZE
3649 };
3650
3651 static const struct intel_watermark_params sandybridge_display_wm_info = {
3652 SNB_DISPLAY_FIFO,
3653 SNB_DISPLAY_MAXWM,
3654 SNB_DISPLAY_DFTWM,
3655 2,
3656 SNB_FIFO_LINE_SIZE
3657 };
3658 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
3659 SNB_CURSOR_FIFO,
3660 SNB_CURSOR_MAXWM,
3661 SNB_CURSOR_DFTWM,
3662 2,
3663 SNB_FIFO_LINE_SIZE
3664 };
3665 static const struct intel_watermark_params sandybridge_display_srwm_info = {
3666 SNB_DISPLAY_SR_FIFO,
3667 SNB_DISPLAY_MAX_SRWM,
3668 SNB_DISPLAY_DFT_SRWM,
3669 2,
3670 SNB_FIFO_LINE_SIZE
3671 };
3672 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
3673 SNB_CURSOR_SR_FIFO,
3674 SNB_CURSOR_MAX_SRWM,
3675 SNB_CURSOR_DFT_SRWM,
3676 2,
3677 SNB_FIFO_LINE_SIZE
3678 };
3679
3680
3681 /**
3682 * intel_calculate_wm - calculate watermark level
3683 * @clock_in_khz: pixel clock
3684 * @wm: chip FIFO params
3685 * @pixel_size: display pixel size
3686 * @latency_ns: memory latency for the platform
3687 *
3688 * Calculate the watermark level (the level at which the display plane will
3689 * start fetching from memory again). Each chip has a different display
3690 * FIFO size and allocation, so the caller needs to figure that out and pass
3691 * in the correct intel_watermark_params structure.
3692 *
3693 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3694 * on the pixel size. When it reaches the watermark level, it'll start
3695 * fetching FIFO line sized based chunks from memory until the FIFO fills
3696 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3697 * will occur, and a display engine hang could result.
3698 */
3699 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
3700 const struct intel_watermark_params *wm,
3701 int fifo_size,
3702 int pixel_size,
3703 unsigned long latency_ns)
3704 {
3705 long entries_required, wm_size;
3706
3707 /*
3708 * Note: we need to make sure we don't overflow for various clock &
3709 * latency values.
3710 * clocks go from a few thousand to several hundred thousand.
3711 * latency is usually a few thousand
3712 */
3713 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3714 1000;
3715 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
3716
3717 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
3718
3719 wm_size = fifo_size - (entries_required + wm->guard_size);
3720
3721 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
3722
3723 /* Don't promote wm_size to unsigned... */
3724 if (wm_size > (long)wm->max_wm)
3725 wm_size = wm->max_wm;
3726 if (wm_size <= 0)
3727 wm_size = wm->default_wm;
3728 return wm_size;
3729 }
3730
3731 struct cxsr_latency {
3732 int is_desktop;
3733 int is_ddr3;
3734 unsigned long fsb_freq;
3735 unsigned long mem_freq;
3736 unsigned long display_sr;
3737 unsigned long display_hpll_disable;
3738 unsigned long cursor_sr;
3739 unsigned long cursor_hpll_disable;
3740 };
3741
3742 static const struct cxsr_latency cxsr_latency_table[] = {
3743 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3744 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3745 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3746 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3747 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3748
3749 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3750 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3751 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3752 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3753 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3754
3755 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3756 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3757 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3758 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3759 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3760
3761 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3762 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3763 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3764 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3765 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3766
3767 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3768 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3769 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3770 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3771 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3772
3773 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3774 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3775 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3776 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3777 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3778 };
3779
3780 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3781 int is_ddr3,
3782 int fsb,
3783 int mem)
3784 {
3785 const struct cxsr_latency *latency;
3786 int i;
3787
3788 if (fsb == 0 || mem == 0)
3789 return NULL;
3790
3791 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3792 latency = &cxsr_latency_table[i];
3793 if (is_desktop == latency->is_desktop &&
3794 is_ddr3 == latency->is_ddr3 &&
3795 fsb == latency->fsb_freq && mem == latency->mem_freq)
3796 return latency;
3797 }
3798
3799 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3800
3801 return NULL;
3802 }
3803
3804 static void pineview_disable_cxsr(struct drm_device *dev)
3805 {
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3807
3808 /* deactivate cxsr */
3809 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3810 }
3811
3812 /*
3813 * Latency for FIFO fetches is dependent on several factors:
3814 * - memory configuration (speed, channels)
3815 * - chipset
3816 * - current MCH state
3817 * It can be fairly high in some situations, so here we assume a fairly
3818 * pessimal value. It's a tradeoff between extra memory fetches (if we
3819 * set this value too high, the FIFO will fetch frequently to stay full)
3820 * and power consumption (set it too low to save power and we might see
3821 * FIFO underruns and display "flicker").
3822 *
3823 * A value of 5us seems to be a good balance; safe for very low end
3824 * platforms but not overly aggressive on lower latency configs.
3825 */
3826 static const int latency_ns = 5000;
3827
3828 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3829 {
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 uint32_t dsparb = I915_READ(DSPARB);
3832 int size;
3833
3834 size = dsparb & 0x7f;
3835 if (plane)
3836 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3837
3838 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3839 plane ? "B" : "A", size);
3840
3841 return size;
3842 }
3843
3844 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3845 {
3846 struct drm_i915_private *dev_priv = dev->dev_private;
3847 uint32_t dsparb = I915_READ(DSPARB);
3848 int size;
3849
3850 size = dsparb & 0x1ff;
3851 if (plane)
3852 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3853 size >>= 1; /* Convert to cachelines */
3854
3855 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3856 plane ? "B" : "A", size);
3857
3858 return size;
3859 }
3860
3861 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3862 {
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864 uint32_t dsparb = I915_READ(DSPARB);
3865 int size;
3866
3867 size = dsparb & 0x7f;
3868 size >>= 2; /* Convert to cachelines */
3869
3870 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3871 plane ? "B" : "A",
3872 size);
3873
3874 return size;
3875 }
3876
3877 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3878 {
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 uint32_t dsparb = I915_READ(DSPARB);
3881 int size;
3882
3883 size = dsparb & 0x7f;
3884 size >>= 1; /* Convert to cachelines */
3885
3886 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3887 plane ? "B" : "A", size);
3888
3889 return size;
3890 }
3891
3892 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3893 {
3894 struct drm_crtc *crtc, *enabled = NULL;
3895
3896 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3897 if (crtc->enabled && crtc->fb) {
3898 if (enabled)
3899 return NULL;
3900 enabled = crtc;
3901 }
3902 }
3903
3904 return enabled;
3905 }
3906
3907 static void pineview_update_wm(struct drm_device *dev)
3908 {
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 struct drm_crtc *crtc;
3911 const struct cxsr_latency *latency;
3912 u32 reg;
3913 unsigned long wm;
3914
3915 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3916 dev_priv->fsb_freq, dev_priv->mem_freq);
3917 if (!latency) {
3918 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3919 pineview_disable_cxsr(dev);
3920 return;
3921 }
3922
3923 crtc = single_enabled_crtc(dev);
3924 if (crtc) {
3925 int clock = crtc->mode.clock;
3926 int pixel_size = crtc->fb->bits_per_pixel / 8;
3927
3928 /* Display SR */
3929 wm = intel_calculate_wm(clock, &pineview_display_wm,
3930 pineview_display_wm.fifo_size,
3931 pixel_size, latency->display_sr);
3932 reg = I915_READ(DSPFW1);
3933 reg &= ~DSPFW_SR_MASK;
3934 reg |= wm << DSPFW_SR_SHIFT;
3935 I915_WRITE(DSPFW1, reg);
3936 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3937
3938 /* cursor SR */
3939 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3940 pineview_display_wm.fifo_size,
3941 pixel_size, latency->cursor_sr);
3942 reg = I915_READ(DSPFW3);
3943 reg &= ~DSPFW_CURSOR_SR_MASK;
3944 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3945 I915_WRITE(DSPFW3, reg);
3946
3947 /* Display HPLL off SR */
3948 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3949 pineview_display_hplloff_wm.fifo_size,
3950 pixel_size, latency->display_hpll_disable);
3951 reg = I915_READ(DSPFW3);
3952 reg &= ~DSPFW_HPLL_SR_MASK;
3953 reg |= wm & DSPFW_HPLL_SR_MASK;
3954 I915_WRITE(DSPFW3, reg);
3955
3956 /* cursor HPLL off SR */
3957 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3958 pineview_display_hplloff_wm.fifo_size,
3959 pixel_size, latency->cursor_hpll_disable);
3960 reg = I915_READ(DSPFW3);
3961 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3962 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3963 I915_WRITE(DSPFW3, reg);
3964 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3965
3966 /* activate cxsr */
3967 I915_WRITE(DSPFW3,
3968 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3969 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3970 } else {
3971 pineview_disable_cxsr(dev);
3972 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3973 }
3974 }
3975
3976 static bool g4x_compute_wm0(struct drm_device *dev,
3977 int plane,
3978 const struct intel_watermark_params *display,
3979 int display_latency_ns,
3980 const struct intel_watermark_params *cursor,
3981 int cursor_latency_ns,
3982 int *plane_wm,
3983 int *cursor_wm)
3984 {
3985 struct drm_crtc *crtc;
3986 int htotal, hdisplay, clock, pixel_size;
3987 int line_time_us, line_count;
3988 int entries, tlb_miss;
3989
3990 crtc = intel_get_crtc_for_plane(dev, plane);
3991 if (crtc->fb == NULL || !crtc->enabled) {
3992 *cursor_wm = cursor->guard_size;
3993 *plane_wm = display->guard_size;
3994 return false;
3995 }
3996
3997 htotal = crtc->mode.htotal;
3998 hdisplay = crtc->mode.hdisplay;
3999 clock = crtc->mode.clock;
4000 pixel_size = crtc->fb->bits_per_pixel / 8;
4001
4002 /* Use the small buffer method to calculate plane watermark */
4003 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4004 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4005 if (tlb_miss > 0)
4006 entries += tlb_miss;
4007 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4008 *plane_wm = entries + display->guard_size;
4009 if (*plane_wm > (int)display->max_wm)
4010 *plane_wm = display->max_wm;
4011
4012 /* Use the large buffer method to calculate cursor watermark */
4013 line_time_us = ((htotal * 1000) / clock);
4014 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4015 entries = line_count * 64 * pixel_size;
4016 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4017 if (tlb_miss > 0)
4018 entries += tlb_miss;
4019 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4020 *cursor_wm = entries + cursor->guard_size;
4021 if (*cursor_wm > (int)cursor->max_wm)
4022 *cursor_wm = (int)cursor->max_wm;
4023
4024 return true;
4025 }
4026
4027 /*
4028 * Check the wm result.
4029 *
4030 * If any calculated watermark values is larger than the maximum value that
4031 * can be programmed into the associated watermark register, that watermark
4032 * must be disabled.
4033 */
4034 static bool g4x_check_srwm(struct drm_device *dev,
4035 int display_wm, int cursor_wm,
4036 const struct intel_watermark_params *display,
4037 const struct intel_watermark_params *cursor)
4038 {
4039 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4040 display_wm, cursor_wm);
4041
4042 if (display_wm > display->max_wm) {
4043 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4044 display_wm, display->max_wm);
4045 return false;
4046 }
4047
4048 if (cursor_wm > cursor->max_wm) {
4049 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4050 cursor_wm, cursor->max_wm);
4051 return false;
4052 }
4053
4054 if (!(display_wm || cursor_wm)) {
4055 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4056 return false;
4057 }
4058
4059 return true;
4060 }
4061
4062 static bool g4x_compute_srwm(struct drm_device *dev,
4063 int plane,
4064 int latency_ns,
4065 const struct intel_watermark_params *display,
4066 const struct intel_watermark_params *cursor,
4067 int *display_wm, int *cursor_wm)
4068 {
4069 struct drm_crtc *crtc;
4070 int hdisplay, htotal, pixel_size, clock;
4071 unsigned long line_time_us;
4072 int line_count, line_size;
4073 int small, large;
4074 int entries;
4075
4076 if (!latency_ns) {
4077 *display_wm = *cursor_wm = 0;
4078 return false;
4079 }
4080
4081 crtc = intel_get_crtc_for_plane(dev, plane);
4082 hdisplay = crtc->mode.hdisplay;
4083 htotal = crtc->mode.htotal;
4084 clock = crtc->mode.clock;
4085 pixel_size = crtc->fb->bits_per_pixel / 8;
4086
4087 line_time_us = (htotal * 1000) / clock;
4088 line_count = (latency_ns / line_time_us + 1000) / 1000;
4089 line_size = hdisplay * pixel_size;
4090
4091 /* Use the minimum of the small and large buffer method for primary */
4092 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4093 large = line_count * line_size;
4094
4095 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4096 *display_wm = entries + display->guard_size;
4097
4098 /* calculate the self-refresh watermark for display cursor */
4099 entries = line_count * pixel_size * 64;
4100 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4101 *cursor_wm = entries + cursor->guard_size;
4102
4103 return g4x_check_srwm(dev,
4104 *display_wm, *cursor_wm,
4105 display, cursor);
4106 }
4107
4108 #define single_plane_enabled(mask) is_power_of_2(mask)
4109
4110 static void g4x_update_wm(struct drm_device *dev)
4111 {
4112 static const int sr_latency_ns = 12000;
4113 struct drm_i915_private *dev_priv = dev->dev_private;
4114 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
4115 int plane_sr, cursor_sr;
4116 unsigned int enabled = 0;
4117
4118 if (g4x_compute_wm0(dev, 0,
4119 &g4x_wm_info, latency_ns,
4120 &g4x_cursor_wm_info, latency_ns,
4121 &planea_wm, &cursora_wm))
4122 enabled |= 1;
4123
4124 if (g4x_compute_wm0(dev, 1,
4125 &g4x_wm_info, latency_ns,
4126 &g4x_cursor_wm_info, latency_ns,
4127 &planeb_wm, &cursorb_wm))
4128 enabled |= 2;
4129
4130 plane_sr = cursor_sr = 0;
4131 if (single_plane_enabled(enabled) &&
4132 g4x_compute_srwm(dev, ffs(enabled) - 1,
4133 sr_latency_ns,
4134 &g4x_wm_info,
4135 &g4x_cursor_wm_info,
4136 &plane_sr, &cursor_sr))
4137 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4138 else
4139 I915_WRITE(FW_BLC_SELF,
4140 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
4141
4142 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4143 planea_wm, cursora_wm,
4144 planeb_wm, cursorb_wm,
4145 plane_sr, cursor_sr);
4146
4147 I915_WRITE(DSPFW1,
4148 (plane_sr << DSPFW_SR_SHIFT) |
4149 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
4150 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4151 planea_wm);
4152 I915_WRITE(DSPFW2,
4153 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
4154 (cursora_wm << DSPFW_CURSORA_SHIFT));
4155 /* HPLL off in SR has some issues on G4x... disable it */
4156 I915_WRITE(DSPFW3,
4157 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
4158 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4159 }
4160
4161 static void i965_update_wm(struct drm_device *dev)
4162 {
4163 struct drm_i915_private *dev_priv = dev->dev_private;
4164 struct drm_crtc *crtc;
4165 int srwm = 1;
4166 int cursor_sr = 16;
4167
4168 /* Calc sr entries for one plane configs */
4169 crtc = single_enabled_crtc(dev);
4170 if (crtc) {
4171 /* self-refresh has much higher latency */
4172 static const int sr_latency_ns = 12000;
4173 int clock = crtc->mode.clock;
4174 int htotal = crtc->mode.htotal;
4175 int hdisplay = crtc->mode.hdisplay;
4176 int pixel_size = crtc->fb->bits_per_pixel / 8;
4177 unsigned long line_time_us;
4178 int entries;
4179
4180 line_time_us = ((htotal * 1000) / clock);
4181
4182 /* Use ns/us then divide to preserve precision */
4183 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4184 pixel_size * hdisplay;
4185 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
4186 srwm = I965_FIFO_SIZE - entries;
4187 if (srwm < 0)
4188 srwm = 1;
4189 srwm &= 0x1ff;
4190 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4191 entries, srwm);
4192
4193 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4194 pixel_size * 64;
4195 entries = DIV_ROUND_UP(entries,
4196 i965_cursor_wm_info.cacheline_size);
4197 cursor_sr = i965_cursor_wm_info.fifo_size -
4198 (entries + i965_cursor_wm_info.guard_size);
4199
4200 if (cursor_sr > i965_cursor_wm_info.max_wm)
4201 cursor_sr = i965_cursor_wm_info.max_wm;
4202
4203 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4204 "cursor %d\n", srwm, cursor_sr);
4205
4206 if (IS_CRESTLINE(dev))
4207 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
4208 } else {
4209 /* Turn off self refresh if both pipes are enabled */
4210 if (IS_CRESTLINE(dev))
4211 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4212 & ~FW_BLC_SELF_EN);
4213 }
4214
4215 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4216 srwm);
4217
4218 /* 965 has limitations... */
4219 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4220 (8 << 16) | (8 << 8) | (8 << 0));
4221 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4222 /* update cursor SR watermark */
4223 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
4224 }
4225
4226 static void i9xx_update_wm(struct drm_device *dev)
4227 {
4228 struct drm_i915_private *dev_priv = dev->dev_private;
4229 const struct intel_watermark_params *wm_info;
4230 uint32_t fwater_lo;
4231 uint32_t fwater_hi;
4232 int cwm, srwm = 1;
4233 int fifo_size;
4234 int planea_wm, planeb_wm;
4235 struct drm_crtc *crtc, *enabled = NULL;
4236
4237 if (IS_I945GM(dev))
4238 wm_info = &i945_wm_info;
4239 else if (!IS_GEN2(dev))
4240 wm_info = &i915_wm_info;
4241 else
4242 wm_info = &i855_wm_info;
4243
4244 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4245 crtc = intel_get_crtc_for_plane(dev, 0);
4246 if (crtc->enabled && crtc->fb) {
4247 planea_wm = intel_calculate_wm(crtc->mode.clock,
4248 wm_info, fifo_size,
4249 crtc->fb->bits_per_pixel / 8,
4250 latency_ns);
4251 enabled = crtc;
4252 } else
4253 planea_wm = fifo_size - wm_info->guard_size;
4254
4255 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4256 crtc = intel_get_crtc_for_plane(dev, 1);
4257 if (crtc->enabled && crtc->fb) {
4258 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4259 wm_info, fifo_size,
4260 crtc->fb->bits_per_pixel / 8,
4261 latency_ns);
4262 if (enabled == NULL)
4263 enabled = crtc;
4264 else
4265 enabled = NULL;
4266 } else
4267 planeb_wm = fifo_size - wm_info->guard_size;
4268
4269 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
4270
4271 /*
4272 * Overlay gets an aggressive default since video jitter is bad.
4273 */
4274 cwm = 2;
4275
4276 /* Play safe and disable self-refresh before adjusting watermarks. */
4277 if (IS_I945G(dev) || IS_I945GM(dev))
4278 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4279 else if (IS_I915GM(dev))
4280 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4281
4282 /* Calc sr entries for one plane configs */
4283 if (HAS_FW_BLC(dev) && enabled) {
4284 /* self-refresh has much higher latency */
4285 static const int sr_latency_ns = 6000;
4286 int clock = enabled->mode.clock;
4287 int htotal = enabled->mode.htotal;
4288 int hdisplay = enabled->mode.hdisplay;
4289 int pixel_size = enabled->fb->bits_per_pixel / 8;
4290 unsigned long line_time_us;
4291 int entries;
4292
4293 line_time_us = (htotal * 1000) / clock;
4294
4295 /* Use ns/us then divide to preserve precision */
4296 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4297 pixel_size * hdisplay;
4298 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4299 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4300 srwm = wm_info->fifo_size - entries;
4301 if (srwm < 0)
4302 srwm = 1;
4303
4304 if (IS_I945G(dev) || IS_I945GM(dev))
4305 I915_WRITE(FW_BLC_SELF,
4306 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4307 else if (IS_I915GM(dev))
4308 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
4309 }
4310
4311 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4312 planea_wm, planeb_wm, cwm, srwm);
4313
4314 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4315 fwater_hi = (cwm & 0x1f);
4316
4317 /* Set request length to 8 cachelines per fetch */
4318 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4319 fwater_hi = fwater_hi | (1 << 8);
4320
4321 I915_WRITE(FW_BLC, fwater_lo);
4322 I915_WRITE(FW_BLC2, fwater_hi);
4323
4324 if (HAS_FW_BLC(dev)) {
4325 if (enabled) {
4326 if (IS_I945G(dev) || IS_I945GM(dev))
4327 I915_WRITE(FW_BLC_SELF,
4328 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4329 else if (IS_I915GM(dev))
4330 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4331 DRM_DEBUG_KMS("memory self refresh enabled\n");
4332 } else
4333 DRM_DEBUG_KMS("memory self refresh disabled\n");
4334 }
4335 }
4336
4337 static void i830_update_wm(struct drm_device *dev)
4338 {
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340 struct drm_crtc *crtc;
4341 uint32_t fwater_lo;
4342 int planea_wm;
4343
4344 crtc = single_enabled_crtc(dev);
4345 if (crtc == NULL)
4346 return;
4347
4348 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4349 dev_priv->display.get_fifo_size(dev, 0),
4350 crtc->fb->bits_per_pixel / 8,
4351 latency_ns);
4352 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
4353 fwater_lo |= (3<<8) | planea_wm;
4354
4355 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
4356
4357 I915_WRITE(FW_BLC, fwater_lo);
4358 }
4359
4360 #define ILK_LP0_PLANE_LATENCY 700
4361 #define ILK_LP0_CURSOR_LATENCY 1300
4362
4363 /*
4364 * Check the wm result.
4365 *
4366 * If any calculated watermark values is larger than the maximum value that
4367 * can be programmed into the associated watermark register, that watermark
4368 * must be disabled.
4369 */
4370 static bool ironlake_check_srwm(struct drm_device *dev, int level,
4371 int fbc_wm, int display_wm, int cursor_wm,
4372 const struct intel_watermark_params *display,
4373 const struct intel_watermark_params *cursor)
4374 {
4375 struct drm_i915_private *dev_priv = dev->dev_private;
4376
4377 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4378 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4379
4380 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4381 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4382 fbc_wm, SNB_FBC_MAX_SRWM, level);
4383
4384 /* fbc has it's own way to disable FBC WM */
4385 I915_WRITE(DISP_ARB_CTL,
4386 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4387 return false;
4388 }
4389
4390 if (display_wm > display->max_wm) {
4391 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4392 display_wm, SNB_DISPLAY_MAX_SRWM, level);
4393 return false;
4394 }
4395
4396 if (cursor_wm > cursor->max_wm) {
4397 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4398 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
4399 return false;
4400 }
4401
4402 if (!(fbc_wm || display_wm || cursor_wm)) {
4403 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4404 return false;
4405 }
4406
4407 return true;
4408 }
4409
4410 /*
4411 * Compute watermark values of WM[1-3],
4412 */
4413 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4414 int latency_ns,
4415 const struct intel_watermark_params *display,
4416 const struct intel_watermark_params *cursor,
4417 int *fbc_wm, int *display_wm, int *cursor_wm)
4418 {
4419 struct drm_crtc *crtc;
4420 unsigned long line_time_us;
4421 int hdisplay, htotal, pixel_size, clock;
4422 int line_count, line_size;
4423 int small, large;
4424 int entries;
4425
4426 if (!latency_ns) {
4427 *fbc_wm = *display_wm = *cursor_wm = 0;
4428 return false;
4429 }
4430
4431 crtc = intel_get_crtc_for_plane(dev, plane);
4432 hdisplay = crtc->mode.hdisplay;
4433 htotal = crtc->mode.htotal;
4434 clock = crtc->mode.clock;
4435 pixel_size = crtc->fb->bits_per_pixel / 8;
4436
4437 line_time_us = (htotal * 1000) / clock;
4438 line_count = (latency_ns / line_time_us + 1000) / 1000;
4439 line_size = hdisplay * pixel_size;
4440
4441 /* Use the minimum of the small and large buffer method for primary */
4442 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4443 large = line_count * line_size;
4444
4445 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4446 *display_wm = entries + display->guard_size;
4447
4448 /*
4449 * Spec says:
4450 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4451 */
4452 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4453
4454 /* calculate the self-refresh watermark for display cursor */
4455 entries = line_count * pixel_size * 64;
4456 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4457 *cursor_wm = entries + cursor->guard_size;
4458
4459 return ironlake_check_srwm(dev, level,
4460 *fbc_wm, *display_wm, *cursor_wm,
4461 display, cursor);
4462 }
4463
4464 static void ironlake_update_wm(struct drm_device *dev)
4465 {
4466 struct drm_i915_private *dev_priv = dev->dev_private;
4467 int fbc_wm, plane_wm, cursor_wm;
4468 unsigned int enabled;
4469
4470 enabled = 0;
4471 if (g4x_compute_wm0(dev, 0,
4472 &ironlake_display_wm_info,
4473 ILK_LP0_PLANE_LATENCY,
4474 &ironlake_cursor_wm_info,
4475 ILK_LP0_CURSOR_LATENCY,
4476 &plane_wm, &cursor_wm)) {
4477 I915_WRITE(WM0_PIPEA_ILK,
4478 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4479 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4480 " plane %d, " "cursor: %d\n",
4481 plane_wm, cursor_wm);
4482 enabled |= 1;
4483 }
4484
4485 if (g4x_compute_wm0(dev, 1,
4486 &ironlake_display_wm_info,
4487 ILK_LP0_PLANE_LATENCY,
4488 &ironlake_cursor_wm_info,
4489 ILK_LP0_CURSOR_LATENCY,
4490 &plane_wm, &cursor_wm)) {
4491 I915_WRITE(WM0_PIPEB_ILK,
4492 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4493 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4494 " plane %d, cursor: %d\n",
4495 plane_wm, cursor_wm);
4496 enabled |= 2;
4497 }
4498
4499 /*
4500 * Calculate and update the self-refresh watermark only when one
4501 * display plane is used.
4502 */
4503 I915_WRITE(WM3_LP_ILK, 0);
4504 I915_WRITE(WM2_LP_ILK, 0);
4505 I915_WRITE(WM1_LP_ILK, 0);
4506
4507 if (!single_plane_enabled(enabled))
4508 return;
4509 enabled = ffs(enabled) - 1;
4510
4511 /* WM1 */
4512 if (!ironlake_compute_srwm(dev, 1, enabled,
4513 ILK_READ_WM1_LATENCY() * 500,
4514 &ironlake_display_srwm_info,
4515 &ironlake_cursor_srwm_info,
4516 &fbc_wm, &plane_wm, &cursor_wm))
4517 return;
4518
4519 I915_WRITE(WM1_LP_ILK,
4520 WM1_LP_SR_EN |
4521 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4522 (fbc_wm << WM1_LP_FBC_SHIFT) |
4523 (plane_wm << WM1_LP_SR_SHIFT) |
4524 cursor_wm);
4525
4526 /* WM2 */
4527 if (!ironlake_compute_srwm(dev, 2, enabled,
4528 ILK_READ_WM2_LATENCY() * 500,
4529 &ironlake_display_srwm_info,
4530 &ironlake_cursor_srwm_info,
4531 &fbc_wm, &plane_wm, &cursor_wm))
4532 return;
4533
4534 I915_WRITE(WM2_LP_ILK,
4535 WM2_LP_EN |
4536 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4537 (fbc_wm << WM1_LP_FBC_SHIFT) |
4538 (plane_wm << WM1_LP_SR_SHIFT) |
4539 cursor_wm);
4540
4541 /*
4542 * WM3 is unsupported on ILK, probably because we don't have latency
4543 * data for that power state
4544 */
4545 }
4546
4547 void sandybridge_update_wm(struct drm_device *dev)
4548 {
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4551 int fbc_wm, plane_wm, cursor_wm;
4552 unsigned int enabled;
4553
4554 enabled = 0;
4555 if (g4x_compute_wm0(dev, 0,
4556 &sandybridge_display_wm_info, latency,
4557 &sandybridge_cursor_wm_info, latency,
4558 &plane_wm, &cursor_wm)) {
4559 I915_WRITE(WM0_PIPEA_ILK,
4560 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4561 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4562 " plane %d, " "cursor: %d\n",
4563 plane_wm, cursor_wm);
4564 enabled |= 1;
4565 }
4566
4567 if (g4x_compute_wm0(dev, 1,
4568 &sandybridge_display_wm_info, latency,
4569 &sandybridge_cursor_wm_info, latency,
4570 &plane_wm, &cursor_wm)) {
4571 I915_WRITE(WM0_PIPEB_ILK,
4572 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4573 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4574 " plane %d, cursor: %d\n",
4575 plane_wm, cursor_wm);
4576 enabled |= 2;
4577 }
4578
4579 /* IVB has 3 pipes */
4580 if (IS_IVYBRIDGE(dev) &&
4581 g4x_compute_wm0(dev, 2,
4582 &sandybridge_display_wm_info, latency,
4583 &sandybridge_cursor_wm_info, latency,
4584 &plane_wm, &cursor_wm)) {
4585 I915_WRITE(WM0_PIPEC_IVB,
4586 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4587 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4588 " plane %d, cursor: %d\n",
4589 plane_wm, cursor_wm);
4590 enabled |= 3;
4591 }
4592
4593 /*
4594 * Calculate and update the self-refresh watermark only when one
4595 * display plane is used.
4596 *
4597 * SNB support 3 levels of watermark.
4598 *
4599 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4600 * and disabled in the descending order
4601 *
4602 */
4603 I915_WRITE(WM3_LP_ILK, 0);
4604 I915_WRITE(WM2_LP_ILK, 0);
4605 I915_WRITE(WM1_LP_ILK, 0);
4606
4607 if (!single_plane_enabled(enabled) ||
4608 dev_priv->sprite_scaling_enabled)
4609 return;
4610 enabled = ffs(enabled) - 1;
4611
4612 /* WM1 */
4613 if (!ironlake_compute_srwm(dev, 1, enabled,
4614 SNB_READ_WM1_LATENCY() * 500,
4615 &sandybridge_display_srwm_info,
4616 &sandybridge_cursor_srwm_info,
4617 &fbc_wm, &plane_wm, &cursor_wm))
4618 return;
4619
4620 I915_WRITE(WM1_LP_ILK,
4621 WM1_LP_SR_EN |
4622 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4623 (fbc_wm << WM1_LP_FBC_SHIFT) |
4624 (plane_wm << WM1_LP_SR_SHIFT) |
4625 cursor_wm);
4626
4627 /* WM2 */
4628 if (!ironlake_compute_srwm(dev, 2, enabled,
4629 SNB_READ_WM2_LATENCY() * 500,
4630 &sandybridge_display_srwm_info,
4631 &sandybridge_cursor_srwm_info,
4632 &fbc_wm, &plane_wm, &cursor_wm))
4633 return;
4634
4635 I915_WRITE(WM2_LP_ILK,
4636 WM2_LP_EN |
4637 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4638 (fbc_wm << WM1_LP_FBC_SHIFT) |
4639 (plane_wm << WM1_LP_SR_SHIFT) |
4640 cursor_wm);
4641
4642 /* WM3 */
4643 if (!ironlake_compute_srwm(dev, 3, enabled,
4644 SNB_READ_WM3_LATENCY() * 500,
4645 &sandybridge_display_srwm_info,
4646 &sandybridge_cursor_srwm_info,
4647 &fbc_wm, &plane_wm, &cursor_wm))
4648 return;
4649
4650 I915_WRITE(WM3_LP_ILK,
4651 WM3_LP_EN |
4652 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4653 (fbc_wm << WM1_LP_FBC_SHIFT) |
4654 (plane_wm << WM1_LP_SR_SHIFT) |
4655 cursor_wm);
4656 }
4657
4658 static bool
4659 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4660 uint32_t sprite_width, int pixel_size,
4661 const struct intel_watermark_params *display,
4662 int display_latency_ns, int *sprite_wm)
4663 {
4664 struct drm_crtc *crtc;
4665 int clock;
4666 int entries, tlb_miss;
4667
4668 crtc = intel_get_crtc_for_plane(dev, plane);
4669 if (crtc->fb == NULL || !crtc->enabled) {
4670 *sprite_wm = display->guard_size;
4671 return false;
4672 }
4673
4674 clock = crtc->mode.clock;
4675
4676 /* Use the small buffer method to calculate the sprite watermark */
4677 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4678 tlb_miss = display->fifo_size*display->cacheline_size -
4679 sprite_width * 8;
4680 if (tlb_miss > 0)
4681 entries += tlb_miss;
4682 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4683 *sprite_wm = entries + display->guard_size;
4684 if (*sprite_wm > (int)display->max_wm)
4685 *sprite_wm = display->max_wm;
4686
4687 return true;
4688 }
4689
4690 static bool
4691 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4692 uint32_t sprite_width, int pixel_size,
4693 const struct intel_watermark_params *display,
4694 int latency_ns, int *sprite_wm)
4695 {
4696 struct drm_crtc *crtc;
4697 unsigned long line_time_us;
4698 int clock;
4699 int line_count, line_size;
4700 int small, large;
4701 int entries;
4702
4703 if (!latency_ns) {
4704 *sprite_wm = 0;
4705 return false;
4706 }
4707
4708 crtc = intel_get_crtc_for_plane(dev, plane);
4709 clock = crtc->mode.clock;
4710
4711 line_time_us = (sprite_width * 1000) / clock;
4712 line_count = (latency_ns / line_time_us + 1000) / 1000;
4713 line_size = sprite_width * pixel_size;
4714
4715 /* Use the minimum of the small and large buffer method for primary */
4716 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4717 large = line_count * line_size;
4718
4719 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4720 *sprite_wm = entries + display->guard_size;
4721
4722 return *sprite_wm > 0x3ff ? false : true;
4723 }
4724
4725 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4726 uint32_t sprite_width, int pixel_size)
4727 {
4728 struct drm_i915_private *dev_priv = dev->dev_private;
4729 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4730 int sprite_wm, reg;
4731 int ret;
4732
4733 switch (pipe) {
4734 case 0:
4735 reg = WM0_PIPEA_ILK;
4736 break;
4737 case 1:
4738 reg = WM0_PIPEB_ILK;
4739 break;
4740 case 2:
4741 reg = WM0_PIPEC_IVB;
4742 break;
4743 default:
4744 return; /* bad pipe */
4745 }
4746
4747 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4748 &sandybridge_display_wm_info,
4749 latency, &sprite_wm);
4750 if (!ret) {
4751 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4752 pipe);
4753 return;
4754 }
4755
4756 I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4757 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4758
4759
4760 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4761 pixel_size,
4762 &sandybridge_display_srwm_info,
4763 SNB_READ_WM1_LATENCY() * 500,
4764 &sprite_wm);
4765 if (!ret) {
4766 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4767 pipe);
4768 return;
4769 }
4770 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4771
4772 /* Only IVB has two more LP watermarks for sprite */
4773 if (!IS_IVYBRIDGE(dev))
4774 return;
4775
4776 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4777 pixel_size,
4778 &sandybridge_display_srwm_info,
4779 SNB_READ_WM2_LATENCY() * 500,
4780 &sprite_wm);
4781 if (!ret) {
4782 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4783 pipe);
4784 return;
4785 }
4786 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4787
4788 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4789 pixel_size,
4790 &sandybridge_display_srwm_info,
4791 SNB_READ_WM3_LATENCY() * 500,
4792 &sprite_wm);
4793 if (!ret) {
4794 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4795 pipe);
4796 return;
4797 }
4798 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4799 }
4800
4801 /**
4802 * intel_update_watermarks - update FIFO watermark values based on current modes
4803 *
4804 * Calculate watermark values for the various WM regs based on current mode
4805 * and plane configuration.
4806 *
4807 * There are several cases to deal with here:
4808 * - normal (i.e. non-self-refresh)
4809 * - self-refresh (SR) mode
4810 * - lines are large relative to FIFO size (buffer can hold up to 2)
4811 * - lines are small relative to FIFO size (buffer can hold more than 2
4812 * lines), so need to account for TLB latency
4813 *
4814 * The normal calculation is:
4815 * watermark = dotclock * bytes per pixel * latency
4816 * where latency is platform & configuration dependent (we assume pessimal
4817 * values here).
4818 *
4819 * The SR calculation is:
4820 * watermark = (trunc(latency/line time)+1) * surface width *
4821 * bytes per pixel
4822 * where
4823 * line time = htotal / dotclock
4824 * surface width = hdisplay for normal plane and 64 for cursor
4825 * and latency is assumed to be high, as above.
4826 *
4827 * The final value programmed to the register should always be rounded up,
4828 * and include an extra 2 entries to account for clock crossings.
4829 *
4830 * We don't use the sprite, so we can ignore that. And on Crestline we have
4831 * to set the non-SR watermarks to 8.
4832 */
4833 static void intel_update_watermarks(struct drm_device *dev)
4834 {
4835 struct drm_i915_private *dev_priv = dev->dev_private;
4836
4837 if (dev_priv->display.update_wm)
4838 dev_priv->display.update_wm(dev);
4839 }
4840
4841 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4842 uint32_t sprite_width, int pixel_size)
4843 {
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845
4846 if (dev_priv->display.update_sprite_wm)
4847 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4848 pixel_size);
4849 }
4850
4851 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4852 {
4853 if (i915_panel_use_ssc >= 0)
4854 return i915_panel_use_ssc != 0;
4855 return dev_priv->lvds_use_ssc
4856 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4857 }
4858
4859 /**
4860 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4861 * @crtc: CRTC structure
4862 * @mode: requested mode
4863 *
4864 * A pipe may be connected to one or more outputs. Based on the depth of the
4865 * attached framebuffer, choose a good color depth to use on the pipe.
4866 *
4867 * If possible, match the pipe depth to the fb depth. In some cases, this
4868 * isn't ideal, because the connected output supports a lesser or restricted
4869 * set of depths. Resolve that here:
4870 * LVDS typically supports only 6bpc, so clamp down in that case
4871 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4872 * Displays may support a restricted set as well, check EDID and clamp as
4873 * appropriate.
4874 * DP may want to dither down to 6bpc to fit larger modes
4875 *
4876 * RETURNS:
4877 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4878 * true if they don't match).
4879 */
4880 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4881 unsigned int *pipe_bpp,
4882 struct drm_display_mode *mode)
4883 {
4884 struct drm_device *dev = crtc->dev;
4885 struct drm_i915_private *dev_priv = dev->dev_private;
4886 struct drm_encoder *encoder;
4887 struct drm_connector *connector;
4888 unsigned int display_bpc = UINT_MAX, bpc;
4889
4890 /* Walk the encoders & connectors on this crtc, get min bpc */
4891 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4892 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4893
4894 if (encoder->crtc != crtc)
4895 continue;
4896
4897 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4898 unsigned int lvds_bpc;
4899
4900 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4901 LVDS_A3_POWER_UP)
4902 lvds_bpc = 8;
4903 else
4904 lvds_bpc = 6;
4905
4906 if (lvds_bpc < display_bpc) {
4907 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4908 display_bpc = lvds_bpc;
4909 }
4910 continue;
4911 }
4912
4913 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4914 /* Use VBT settings if we have an eDP panel */
4915 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4916
4917 if (edp_bpc < display_bpc) {
4918 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4919 display_bpc = edp_bpc;
4920 }
4921 continue;
4922 }
4923
4924 /* Not one of the known troublemakers, check the EDID */
4925 list_for_each_entry(connector, &dev->mode_config.connector_list,
4926 head) {
4927 if (connector->encoder != encoder)
4928 continue;
4929
4930 /* Don't use an invalid EDID bpc value */
4931 if (connector->display_info.bpc &&
4932 connector->display_info.bpc < display_bpc) {
4933 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4934 display_bpc = connector->display_info.bpc;
4935 }
4936 }
4937
4938 /*
4939 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4940 * through, clamp it down. (Note: >12bpc will be caught below.)
4941 */
4942 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4943 if (display_bpc > 8 && display_bpc < 12) {
4944 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4945 display_bpc = 12;
4946 } else {
4947 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4948 display_bpc = 8;
4949 }
4950 }
4951 }
4952
4953 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4954 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4955 display_bpc = 6;
4956 }
4957
4958 /*
4959 * We could just drive the pipe at the highest bpc all the time and
4960 * enable dithering as needed, but that costs bandwidth. So choose
4961 * the minimum value that expresses the full color range of the fb but
4962 * also stays within the max display bpc discovered above.
4963 */
4964
4965 switch (crtc->fb->depth) {
4966 case 8:
4967 bpc = 8; /* since we go through a colormap */
4968 break;
4969 case 15:
4970 case 16:
4971 bpc = 6; /* min is 18bpp */
4972 break;
4973 case 24:
4974 bpc = 8;
4975 break;
4976 case 30:
4977 bpc = 10;
4978 break;
4979 case 48:
4980 bpc = 12;
4981 break;
4982 default:
4983 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4984 bpc = min((unsigned int)8, display_bpc);
4985 break;
4986 }
4987
4988 display_bpc = min(display_bpc, bpc);
4989
4990 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4991 bpc, display_bpc);
4992
4993 *pipe_bpp = display_bpc * 3;
4994
4995 return display_bpc != bpc;
4996 }
4997
4998 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4999 {
5000 struct drm_device *dev = crtc->dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 int refclk;
5003
5004 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5005 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5006 refclk = dev_priv->lvds_ssc_freq * 1000;
5007 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5008 refclk / 1000);
5009 } else if (!IS_GEN2(dev)) {
5010 refclk = 96000;
5011 } else {
5012 refclk = 48000;
5013 }
5014
5015 return refclk;
5016 }
5017
5018 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5019 intel_clock_t *clock)
5020 {
5021 /* SDVO TV has fixed PLL values depend on its clock range,
5022 this mirrors vbios setting. */
5023 if (adjusted_mode->clock >= 100000
5024 && adjusted_mode->clock < 140500) {
5025 clock->p1 = 2;
5026 clock->p2 = 10;
5027 clock->n = 3;
5028 clock->m1 = 16;
5029 clock->m2 = 8;
5030 } else if (adjusted_mode->clock >= 140500
5031 && adjusted_mode->clock <= 200000) {
5032 clock->p1 = 1;
5033 clock->p2 = 10;
5034 clock->n = 6;
5035 clock->m1 = 12;
5036 clock->m2 = 8;
5037 }
5038 }
5039
5040 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5041 intel_clock_t *clock,
5042 intel_clock_t *reduced_clock)
5043 {
5044 struct drm_device *dev = crtc->dev;
5045 struct drm_i915_private *dev_priv = dev->dev_private;
5046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5047 int pipe = intel_crtc->pipe;
5048 u32 fp, fp2 = 0;
5049
5050 if (IS_PINEVIEW(dev)) {
5051 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5052 if (reduced_clock)
5053 fp2 = (1 << reduced_clock->n) << 16 |
5054 reduced_clock->m1 << 8 | reduced_clock->m2;
5055 } else {
5056 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5057 if (reduced_clock)
5058 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5059 reduced_clock->m2;
5060 }
5061
5062 I915_WRITE(FP0(pipe), fp);
5063
5064 intel_crtc->lowfreq_avail = false;
5065 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5066 reduced_clock && i915_powersave) {
5067 I915_WRITE(FP1(pipe), fp2);
5068 intel_crtc->lowfreq_avail = true;
5069 } else {
5070 I915_WRITE(FP1(pipe), fp);
5071 }
5072 }
5073
5074 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5075 struct drm_display_mode *mode,
5076 struct drm_display_mode *adjusted_mode,
5077 int x, int y,
5078 struct drm_framebuffer *old_fb)
5079 {
5080 struct drm_device *dev = crtc->dev;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083 int pipe = intel_crtc->pipe;
5084 int plane = intel_crtc->plane;
5085 int refclk, num_connectors = 0;
5086 intel_clock_t clock, reduced_clock;
5087 u32 dpll, dspcntr, pipeconf;
5088 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
5089 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5090 struct drm_mode_config *mode_config = &dev->mode_config;
5091 struct intel_encoder *encoder;
5092 const intel_limit_t *limit;
5093 int ret;
5094 u32 temp;
5095 u32 lvds_sync = 0;
5096
5097 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5098 if (encoder->base.crtc != crtc)
5099 continue;
5100
5101 switch (encoder->type) {
5102 case INTEL_OUTPUT_LVDS:
5103 is_lvds = true;
5104 break;
5105 case INTEL_OUTPUT_SDVO:
5106 case INTEL_OUTPUT_HDMI:
5107 is_sdvo = true;
5108 if (encoder->needs_tv_clock)
5109 is_tv = true;
5110 break;
5111 case INTEL_OUTPUT_DVO:
5112 is_dvo = true;
5113 break;
5114 case INTEL_OUTPUT_TVOUT:
5115 is_tv = true;
5116 break;
5117 case INTEL_OUTPUT_ANALOG:
5118 is_crt = true;
5119 break;
5120 case INTEL_OUTPUT_DISPLAYPORT:
5121 is_dp = true;
5122 break;
5123 }
5124
5125 num_connectors++;
5126 }
5127
5128 refclk = i9xx_get_refclk(crtc, num_connectors);
5129
5130 /*
5131 * Returns a set of divisors for the desired target clock with the given
5132 * refclk, or FALSE. The returned values represent the clock equation:
5133 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5134 */
5135 limit = intel_limit(crtc, refclk);
5136 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5137 &clock);
5138 if (!ok) {
5139 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5140 return -EINVAL;
5141 }
5142
5143 /* Ensure that the cursor is valid for the new mode before changing... */
5144 intel_crtc_update_cursor(crtc, true);
5145
5146 if (is_lvds && dev_priv->lvds_downclock_avail) {
5147 /*
5148 * Ensure we match the reduced clock's P to the target clock.
5149 * If the clocks don't match, we can't switch the display clock
5150 * by using the FP0/FP1. In such case we will disable the LVDS
5151 * downclock feature.
5152 */
5153 has_reduced_clock = limit->find_pll(limit, crtc,
5154 dev_priv->lvds_downclock,
5155 refclk,
5156 &clock,
5157 &reduced_clock);
5158 }
5159
5160 if (is_sdvo && is_tv)
5161 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
5162
5163 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5164 &reduced_clock : NULL);
5165
5166 dpll = DPLL_VGA_MODE_DIS;
5167
5168 if (!IS_GEN2(dev)) {
5169 if (is_lvds)
5170 dpll |= DPLLB_MODE_LVDS;
5171 else
5172 dpll |= DPLLB_MODE_DAC_SERIAL;
5173 if (is_sdvo) {
5174 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5175 if (pixel_multiplier > 1) {
5176 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5177 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
5178 }
5179 dpll |= DPLL_DVO_HIGH_SPEED;
5180 }
5181 if (is_dp)
5182 dpll |= DPLL_DVO_HIGH_SPEED;
5183
5184 /* compute bitmask from p1 value */
5185 if (IS_PINEVIEW(dev))
5186 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5187 else {
5188 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5189 if (IS_G4X(dev) && has_reduced_clock)
5190 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5191 }
5192 switch (clock.p2) {
5193 case 5:
5194 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5195 break;
5196 case 7:
5197 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5198 break;
5199 case 10:
5200 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5201 break;
5202 case 14:
5203 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5204 break;
5205 }
5206 if (INTEL_INFO(dev)->gen >= 4)
5207 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5208 } else {
5209 if (is_lvds) {
5210 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5211 } else {
5212 if (clock.p1 == 2)
5213 dpll |= PLL_P1_DIVIDE_BY_TWO;
5214 else
5215 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5216 if (clock.p2 == 4)
5217 dpll |= PLL_P2_DIVIDE_BY_4;
5218 }
5219 }
5220
5221 if (is_sdvo && is_tv)
5222 dpll |= PLL_REF_INPUT_TVCLKINBC;
5223 else if (is_tv)
5224 /* XXX: just matching BIOS for now */
5225 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5226 dpll |= 3;
5227 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5228 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5229 else
5230 dpll |= PLL_REF_INPUT_DREFCLK;
5231
5232 /* setup pipeconf */
5233 pipeconf = I915_READ(PIPECONF(pipe));
5234
5235 /* Set up the display plane register */
5236 dspcntr = DISPPLANE_GAMMA_ENABLE;
5237
5238 if (pipe == 0)
5239 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5240 else
5241 dspcntr |= DISPPLANE_SEL_PIPE_B;
5242
5243 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
5244 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5245 * core speed.
5246 *
5247 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5248 * pipe == 0 check?
5249 */
5250 if (mode->clock >
5251 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5252 pipeconf |= PIPECONF_DOUBLE_WIDE;
5253 else
5254 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
5255 }
5256
5257 /* default to 8bpc */
5258 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5259 if (is_dp) {
5260 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5261 pipeconf |= PIPECONF_BPP_6 |
5262 PIPECONF_DITHER_EN |
5263 PIPECONF_DITHER_TYPE_SP;
5264 }
5265 }
5266
5267 dpll |= DPLL_VCO_ENABLE;
5268
5269 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
5270 drm_mode_debug_printmodeline(mode);
5271
5272 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5273
5274 POSTING_READ(DPLL(pipe));
5275 udelay(150);
5276
5277 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5278 * This is an exception to the general rule that mode_set doesn't turn
5279 * things on.
5280 */
5281 if (is_lvds) {
5282 temp = I915_READ(LVDS);
5283 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5284 if (pipe == 1) {
5285 temp |= LVDS_PIPEB_SELECT;
5286 } else {
5287 temp &= ~LVDS_PIPEB_SELECT;
5288 }
5289 /* set the corresponsding LVDS_BORDER bit */
5290 temp |= dev_priv->lvds_border_bits;
5291 /* Set the B0-B3 data pairs corresponding to whether we're going to
5292 * set the DPLLs for dual-channel mode or not.
5293 */
5294 if (clock.p2 == 7)
5295 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5296 else
5297 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5298
5299 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5300 * appropriately here, but we need to look more thoroughly into how
5301 * panels behave in the two modes.
5302 */
5303 /* set the dithering flag on LVDS as needed */
5304 if (INTEL_INFO(dev)->gen >= 4) {
5305 if (dev_priv->lvds_dither)
5306 temp |= LVDS_ENABLE_DITHER;
5307 else
5308 temp &= ~LVDS_ENABLE_DITHER;
5309 }
5310 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5311 lvds_sync |= LVDS_HSYNC_POLARITY;
5312 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5313 lvds_sync |= LVDS_VSYNC_POLARITY;
5314 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5315 != lvds_sync) {
5316 char flags[2] = "-+";
5317 DRM_INFO("Changing LVDS panel from "
5318 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5319 flags[!(temp & LVDS_HSYNC_POLARITY)],
5320 flags[!(temp & LVDS_VSYNC_POLARITY)],
5321 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5322 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5323 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5324 temp |= lvds_sync;
5325 }
5326 I915_WRITE(LVDS, temp);
5327 }
5328
5329 if (is_dp) {
5330 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5331 }
5332
5333 I915_WRITE(DPLL(pipe), dpll);
5334
5335 /* Wait for the clocks to stabilize. */
5336 POSTING_READ(DPLL(pipe));
5337 udelay(150);
5338
5339 if (INTEL_INFO(dev)->gen >= 4) {
5340 temp = 0;
5341 if (is_sdvo) {
5342 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5343 if (temp > 1)
5344 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5345 else
5346 temp = 0;
5347 }
5348 I915_WRITE(DPLL_MD(pipe), temp);
5349 } else {
5350 /* The pixel multiplier can only be updated once the
5351 * DPLL is enabled and the clocks are stable.
5352 *
5353 * So write it again.
5354 */
5355 I915_WRITE(DPLL(pipe), dpll);
5356 }
5357
5358 if (HAS_PIPE_CXSR(dev)) {
5359 if (intel_crtc->lowfreq_avail) {
5360 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5361 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5362 } else {
5363 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5364 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5365 }
5366 }
5367
5368 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5369 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5370 /* the chip adds 2 halflines automatically */
5371 adjusted_mode->crtc_vdisplay -= 1;
5372 adjusted_mode->crtc_vtotal -= 1;
5373 adjusted_mode->crtc_vblank_start -= 1;
5374 adjusted_mode->crtc_vblank_end -= 1;
5375 adjusted_mode->crtc_vsync_end -= 1;
5376 adjusted_mode->crtc_vsync_start -= 1;
5377 } else
5378 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
5379
5380 I915_WRITE(HTOTAL(pipe),
5381 (adjusted_mode->crtc_hdisplay - 1) |
5382 ((adjusted_mode->crtc_htotal - 1) << 16));
5383 I915_WRITE(HBLANK(pipe),
5384 (adjusted_mode->crtc_hblank_start - 1) |
5385 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5386 I915_WRITE(HSYNC(pipe),
5387 (adjusted_mode->crtc_hsync_start - 1) |
5388 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5389
5390 I915_WRITE(VTOTAL(pipe),
5391 (adjusted_mode->crtc_vdisplay - 1) |
5392 ((adjusted_mode->crtc_vtotal - 1) << 16));
5393 I915_WRITE(VBLANK(pipe),
5394 (adjusted_mode->crtc_vblank_start - 1) |
5395 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5396 I915_WRITE(VSYNC(pipe),
5397 (adjusted_mode->crtc_vsync_start - 1) |
5398 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5399
5400 /* pipesrc and dspsize control the size that is scaled from,
5401 * which should always be the user's requested size.
5402 */
5403 I915_WRITE(DSPSIZE(plane),
5404 ((mode->vdisplay - 1) << 16) |
5405 (mode->hdisplay - 1));
5406 I915_WRITE(DSPPOS(plane), 0);
5407 I915_WRITE(PIPESRC(pipe),
5408 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5409
5410 I915_WRITE(PIPECONF(pipe), pipeconf);
5411 POSTING_READ(PIPECONF(pipe));
5412 intel_enable_pipe(dev_priv, pipe, false);
5413
5414 intel_wait_for_vblank(dev, pipe);
5415
5416 I915_WRITE(DSPCNTR(plane), dspcntr);
5417 POSTING_READ(DSPCNTR(plane));
5418 intel_enable_plane(dev_priv, plane, pipe);
5419
5420 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5421
5422 intel_update_watermarks(dev);
5423
5424 return ret;
5425 }
5426
5427 /*
5428 * Initialize reference clocks when the driver loads
5429 */
5430 void ironlake_init_pch_refclk(struct drm_device *dev)
5431 {
5432 struct drm_i915_private *dev_priv = dev->dev_private;
5433 struct drm_mode_config *mode_config = &dev->mode_config;
5434 struct intel_encoder *encoder;
5435 u32 temp;
5436 bool has_lvds = false;
5437 bool has_cpu_edp = false;
5438 bool has_pch_edp = false;
5439 bool has_panel = false;
5440 bool has_ck505 = false;
5441 bool can_ssc = false;
5442
5443 /* We need to take the global config into account */
5444 list_for_each_entry(encoder, &mode_config->encoder_list,
5445 base.head) {
5446 switch (encoder->type) {
5447 case INTEL_OUTPUT_LVDS:
5448 has_panel = true;
5449 has_lvds = true;
5450 break;
5451 case INTEL_OUTPUT_EDP:
5452 has_panel = true;
5453 if (intel_encoder_is_pch_edp(&encoder->base))
5454 has_pch_edp = true;
5455 else
5456 has_cpu_edp = true;
5457 break;
5458 }
5459 }
5460
5461 if (HAS_PCH_IBX(dev)) {
5462 has_ck505 = dev_priv->display_clock_mode;
5463 can_ssc = has_ck505;
5464 } else {
5465 has_ck505 = false;
5466 can_ssc = true;
5467 }
5468
5469 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5470 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5471 has_ck505);
5472
5473 /* Ironlake: try to setup display ref clock before DPLL
5474 * enabling. This is only under driver's control after
5475 * PCH B stepping, previous chipset stepping should be
5476 * ignoring this setting.
5477 */
5478 temp = I915_READ(PCH_DREF_CONTROL);
5479 /* Always enable nonspread source */
5480 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
5481
5482 if (has_ck505)
5483 temp |= DREF_NONSPREAD_CK505_ENABLE;
5484 else
5485 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
5486
5487 if (has_panel) {
5488 temp &= ~DREF_SSC_SOURCE_MASK;
5489 temp |= DREF_SSC_SOURCE_ENABLE;
5490
5491 /* SSC must be turned on before enabling the CPU output */
5492 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5493 DRM_DEBUG_KMS("Using SSC on panel\n");
5494 temp |= DREF_SSC1_ENABLE;
5495 }
5496
5497 /* Get SSC going before enabling the outputs */
5498 I915_WRITE(PCH_DREF_CONTROL, temp);
5499 POSTING_READ(PCH_DREF_CONTROL);
5500 udelay(200);
5501
5502 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5503
5504 /* Enable CPU source on CPU attached eDP */
5505 if (has_cpu_edp) {
5506 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5507 DRM_DEBUG_KMS("Using SSC on eDP\n");
5508 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5509 }
5510 else
5511 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5512 } else
5513 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5514
5515 I915_WRITE(PCH_DREF_CONTROL, temp);
5516 POSTING_READ(PCH_DREF_CONTROL);
5517 udelay(200);
5518 } else {
5519 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5520
5521 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5522
5523 /* Turn off CPU output */
5524 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5525
5526 I915_WRITE(PCH_DREF_CONTROL, temp);
5527 POSTING_READ(PCH_DREF_CONTROL);
5528 udelay(200);
5529
5530 /* Turn off the SSC source */
5531 temp &= ~DREF_SSC_SOURCE_MASK;
5532 temp |= DREF_SSC_SOURCE_DISABLE;
5533
5534 /* Turn off SSC1 */
5535 temp &= ~ DREF_SSC1_ENABLE;
5536
5537 I915_WRITE(PCH_DREF_CONTROL, temp);
5538 POSTING_READ(PCH_DREF_CONTROL);
5539 udelay(200);
5540 }
5541 }
5542
5543 static int ironlake_get_refclk(struct drm_crtc *crtc)
5544 {
5545 struct drm_device *dev = crtc->dev;
5546 struct drm_i915_private *dev_priv = dev->dev_private;
5547 struct intel_encoder *encoder;
5548 struct drm_mode_config *mode_config = &dev->mode_config;
5549 struct intel_encoder *edp_encoder = NULL;
5550 int num_connectors = 0;
5551 bool is_lvds = false;
5552
5553 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5554 if (encoder->base.crtc != crtc)
5555 continue;
5556
5557 switch (encoder->type) {
5558 case INTEL_OUTPUT_LVDS:
5559 is_lvds = true;
5560 break;
5561 case INTEL_OUTPUT_EDP:
5562 edp_encoder = encoder;
5563 break;
5564 }
5565 num_connectors++;
5566 }
5567
5568 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5569 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5570 dev_priv->lvds_ssc_freq);
5571 return dev_priv->lvds_ssc_freq * 1000;
5572 }
5573
5574 return 120000;
5575 }
5576
5577 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5578 struct drm_display_mode *mode,
5579 struct drm_display_mode *adjusted_mode,
5580 int x, int y,
5581 struct drm_framebuffer *old_fb)
5582 {
5583 struct drm_device *dev = crtc->dev;
5584 struct drm_i915_private *dev_priv = dev->dev_private;
5585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5586 int pipe = intel_crtc->pipe;
5587 int plane = intel_crtc->plane;
5588 int refclk, num_connectors = 0;
5589 intel_clock_t clock, reduced_clock;
5590 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
5591 bool ok, has_reduced_clock = false, is_sdvo = false;
5592 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
5593 struct intel_encoder *has_edp_encoder = NULL;
5594 struct drm_mode_config *mode_config = &dev->mode_config;
5595 struct intel_encoder *encoder;
5596 const intel_limit_t *limit;
5597 int ret;
5598 struct fdi_m_n m_n = {0};
5599 u32 temp;
5600 u32 lvds_sync = 0;
5601 int target_clock, pixel_multiplier, lane, link_bw, factor;
5602 unsigned int pipe_bpp;
5603 bool dither;
5604
5605 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5606 if (encoder->base.crtc != crtc)
5607 continue;
5608
5609 switch (encoder->type) {
5610 case INTEL_OUTPUT_LVDS:
5611 is_lvds = true;
5612 break;
5613 case INTEL_OUTPUT_SDVO:
5614 case INTEL_OUTPUT_HDMI:
5615 is_sdvo = true;
5616 if (encoder->needs_tv_clock)
5617 is_tv = true;
5618 break;
5619 case INTEL_OUTPUT_TVOUT:
5620 is_tv = true;
5621 break;
5622 case INTEL_OUTPUT_ANALOG:
5623 is_crt = true;
5624 break;
5625 case INTEL_OUTPUT_DISPLAYPORT:
5626 is_dp = true;
5627 break;
5628 case INTEL_OUTPUT_EDP:
5629 has_edp_encoder = encoder;
5630 break;
5631 }
5632
5633 num_connectors++;
5634 }
5635
5636 refclk = ironlake_get_refclk(crtc);
5637
5638 /*
5639 * Returns a set of divisors for the desired target clock with the given
5640 * refclk, or FALSE. The returned values represent the clock equation:
5641 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5642 */
5643 limit = intel_limit(crtc, refclk);
5644 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5645 &clock);
5646 if (!ok) {
5647 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5648 return -EINVAL;
5649 }
5650
5651 /* Ensure that the cursor is valid for the new mode before changing... */
5652 intel_crtc_update_cursor(crtc, true);
5653
5654 if (is_lvds && dev_priv->lvds_downclock_avail) {
5655 /*
5656 * Ensure we match the reduced clock's P to the target clock.
5657 * If the clocks don't match, we can't switch the display clock
5658 * by using the FP0/FP1. In such case we will disable the LVDS
5659 * downclock feature.
5660 */
5661 has_reduced_clock = limit->find_pll(limit, crtc,
5662 dev_priv->lvds_downclock,
5663 refclk,
5664 &clock,
5665 &reduced_clock);
5666 }
5667 /* SDVO TV has fixed PLL values depend on its clock range,
5668 this mirrors vbios setting. */
5669 if (is_sdvo && is_tv) {
5670 if (adjusted_mode->clock >= 100000
5671 && adjusted_mode->clock < 140500) {
5672 clock.p1 = 2;
5673 clock.p2 = 10;
5674 clock.n = 3;
5675 clock.m1 = 16;
5676 clock.m2 = 8;
5677 } else if (adjusted_mode->clock >= 140500
5678 && adjusted_mode->clock <= 200000) {
5679 clock.p1 = 1;
5680 clock.p2 = 10;
5681 clock.n = 6;
5682 clock.m1 = 12;
5683 clock.m2 = 8;
5684 }
5685 }
5686
5687 /* FDI link */
5688 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5689 lane = 0;
5690 /* CPU eDP doesn't require FDI link, so just set DP M/N
5691 according to current link config */
5692 if (has_edp_encoder &&
5693 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5694 target_clock = mode->clock;
5695 intel_edp_link_config(has_edp_encoder,
5696 &lane, &link_bw);
5697 } else {
5698 /* [e]DP over FDI requires target mode clock
5699 instead of link clock */
5700 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5701 target_clock = mode->clock;
5702 else
5703 target_clock = adjusted_mode->clock;
5704
5705 /* FDI is a binary signal running at ~2.7GHz, encoding
5706 * each output octet as 10 bits. The actual frequency
5707 * is stored as a divider into a 100MHz clock, and the
5708 * mode pixel clock is stored in units of 1KHz.
5709 * Hence the bw of each lane in terms of the mode signal
5710 * is:
5711 */
5712 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5713 }
5714
5715 /* determine panel color depth */
5716 temp = I915_READ(PIPECONF(pipe));
5717 temp &= ~PIPE_BPC_MASK;
5718 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5719 switch (pipe_bpp) {
5720 case 18:
5721 temp |= PIPE_6BPC;
5722 break;
5723 case 24:
5724 temp |= PIPE_8BPC;
5725 break;
5726 case 30:
5727 temp |= PIPE_10BPC;
5728 break;
5729 case 36:
5730 temp |= PIPE_12BPC;
5731 break;
5732 default:
5733 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5734 pipe_bpp);
5735 temp |= PIPE_8BPC;
5736 pipe_bpp = 24;
5737 break;
5738 }
5739
5740 intel_crtc->bpp = pipe_bpp;
5741 I915_WRITE(PIPECONF(pipe), temp);
5742
5743 if (!lane) {
5744 /*
5745 * Account for spread spectrum to avoid
5746 * oversubscribing the link. Max center spread
5747 * is 2.5%; use 5% for safety's sake.
5748 */
5749 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5750 lane = bps / (link_bw * 8) + 1;
5751 }
5752
5753 intel_crtc->fdi_lanes = lane;
5754
5755 if (pixel_multiplier > 1)
5756 link_bw *= pixel_multiplier;
5757 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5758 &m_n);
5759
5760 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5761 if (has_reduced_clock)
5762 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5763 reduced_clock.m2;
5764
5765 /* Enable autotuning of the PLL clock (if permissible) */
5766 factor = 21;
5767 if (is_lvds) {
5768 if ((intel_panel_use_ssc(dev_priv) &&
5769 dev_priv->lvds_ssc_freq == 100) ||
5770 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5771 factor = 25;
5772 } else if (is_sdvo && is_tv)
5773 factor = 20;
5774
5775 if (clock.m < factor * clock.n)
5776 fp |= FP_CB_TUNE;
5777
5778 dpll = 0;
5779
5780 if (is_lvds)
5781 dpll |= DPLLB_MODE_LVDS;
5782 else
5783 dpll |= DPLLB_MODE_DAC_SERIAL;
5784 if (is_sdvo) {
5785 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5786 if (pixel_multiplier > 1) {
5787 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5788 }
5789 dpll |= DPLL_DVO_HIGH_SPEED;
5790 }
5791 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5792 dpll |= DPLL_DVO_HIGH_SPEED;
5793
5794 /* compute bitmask from p1 value */
5795 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5796 /* also FPA1 */
5797 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5798
5799 switch (clock.p2) {
5800 case 5:
5801 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5802 break;
5803 case 7:
5804 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5805 break;
5806 case 10:
5807 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5808 break;
5809 case 14:
5810 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5811 break;
5812 }
5813
5814 if (is_sdvo && is_tv)
5815 dpll |= PLL_REF_INPUT_TVCLKINBC;
5816 else if (is_tv)
5817 /* XXX: just matching BIOS for now */
5818 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5819 dpll |= 3;
5820 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5821 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5822 else
5823 dpll |= PLL_REF_INPUT_DREFCLK;
5824
5825 /* setup pipeconf */
5826 pipeconf = I915_READ(PIPECONF(pipe));
5827
5828 /* Set up the display plane register */
5829 dspcntr = DISPPLANE_GAMMA_ENABLE;
5830
5831 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5832 drm_mode_debug_printmodeline(mode);
5833
5834 /* PCH eDP needs FDI, but CPU eDP does not */
5835 if (!intel_crtc->no_pll) {
5836 if (!has_edp_encoder ||
5837 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5838 I915_WRITE(PCH_FP0(pipe), fp);
5839 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5840
5841 POSTING_READ(PCH_DPLL(pipe));
5842 udelay(150);
5843 }
5844 } else {
5845 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5846 fp == I915_READ(PCH_FP0(0))) {
5847 intel_crtc->use_pll_a = true;
5848 DRM_DEBUG_KMS("using pipe a dpll\n");
5849 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5850 fp == I915_READ(PCH_FP0(1))) {
5851 intel_crtc->use_pll_a = false;
5852 DRM_DEBUG_KMS("using pipe b dpll\n");
5853 } else {
5854 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5855 return -EINVAL;
5856 }
5857 }
5858
5859 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5860 * This is an exception to the general rule that mode_set doesn't turn
5861 * things on.
5862 */
5863 if (is_lvds) {
5864 temp = I915_READ(PCH_LVDS);
5865 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5866 if (HAS_PCH_CPT(dev))
5867 temp |= PORT_TRANS_SEL_CPT(pipe);
5868 else if (pipe == 1)
5869 temp |= LVDS_PIPEB_SELECT;
5870 else
5871 temp &= ~LVDS_PIPEB_SELECT;
5872
5873 /* set the corresponsding LVDS_BORDER bit */
5874 temp |= dev_priv->lvds_border_bits;
5875 /* Set the B0-B3 data pairs corresponding to whether we're going to
5876 * set the DPLLs for dual-channel mode or not.
5877 */
5878 if (clock.p2 == 7)
5879 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5880 else
5881 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5882
5883 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5884 * appropriately here, but we need to look more thoroughly into how
5885 * panels behave in the two modes.
5886 */
5887 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5888 lvds_sync |= LVDS_HSYNC_POLARITY;
5889 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5890 lvds_sync |= LVDS_VSYNC_POLARITY;
5891 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5892 != lvds_sync) {
5893 char flags[2] = "-+";
5894 DRM_INFO("Changing LVDS panel from "
5895 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5896 flags[!(temp & LVDS_HSYNC_POLARITY)],
5897 flags[!(temp & LVDS_VSYNC_POLARITY)],
5898 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5899 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5900 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5901 temp |= lvds_sync;
5902 }
5903 I915_WRITE(PCH_LVDS, temp);
5904 }
5905
5906 pipeconf &= ~PIPECONF_DITHER_EN;
5907 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5908 if ((is_lvds && dev_priv->lvds_dither) || dither) {
5909 pipeconf |= PIPECONF_DITHER_EN;
5910 pipeconf |= PIPECONF_DITHER_TYPE_SP;
5911 }
5912 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5913 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5914 } else {
5915 /* For non-DP output, clear any trans DP clock recovery setting.*/
5916 I915_WRITE(TRANSDATA_M1(pipe), 0);
5917 I915_WRITE(TRANSDATA_N1(pipe), 0);
5918 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5919 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5920 }
5921
5922 if (!intel_crtc->no_pll &&
5923 (!has_edp_encoder ||
5924 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
5925 I915_WRITE(PCH_DPLL(pipe), dpll);
5926
5927 /* Wait for the clocks to stabilize. */
5928 POSTING_READ(PCH_DPLL(pipe));
5929 udelay(150);
5930
5931 /* The pixel multiplier can only be updated once the
5932 * DPLL is enabled and the clocks are stable.
5933 *
5934 * So write it again.
5935 */
5936 I915_WRITE(PCH_DPLL(pipe), dpll);
5937 }
5938
5939 intel_crtc->lowfreq_avail = false;
5940 if (!intel_crtc->no_pll) {
5941 if (is_lvds && has_reduced_clock && i915_powersave) {
5942 I915_WRITE(PCH_FP1(pipe), fp2);
5943 intel_crtc->lowfreq_avail = true;
5944 if (HAS_PIPE_CXSR(dev)) {
5945 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5946 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5947 }
5948 } else {
5949 I915_WRITE(PCH_FP1(pipe), fp);
5950 if (HAS_PIPE_CXSR(dev)) {
5951 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5952 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5953 }
5954 }
5955 }
5956
5957 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5958 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5959 /* the chip adds 2 halflines automatically */
5960 adjusted_mode->crtc_vdisplay -= 1;
5961 adjusted_mode->crtc_vtotal -= 1;
5962 adjusted_mode->crtc_vblank_start -= 1;
5963 adjusted_mode->crtc_vblank_end -= 1;
5964 adjusted_mode->crtc_vsync_end -= 1;
5965 adjusted_mode->crtc_vsync_start -= 1;
5966 } else
5967 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5968
5969 I915_WRITE(HTOTAL(pipe),
5970 (adjusted_mode->crtc_hdisplay - 1) |
5971 ((adjusted_mode->crtc_htotal - 1) << 16));
5972 I915_WRITE(HBLANK(pipe),
5973 (adjusted_mode->crtc_hblank_start - 1) |
5974 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5975 I915_WRITE(HSYNC(pipe),
5976 (adjusted_mode->crtc_hsync_start - 1) |
5977 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5978
5979 I915_WRITE(VTOTAL(pipe),
5980 (adjusted_mode->crtc_vdisplay - 1) |
5981 ((adjusted_mode->crtc_vtotal - 1) << 16));
5982 I915_WRITE(VBLANK(pipe),
5983 (adjusted_mode->crtc_vblank_start - 1) |
5984 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5985 I915_WRITE(VSYNC(pipe),
5986 (adjusted_mode->crtc_vsync_start - 1) |
5987 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5988
5989 /* pipesrc controls the size that is scaled from, which should
5990 * always be the user's requested size.
5991 */
5992 I915_WRITE(PIPESRC(pipe),
5993 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
5994
5995 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5996 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5997 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5998 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
5999
6000 if (has_edp_encoder &&
6001 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6002 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
6003 }
6004
6005 I915_WRITE(PIPECONF(pipe), pipeconf);
6006 POSTING_READ(PIPECONF(pipe));
6007
6008 intel_wait_for_vblank(dev, pipe);
6009
6010 if (IS_GEN5(dev)) {
6011 /* enable address swizzle for tiling buffer */
6012 temp = I915_READ(DISP_ARB_CTL);
6013 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
6014 }
6015
6016 I915_WRITE(DSPCNTR(plane), dspcntr);
6017 POSTING_READ(DSPCNTR(plane));
6018
6019 ret = intel_pipe_set_base(crtc, x, y, old_fb);
6020
6021 intel_update_watermarks(dev);
6022
6023 return ret;
6024 }
6025
6026 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6027 struct drm_display_mode *mode,
6028 struct drm_display_mode *adjusted_mode,
6029 int x, int y,
6030 struct drm_framebuffer *old_fb)
6031 {
6032 struct drm_device *dev = crtc->dev;
6033 struct drm_i915_private *dev_priv = dev->dev_private;
6034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6035 int pipe = intel_crtc->pipe;
6036 int ret;
6037
6038 drm_vblank_pre_modeset(dev, pipe);
6039
6040 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6041 x, y, old_fb);
6042 drm_vblank_post_modeset(dev, pipe);
6043
6044 if (ret)
6045 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6046 else
6047 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
6048
6049 return ret;
6050 }
6051
6052 static bool intel_eld_uptodate(struct drm_connector *connector,
6053 int reg_eldv, uint32_t bits_eldv,
6054 int reg_elda, uint32_t bits_elda,
6055 int reg_edid)
6056 {
6057 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6058 uint8_t *eld = connector->eld;
6059 uint32_t i;
6060
6061 i = I915_READ(reg_eldv);
6062 i &= bits_eldv;
6063
6064 if (!eld[0])
6065 return !i;
6066
6067 if (!i)
6068 return false;
6069
6070 i = I915_READ(reg_elda);
6071 i &= ~bits_elda;
6072 I915_WRITE(reg_elda, i);
6073
6074 for (i = 0; i < eld[2]; i++)
6075 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6076 return false;
6077
6078 return true;
6079 }
6080
6081 static void g4x_write_eld(struct drm_connector *connector,
6082 struct drm_crtc *crtc)
6083 {
6084 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6085 uint8_t *eld = connector->eld;
6086 uint32_t eldv;
6087 uint32_t len;
6088 uint32_t i;
6089
6090 i = I915_READ(G4X_AUD_VID_DID);
6091
6092 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6093 eldv = G4X_ELDV_DEVCL_DEVBLC;
6094 else
6095 eldv = G4X_ELDV_DEVCTG;
6096
6097 if (intel_eld_uptodate(connector,
6098 G4X_AUD_CNTL_ST, eldv,
6099 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6100 G4X_HDMIW_HDMIEDID))
6101 return;
6102
6103 i = I915_READ(G4X_AUD_CNTL_ST);
6104 i &= ~(eldv | G4X_ELD_ADDR);
6105 len = (i >> 9) & 0x1f; /* ELD buffer size */
6106 I915_WRITE(G4X_AUD_CNTL_ST, i);
6107
6108 if (!eld[0])
6109 return;
6110
6111 len = min_t(uint8_t, eld[2], len);
6112 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6113 for (i = 0; i < len; i++)
6114 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6115
6116 i = I915_READ(G4X_AUD_CNTL_ST);
6117 i |= eldv;
6118 I915_WRITE(G4X_AUD_CNTL_ST, i);
6119 }
6120
6121 static void ironlake_write_eld(struct drm_connector *connector,
6122 struct drm_crtc *crtc)
6123 {
6124 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6125 uint8_t *eld = connector->eld;
6126 uint32_t eldv;
6127 uint32_t i;
6128 int len;
6129 int hdmiw_hdmiedid;
6130 int aud_cntl_st;
6131 int aud_cntrl_st2;
6132
6133 if (HAS_PCH_IBX(connector->dev)) {
6134 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6135 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6136 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6137 } else {
6138 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6139 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6140 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6141 }
6142
6143 i = to_intel_crtc(crtc)->pipe;
6144 hdmiw_hdmiedid += i * 0x100;
6145 aud_cntl_st += i * 0x100;
6146
6147 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6148
6149 i = I915_READ(aud_cntl_st);
6150 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6151 if (!i) {
6152 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6153 /* operate blindly on all ports */
6154 eldv = IBX_ELD_VALIDB;
6155 eldv |= IBX_ELD_VALIDB << 4;
6156 eldv |= IBX_ELD_VALIDB << 8;
6157 } else {
6158 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6159 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6160 }
6161
6162 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6163 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6164 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6165 }
6166
6167 if (intel_eld_uptodate(connector,
6168 aud_cntrl_st2, eldv,
6169 aud_cntl_st, IBX_ELD_ADDRESS,
6170 hdmiw_hdmiedid))
6171 return;
6172
6173 i = I915_READ(aud_cntrl_st2);
6174 i &= ~eldv;
6175 I915_WRITE(aud_cntrl_st2, i);
6176
6177 if (!eld[0])
6178 return;
6179
6180 i = I915_READ(aud_cntl_st);
6181 i &= ~IBX_ELD_ADDRESS;
6182 I915_WRITE(aud_cntl_st, i);
6183
6184 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6185 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6186 for (i = 0; i < len; i++)
6187 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6188
6189 i = I915_READ(aud_cntrl_st2);
6190 i |= eldv;
6191 I915_WRITE(aud_cntrl_st2, i);
6192 }
6193
6194 void intel_write_eld(struct drm_encoder *encoder,
6195 struct drm_display_mode *mode)
6196 {
6197 struct drm_crtc *crtc = encoder->crtc;
6198 struct drm_connector *connector;
6199 struct drm_device *dev = encoder->dev;
6200 struct drm_i915_private *dev_priv = dev->dev_private;
6201
6202 connector = drm_select_eld(encoder, mode);
6203 if (!connector)
6204 return;
6205
6206 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6207 connector->base.id,
6208 drm_get_connector_name(connector),
6209 connector->encoder->base.id,
6210 drm_get_encoder_name(connector->encoder));
6211
6212 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6213
6214 if (dev_priv->display.write_eld)
6215 dev_priv->display.write_eld(connector, crtc);
6216 }
6217
6218 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6219 void intel_crtc_load_lut(struct drm_crtc *crtc)
6220 {
6221 struct drm_device *dev = crtc->dev;
6222 struct drm_i915_private *dev_priv = dev->dev_private;
6223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6224 int palreg = PALETTE(intel_crtc->pipe);
6225 int i;
6226
6227 /* The clocks have to be on to load the palette. */
6228 if (!crtc->enabled)
6229 return;
6230
6231 /* use legacy palette for Ironlake */
6232 if (HAS_PCH_SPLIT(dev))
6233 palreg = LGC_PALETTE(intel_crtc->pipe);
6234
6235 for (i = 0; i < 256; i++) {
6236 I915_WRITE(palreg + 4 * i,
6237 (intel_crtc->lut_r[i] << 16) |
6238 (intel_crtc->lut_g[i] << 8) |
6239 intel_crtc->lut_b[i]);
6240 }
6241 }
6242
6243 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6244 {
6245 struct drm_device *dev = crtc->dev;
6246 struct drm_i915_private *dev_priv = dev->dev_private;
6247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6248 bool visible = base != 0;
6249 u32 cntl;
6250
6251 if (intel_crtc->cursor_visible == visible)
6252 return;
6253
6254 cntl = I915_READ(_CURACNTR);
6255 if (visible) {
6256 /* On these chipsets we can only modify the base whilst
6257 * the cursor is disabled.
6258 */
6259 I915_WRITE(_CURABASE, base);
6260
6261 cntl &= ~(CURSOR_FORMAT_MASK);
6262 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6263 cntl |= CURSOR_ENABLE |
6264 CURSOR_GAMMA_ENABLE |
6265 CURSOR_FORMAT_ARGB;
6266 } else
6267 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6268 I915_WRITE(_CURACNTR, cntl);
6269
6270 intel_crtc->cursor_visible = visible;
6271 }
6272
6273 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6274 {
6275 struct drm_device *dev = crtc->dev;
6276 struct drm_i915_private *dev_priv = dev->dev_private;
6277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6278 int pipe = intel_crtc->pipe;
6279 bool visible = base != 0;
6280
6281 if (intel_crtc->cursor_visible != visible) {
6282 uint32_t cntl = I915_READ(CURCNTR(pipe));
6283 if (base) {
6284 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6285 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6286 cntl |= pipe << 28; /* Connect to correct pipe */
6287 } else {
6288 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6289 cntl |= CURSOR_MODE_DISABLE;
6290 }
6291 I915_WRITE(CURCNTR(pipe), cntl);
6292
6293 intel_crtc->cursor_visible = visible;
6294 }
6295 /* and commit changes on next vblank */
6296 I915_WRITE(CURBASE(pipe), base);
6297 }
6298
6299 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6300 {
6301 struct drm_device *dev = crtc->dev;
6302 struct drm_i915_private *dev_priv = dev->dev_private;
6303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6304 int pipe = intel_crtc->pipe;
6305 bool visible = base != 0;
6306
6307 if (intel_crtc->cursor_visible != visible) {
6308 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6309 if (base) {
6310 cntl &= ~CURSOR_MODE;
6311 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6312 } else {
6313 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6314 cntl |= CURSOR_MODE_DISABLE;
6315 }
6316 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6317
6318 intel_crtc->cursor_visible = visible;
6319 }
6320 /* and commit changes on next vblank */
6321 I915_WRITE(CURBASE_IVB(pipe), base);
6322 }
6323
6324 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6325 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6326 bool on)
6327 {
6328 struct drm_device *dev = crtc->dev;
6329 struct drm_i915_private *dev_priv = dev->dev_private;
6330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331 int pipe = intel_crtc->pipe;
6332 int x = intel_crtc->cursor_x;
6333 int y = intel_crtc->cursor_y;
6334 u32 base, pos;
6335 bool visible;
6336
6337 pos = 0;
6338
6339 if (on && crtc->enabled && crtc->fb) {
6340 base = intel_crtc->cursor_addr;
6341 if (x > (int) crtc->fb->width)
6342 base = 0;
6343
6344 if (y > (int) crtc->fb->height)
6345 base = 0;
6346 } else
6347 base = 0;
6348
6349 if (x < 0) {
6350 if (x + intel_crtc->cursor_width < 0)
6351 base = 0;
6352
6353 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6354 x = -x;
6355 }
6356 pos |= x << CURSOR_X_SHIFT;
6357
6358 if (y < 0) {
6359 if (y + intel_crtc->cursor_height < 0)
6360 base = 0;
6361
6362 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6363 y = -y;
6364 }
6365 pos |= y << CURSOR_Y_SHIFT;
6366
6367 visible = base != 0;
6368 if (!visible && !intel_crtc->cursor_visible)
6369 return;
6370
6371 if (IS_IVYBRIDGE(dev)) {
6372 I915_WRITE(CURPOS_IVB(pipe), pos);
6373 ivb_update_cursor(crtc, base);
6374 } else {
6375 I915_WRITE(CURPOS(pipe), pos);
6376 if (IS_845G(dev) || IS_I865G(dev))
6377 i845_update_cursor(crtc, base);
6378 else
6379 i9xx_update_cursor(crtc, base);
6380 }
6381
6382 if (visible)
6383 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6384 }
6385
6386 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6387 struct drm_file *file,
6388 uint32_t handle,
6389 uint32_t width, uint32_t height)
6390 {
6391 struct drm_device *dev = crtc->dev;
6392 struct drm_i915_private *dev_priv = dev->dev_private;
6393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6394 struct drm_i915_gem_object *obj;
6395 uint32_t addr;
6396 int ret;
6397
6398 DRM_DEBUG_KMS("\n");
6399
6400 /* if we want to turn off the cursor ignore width and height */
6401 if (!handle) {
6402 DRM_DEBUG_KMS("cursor off\n");
6403 addr = 0;
6404 obj = NULL;
6405 mutex_lock(&dev->struct_mutex);
6406 goto finish;
6407 }
6408
6409 /* Currently we only support 64x64 cursors */
6410 if (width != 64 || height != 64) {
6411 DRM_ERROR("we currently only support 64x64 cursors\n");
6412 return -EINVAL;
6413 }
6414
6415 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6416 if (&obj->base == NULL)
6417 return -ENOENT;
6418
6419 if (obj->base.size < width * height * 4) {
6420 DRM_ERROR("buffer is to small\n");
6421 ret = -ENOMEM;
6422 goto fail;
6423 }
6424
6425 /* we only need to pin inside GTT if cursor is non-phy */
6426 mutex_lock(&dev->struct_mutex);
6427 if (!dev_priv->info->cursor_needs_physical) {
6428 if (obj->tiling_mode) {
6429 DRM_ERROR("cursor cannot be tiled\n");
6430 ret = -EINVAL;
6431 goto fail_locked;
6432 }
6433
6434 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6435 if (ret) {
6436 DRM_ERROR("failed to move cursor bo into the GTT\n");
6437 goto fail_locked;
6438 }
6439
6440 ret = i915_gem_object_put_fence(obj);
6441 if (ret) {
6442 DRM_ERROR("failed to release fence for cursor");
6443 goto fail_unpin;
6444 }
6445
6446 addr = obj->gtt_offset;
6447 } else {
6448 int align = IS_I830(dev) ? 16 * 1024 : 256;
6449 ret = i915_gem_attach_phys_object(dev, obj,
6450 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6451 align);
6452 if (ret) {
6453 DRM_ERROR("failed to attach phys object\n");
6454 goto fail_locked;
6455 }
6456 addr = obj->phys_obj->handle->busaddr;
6457 }
6458
6459 if (IS_GEN2(dev))
6460 I915_WRITE(CURSIZE, (height << 12) | width);
6461
6462 finish:
6463 if (intel_crtc->cursor_bo) {
6464 if (dev_priv->info->cursor_needs_physical) {
6465 if (intel_crtc->cursor_bo != obj)
6466 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6467 } else
6468 i915_gem_object_unpin(intel_crtc->cursor_bo);
6469 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6470 }
6471
6472 mutex_unlock(&dev->struct_mutex);
6473
6474 intel_crtc->cursor_addr = addr;
6475 intel_crtc->cursor_bo = obj;
6476 intel_crtc->cursor_width = width;
6477 intel_crtc->cursor_height = height;
6478
6479 intel_crtc_update_cursor(crtc, true);
6480
6481 return 0;
6482 fail_unpin:
6483 i915_gem_object_unpin(obj);
6484 fail_locked:
6485 mutex_unlock(&dev->struct_mutex);
6486 fail:
6487 drm_gem_object_unreference_unlocked(&obj->base);
6488 return ret;
6489 }
6490
6491 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6492 {
6493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6494
6495 intel_crtc->cursor_x = x;
6496 intel_crtc->cursor_y = y;
6497
6498 intel_crtc_update_cursor(crtc, true);
6499
6500 return 0;
6501 }
6502
6503 /** Sets the color ramps on behalf of RandR */
6504 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6505 u16 blue, int regno)
6506 {
6507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6508
6509 intel_crtc->lut_r[regno] = red >> 8;
6510 intel_crtc->lut_g[regno] = green >> 8;
6511 intel_crtc->lut_b[regno] = blue >> 8;
6512 }
6513
6514 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6515 u16 *blue, int regno)
6516 {
6517 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6518
6519 *red = intel_crtc->lut_r[regno] << 8;
6520 *green = intel_crtc->lut_g[regno] << 8;
6521 *blue = intel_crtc->lut_b[regno] << 8;
6522 }
6523
6524 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6525 u16 *blue, uint32_t start, uint32_t size)
6526 {
6527 int end = (start + size > 256) ? 256 : start + size, i;
6528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6529
6530 for (i = start; i < end; i++) {
6531 intel_crtc->lut_r[i] = red[i] >> 8;
6532 intel_crtc->lut_g[i] = green[i] >> 8;
6533 intel_crtc->lut_b[i] = blue[i] >> 8;
6534 }
6535
6536 intel_crtc_load_lut(crtc);
6537 }
6538
6539 /**
6540 * Get a pipe with a simple mode set on it for doing load-based monitor
6541 * detection.
6542 *
6543 * It will be up to the load-detect code to adjust the pipe as appropriate for
6544 * its requirements. The pipe will be connected to no other encoders.
6545 *
6546 * Currently this code will only succeed if there is a pipe with no encoders
6547 * configured for it. In the future, it could choose to temporarily disable
6548 * some outputs to free up a pipe for its use.
6549 *
6550 * \return crtc, or NULL if no pipes are available.
6551 */
6552
6553 /* VESA 640x480x72Hz mode to set on the pipe */
6554 static struct drm_display_mode load_detect_mode = {
6555 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6556 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6557 };
6558
6559 static struct drm_framebuffer *
6560 intel_framebuffer_create(struct drm_device *dev,
6561 struct drm_mode_fb_cmd2 *mode_cmd,
6562 struct drm_i915_gem_object *obj)
6563 {
6564 struct intel_framebuffer *intel_fb;
6565 int ret;
6566
6567 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6568 if (!intel_fb) {
6569 drm_gem_object_unreference_unlocked(&obj->base);
6570 return ERR_PTR(-ENOMEM);
6571 }
6572
6573 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6574 if (ret) {
6575 drm_gem_object_unreference_unlocked(&obj->base);
6576 kfree(intel_fb);
6577 return ERR_PTR(ret);
6578 }
6579
6580 return &intel_fb->base;
6581 }
6582
6583 static u32
6584 intel_framebuffer_pitch_for_width(int width, int bpp)
6585 {
6586 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6587 return ALIGN(pitch, 64);
6588 }
6589
6590 static u32
6591 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6592 {
6593 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6594 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6595 }
6596
6597 static struct drm_framebuffer *
6598 intel_framebuffer_create_for_mode(struct drm_device *dev,
6599 struct drm_display_mode *mode,
6600 int depth, int bpp)
6601 {
6602 struct drm_i915_gem_object *obj;
6603 struct drm_mode_fb_cmd2 mode_cmd;
6604
6605 obj = i915_gem_alloc_object(dev,
6606 intel_framebuffer_size_for_mode(mode, bpp));
6607 if (obj == NULL)
6608 return ERR_PTR(-ENOMEM);
6609
6610 mode_cmd.width = mode->hdisplay;
6611 mode_cmd.height = mode->vdisplay;
6612 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6613 bpp);
6614 mode_cmd.pixel_format = 0;
6615
6616 return intel_framebuffer_create(dev, &mode_cmd, obj);
6617 }
6618
6619 static struct drm_framebuffer *
6620 mode_fits_in_fbdev(struct drm_device *dev,
6621 struct drm_display_mode *mode)
6622 {
6623 struct drm_i915_private *dev_priv = dev->dev_private;
6624 struct drm_i915_gem_object *obj;
6625 struct drm_framebuffer *fb;
6626
6627 if (dev_priv->fbdev == NULL)
6628 return NULL;
6629
6630 obj = dev_priv->fbdev->ifb.obj;
6631 if (obj == NULL)
6632 return NULL;
6633
6634 fb = &dev_priv->fbdev->ifb.base;
6635 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6636 fb->bits_per_pixel))
6637 return NULL;
6638
6639 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6640 return NULL;
6641
6642 return fb;
6643 }
6644
6645 bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6646 struct drm_connector *connector,
6647 struct drm_display_mode *mode,
6648 struct intel_load_detect_pipe *old)
6649 {
6650 struct intel_crtc *intel_crtc;
6651 struct drm_crtc *possible_crtc;
6652 struct drm_encoder *encoder = &intel_encoder->base;
6653 struct drm_crtc *crtc = NULL;
6654 struct drm_device *dev = encoder->dev;
6655 struct drm_framebuffer *old_fb;
6656 int i = -1;
6657
6658 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6659 connector->base.id, drm_get_connector_name(connector),
6660 encoder->base.id, drm_get_encoder_name(encoder));
6661
6662 /*
6663 * Algorithm gets a little messy:
6664 *
6665 * - if the connector already has an assigned crtc, use it (but make
6666 * sure it's on first)
6667 *
6668 * - try to find the first unused crtc that can drive this connector,
6669 * and use that if we find one
6670 */
6671
6672 /* See if we already have a CRTC for this connector */
6673 if (encoder->crtc) {
6674 crtc = encoder->crtc;
6675
6676 intel_crtc = to_intel_crtc(crtc);
6677 old->dpms_mode = intel_crtc->dpms_mode;
6678 old->load_detect_temp = false;
6679
6680 /* Make sure the crtc and connector are running */
6681 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6682 struct drm_encoder_helper_funcs *encoder_funcs;
6683 struct drm_crtc_helper_funcs *crtc_funcs;
6684
6685 crtc_funcs = crtc->helper_private;
6686 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6687
6688 encoder_funcs = encoder->helper_private;
6689 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6690 }
6691
6692 return true;
6693 }
6694
6695 /* Find an unused one (if possible) */
6696 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6697 i++;
6698 if (!(encoder->possible_crtcs & (1 << i)))
6699 continue;
6700 if (!possible_crtc->enabled) {
6701 crtc = possible_crtc;
6702 break;
6703 }
6704 }
6705
6706 /*
6707 * If we didn't find an unused CRTC, don't use any.
6708 */
6709 if (!crtc) {
6710 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6711 return false;
6712 }
6713
6714 encoder->crtc = crtc;
6715 connector->encoder = encoder;
6716
6717 intel_crtc = to_intel_crtc(crtc);
6718 old->dpms_mode = intel_crtc->dpms_mode;
6719 old->load_detect_temp = true;
6720 old->release_fb = NULL;
6721
6722 if (!mode)
6723 mode = &load_detect_mode;
6724
6725 old_fb = crtc->fb;
6726
6727 /* We need a framebuffer large enough to accommodate all accesses
6728 * that the plane may generate whilst we perform load detection.
6729 * We can not rely on the fbcon either being present (we get called
6730 * during its initialisation to detect all boot displays, or it may
6731 * not even exist) or that it is large enough to satisfy the
6732 * requested mode.
6733 */
6734 crtc->fb = mode_fits_in_fbdev(dev, mode);
6735 if (crtc->fb == NULL) {
6736 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6737 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6738 old->release_fb = crtc->fb;
6739 } else
6740 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6741 if (IS_ERR(crtc->fb)) {
6742 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6743 crtc->fb = old_fb;
6744 return false;
6745 }
6746
6747 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6748 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6749 if (old->release_fb)
6750 old->release_fb->funcs->destroy(old->release_fb);
6751 crtc->fb = old_fb;
6752 return false;
6753 }
6754
6755 /* let the connector get through one full cycle before testing */
6756 intel_wait_for_vblank(dev, intel_crtc->pipe);
6757
6758 return true;
6759 }
6760
6761 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
6762 struct drm_connector *connector,
6763 struct intel_load_detect_pipe *old)
6764 {
6765 struct drm_encoder *encoder = &intel_encoder->base;
6766 struct drm_device *dev = encoder->dev;
6767 struct drm_crtc *crtc = encoder->crtc;
6768 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6769 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6770
6771 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6772 connector->base.id, drm_get_connector_name(connector),
6773 encoder->base.id, drm_get_encoder_name(encoder));
6774
6775 if (old->load_detect_temp) {
6776 connector->encoder = NULL;
6777 drm_helper_disable_unused_functions(dev);
6778
6779 if (old->release_fb)
6780 old->release_fb->funcs->destroy(old->release_fb);
6781
6782 return;
6783 }
6784
6785 /* Switch crtc and encoder back off if necessary */
6786 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6787 encoder_funcs->dpms(encoder, old->dpms_mode);
6788 crtc_funcs->dpms(crtc, old->dpms_mode);
6789 }
6790 }
6791
6792 /* Returns the clock of the currently programmed mode of the given pipe. */
6793 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6794 {
6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6797 int pipe = intel_crtc->pipe;
6798 u32 dpll = I915_READ(DPLL(pipe));
6799 u32 fp;
6800 intel_clock_t clock;
6801
6802 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6803 fp = I915_READ(FP0(pipe));
6804 else
6805 fp = I915_READ(FP1(pipe));
6806
6807 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6808 if (IS_PINEVIEW(dev)) {
6809 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6810 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6811 } else {
6812 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6813 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6814 }
6815
6816 if (!IS_GEN2(dev)) {
6817 if (IS_PINEVIEW(dev))
6818 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6819 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6820 else
6821 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6822 DPLL_FPA01_P1_POST_DIV_SHIFT);
6823
6824 switch (dpll & DPLL_MODE_MASK) {
6825 case DPLLB_MODE_DAC_SERIAL:
6826 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6827 5 : 10;
6828 break;
6829 case DPLLB_MODE_LVDS:
6830 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6831 7 : 14;
6832 break;
6833 default:
6834 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6835 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6836 return 0;
6837 }
6838
6839 /* XXX: Handle the 100Mhz refclk */
6840 intel_clock(dev, 96000, &clock);
6841 } else {
6842 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6843
6844 if (is_lvds) {
6845 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6846 DPLL_FPA01_P1_POST_DIV_SHIFT);
6847 clock.p2 = 14;
6848
6849 if ((dpll & PLL_REF_INPUT_MASK) ==
6850 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6851 /* XXX: might not be 66MHz */
6852 intel_clock(dev, 66000, &clock);
6853 } else
6854 intel_clock(dev, 48000, &clock);
6855 } else {
6856 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6857 clock.p1 = 2;
6858 else {
6859 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6860 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6861 }
6862 if (dpll & PLL_P2_DIVIDE_BY_4)
6863 clock.p2 = 4;
6864 else
6865 clock.p2 = 2;
6866
6867 intel_clock(dev, 48000, &clock);
6868 }
6869 }
6870
6871 /* XXX: It would be nice to validate the clocks, but we can't reuse
6872 * i830PllIsValid() because it relies on the xf86_config connector
6873 * configuration being accurate, which it isn't necessarily.
6874 */
6875
6876 return clock.dot;
6877 }
6878
6879 /** Returns the currently programmed mode of the given pipe. */
6880 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6881 struct drm_crtc *crtc)
6882 {
6883 struct drm_i915_private *dev_priv = dev->dev_private;
6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885 int pipe = intel_crtc->pipe;
6886 struct drm_display_mode *mode;
6887 int htot = I915_READ(HTOTAL(pipe));
6888 int hsync = I915_READ(HSYNC(pipe));
6889 int vtot = I915_READ(VTOTAL(pipe));
6890 int vsync = I915_READ(VSYNC(pipe));
6891
6892 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6893 if (!mode)
6894 return NULL;
6895
6896 mode->clock = intel_crtc_clock_get(dev, crtc);
6897 mode->hdisplay = (htot & 0xffff) + 1;
6898 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6899 mode->hsync_start = (hsync & 0xffff) + 1;
6900 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6901 mode->vdisplay = (vtot & 0xffff) + 1;
6902 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6903 mode->vsync_start = (vsync & 0xffff) + 1;
6904 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6905
6906 drm_mode_set_name(mode);
6907 drm_mode_set_crtcinfo(mode, 0);
6908
6909 return mode;
6910 }
6911
6912 #define GPU_IDLE_TIMEOUT 500 /* ms */
6913
6914 /* When this timer fires, we've been idle for awhile */
6915 static void intel_gpu_idle_timer(unsigned long arg)
6916 {
6917 struct drm_device *dev = (struct drm_device *)arg;
6918 drm_i915_private_t *dev_priv = dev->dev_private;
6919
6920 if (!list_empty(&dev_priv->mm.active_list)) {
6921 /* Still processing requests, so just re-arm the timer. */
6922 mod_timer(&dev_priv->idle_timer, jiffies +
6923 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6924 return;
6925 }
6926
6927 dev_priv->busy = false;
6928 queue_work(dev_priv->wq, &dev_priv->idle_work);
6929 }
6930
6931 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6932
6933 static void intel_crtc_idle_timer(unsigned long arg)
6934 {
6935 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6936 struct drm_crtc *crtc = &intel_crtc->base;
6937 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
6938 struct intel_framebuffer *intel_fb;
6939
6940 intel_fb = to_intel_framebuffer(crtc->fb);
6941 if (intel_fb && intel_fb->obj->active) {
6942 /* The framebuffer is still being accessed by the GPU. */
6943 mod_timer(&intel_crtc->idle_timer, jiffies +
6944 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6945 return;
6946 }
6947
6948 intel_crtc->busy = false;
6949 queue_work(dev_priv->wq, &dev_priv->idle_work);
6950 }
6951
6952 static void intel_increase_pllclock(struct drm_crtc *crtc)
6953 {
6954 struct drm_device *dev = crtc->dev;
6955 drm_i915_private_t *dev_priv = dev->dev_private;
6956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6957 int pipe = intel_crtc->pipe;
6958 int dpll_reg = DPLL(pipe);
6959 int dpll;
6960
6961 if (HAS_PCH_SPLIT(dev))
6962 return;
6963
6964 if (!dev_priv->lvds_downclock_avail)
6965 return;
6966
6967 dpll = I915_READ(dpll_reg);
6968 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6969 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6970
6971 /* Unlock panel regs */
6972 I915_WRITE(PP_CONTROL,
6973 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
6974
6975 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6976 I915_WRITE(dpll_reg, dpll);
6977 intel_wait_for_vblank(dev, pipe);
6978
6979 dpll = I915_READ(dpll_reg);
6980 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6981 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6982
6983 /* ...and lock them again */
6984 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6985 }
6986
6987 /* Schedule downclock */
6988 mod_timer(&intel_crtc->idle_timer, jiffies +
6989 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6990 }
6991
6992 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6993 {
6994 struct drm_device *dev = crtc->dev;
6995 drm_i915_private_t *dev_priv = dev->dev_private;
6996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6997 int pipe = intel_crtc->pipe;
6998 int dpll_reg = DPLL(pipe);
6999 int dpll = I915_READ(dpll_reg);
7000
7001 if (HAS_PCH_SPLIT(dev))
7002 return;
7003
7004 if (!dev_priv->lvds_downclock_avail)
7005 return;
7006
7007 /*
7008 * Since this is called by a timer, we should never get here in
7009 * the manual case.
7010 */
7011 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7012 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7013
7014 /* Unlock panel regs */
7015 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7016 PANEL_UNLOCK_REGS);
7017
7018 dpll |= DISPLAY_RATE_SELECT_FPA1;
7019 I915_WRITE(dpll_reg, dpll);
7020 intel_wait_for_vblank(dev, pipe);
7021 dpll = I915_READ(dpll_reg);
7022 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7023 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7024
7025 /* ...and lock them again */
7026 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7027 }
7028
7029 }
7030
7031 /**
7032 * intel_idle_update - adjust clocks for idleness
7033 * @work: work struct
7034 *
7035 * Either the GPU or display (or both) went idle. Check the busy status
7036 * here and adjust the CRTC and GPU clocks as necessary.
7037 */
7038 static void intel_idle_update(struct work_struct *work)
7039 {
7040 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7041 idle_work);
7042 struct drm_device *dev = dev_priv->dev;
7043 struct drm_crtc *crtc;
7044 struct intel_crtc *intel_crtc;
7045
7046 if (!i915_powersave)
7047 return;
7048
7049 mutex_lock(&dev->struct_mutex);
7050
7051 i915_update_gfx_val(dev_priv);
7052
7053 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7054 /* Skip inactive CRTCs */
7055 if (!crtc->fb)
7056 continue;
7057
7058 intel_crtc = to_intel_crtc(crtc);
7059 if (!intel_crtc->busy)
7060 intel_decrease_pllclock(crtc);
7061 }
7062
7063
7064 mutex_unlock(&dev->struct_mutex);
7065 }
7066
7067 /**
7068 * intel_mark_busy - mark the GPU and possibly the display busy
7069 * @dev: drm device
7070 * @obj: object we're operating on
7071 *
7072 * Callers can use this function to indicate that the GPU is busy processing
7073 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7074 * buffer), we'll also mark the display as busy, so we know to increase its
7075 * clock frequency.
7076 */
7077 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
7078 {
7079 drm_i915_private_t *dev_priv = dev->dev_private;
7080 struct drm_crtc *crtc = NULL;
7081 struct intel_framebuffer *intel_fb;
7082 struct intel_crtc *intel_crtc;
7083
7084 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7085 return;
7086
7087 if (!dev_priv->busy)
7088 dev_priv->busy = true;
7089 else
7090 mod_timer(&dev_priv->idle_timer, jiffies +
7091 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
7092
7093 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7094 if (!crtc->fb)
7095 continue;
7096
7097 intel_crtc = to_intel_crtc(crtc);
7098 intel_fb = to_intel_framebuffer(crtc->fb);
7099 if (intel_fb->obj == obj) {
7100 if (!intel_crtc->busy) {
7101 /* Non-busy -> busy, upclock */
7102 intel_increase_pllclock(crtc);
7103 intel_crtc->busy = true;
7104 } else {
7105 /* Busy -> busy, put off timer */
7106 mod_timer(&intel_crtc->idle_timer, jiffies +
7107 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7108 }
7109 }
7110 }
7111 }
7112
7113 static void intel_crtc_destroy(struct drm_crtc *crtc)
7114 {
7115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7116 struct drm_device *dev = crtc->dev;
7117 struct intel_unpin_work *work;
7118 unsigned long flags;
7119
7120 spin_lock_irqsave(&dev->event_lock, flags);
7121 work = intel_crtc->unpin_work;
7122 intel_crtc->unpin_work = NULL;
7123 spin_unlock_irqrestore(&dev->event_lock, flags);
7124
7125 if (work) {
7126 cancel_work_sync(&work->work);
7127 kfree(work);
7128 }
7129
7130 drm_crtc_cleanup(crtc);
7131
7132 kfree(intel_crtc);
7133 }
7134
7135 static void intel_unpin_work_fn(struct work_struct *__work)
7136 {
7137 struct intel_unpin_work *work =
7138 container_of(__work, struct intel_unpin_work, work);
7139
7140 mutex_lock(&work->dev->struct_mutex);
7141 i915_gem_object_unpin(work->old_fb_obj);
7142 drm_gem_object_unreference(&work->pending_flip_obj->base);
7143 drm_gem_object_unreference(&work->old_fb_obj->base);
7144
7145 intel_update_fbc(work->dev);
7146 mutex_unlock(&work->dev->struct_mutex);
7147 kfree(work);
7148 }
7149
7150 static void do_intel_finish_page_flip(struct drm_device *dev,
7151 struct drm_crtc *crtc)
7152 {
7153 drm_i915_private_t *dev_priv = dev->dev_private;
7154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7155 struct intel_unpin_work *work;
7156 struct drm_i915_gem_object *obj;
7157 struct drm_pending_vblank_event *e;
7158 struct timeval tnow, tvbl;
7159 unsigned long flags;
7160
7161 /* Ignore early vblank irqs */
7162 if (intel_crtc == NULL)
7163 return;
7164
7165 do_gettimeofday(&tnow);
7166
7167 spin_lock_irqsave(&dev->event_lock, flags);
7168 work = intel_crtc->unpin_work;
7169 if (work == NULL || !work->pending) {
7170 spin_unlock_irqrestore(&dev->event_lock, flags);
7171 return;
7172 }
7173
7174 intel_crtc->unpin_work = NULL;
7175
7176 if (work->event) {
7177 e = work->event;
7178 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
7179
7180 /* Called before vblank count and timestamps have
7181 * been updated for the vblank interval of flip
7182 * completion? Need to increment vblank count and
7183 * add one videorefresh duration to returned timestamp
7184 * to account for this. We assume this happened if we
7185 * get called over 0.9 frame durations after the last
7186 * timestamped vblank.
7187 *
7188 * This calculation can not be used with vrefresh rates
7189 * below 5Hz (10Hz to be on the safe side) without
7190 * promoting to 64 integers.
7191 */
7192 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7193 9 * crtc->framedur_ns) {
7194 e->event.sequence++;
7195 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7196 crtc->framedur_ns);
7197 }
7198
7199 e->event.tv_sec = tvbl.tv_sec;
7200 e->event.tv_usec = tvbl.tv_usec;
7201
7202 list_add_tail(&e->base.link,
7203 &e->base.file_priv->event_list);
7204 wake_up_interruptible(&e->base.file_priv->event_wait);
7205 }
7206
7207 drm_vblank_put(dev, intel_crtc->pipe);
7208
7209 spin_unlock_irqrestore(&dev->event_lock, flags);
7210
7211 obj = work->old_fb_obj;
7212
7213 atomic_clear_mask(1 << intel_crtc->plane,
7214 &obj->pending_flip.counter);
7215 if (atomic_read(&obj->pending_flip) == 0)
7216 wake_up(&dev_priv->pending_flip_queue);
7217
7218 schedule_work(&work->work);
7219
7220 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7221 }
7222
7223 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7224 {
7225 drm_i915_private_t *dev_priv = dev->dev_private;
7226 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7227
7228 do_intel_finish_page_flip(dev, crtc);
7229 }
7230
7231 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7232 {
7233 drm_i915_private_t *dev_priv = dev->dev_private;
7234 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7235
7236 do_intel_finish_page_flip(dev, crtc);
7237 }
7238
7239 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7240 {
7241 drm_i915_private_t *dev_priv = dev->dev_private;
7242 struct intel_crtc *intel_crtc =
7243 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7244 unsigned long flags;
7245
7246 spin_lock_irqsave(&dev->event_lock, flags);
7247 if (intel_crtc->unpin_work) {
7248 if ((++intel_crtc->unpin_work->pending) > 1)
7249 DRM_ERROR("Prepared flip multiple times\n");
7250 } else {
7251 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7252 }
7253 spin_unlock_irqrestore(&dev->event_lock, flags);
7254 }
7255
7256 static int intel_gen2_queue_flip(struct drm_device *dev,
7257 struct drm_crtc *crtc,
7258 struct drm_framebuffer *fb,
7259 struct drm_i915_gem_object *obj)
7260 {
7261 struct drm_i915_private *dev_priv = dev->dev_private;
7262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7263 unsigned long offset;
7264 u32 flip_mask;
7265 int ret;
7266
7267 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7268 if (ret)
7269 goto out;
7270
7271 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7272 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7273
7274 ret = BEGIN_LP_RING(6);
7275 if (ret)
7276 goto out;
7277
7278 /* Can't queue multiple flips, so wait for the previous
7279 * one to finish before executing the next.
7280 */
7281 if (intel_crtc->plane)
7282 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7283 else
7284 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7285 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7286 OUT_RING(MI_NOOP);
7287 OUT_RING(MI_DISPLAY_FLIP |
7288 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7289 OUT_RING(fb->pitches[0]);
7290 OUT_RING(obj->gtt_offset + offset);
7291 OUT_RING(0); /* aux display base address, unused */
7292 ADVANCE_LP_RING();
7293 out:
7294 return ret;
7295 }
7296
7297 static int intel_gen3_queue_flip(struct drm_device *dev,
7298 struct drm_crtc *crtc,
7299 struct drm_framebuffer *fb,
7300 struct drm_i915_gem_object *obj)
7301 {
7302 struct drm_i915_private *dev_priv = dev->dev_private;
7303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7304 unsigned long offset;
7305 u32 flip_mask;
7306 int ret;
7307
7308 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7309 if (ret)
7310 goto out;
7311
7312 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7313 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
7314
7315 ret = BEGIN_LP_RING(6);
7316 if (ret)
7317 goto out;
7318
7319 if (intel_crtc->plane)
7320 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7321 else
7322 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7323 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7324 OUT_RING(MI_NOOP);
7325 OUT_RING(MI_DISPLAY_FLIP_I915 |
7326 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7327 OUT_RING(fb->pitches[0]);
7328 OUT_RING(obj->gtt_offset + offset);
7329 OUT_RING(MI_NOOP);
7330
7331 ADVANCE_LP_RING();
7332 out:
7333 return ret;
7334 }
7335
7336 static int intel_gen4_queue_flip(struct drm_device *dev,
7337 struct drm_crtc *crtc,
7338 struct drm_framebuffer *fb,
7339 struct drm_i915_gem_object *obj)
7340 {
7341 struct drm_i915_private *dev_priv = dev->dev_private;
7342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7343 uint32_t pf, pipesrc;
7344 int ret;
7345
7346 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7347 if (ret)
7348 goto out;
7349
7350 ret = BEGIN_LP_RING(4);
7351 if (ret)
7352 goto out;
7353
7354 /* i965+ uses the linear or tiled offsets from the
7355 * Display Registers (which do not change across a page-flip)
7356 * so we need only reprogram the base address.
7357 */
7358 OUT_RING(MI_DISPLAY_FLIP |
7359 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7360 OUT_RING(fb->pitches[0]);
7361 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7362
7363 /* XXX Enabling the panel-fitter across page-flip is so far
7364 * untested on non-native modes, so ignore it for now.
7365 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7366 */
7367 pf = 0;
7368 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7369 OUT_RING(pf | pipesrc);
7370 ADVANCE_LP_RING();
7371 out:
7372 return ret;
7373 }
7374
7375 static int intel_gen6_queue_flip(struct drm_device *dev,
7376 struct drm_crtc *crtc,
7377 struct drm_framebuffer *fb,
7378 struct drm_i915_gem_object *obj)
7379 {
7380 struct drm_i915_private *dev_priv = dev->dev_private;
7381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7382 uint32_t pf, pipesrc;
7383 int ret;
7384
7385 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7386 if (ret)
7387 goto out;
7388
7389 ret = BEGIN_LP_RING(4);
7390 if (ret)
7391 goto out;
7392
7393 OUT_RING(MI_DISPLAY_FLIP |
7394 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7395 OUT_RING(fb->pitches[0] | obj->tiling_mode);
7396 OUT_RING(obj->gtt_offset);
7397
7398 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7399 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7400 OUT_RING(pf | pipesrc);
7401 ADVANCE_LP_RING();
7402 out:
7403 return ret;
7404 }
7405
7406 /*
7407 * On gen7 we currently use the blit ring because (in early silicon at least)
7408 * the render ring doesn't give us interrpts for page flip completion, which
7409 * means clients will hang after the first flip is queued. Fortunately the
7410 * blit ring generates interrupts properly, so use it instead.
7411 */
7412 static int intel_gen7_queue_flip(struct drm_device *dev,
7413 struct drm_crtc *crtc,
7414 struct drm_framebuffer *fb,
7415 struct drm_i915_gem_object *obj)
7416 {
7417 struct drm_i915_private *dev_priv = dev->dev_private;
7418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7419 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7420 int ret;
7421
7422 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7423 if (ret)
7424 goto out;
7425
7426 ret = intel_ring_begin(ring, 4);
7427 if (ret)
7428 goto out;
7429
7430 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7431 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7432 intel_ring_emit(ring, (obj->gtt_offset));
7433 intel_ring_emit(ring, (MI_NOOP));
7434 intel_ring_advance(ring);
7435 out:
7436 return ret;
7437 }
7438
7439 static int intel_default_queue_flip(struct drm_device *dev,
7440 struct drm_crtc *crtc,
7441 struct drm_framebuffer *fb,
7442 struct drm_i915_gem_object *obj)
7443 {
7444 return -ENODEV;
7445 }
7446
7447 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7448 struct drm_framebuffer *fb,
7449 struct drm_pending_vblank_event *event)
7450 {
7451 struct drm_device *dev = crtc->dev;
7452 struct drm_i915_private *dev_priv = dev->dev_private;
7453 struct intel_framebuffer *intel_fb;
7454 struct drm_i915_gem_object *obj;
7455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7456 struct intel_unpin_work *work;
7457 unsigned long flags;
7458 int ret;
7459
7460 work = kzalloc(sizeof *work, GFP_KERNEL);
7461 if (work == NULL)
7462 return -ENOMEM;
7463
7464 work->event = event;
7465 work->dev = crtc->dev;
7466 intel_fb = to_intel_framebuffer(crtc->fb);
7467 work->old_fb_obj = intel_fb->obj;
7468 INIT_WORK(&work->work, intel_unpin_work_fn);
7469
7470 ret = drm_vblank_get(dev, intel_crtc->pipe);
7471 if (ret)
7472 goto free_work;
7473
7474 /* We borrow the event spin lock for protecting unpin_work */
7475 spin_lock_irqsave(&dev->event_lock, flags);
7476 if (intel_crtc->unpin_work) {
7477 spin_unlock_irqrestore(&dev->event_lock, flags);
7478 kfree(work);
7479 drm_vblank_put(dev, intel_crtc->pipe);
7480
7481 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7482 return -EBUSY;
7483 }
7484 intel_crtc->unpin_work = work;
7485 spin_unlock_irqrestore(&dev->event_lock, flags);
7486
7487 intel_fb = to_intel_framebuffer(fb);
7488 obj = intel_fb->obj;
7489
7490 mutex_lock(&dev->struct_mutex);
7491
7492 /* Reference the objects for the scheduled work. */
7493 drm_gem_object_reference(&work->old_fb_obj->base);
7494 drm_gem_object_reference(&obj->base);
7495
7496 crtc->fb = fb;
7497
7498 work->pending_flip_obj = obj;
7499
7500 work->enable_stall_check = true;
7501
7502 /* Block clients from rendering to the new back buffer until
7503 * the flip occurs and the object is no longer visible.
7504 */
7505 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7506
7507 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7508 if (ret)
7509 goto cleanup_pending;
7510
7511 intel_disable_fbc(dev);
7512 mutex_unlock(&dev->struct_mutex);
7513
7514 trace_i915_flip_request(intel_crtc->plane, obj);
7515
7516 return 0;
7517
7518 cleanup_pending:
7519 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7520 drm_gem_object_unreference(&work->old_fb_obj->base);
7521 drm_gem_object_unreference(&obj->base);
7522 mutex_unlock(&dev->struct_mutex);
7523
7524 spin_lock_irqsave(&dev->event_lock, flags);
7525 intel_crtc->unpin_work = NULL;
7526 spin_unlock_irqrestore(&dev->event_lock, flags);
7527
7528 drm_vblank_put(dev, intel_crtc->pipe);
7529 free_work:
7530 kfree(work);
7531
7532 return ret;
7533 }
7534
7535 static void intel_sanitize_modesetting(struct drm_device *dev,
7536 int pipe, int plane)
7537 {
7538 struct drm_i915_private *dev_priv = dev->dev_private;
7539 u32 reg, val;
7540
7541 if (HAS_PCH_SPLIT(dev))
7542 return;
7543
7544 /* Who knows what state these registers were left in by the BIOS or
7545 * grub?
7546 *
7547 * If we leave the registers in a conflicting state (e.g. with the
7548 * display plane reading from the other pipe than the one we intend
7549 * to use) then when we attempt to teardown the active mode, we will
7550 * not disable the pipes and planes in the correct order -- leaving
7551 * a plane reading from a disabled pipe and possibly leading to
7552 * undefined behaviour.
7553 */
7554
7555 reg = DSPCNTR(plane);
7556 val = I915_READ(reg);
7557
7558 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7559 return;
7560 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7561 return;
7562
7563 /* This display plane is active and attached to the other CPU pipe. */
7564 pipe = !pipe;
7565
7566 /* Disable the plane and wait for it to stop reading from the pipe. */
7567 intel_disable_plane(dev_priv, plane, pipe);
7568 intel_disable_pipe(dev_priv, pipe);
7569 }
7570
7571 static void intel_crtc_reset(struct drm_crtc *crtc)
7572 {
7573 struct drm_device *dev = crtc->dev;
7574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7575
7576 /* Reset flags back to the 'unknown' status so that they
7577 * will be correctly set on the initial modeset.
7578 */
7579 intel_crtc->dpms_mode = -1;
7580
7581 /* We need to fix up any BIOS configuration that conflicts with
7582 * our expectations.
7583 */
7584 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7585 }
7586
7587 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7588 .dpms = intel_crtc_dpms,
7589 .mode_fixup = intel_crtc_mode_fixup,
7590 .mode_set = intel_crtc_mode_set,
7591 .mode_set_base = intel_pipe_set_base,
7592 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7593 .load_lut = intel_crtc_load_lut,
7594 .disable = intel_crtc_disable,
7595 };
7596
7597 static const struct drm_crtc_funcs intel_crtc_funcs = {
7598 .reset = intel_crtc_reset,
7599 .cursor_set = intel_crtc_cursor_set,
7600 .cursor_move = intel_crtc_cursor_move,
7601 .gamma_set = intel_crtc_gamma_set,
7602 .set_config = drm_crtc_helper_set_config,
7603 .destroy = intel_crtc_destroy,
7604 .page_flip = intel_crtc_page_flip,
7605 };
7606
7607 static void intel_crtc_init(struct drm_device *dev, int pipe)
7608 {
7609 drm_i915_private_t *dev_priv = dev->dev_private;
7610 struct intel_crtc *intel_crtc;
7611 int i;
7612
7613 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7614 if (intel_crtc == NULL)
7615 return;
7616
7617 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7618
7619 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
7620 for (i = 0; i < 256; i++) {
7621 intel_crtc->lut_r[i] = i;
7622 intel_crtc->lut_g[i] = i;
7623 intel_crtc->lut_b[i] = i;
7624 }
7625
7626 /* Swap pipes & planes for FBC on pre-965 */
7627 intel_crtc->pipe = pipe;
7628 intel_crtc->plane = pipe;
7629 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
7630 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7631 intel_crtc->plane = !pipe;
7632 }
7633
7634 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7635 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7636 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7637 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7638
7639 intel_crtc_reset(&intel_crtc->base);
7640 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7641 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7642
7643 if (HAS_PCH_SPLIT(dev)) {
7644 if (pipe == 2 && IS_IVYBRIDGE(dev))
7645 intel_crtc->no_pll = true;
7646 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7647 intel_helper_funcs.commit = ironlake_crtc_commit;
7648 } else {
7649 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7650 intel_helper_funcs.commit = i9xx_crtc_commit;
7651 }
7652
7653 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7654
7655 intel_crtc->busy = false;
7656
7657 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7658 (unsigned long)intel_crtc);
7659 }
7660
7661 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
7662 struct drm_file *file)
7663 {
7664 drm_i915_private_t *dev_priv = dev->dev_private;
7665 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7666 struct drm_mode_object *drmmode_obj;
7667 struct intel_crtc *crtc;
7668
7669 if (!dev_priv) {
7670 DRM_ERROR("called with no initialization\n");
7671 return -EINVAL;
7672 }
7673
7674 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7675 DRM_MODE_OBJECT_CRTC);
7676
7677 if (!drmmode_obj) {
7678 DRM_ERROR("no such CRTC id\n");
7679 return -EINVAL;
7680 }
7681
7682 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7683 pipe_from_crtc_id->pipe = crtc->pipe;
7684
7685 return 0;
7686 }
7687
7688 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
7689 {
7690 struct intel_encoder *encoder;
7691 int index_mask = 0;
7692 int entry = 0;
7693
7694 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7695 if (type_mask & encoder->clone_mask)
7696 index_mask |= (1 << entry);
7697 entry++;
7698 }
7699
7700 return index_mask;
7701 }
7702
7703 static bool has_edp_a(struct drm_device *dev)
7704 {
7705 struct drm_i915_private *dev_priv = dev->dev_private;
7706
7707 if (!IS_MOBILE(dev))
7708 return false;
7709
7710 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7711 return false;
7712
7713 if (IS_GEN5(dev) &&
7714 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7715 return false;
7716
7717 return true;
7718 }
7719
7720 static void intel_setup_outputs(struct drm_device *dev)
7721 {
7722 struct drm_i915_private *dev_priv = dev->dev_private;
7723 struct intel_encoder *encoder;
7724 bool dpd_is_edp = false;
7725 bool has_lvds = false;
7726
7727 if (IS_MOBILE(dev) && !IS_I830(dev))
7728 has_lvds = intel_lvds_init(dev);
7729 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7730 /* disable the panel fitter on everything but LVDS */
7731 I915_WRITE(PFIT_CONTROL, 0);
7732 }
7733
7734 if (HAS_PCH_SPLIT(dev)) {
7735 dpd_is_edp = intel_dpd_is_edp(dev);
7736
7737 if (has_edp_a(dev))
7738 intel_dp_init(dev, DP_A);
7739
7740 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7741 intel_dp_init(dev, PCH_DP_D);
7742 }
7743
7744 intel_crt_init(dev);
7745
7746 if (HAS_PCH_SPLIT(dev)) {
7747 int found;
7748
7749 if (I915_READ(HDMIB) & PORT_DETECTED) {
7750 /* PCH SDVOB multiplex with HDMIB */
7751 found = intel_sdvo_init(dev, PCH_SDVOB);
7752 if (!found)
7753 intel_hdmi_init(dev, HDMIB);
7754 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7755 intel_dp_init(dev, PCH_DP_B);
7756 }
7757
7758 if (I915_READ(HDMIC) & PORT_DETECTED)
7759 intel_hdmi_init(dev, HDMIC);
7760
7761 if (I915_READ(HDMID) & PORT_DETECTED)
7762 intel_hdmi_init(dev, HDMID);
7763
7764 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7765 intel_dp_init(dev, PCH_DP_C);
7766
7767 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7768 intel_dp_init(dev, PCH_DP_D);
7769
7770 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
7771 bool found = false;
7772
7773 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7774 DRM_DEBUG_KMS("probing SDVOB\n");
7775 found = intel_sdvo_init(dev, SDVOB);
7776 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7777 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7778 intel_hdmi_init(dev, SDVOB);
7779 }
7780
7781 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7782 DRM_DEBUG_KMS("probing DP_B\n");
7783 intel_dp_init(dev, DP_B);
7784 }
7785 }
7786
7787 /* Before G4X SDVOC doesn't have its own detect register */
7788
7789 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7790 DRM_DEBUG_KMS("probing SDVOC\n");
7791 found = intel_sdvo_init(dev, SDVOC);
7792 }
7793
7794 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7795
7796 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7797 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7798 intel_hdmi_init(dev, SDVOC);
7799 }
7800 if (SUPPORTS_INTEGRATED_DP(dev)) {
7801 DRM_DEBUG_KMS("probing DP_C\n");
7802 intel_dp_init(dev, DP_C);
7803 }
7804 }
7805
7806 if (SUPPORTS_INTEGRATED_DP(dev) &&
7807 (I915_READ(DP_D) & DP_DETECTED)) {
7808 DRM_DEBUG_KMS("probing DP_D\n");
7809 intel_dp_init(dev, DP_D);
7810 }
7811 } else if (IS_GEN2(dev))
7812 intel_dvo_init(dev);
7813
7814 if (SUPPORTS_TV(dev))
7815 intel_tv_init(dev);
7816
7817 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7818 encoder->base.possible_crtcs = encoder->crtc_mask;
7819 encoder->base.possible_clones =
7820 intel_encoder_clones(dev, encoder->clone_mask);
7821 }
7822
7823 /* disable all the possible outputs/crtcs before entering KMS mode */
7824 drm_helper_disable_unused_functions(dev);
7825
7826 if (HAS_PCH_SPLIT(dev))
7827 ironlake_init_pch_refclk(dev);
7828 }
7829
7830 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7831 {
7832 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7833
7834 drm_framebuffer_cleanup(fb);
7835 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
7836
7837 kfree(intel_fb);
7838 }
7839
7840 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
7841 struct drm_file *file,
7842 unsigned int *handle)
7843 {
7844 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
7845 struct drm_i915_gem_object *obj = intel_fb->obj;
7846
7847 return drm_gem_handle_create(file, &obj->base, handle);
7848 }
7849
7850 static const struct drm_framebuffer_funcs intel_fb_funcs = {
7851 .destroy = intel_user_framebuffer_destroy,
7852 .create_handle = intel_user_framebuffer_create_handle,
7853 };
7854
7855 int intel_framebuffer_init(struct drm_device *dev,
7856 struct intel_framebuffer *intel_fb,
7857 struct drm_mode_fb_cmd2 *mode_cmd,
7858 struct drm_i915_gem_object *obj)
7859 {
7860 int ret;
7861
7862 if (obj->tiling_mode == I915_TILING_Y)
7863 return -EINVAL;
7864
7865 if (mode_cmd->pitches[0] & 63)
7866 return -EINVAL;
7867
7868 switch (mode_cmd->pixel_format) {
7869 case DRM_FORMAT_RGB332:
7870 case DRM_FORMAT_RGB565:
7871 case DRM_FORMAT_XRGB8888:
7872 case DRM_FORMAT_ARGB8888:
7873 case DRM_FORMAT_XRGB2101010:
7874 case DRM_FORMAT_ARGB2101010:
7875 /* RGB formats are common across chipsets */
7876 break;
7877 case DRM_FORMAT_YUYV:
7878 case DRM_FORMAT_UYVY:
7879 case DRM_FORMAT_YVYU:
7880 case DRM_FORMAT_VYUY:
7881 break;
7882 default:
7883 DRM_ERROR("unsupported pixel format\n");
7884 return -EINVAL;
7885 }
7886
7887 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7888 if (ret) {
7889 DRM_ERROR("framebuffer init failed %d\n", ret);
7890 return ret;
7891 }
7892
7893 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
7894 intel_fb->obj = obj;
7895 return 0;
7896 }
7897
7898 static struct drm_framebuffer *
7899 intel_user_framebuffer_create(struct drm_device *dev,
7900 struct drm_file *filp,
7901 struct drm_mode_fb_cmd2 *mode_cmd)
7902 {
7903 struct drm_i915_gem_object *obj;
7904
7905 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7906 mode_cmd->handles[0]));
7907 if (&obj->base == NULL)
7908 return ERR_PTR(-ENOENT);
7909
7910 return intel_framebuffer_create(dev, mode_cmd, obj);
7911 }
7912
7913 static const struct drm_mode_config_funcs intel_mode_funcs = {
7914 .fb_create = intel_user_framebuffer_create,
7915 .output_poll_changed = intel_fb_output_poll_changed,
7916 };
7917
7918 static struct drm_i915_gem_object *
7919 intel_alloc_context_page(struct drm_device *dev)
7920 {
7921 struct drm_i915_gem_object *ctx;
7922 int ret;
7923
7924 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7925
7926 ctx = i915_gem_alloc_object(dev, 4096);
7927 if (!ctx) {
7928 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7929 return NULL;
7930 }
7931
7932 ret = i915_gem_object_pin(ctx, 4096, true);
7933 if (ret) {
7934 DRM_ERROR("failed to pin power context: %d\n", ret);
7935 goto err_unref;
7936 }
7937
7938 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
7939 if (ret) {
7940 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7941 goto err_unpin;
7942 }
7943
7944 return ctx;
7945
7946 err_unpin:
7947 i915_gem_object_unpin(ctx);
7948 err_unref:
7949 drm_gem_object_unreference(&ctx->base);
7950 mutex_unlock(&dev->struct_mutex);
7951 return NULL;
7952 }
7953
7954 bool ironlake_set_drps(struct drm_device *dev, u8 val)
7955 {
7956 struct drm_i915_private *dev_priv = dev->dev_private;
7957 u16 rgvswctl;
7958
7959 rgvswctl = I915_READ16(MEMSWCTL);
7960 if (rgvswctl & MEMCTL_CMD_STS) {
7961 DRM_DEBUG("gpu busy, RCS change rejected\n");
7962 return false; /* still busy with another command */
7963 }
7964
7965 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7966 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7967 I915_WRITE16(MEMSWCTL, rgvswctl);
7968 POSTING_READ16(MEMSWCTL);
7969
7970 rgvswctl |= MEMCTL_CMD_STS;
7971 I915_WRITE16(MEMSWCTL, rgvswctl);
7972
7973 return true;
7974 }
7975
7976 void ironlake_enable_drps(struct drm_device *dev)
7977 {
7978 struct drm_i915_private *dev_priv = dev->dev_private;
7979 u32 rgvmodectl = I915_READ(MEMMODECTL);
7980 u8 fmax, fmin, fstart, vstart;
7981
7982 /* Enable temp reporting */
7983 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7984 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7985
7986 /* 100ms RC evaluation intervals */
7987 I915_WRITE(RCUPEI, 100000);
7988 I915_WRITE(RCDNEI, 100000);
7989
7990 /* Set max/min thresholds to 90ms and 80ms respectively */
7991 I915_WRITE(RCBMAXAVG, 90000);
7992 I915_WRITE(RCBMINAVG, 80000);
7993
7994 I915_WRITE(MEMIHYST, 1);
7995
7996 /* Set up min, max, and cur for interrupt handling */
7997 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7998 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7999 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8000 MEMMODE_FSTART_SHIFT;
8001
8002 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8003 PXVFREQ_PX_SHIFT;
8004
8005 dev_priv->fmax = fmax; /* IPS callback will increase this */
8006 dev_priv->fstart = fstart;
8007
8008 dev_priv->max_delay = fstart;
8009 dev_priv->min_delay = fmin;
8010 dev_priv->cur_delay = fstart;
8011
8012 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8013 fmax, fmin, fstart);
8014
8015 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8016
8017 /*
8018 * Interrupts will be enabled in ironlake_irq_postinstall
8019 */
8020
8021 I915_WRITE(VIDSTART, vstart);
8022 POSTING_READ(VIDSTART);
8023
8024 rgvmodectl |= MEMMODE_SWMODE_EN;
8025 I915_WRITE(MEMMODECTL, rgvmodectl);
8026
8027 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
8028 DRM_ERROR("stuck trying to change perf mode\n");
8029 msleep(1);
8030
8031 ironlake_set_drps(dev, fstart);
8032
8033 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8034 I915_READ(0x112e0);
8035 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8036 dev_priv->last_count2 = I915_READ(0x112f4);
8037 getrawmonotonic(&dev_priv->last_time2);
8038 }
8039
8040 void ironlake_disable_drps(struct drm_device *dev)
8041 {
8042 struct drm_i915_private *dev_priv = dev->dev_private;
8043 u16 rgvswctl = I915_READ16(MEMSWCTL);
8044
8045 /* Ack interrupts, disable EFC interrupt */
8046 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8047 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8048 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8049 I915_WRITE(DEIIR, DE_PCU_EVENT);
8050 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8051
8052 /* Go back to the starting frequency */
8053 ironlake_set_drps(dev, dev_priv->fstart);
8054 msleep(1);
8055 rgvswctl |= MEMCTL_CMD_STS;
8056 I915_WRITE(MEMSWCTL, rgvswctl);
8057 msleep(1);
8058
8059 }
8060
8061 void gen6_set_rps(struct drm_device *dev, u8 val)
8062 {
8063 struct drm_i915_private *dev_priv = dev->dev_private;
8064 u32 swreq;
8065
8066 swreq = (val & 0x3ff) << 25;
8067 I915_WRITE(GEN6_RPNSWREQ, swreq);
8068 }
8069
8070 void gen6_disable_rps(struct drm_device *dev)
8071 {
8072 struct drm_i915_private *dev_priv = dev->dev_private;
8073
8074 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8075 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8076 I915_WRITE(GEN6_PMIER, 0);
8077 /* Complete PM interrupt masking here doesn't race with the rps work
8078 * item again unmasking PM interrupts because that is using a different
8079 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8080 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8081
8082 spin_lock_irq(&dev_priv->rps_lock);
8083 dev_priv->pm_iir = 0;
8084 spin_unlock_irq(&dev_priv->rps_lock);
8085
8086 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8087 }
8088
8089 static unsigned long intel_pxfreq(u32 vidfreq)
8090 {
8091 unsigned long freq;
8092 int div = (vidfreq & 0x3f0000) >> 16;
8093 int post = (vidfreq & 0x3000) >> 12;
8094 int pre = (vidfreq & 0x7);
8095
8096 if (!pre)
8097 return 0;
8098
8099 freq = ((div * 133333) / ((1<<post) * pre));
8100
8101 return freq;
8102 }
8103
8104 void intel_init_emon(struct drm_device *dev)
8105 {
8106 struct drm_i915_private *dev_priv = dev->dev_private;
8107 u32 lcfuse;
8108 u8 pxw[16];
8109 int i;
8110
8111 /* Disable to program */
8112 I915_WRITE(ECR, 0);
8113 POSTING_READ(ECR);
8114
8115 /* Program energy weights for various events */
8116 I915_WRITE(SDEW, 0x15040d00);
8117 I915_WRITE(CSIEW0, 0x007f0000);
8118 I915_WRITE(CSIEW1, 0x1e220004);
8119 I915_WRITE(CSIEW2, 0x04000004);
8120
8121 for (i = 0; i < 5; i++)
8122 I915_WRITE(PEW + (i * 4), 0);
8123 for (i = 0; i < 3; i++)
8124 I915_WRITE(DEW + (i * 4), 0);
8125
8126 /* Program P-state weights to account for frequency power adjustment */
8127 for (i = 0; i < 16; i++) {
8128 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8129 unsigned long freq = intel_pxfreq(pxvidfreq);
8130 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8131 PXVFREQ_PX_SHIFT;
8132 unsigned long val;
8133
8134 val = vid * vid;
8135 val *= (freq / 1000);
8136 val *= 255;
8137 val /= (127*127*900);
8138 if (val > 0xff)
8139 DRM_ERROR("bad pxval: %ld\n", val);
8140 pxw[i] = val;
8141 }
8142 /* Render standby states get 0 weight */
8143 pxw[14] = 0;
8144 pxw[15] = 0;
8145
8146 for (i = 0; i < 4; i++) {
8147 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8148 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8149 I915_WRITE(PXW + (i * 4), val);
8150 }
8151
8152 /* Adjust magic regs to magic values (more experimental results) */
8153 I915_WRITE(OGW0, 0);
8154 I915_WRITE(OGW1, 0);
8155 I915_WRITE(EG0, 0x00007f00);
8156 I915_WRITE(EG1, 0x0000000e);
8157 I915_WRITE(EG2, 0x000e0000);
8158 I915_WRITE(EG3, 0x68000300);
8159 I915_WRITE(EG4, 0x42000000);
8160 I915_WRITE(EG5, 0x00140031);
8161 I915_WRITE(EG6, 0);
8162 I915_WRITE(EG7, 0);
8163
8164 for (i = 0; i < 8; i++)
8165 I915_WRITE(PXWL + (i * 4), 0);
8166
8167 /* Enable PMON + select events */
8168 I915_WRITE(ECR, 0x80000019);
8169
8170 lcfuse = I915_READ(LCFUSE02);
8171
8172 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8173 }
8174
8175 static bool intel_enable_rc6(struct drm_device *dev)
8176 {
8177 /*
8178 * Respect the kernel parameter if it is set
8179 */
8180 if (i915_enable_rc6 >= 0)
8181 return i915_enable_rc6;
8182
8183 /*
8184 * Disable RC6 on Ironlake
8185 */
8186 if (INTEL_INFO(dev)->gen == 5)
8187 return 0;
8188
8189 /*
8190 * Enable rc6 on Sandybridge if DMA remapping is disabled
8191 */
8192 if (INTEL_INFO(dev)->gen == 6) {
8193 DRM_DEBUG_DRIVER("Sandybridge: intel_iommu_enabled %s -- RC6 %sabled\n",
8194 intel_iommu_enabled ? "true" : "false",
8195 !intel_iommu_enabled ? "en" : "dis");
8196 return !intel_iommu_enabled;
8197 }
8198 DRM_DEBUG_DRIVER("RC6 enabled\n");
8199 return 1;
8200 }
8201
8202 void gen6_enable_rps(struct drm_i915_private *dev_priv)
8203 {
8204 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8205 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
8206 u32 pcu_mbox, rc6_mask = 0;
8207 int cur_freq, min_freq, max_freq;
8208 int i;
8209
8210 /* Here begins a magic sequence of register writes to enable
8211 * auto-downclocking.
8212 *
8213 * Perhaps there might be some value in exposing these to
8214 * userspace...
8215 */
8216 I915_WRITE(GEN6_RC_STATE, 0);
8217 mutex_lock(&dev_priv->dev->struct_mutex);
8218 gen6_gt_force_wake_get(dev_priv);
8219
8220 /* disable the counters and set deterministic thresholds */
8221 I915_WRITE(GEN6_RC_CONTROL, 0);
8222
8223 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8224 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8225 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8226 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8227 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8228
8229 for (i = 0; i < I915_NUM_RINGS; i++)
8230 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8231
8232 I915_WRITE(GEN6_RC_SLEEP, 0);
8233 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8234 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8235 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8236 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8237
8238 if (intel_enable_rc6(dev_priv->dev))
8239 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8240 GEN6_RC_CTL_RC6_ENABLE;
8241
8242 I915_WRITE(GEN6_RC_CONTROL,
8243 rc6_mask |
8244 GEN6_RC_CTL_EI_MODE(1) |
8245 GEN6_RC_CTL_HW_ENABLE);
8246
8247 I915_WRITE(GEN6_RPNSWREQ,
8248 GEN6_FREQUENCY(10) |
8249 GEN6_OFFSET(0) |
8250 GEN6_AGGRESSIVE_TURBO);
8251 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8252 GEN6_FREQUENCY(12));
8253
8254 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8255 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8256 18 << 24 |
8257 6 << 16);
8258 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8259 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8260 I915_WRITE(GEN6_RP_UP_EI, 100000);
8261 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8262 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8263 I915_WRITE(GEN6_RP_CONTROL,
8264 GEN6_RP_MEDIA_TURBO |
8265 GEN6_RP_MEDIA_HW_MODE |
8266 GEN6_RP_MEDIA_IS_GFX |
8267 GEN6_RP_ENABLE |
8268 GEN6_RP_UP_BUSY_AVG |
8269 GEN6_RP_DOWN_IDLE_CONT);
8270
8271 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8272 500))
8273 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8274
8275 I915_WRITE(GEN6_PCODE_DATA, 0);
8276 I915_WRITE(GEN6_PCODE_MAILBOX,
8277 GEN6_PCODE_READY |
8278 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8279 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8280 500))
8281 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8282
8283 min_freq = (rp_state_cap & 0xff0000) >> 16;
8284 max_freq = rp_state_cap & 0xff;
8285 cur_freq = (gt_perf_status & 0xff00) >> 8;
8286
8287 /* Check for overclock support */
8288 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8289 500))
8290 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8291 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8292 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8293 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8294 500))
8295 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8296 if (pcu_mbox & (1<<31)) { /* OC supported */
8297 max_freq = pcu_mbox & 0xff;
8298 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
8299 }
8300
8301 /* In units of 100MHz */
8302 dev_priv->max_delay = max_freq;
8303 dev_priv->min_delay = min_freq;
8304 dev_priv->cur_delay = cur_freq;
8305
8306 /* requires MSI enabled */
8307 I915_WRITE(GEN6_PMIER,
8308 GEN6_PM_MBOX_EVENT |
8309 GEN6_PM_THERMAL_EVENT |
8310 GEN6_PM_RP_DOWN_TIMEOUT |
8311 GEN6_PM_RP_UP_THRESHOLD |
8312 GEN6_PM_RP_DOWN_THRESHOLD |
8313 GEN6_PM_RP_UP_EI_EXPIRED |
8314 GEN6_PM_RP_DOWN_EI_EXPIRED);
8315 spin_lock_irq(&dev_priv->rps_lock);
8316 WARN_ON(dev_priv->pm_iir != 0);
8317 I915_WRITE(GEN6_PMIMR, 0);
8318 spin_unlock_irq(&dev_priv->rps_lock);
8319 /* enable all PM interrupts */
8320 I915_WRITE(GEN6_PMINTRMSK, 0);
8321
8322 gen6_gt_force_wake_put(dev_priv);
8323 mutex_unlock(&dev_priv->dev->struct_mutex);
8324 }
8325
8326 void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8327 {
8328 int min_freq = 15;
8329 int gpu_freq, ia_freq, max_ia_freq;
8330 int scaling_factor = 180;
8331
8332 max_ia_freq = cpufreq_quick_get_max(0);
8333 /*
8334 * Default to measured freq if none found, PCU will ensure we don't go
8335 * over
8336 */
8337 if (!max_ia_freq)
8338 max_ia_freq = tsc_khz;
8339
8340 /* Convert from kHz to MHz */
8341 max_ia_freq /= 1000;
8342
8343 mutex_lock(&dev_priv->dev->struct_mutex);
8344
8345 /*
8346 * For each potential GPU frequency, load a ring frequency we'd like
8347 * to use for memory access. We do this by specifying the IA frequency
8348 * the PCU should use as a reference to determine the ring frequency.
8349 */
8350 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8351 gpu_freq--) {
8352 int diff = dev_priv->max_delay - gpu_freq;
8353
8354 /*
8355 * For GPU frequencies less than 750MHz, just use the lowest
8356 * ring freq.
8357 */
8358 if (gpu_freq < min_freq)
8359 ia_freq = 800;
8360 else
8361 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8362 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8363
8364 I915_WRITE(GEN6_PCODE_DATA,
8365 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8366 gpu_freq);
8367 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8368 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8369 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8370 GEN6_PCODE_READY) == 0, 10)) {
8371 DRM_ERROR("pcode write of freq table timed out\n");
8372 continue;
8373 }
8374 }
8375
8376 mutex_unlock(&dev_priv->dev->struct_mutex);
8377 }
8378
8379 static void ironlake_init_clock_gating(struct drm_device *dev)
8380 {
8381 struct drm_i915_private *dev_priv = dev->dev_private;
8382 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8383
8384 /* Required for FBC */
8385 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8386 DPFCRUNIT_CLOCK_GATE_DISABLE |
8387 DPFDUNIT_CLOCK_GATE_DISABLE;
8388 /* Required for CxSR */
8389 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8390
8391 I915_WRITE(PCH_3DCGDIS0,
8392 MARIUNIT_CLOCK_GATE_DISABLE |
8393 SVSMUNIT_CLOCK_GATE_DISABLE);
8394 I915_WRITE(PCH_3DCGDIS1,
8395 VFMUNIT_CLOCK_GATE_DISABLE);
8396
8397 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8398
8399 /*
8400 * According to the spec the following bits should be set in
8401 * order to enable memory self-refresh
8402 * The bit 22/21 of 0x42004
8403 * The bit 5 of 0x42020
8404 * The bit 15 of 0x45000
8405 */
8406 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8407 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8408 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8409 I915_WRITE(ILK_DSPCLK_GATE,
8410 (I915_READ(ILK_DSPCLK_GATE) |
8411 ILK_DPARB_CLK_GATE));
8412 I915_WRITE(DISP_ARB_CTL,
8413 (I915_READ(DISP_ARB_CTL) |
8414 DISP_FBC_WM_DIS));
8415 I915_WRITE(WM3_LP_ILK, 0);
8416 I915_WRITE(WM2_LP_ILK, 0);
8417 I915_WRITE(WM1_LP_ILK, 0);
8418
8419 /*
8420 * Based on the document from hardware guys the following bits
8421 * should be set unconditionally in order to enable FBC.
8422 * The bit 22 of 0x42000
8423 * The bit 22 of 0x42004
8424 * The bit 7,8,9 of 0x42020.
8425 */
8426 if (IS_IRONLAKE_M(dev)) {
8427 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8428 I915_READ(ILK_DISPLAY_CHICKEN1) |
8429 ILK_FBCQ_DIS);
8430 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8431 I915_READ(ILK_DISPLAY_CHICKEN2) |
8432 ILK_DPARB_GATE);
8433 I915_WRITE(ILK_DSPCLK_GATE,
8434 I915_READ(ILK_DSPCLK_GATE) |
8435 ILK_DPFC_DIS1 |
8436 ILK_DPFC_DIS2 |
8437 ILK_CLK_FBC);
8438 }
8439
8440 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8441 I915_READ(ILK_DISPLAY_CHICKEN2) |
8442 ILK_ELPIN_409_SELECT);
8443 I915_WRITE(_3D_CHICKEN2,
8444 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8445 _3D_CHICKEN2_WM_READ_PIPELINED);
8446 }
8447
8448 static void gen6_init_clock_gating(struct drm_device *dev)
8449 {
8450 struct drm_i915_private *dev_priv = dev->dev_private;
8451 int pipe;
8452 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8453
8454 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8455
8456 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8457 I915_READ(ILK_DISPLAY_CHICKEN2) |
8458 ILK_ELPIN_409_SELECT);
8459
8460 I915_WRITE(WM3_LP_ILK, 0);
8461 I915_WRITE(WM2_LP_ILK, 0);
8462 I915_WRITE(WM1_LP_ILK, 0);
8463
8464 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8465 * gating disable must be set. Failure to set it results in
8466 * flickering pixels due to Z write ordering failures after
8467 * some amount of runtime in the Mesa "fire" demo, and Unigine
8468 * Sanctuary and Tropics, and apparently anything else with
8469 * alpha test or pixel discard.
8470 *
8471 * According to the spec, bit 11 (RCCUNIT) must also be set,
8472 * but we didn't debug actual testcases to find it out.
8473 */
8474 I915_WRITE(GEN6_UCGCTL2,
8475 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8476 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
8477
8478 /*
8479 * According to the spec the following bits should be
8480 * set in order to enable memory self-refresh and fbc:
8481 * The bit21 and bit22 of 0x42000
8482 * The bit21 and bit22 of 0x42004
8483 * The bit5 and bit7 of 0x42020
8484 * The bit14 of 0x70180
8485 * The bit14 of 0x71180
8486 */
8487 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8488 I915_READ(ILK_DISPLAY_CHICKEN1) |
8489 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8490 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8491 I915_READ(ILK_DISPLAY_CHICKEN2) |
8492 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8493 I915_WRITE(ILK_DSPCLK_GATE,
8494 I915_READ(ILK_DSPCLK_GATE) |
8495 ILK_DPARB_CLK_GATE |
8496 ILK_DPFD_CLK_GATE);
8497
8498 for_each_pipe(pipe) {
8499 I915_WRITE(DSPCNTR(pipe),
8500 I915_READ(DSPCNTR(pipe)) |
8501 DISPPLANE_TRICKLE_FEED_DISABLE);
8502 intel_flush_display_plane(dev_priv, pipe);
8503 }
8504 }
8505
8506 static void ivybridge_init_clock_gating(struct drm_device *dev)
8507 {
8508 struct drm_i915_private *dev_priv = dev->dev_private;
8509 int pipe;
8510 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8511
8512 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8513
8514 I915_WRITE(WM3_LP_ILK, 0);
8515 I915_WRITE(WM2_LP_ILK, 0);
8516 I915_WRITE(WM1_LP_ILK, 0);
8517
8518 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
8519
8520 I915_WRITE(IVB_CHICKEN3,
8521 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8522 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8523
8524 for_each_pipe(pipe) {
8525 I915_WRITE(DSPCNTR(pipe),
8526 I915_READ(DSPCNTR(pipe)) |
8527 DISPPLANE_TRICKLE_FEED_DISABLE);
8528 intel_flush_display_plane(dev_priv, pipe);
8529 }
8530 }
8531
8532 static void g4x_init_clock_gating(struct drm_device *dev)
8533 {
8534 struct drm_i915_private *dev_priv = dev->dev_private;
8535 uint32_t dspclk_gate;
8536
8537 I915_WRITE(RENCLK_GATE_D1, 0);
8538 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8539 GS_UNIT_CLOCK_GATE_DISABLE |
8540 CL_UNIT_CLOCK_GATE_DISABLE);
8541 I915_WRITE(RAMCLK_GATE_D, 0);
8542 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8543 OVRUNIT_CLOCK_GATE_DISABLE |
8544 OVCUNIT_CLOCK_GATE_DISABLE;
8545 if (IS_GM45(dev))
8546 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8547 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8548 }
8549
8550 static void crestline_init_clock_gating(struct drm_device *dev)
8551 {
8552 struct drm_i915_private *dev_priv = dev->dev_private;
8553
8554 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8555 I915_WRITE(RENCLK_GATE_D2, 0);
8556 I915_WRITE(DSPCLK_GATE_D, 0);
8557 I915_WRITE(RAMCLK_GATE_D, 0);
8558 I915_WRITE16(DEUC, 0);
8559 }
8560
8561 static void broadwater_init_clock_gating(struct drm_device *dev)
8562 {
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564
8565 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8566 I965_RCC_CLOCK_GATE_DISABLE |
8567 I965_RCPB_CLOCK_GATE_DISABLE |
8568 I965_ISC_CLOCK_GATE_DISABLE |
8569 I965_FBC_CLOCK_GATE_DISABLE);
8570 I915_WRITE(RENCLK_GATE_D2, 0);
8571 }
8572
8573 static void gen3_init_clock_gating(struct drm_device *dev)
8574 {
8575 struct drm_i915_private *dev_priv = dev->dev_private;
8576 u32 dstate = I915_READ(D_STATE);
8577
8578 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8579 DSTATE_DOT_CLOCK_GATING;
8580 I915_WRITE(D_STATE, dstate);
8581 }
8582
8583 static void i85x_init_clock_gating(struct drm_device *dev)
8584 {
8585 struct drm_i915_private *dev_priv = dev->dev_private;
8586
8587 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8588 }
8589
8590 static void i830_init_clock_gating(struct drm_device *dev)
8591 {
8592 struct drm_i915_private *dev_priv = dev->dev_private;
8593
8594 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
8595 }
8596
8597 static void ibx_init_clock_gating(struct drm_device *dev)
8598 {
8599 struct drm_i915_private *dev_priv = dev->dev_private;
8600
8601 /*
8602 * On Ibex Peak and Cougar Point, we need to disable clock
8603 * gating for the panel power sequencer or it will fail to
8604 * start up when no ports are active.
8605 */
8606 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8607 }
8608
8609 static void cpt_init_clock_gating(struct drm_device *dev)
8610 {
8611 struct drm_i915_private *dev_priv = dev->dev_private;
8612 int pipe;
8613
8614 /*
8615 * On Ibex Peak and Cougar Point, we need to disable clock
8616 * gating for the panel power sequencer or it will fail to
8617 * start up when no ports are active.
8618 */
8619 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8620 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8621 DPLS_EDP_PPS_FIX_DIS);
8622 /* Without this, mode sets may fail silently on FDI */
8623 for_each_pipe(pipe)
8624 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
8625 }
8626
8627 static void ironlake_teardown_rc6(struct drm_device *dev)
8628 {
8629 struct drm_i915_private *dev_priv = dev->dev_private;
8630
8631 if (dev_priv->renderctx) {
8632 i915_gem_object_unpin(dev_priv->renderctx);
8633 drm_gem_object_unreference(&dev_priv->renderctx->base);
8634 dev_priv->renderctx = NULL;
8635 }
8636
8637 if (dev_priv->pwrctx) {
8638 i915_gem_object_unpin(dev_priv->pwrctx);
8639 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8640 dev_priv->pwrctx = NULL;
8641 }
8642 }
8643
8644 static void ironlake_disable_rc6(struct drm_device *dev)
8645 {
8646 struct drm_i915_private *dev_priv = dev->dev_private;
8647
8648 if (I915_READ(PWRCTXA)) {
8649 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8650 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8651 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8652 50);
8653
8654 I915_WRITE(PWRCTXA, 0);
8655 POSTING_READ(PWRCTXA);
8656
8657 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8658 POSTING_READ(RSTDBYCTL);
8659 }
8660
8661 ironlake_teardown_rc6(dev);
8662 }
8663
8664 static int ironlake_setup_rc6(struct drm_device *dev)
8665 {
8666 struct drm_i915_private *dev_priv = dev->dev_private;
8667
8668 if (dev_priv->renderctx == NULL)
8669 dev_priv->renderctx = intel_alloc_context_page(dev);
8670 if (!dev_priv->renderctx)
8671 return -ENOMEM;
8672
8673 if (dev_priv->pwrctx == NULL)
8674 dev_priv->pwrctx = intel_alloc_context_page(dev);
8675 if (!dev_priv->pwrctx) {
8676 ironlake_teardown_rc6(dev);
8677 return -ENOMEM;
8678 }
8679
8680 return 0;
8681 }
8682
8683 void ironlake_enable_rc6(struct drm_device *dev)
8684 {
8685 struct drm_i915_private *dev_priv = dev->dev_private;
8686 int ret;
8687
8688 /* rc6 disabled by default due to repeated reports of hanging during
8689 * boot and resume.
8690 */
8691 if (!intel_enable_rc6(dev))
8692 return;
8693
8694 mutex_lock(&dev->struct_mutex);
8695 ret = ironlake_setup_rc6(dev);
8696 if (ret) {
8697 mutex_unlock(&dev->struct_mutex);
8698 return;
8699 }
8700
8701 /*
8702 * GPU can automatically power down the render unit if given a page
8703 * to save state.
8704 */
8705 ret = BEGIN_LP_RING(6);
8706 if (ret) {
8707 ironlake_teardown_rc6(dev);
8708 mutex_unlock(&dev->struct_mutex);
8709 return;
8710 }
8711
8712 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8713 OUT_RING(MI_SET_CONTEXT);
8714 OUT_RING(dev_priv->renderctx->gtt_offset |
8715 MI_MM_SPACE_GTT |
8716 MI_SAVE_EXT_STATE_EN |
8717 MI_RESTORE_EXT_STATE_EN |
8718 MI_RESTORE_INHIBIT);
8719 OUT_RING(MI_SUSPEND_FLUSH);
8720 OUT_RING(MI_NOOP);
8721 OUT_RING(MI_FLUSH);
8722 ADVANCE_LP_RING();
8723
8724 /*
8725 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8726 * does an implicit flush, combined with MI_FLUSH above, it should be
8727 * safe to assume that renderctx is valid
8728 */
8729 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8730 if (ret) {
8731 DRM_ERROR("failed to enable ironlake power power savings\n");
8732 ironlake_teardown_rc6(dev);
8733 mutex_unlock(&dev->struct_mutex);
8734 return;
8735 }
8736
8737 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8738 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8739 mutex_unlock(&dev->struct_mutex);
8740 }
8741
8742 void intel_init_clock_gating(struct drm_device *dev)
8743 {
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745
8746 dev_priv->display.init_clock_gating(dev);
8747
8748 if (dev_priv->display.init_pch_clock_gating)
8749 dev_priv->display.init_pch_clock_gating(dev);
8750 }
8751
8752 /* Set up chip specific display functions */
8753 static void intel_init_display(struct drm_device *dev)
8754 {
8755 struct drm_i915_private *dev_priv = dev->dev_private;
8756
8757 /* We always want a DPMS function */
8758 if (HAS_PCH_SPLIT(dev)) {
8759 dev_priv->display.dpms = ironlake_crtc_dpms;
8760 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8761 dev_priv->display.update_plane = ironlake_update_plane;
8762 } else {
8763 dev_priv->display.dpms = i9xx_crtc_dpms;
8764 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8765 dev_priv->display.update_plane = i9xx_update_plane;
8766 }
8767
8768 if (I915_HAS_FBC(dev)) {
8769 if (HAS_PCH_SPLIT(dev)) {
8770 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8771 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8772 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8773 } else if (IS_GM45(dev)) {
8774 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8775 dev_priv->display.enable_fbc = g4x_enable_fbc;
8776 dev_priv->display.disable_fbc = g4x_disable_fbc;
8777 } else if (IS_CRESTLINE(dev)) {
8778 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8779 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8780 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8781 }
8782 /* 855GM needs testing */
8783 }
8784
8785 /* Returns the core display clock speed */
8786 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8787 dev_priv->display.get_display_clock_speed =
8788 i945_get_display_clock_speed;
8789 else if (IS_I915G(dev))
8790 dev_priv->display.get_display_clock_speed =
8791 i915_get_display_clock_speed;
8792 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8793 dev_priv->display.get_display_clock_speed =
8794 i9xx_misc_get_display_clock_speed;
8795 else if (IS_I915GM(dev))
8796 dev_priv->display.get_display_clock_speed =
8797 i915gm_get_display_clock_speed;
8798 else if (IS_I865G(dev))
8799 dev_priv->display.get_display_clock_speed =
8800 i865_get_display_clock_speed;
8801 else if (IS_I85X(dev))
8802 dev_priv->display.get_display_clock_speed =
8803 i855_get_display_clock_speed;
8804 else /* 852, 830 */
8805 dev_priv->display.get_display_clock_speed =
8806 i830_get_display_clock_speed;
8807
8808 /* For FIFO watermark updates */
8809 if (HAS_PCH_SPLIT(dev)) {
8810 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8811 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8812
8813 /* IVB configs may use multi-threaded forcewake */
8814 if (IS_IVYBRIDGE(dev)) {
8815 u32 ecobus;
8816
8817 /* A small trick here - if the bios hasn't configured MT forcewake,
8818 * and if the device is in RC6, then force_wake_mt_get will not wake
8819 * the device and the ECOBUS read will return zero. Which will be
8820 * (correctly) interpreted by the test below as MT forcewake being
8821 * disabled.
8822 */
8823 mutex_lock(&dev->struct_mutex);
8824 __gen6_gt_force_wake_mt_get(dev_priv);
8825 ecobus = I915_READ_NOTRACE(ECOBUS);
8826 __gen6_gt_force_wake_mt_put(dev_priv);
8827 mutex_unlock(&dev->struct_mutex);
8828
8829 if (ecobus & FORCEWAKE_MT_ENABLE) {
8830 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8831 dev_priv->display.force_wake_get =
8832 __gen6_gt_force_wake_mt_get;
8833 dev_priv->display.force_wake_put =
8834 __gen6_gt_force_wake_mt_put;
8835 }
8836 }
8837
8838 if (HAS_PCH_IBX(dev))
8839 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8840 else if (HAS_PCH_CPT(dev))
8841 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8842
8843 if (IS_GEN5(dev)) {
8844 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8845 dev_priv->display.update_wm = ironlake_update_wm;
8846 else {
8847 DRM_DEBUG_KMS("Failed to get proper latency. "
8848 "Disable CxSR\n");
8849 dev_priv->display.update_wm = NULL;
8850 }
8851 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8852 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
8853 dev_priv->display.write_eld = ironlake_write_eld;
8854 } else if (IS_GEN6(dev)) {
8855 if (SNB_READ_WM0_LATENCY()) {
8856 dev_priv->display.update_wm = sandybridge_update_wm;
8857 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8858 } else {
8859 DRM_DEBUG_KMS("Failed to read display plane latency. "
8860 "Disable CxSR\n");
8861 dev_priv->display.update_wm = NULL;
8862 }
8863 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8864 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
8865 dev_priv->display.write_eld = ironlake_write_eld;
8866 } else if (IS_IVYBRIDGE(dev)) {
8867 /* FIXME: detect B0+ stepping and use auto training */
8868 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8869 if (SNB_READ_WM0_LATENCY()) {
8870 dev_priv->display.update_wm = sandybridge_update_wm;
8871 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
8872 } else {
8873 DRM_DEBUG_KMS("Failed to read display plane latency. "
8874 "Disable CxSR\n");
8875 dev_priv->display.update_wm = NULL;
8876 }
8877 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
8878 dev_priv->display.write_eld = ironlake_write_eld;
8879 } else
8880 dev_priv->display.update_wm = NULL;
8881 } else if (IS_PINEVIEW(dev)) {
8882 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
8883 dev_priv->is_ddr3,
8884 dev_priv->fsb_freq,
8885 dev_priv->mem_freq)) {
8886 DRM_INFO("failed to find known CxSR latency "
8887 "(found ddr%s fsb freq %d, mem freq %d), "
8888 "disabling CxSR\n",
8889 (dev_priv->is_ddr3 == 1) ? "3" : "2",
8890 dev_priv->fsb_freq, dev_priv->mem_freq);
8891 /* Disable CxSR and never update its watermark again */
8892 pineview_disable_cxsr(dev);
8893 dev_priv->display.update_wm = NULL;
8894 } else
8895 dev_priv->display.update_wm = pineview_update_wm;
8896 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8897 } else if (IS_G4X(dev)) {
8898 dev_priv->display.write_eld = g4x_write_eld;
8899 dev_priv->display.update_wm = g4x_update_wm;
8900 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8901 } else if (IS_GEN4(dev)) {
8902 dev_priv->display.update_wm = i965_update_wm;
8903 if (IS_CRESTLINE(dev))
8904 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8905 else if (IS_BROADWATER(dev))
8906 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8907 } else if (IS_GEN3(dev)) {
8908 dev_priv->display.update_wm = i9xx_update_wm;
8909 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
8910 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8911 } else if (IS_I865G(dev)) {
8912 dev_priv->display.update_wm = i830_update_wm;
8913 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8914 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8915 } else if (IS_I85X(dev)) {
8916 dev_priv->display.update_wm = i9xx_update_wm;
8917 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
8918 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8919 } else {
8920 dev_priv->display.update_wm = i830_update_wm;
8921 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8922 if (IS_845G(dev))
8923 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8924 else
8925 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8926 }
8927
8928 /* Default just returns -ENODEV to indicate unsupported */
8929 dev_priv->display.queue_flip = intel_default_queue_flip;
8930
8931 switch (INTEL_INFO(dev)->gen) {
8932 case 2:
8933 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8934 break;
8935
8936 case 3:
8937 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8938 break;
8939
8940 case 4:
8941 case 5:
8942 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8943 break;
8944
8945 case 6:
8946 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8947 break;
8948 case 7:
8949 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8950 break;
8951 }
8952 }
8953
8954 /*
8955 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8956 * resume, or other times. This quirk makes sure that's the case for
8957 * affected systems.
8958 */
8959 static void quirk_pipea_force(struct drm_device *dev)
8960 {
8961 struct drm_i915_private *dev_priv = dev->dev_private;
8962
8963 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8964 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8965 }
8966
8967 /*
8968 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8969 */
8970 static void quirk_ssc_force_disable(struct drm_device *dev)
8971 {
8972 struct drm_i915_private *dev_priv = dev->dev_private;
8973 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8974 }
8975
8976 struct intel_quirk {
8977 int device;
8978 int subsystem_vendor;
8979 int subsystem_device;
8980 void (*hook)(struct drm_device *dev);
8981 };
8982
8983 struct intel_quirk intel_quirks[] = {
8984 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8985 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8986 /* HP Mini needs pipe A force quirk (LP: #322104) */
8987 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8988
8989 /* Thinkpad R31 needs pipe A force quirk */
8990 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8991 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8992 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8993
8994 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8995 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8996 /* ThinkPad X40 needs pipe A force quirk */
8997
8998 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8999 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9000
9001 /* 855 & before need to leave pipe A & dpll A up */
9002 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9003 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9004
9005 /* Lenovo U160 cannot use SSC on LVDS */
9006 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9007
9008 /* Sony Vaio Y cannot use SSC on LVDS */
9009 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9010 };
9011
9012 static void intel_init_quirks(struct drm_device *dev)
9013 {
9014 struct pci_dev *d = dev->pdev;
9015 int i;
9016
9017 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9018 struct intel_quirk *q = &intel_quirks[i];
9019
9020 if (d->device == q->device &&
9021 (d->subsystem_vendor == q->subsystem_vendor ||
9022 q->subsystem_vendor == PCI_ANY_ID) &&
9023 (d->subsystem_device == q->subsystem_device ||
9024 q->subsystem_device == PCI_ANY_ID))
9025 q->hook(dev);
9026 }
9027 }
9028
9029 /* Disable the VGA plane that we never use */
9030 static void i915_disable_vga(struct drm_device *dev)
9031 {
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033 u8 sr1;
9034 u32 vga_reg;
9035
9036 if (HAS_PCH_SPLIT(dev))
9037 vga_reg = CPU_VGACNTRL;
9038 else
9039 vga_reg = VGACNTRL;
9040
9041 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9042 outb(1, VGA_SR_INDEX);
9043 sr1 = inb(VGA_SR_DATA);
9044 outb(sr1 | 1<<5, VGA_SR_DATA);
9045 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9046 udelay(300);
9047
9048 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9049 POSTING_READ(vga_reg);
9050 }
9051
9052 void intel_modeset_init(struct drm_device *dev)
9053 {
9054 struct drm_i915_private *dev_priv = dev->dev_private;
9055 int i, ret;
9056
9057 drm_mode_config_init(dev);
9058
9059 dev->mode_config.min_width = 0;
9060 dev->mode_config.min_height = 0;
9061
9062 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9063
9064 intel_init_quirks(dev);
9065
9066 intel_init_display(dev);
9067
9068 if (IS_GEN2(dev)) {
9069 dev->mode_config.max_width = 2048;
9070 dev->mode_config.max_height = 2048;
9071 } else if (IS_GEN3(dev)) {
9072 dev->mode_config.max_width = 4096;
9073 dev->mode_config.max_height = 4096;
9074 } else {
9075 dev->mode_config.max_width = 8192;
9076 dev->mode_config.max_height = 8192;
9077 }
9078 dev->mode_config.fb_base = dev->agp->base;
9079
9080 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9081 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
9082
9083 for (i = 0; i < dev_priv->num_pipe; i++) {
9084 intel_crtc_init(dev, i);
9085 if (HAS_PCH_SPLIT(dev)) {
9086 ret = intel_plane_init(dev, i);
9087 if (ret)
9088 DRM_ERROR("plane %d init failed: %d\n",
9089 i, ret);
9090 }
9091 }
9092
9093 /* Just disable it once at startup */
9094 i915_disable_vga(dev);
9095 intel_setup_outputs(dev);
9096
9097 intel_init_clock_gating(dev);
9098
9099 if (IS_IRONLAKE_M(dev)) {
9100 ironlake_enable_drps(dev);
9101 intel_init_emon(dev);
9102 }
9103
9104 if (IS_GEN6(dev) || IS_GEN7(dev)) {
9105 gen6_enable_rps(dev_priv);
9106 gen6_update_ring_freq(dev_priv);
9107 }
9108
9109 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9110 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9111 (unsigned long)dev);
9112 }
9113
9114 void intel_modeset_gem_init(struct drm_device *dev)
9115 {
9116 if (IS_IRONLAKE_M(dev))
9117 ironlake_enable_rc6(dev);
9118
9119 intel_setup_overlay(dev);
9120 }
9121
9122 void intel_modeset_cleanup(struct drm_device *dev)
9123 {
9124 struct drm_i915_private *dev_priv = dev->dev_private;
9125 struct drm_crtc *crtc;
9126 struct intel_crtc *intel_crtc;
9127
9128 drm_kms_helper_poll_fini(dev);
9129 mutex_lock(&dev->struct_mutex);
9130
9131 intel_unregister_dsm_handler();
9132
9133
9134 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9135 /* Skip inactive CRTCs */
9136 if (!crtc->fb)
9137 continue;
9138
9139 intel_crtc = to_intel_crtc(crtc);
9140 intel_increase_pllclock(crtc);
9141 }
9142
9143 intel_disable_fbc(dev);
9144
9145 if (IS_IRONLAKE_M(dev))
9146 ironlake_disable_drps(dev);
9147 if (IS_GEN6(dev) || IS_GEN7(dev))
9148 gen6_disable_rps(dev);
9149
9150 if (IS_IRONLAKE_M(dev))
9151 ironlake_disable_rc6(dev);
9152
9153 mutex_unlock(&dev->struct_mutex);
9154
9155 /* Disable the irq before mode object teardown, for the irq might
9156 * enqueue unpin/hotplug work. */
9157 drm_irq_uninstall(dev);
9158 cancel_work_sync(&dev_priv->hotplug_work);
9159 cancel_work_sync(&dev_priv->rps_work);
9160
9161 /* flush any delayed tasks or pending work */
9162 flush_scheduled_work();
9163
9164 /* Shut off idle work before the crtcs get freed. */
9165 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9166 intel_crtc = to_intel_crtc(crtc);
9167 del_timer_sync(&intel_crtc->idle_timer);
9168 }
9169 del_timer_sync(&dev_priv->idle_timer);
9170 cancel_work_sync(&dev_priv->idle_work);
9171
9172 drm_mode_config_cleanup(dev);
9173 }
9174
9175 /*
9176 * Return which encoder is currently attached for connector.
9177 */
9178 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9179 {
9180 return &intel_attached_encoder(connector)->base;
9181 }
9182
9183 void intel_connector_attach_encoder(struct intel_connector *connector,
9184 struct intel_encoder *encoder)
9185 {
9186 connector->encoder = encoder;
9187 drm_mode_connector_attach_encoder(&connector->base,
9188 &encoder->base);
9189 }
9190
9191 /*
9192 * set vga decode state - true == enable VGA decode
9193 */
9194 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9195 {
9196 struct drm_i915_private *dev_priv = dev->dev_private;
9197 u16 gmch_ctrl;
9198
9199 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9200 if (state)
9201 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9202 else
9203 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9204 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9205 return 0;
9206 }
9207
9208 #ifdef CONFIG_DEBUG_FS
9209 #include <linux/seq_file.h>
9210
9211 struct intel_display_error_state {
9212 struct intel_cursor_error_state {
9213 u32 control;
9214 u32 position;
9215 u32 base;
9216 u32 size;
9217 } cursor[2];
9218
9219 struct intel_pipe_error_state {
9220 u32 conf;
9221 u32 source;
9222
9223 u32 htotal;
9224 u32 hblank;
9225 u32 hsync;
9226 u32 vtotal;
9227 u32 vblank;
9228 u32 vsync;
9229 } pipe[2];
9230
9231 struct intel_plane_error_state {
9232 u32 control;
9233 u32 stride;
9234 u32 size;
9235 u32 pos;
9236 u32 addr;
9237 u32 surface;
9238 u32 tile_offset;
9239 } plane[2];
9240 };
9241
9242 struct intel_display_error_state *
9243 intel_display_capture_error_state(struct drm_device *dev)
9244 {
9245 drm_i915_private_t *dev_priv = dev->dev_private;
9246 struct intel_display_error_state *error;
9247 int i;
9248
9249 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9250 if (error == NULL)
9251 return NULL;
9252
9253 for (i = 0; i < 2; i++) {
9254 error->cursor[i].control = I915_READ(CURCNTR(i));
9255 error->cursor[i].position = I915_READ(CURPOS(i));
9256 error->cursor[i].base = I915_READ(CURBASE(i));
9257
9258 error->plane[i].control = I915_READ(DSPCNTR(i));
9259 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9260 error->plane[i].size = I915_READ(DSPSIZE(i));
9261 error->plane[i].pos = I915_READ(DSPPOS(i));
9262 error->plane[i].addr = I915_READ(DSPADDR(i));
9263 if (INTEL_INFO(dev)->gen >= 4) {
9264 error->plane[i].surface = I915_READ(DSPSURF(i));
9265 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9266 }
9267
9268 error->pipe[i].conf = I915_READ(PIPECONF(i));
9269 error->pipe[i].source = I915_READ(PIPESRC(i));
9270 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9271 error->pipe[i].hblank = I915_READ(HBLANK(i));
9272 error->pipe[i].hsync = I915_READ(HSYNC(i));
9273 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9274 error->pipe[i].vblank = I915_READ(VBLANK(i));
9275 error->pipe[i].vsync = I915_READ(VSYNC(i));
9276 }
9277
9278 return error;
9279 }
9280
9281 void
9282 intel_display_print_error_state(struct seq_file *m,
9283 struct drm_device *dev,
9284 struct intel_display_error_state *error)
9285 {
9286 int i;
9287
9288 for (i = 0; i < 2; i++) {
9289 seq_printf(m, "Pipe [%d]:\n", i);
9290 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9291 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9292 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9293 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9294 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9295 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9296 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9297 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9298
9299 seq_printf(m, "Plane [%d]:\n", i);
9300 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9301 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9302 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9303 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9304 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9305 if (INTEL_INFO(dev)->gen >= 4) {
9306 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9307 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9308 }
9309
9310 seq_printf(m, "Cursor [%d]:\n", i);
9311 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9312 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9313 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9314 }
9315 }
9316 #endif
Linux 2.6 libata-dev (mirror)