RDMA/cxgb3: Remove Open Grid Computing copyrights in iw_cxgb3 driver
[linux-2.6/libata-dev.git] / drivers / ata / pata_atiixp.c
blobc3eb40c91c80435c0fefda38c4159cd7eebec136
1 /*
2 * pata_atiixp.c - ATI PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
6 * Based on
8 * linux/drivers/ide/pci/atiixp.c Version 0.01-bart2 Feb. 26, 2004
10 * Copyright (C) 2003 ATI Inc. <hyu@ati.com>
11 * Copyright (C) 2004 Bartlomiej Zolnierkiewicz
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 #include <linux/init.h>
19 #include <linux/blkdev.h>
20 #include <linux/delay.h>
21 #include <scsi/scsi_host.h>
22 #include <linux/libata.h>
24 #define DRV_NAME "pata_atiixp"
25 #define DRV_VERSION "0.4.4"
27 enum {
28 ATIIXP_IDE_PIO_TIMING = 0x40,
29 ATIIXP_IDE_MWDMA_TIMING = 0x44,
30 ATIIXP_IDE_PIO_CONTROL = 0x48,
31 ATIIXP_IDE_PIO_MODE = 0x4a,
32 ATIIXP_IDE_UDMA_CONTROL = 0x54,
33 ATIIXP_IDE_UDMA_MODE = 0x56
36 static int atiixp_pre_reset(struct ata_port *ap)
38 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
39 static const struct pci_bits atiixp_enable_bits[] = {
40 { 0x48, 1, 0x01, 0x00 },
41 { 0x48, 1, 0x08, 0x00 }
43 u8 udma;
45 if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
46 return -ENOENT;
48 /* Hack from drivers/ide/pci. Really we want to know how to do the
49 raw detection not play follow the bios mode guess */
50 pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma);
51 if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40)
52 ap->cbl = ATA_CBL_PATA80;
53 else
54 ap->cbl = ATA_CBL_PATA40;
55 return ata_std_prereset(ap);
58 static void atiixp_error_handler(struct ata_port *ap)
60 ata_bmdma_drive_eh(ap, atiixp_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
63 /**
64 * atiixp_set_pio_timing - set initial PIO mode data
65 * @ap: ATA interface
66 * @adev: ATA device
68 * Called by both the pio and dma setup functions to set the controller
69 * timings for PIO transfers. We must load both the mode number and
70 * timing values into the controller.
73 static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
75 static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
77 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
78 int dn = 2 * ap->port_no + adev->devno;
80 /* Check this is correct - the order is odd in both drivers */
81 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
82 u16 pio_mode_data, pio_timing_data;
84 pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
85 pio_mode_data &= ~(0x7 << (4 * dn));
86 pio_mode_data |= pio << (4 * dn);
87 pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
89 pci_read_config_word(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
90 pio_mode_data &= ~(0xFF << timing_shift);
91 pio_mode_data |= (pio_timings[pio] << timing_shift);
92 pci_write_config_word(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
95 /**
96 * atiixp_set_piomode - set initial PIO mode data
97 * @ap: ATA interface
98 * @adev: ATA device
100 * Called to do the PIO mode setup. We use a shared helper for this
101 * as the DMA setup must also adjust the PIO timing information.
104 static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
106 atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
110 * atiixp_set_dmamode - set initial DMA mode data
111 * @ap: ATA interface
112 * @adev: ATA device
114 * Called to do the DMA mode setup. We use timing tables for most
115 * modes but must tune an appropriate PIO mode to match.
118 static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
120 static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
122 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
123 int dma = adev->dma_mode;
124 int dn = 2 * ap->port_no + adev->devno;
125 int wanted_pio;
127 if (adev->dma_mode >= XFER_UDMA_0) {
128 u16 udma_mode_data;
130 dma -= XFER_UDMA_0;
132 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
133 udma_mode_data &= ~(0x7 << (4 * dn));
134 udma_mode_data |= dma << (4 * dn);
135 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
136 } else {
137 u16 mwdma_timing_data;
138 /* Check this is correct - the order is odd in both drivers */
139 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
141 dma -= XFER_MW_DMA_0;
143 pci_read_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, &mwdma_timing_data);
144 mwdma_timing_data &= ~(0xFF << timing_shift);
145 mwdma_timing_data |= (mwdma_timings[dma] << timing_shift);
146 pci_write_config_word(pdev, ATIIXP_IDE_MWDMA_TIMING, mwdma_timing_data);
149 * We must now look at the PIO mode situation. We may need to
150 * adjust the PIO mode to keep the timings acceptable
152 if (adev->dma_mode >= XFER_MW_DMA_2)
153 wanted_pio = 4;
154 else if (adev->dma_mode == XFER_MW_DMA_1)
155 wanted_pio = 3;
156 else if (adev->dma_mode == XFER_MW_DMA_0)
157 wanted_pio = 0;
158 else BUG();
160 if (adev->pio_mode != wanted_pio)
161 atiixp_set_pio_timing(ap, adev, wanted_pio);
165 * atiixp_bmdma_start - DMA start callback
166 * @qc: Command in progress
168 * When DMA begins we need to ensure that the UDMA control
169 * register for the channel is correctly set.
172 static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
174 struct ata_port *ap = qc->ap;
175 struct ata_device *adev = qc->dev;
177 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
178 int dn = (2 * ap->port_no) + adev->devno;
179 u16 tmp16;
181 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
182 if (adev->dma_mode >= XFER_UDMA_0)
183 tmp16 |= (1 << dn);
184 else
185 tmp16 &= ~(1 << dn);
186 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
187 ata_bmdma_start(qc);
191 * atiixp_dma_stop - DMA stop callback
192 * @qc: Command in progress
194 * DMA has completed. Clear the UDMA flag as the next operations will
195 * be PIO ones not UDMA data transfer.
198 static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
200 struct ata_port *ap = qc->ap;
201 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
202 int dn = (2 * ap->port_no) + qc->dev->devno;
203 u16 tmp16;
205 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
206 tmp16 &= ~(1 << dn);
207 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
208 ata_bmdma_stop(qc);
211 static struct scsi_host_template atiixp_sht = {
212 .module = THIS_MODULE,
213 .name = DRV_NAME,
214 .ioctl = ata_scsi_ioctl,
215 .queuecommand = ata_scsi_queuecmd,
216 .can_queue = ATA_DEF_QUEUE,
217 .this_id = ATA_SHT_THIS_ID,
218 .sg_tablesize = LIBATA_MAX_PRD,
219 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
220 .emulated = ATA_SHT_EMULATED,
221 .use_clustering = ATA_SHT_USE_CLUSTERING,
222 .proc_name = DRV_NAME,
223 .dma_boundary = ATA_DMA_BOUNDARY,
224 .slave_configure = ata_scsi_slave_config,
225 .slave_destroy = ata_scsi_slave_destroy,
226 .bios_param = ata_std_bios_param,
227 .resume = ata_scsi_device_resume,
228 .suspend = ata_scsi_device_suspend,
231 static struct ata_port_operations atiixp_port_ops = {
232 .port_disable = ata_port_disable,
233 .set_piomode = atiixp_set_piomode,
234 .set_dmamode = atiixp_set_dmamode,
235 .mode_filter = ata_pci_default_filter,
236 .tf_load = ata_tf_load,
237 .tf_read = ata_tf_read,
238 .check_status = ata_check_status,
239 .exec_command = ata_exec_command,
240 .dev_select = ata_std_dev_select,
242 .freeze = ata_bmdma_freeze,
243 .thaw = ata_bmdma_thaw,
244 .error_handler = atiixp_error_handler,
245 .post_internal_cmd = ata_bmdma_post_internal_cmd,
247 .bmdma_setup = ata_bmdma_setup,
248 .bmdma_start = atiixp_bmdma_start,
249 .bmdma_stop = atiixp_bmdma_stop,
250 .bmdma_status = ata_bmdma_status,
252 .qc_prep = ata_qc_prep,
253 .qc_issue = ata_qc_issue_prot,
255 .data_xfer = ata_data_xfer,
257 .irq_handler = ata_interrupt,
258 .irq_clear = ata_bmdma_irq_clear,
259 .irq_on = ata_irq_on,
260 .irq_ack = ata_irq_ack,
262 .port_start = ata_port_start,
265 static int atiixp_init_one(struct pci_dev *dev, const struct pci_device_id *id)
267 static struct ata_port_info info = {
268 .sht = &atiixp_sht,
269 .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
270 .pio_mask = 0x1f,
271 .mwdma_mask = 0x06, /* No MWDMA0 support */
272 .udma_mask = 0x3F,
273 .port_ops = &atiixp_port_ops
275 static struct ata_port_info *port_info[2] = { &info, &info };
276 return ata_pci_init_one(dev, port_info, 2);
279 static const struct pci_device_id atiixp[] = {
280 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
281 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
282 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
283 { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
285 { },
288 static struct pci_driver atiixp_pci_driver = {
289 .name = DRV_NAME,
290 .id_table = atiixp,
291 .probe = atiixp_init_one,
292 .remove = ata_pci_remove_one,
293 .resume = ata_pci_device_resume,
294 .suspend = ata_pci_device_suspend,
297 static int __init atiixp_init(void)
299 return pci_register_driver(&atiixp_pci_driver);
303 static void __exit atiixp_exit(void)
305 pci_unregister_driver(&atiixp_pci_driver);
308 MODULE_AUTHOR("Alan Cox");
309 MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
310 MODULE_LICENSE("GPL");
311 MODULE_DEVICE_TABLE(pci, atiixp);
312 MODULE_VERSION(DRV_VERSION);
314 module_init(atiixp_init);
315 module_exit(atiixp_exit);