2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the seperate driver.
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
37 #include <asm/sizes.h>
40 #ifdef CONFIG_ARCH_MX2
41 #include <mach/dma-mx1-mx2.h>
45 #define DRIVER_NAME "mxc-mmc"
47 #define MMC_REG_STR_STP_CLK 0x00
48 #define MMC_REG_STATUS 0x04
49 #define MMC_REG_CLK_RATE 0x08
50 #define MMC_REG_CMD_DAT_CONT 0x0C
51 #define MMC_REG_RES_TO 0x10
52 #define MMC_REG_READ_TO 0x14
53 #define MMC_REG_BLK_LEN 0x18
54 #define MMC_REG_NOB 0x1C
55 #define MMC_REG_REV_NO 0x20
56 #define MMC_REG_INT_CNTR 0x24
57 #define MMC_REG_CMD 0x28
58 #define MMC_REG_ARG 0x2C
59 #define MMC_REG_RES_FIFO 0x34
60 #define MMC_REG_BUFFER_ACCESS 0x38
62 #define STR_STP_CLK_RESET (1 << 3)
63 #define STR_STP_CLK_START_CLK (1 << 1)
64 #define STR_STP_CLK_STOP_CLK (1 << 0)
66 #define STATUS_CARD_INSERTION (1 << 31)
67 #define STATUS_CARD_REMOVAL (1 << 30)
68 #define STATUS_YBUF_EMPTY (1 << 29)
69 #define STATUS_XBUF_EMPTY (1 << 28)
70 #define STATUS_YBUF_FULL (1 << 27)
71 #define STATUS_XBUF_FULL (1 << 26)
72 #define STATUS_BUF_UND_RUN (1 << 25)
73 #define STATUS_BUF_OVFL (1 << 24)
74 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
75 #define STATUS_END_CMD_RESP (1 << 13)
76 #define STATUS_WRITE_OP_DONE (1 << 12)
77 #define STATUS_DATA_TRANS_DONE (1 << 11)
78 #define STATUS_READ_OP_DONE (1 << 11)
79 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
80 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
81 #define STATUS_BUF_READ_RDY (1 << 7)
82 #define STATUS_BUF_WRITE_RDY (1 << 6)
83 #define STATUS_RESP_CRC_ERR (1 << 5)
84 #define STATUS_CRC_READ_ERR (1 << 3)
85 #define STATUS_CRC_WRITE_ERR (1 << 2)
86 #define STATUS_TIME_OUT_RESP (1 << 1)
87 #define STATUS_TIME_OUT_READ (1 << 0)
88 #define STATUS_ERR_MASK 0x2f
90 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
91 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
92 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
93 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
94 #define CMD_DAT_CONT_INIT (1 << 7)
95 #define CMD_DAT_CONT_WRITE (1 << 4)
96 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
97 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
98 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
99 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
101 #define INT_SDIO_INT_WKP_EN (1 << 18)
102 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
103 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
104 #define INT_CARD_INSERTION_EN (1 << 15)
105 #define INT_CARD_REMOVAL_EN (1 << 14)
106 #define INT_SDIO_IRQ_EN (1 << 13)
107 #define INT_DAT0_EN (1 << 12)
108 #define INT_BUF_READ_EN (1 << 4)
109 #define INT_BUF_WRITE_EN (1 << 3)
110 #define INT_END_CMD_RES_EN (1 << 2)
111 #define INT_WRITE_OP_DONE_EN (1 << 1)
112 #define INT_READ_OP_EN (1 << 0)
115 struct mmc_host
*mmc
;
116 struct resource
*res
;
122 unsigned int power_mode
;
123 struct imxmmc_platform_data
*pdata
;
125 struct mmc_request
*req
;
126 struct mmc_command
*cmd
;
127 struct mmc_data
*data
;
129 unsigned int dma_nents
;
130 unsigned int datasize
;
131 unsigned int dma_dir
;
140 struct work_struct datawork
;
143 static inline int mxcmci_use_dma(struct mxcmci_host
*host
)
148 static void mxcmci_softreset(struct mxcmci_host
*host
)
153 writew(STR_STP_CLK_RESET
, host
->base
+ MMC_REG_STR_STP_CLK
);
154 writew(STR_STP_CLK_RESET
| STR_STP_CLK_START_CLK
,
155 host
->base
+ MMC_REG_STR_STP_CLK
);
157 for (i
= 0; i
< 8; i
++)
158 writew(STR_STP_CLK_START_CLK
, host
->base
+ MMC_REG_STR_STP_CLK
);
160 writew(0xff, host
->base
+ MMC_REG_RES_TO
);
163 static void mxcmci_setup_data(struct mxcmci_host
*host
, struct mmc_data
*data
)
165 unsigned int nob
= data
->blocks
;
166 unsigned int blksz
= data
->blksz
;
167 unsigned int datasize
= nob
* blksz
;
169 struct scatterlist
*sg
;
172 if (data
->flags
& MMC_DATA_STREAM
)
176 data
->bytes_xfered
= 0;
178 writew(nob
, host
->base
+ MMC_REG_NOB
);
179 writew(blksz
, host
->base
+ MMC_REG_BLK_LEN
);
180 host
->datasize
= datasize
;
183 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
184 if (sg
->offset
& 3 || sg
->length
& 3) {
190 if (data
->flags
& MMC_DATA_READ
) {
191 host
->dma_dir
= DMA_FROM_DEVICE
;
192 host
->dma_nents
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
193 data
->sg_len
, host
->dma_dir
);
195 imx_dma_setup_sg(host
->dma
, data
->sg
, host
->dma_nents
, datasize
,
196 host
->res
->start
+ MMC_REG_BUFFER_ACCESS
,
199 host
->dma_dir
= DMA_TO_DEVICE
;
200 host
->dma_nents
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
201 data
->sg_len
, host
->dma_dir
);
203 imx_dma_setup_sg(host
->dma
, data
->sg
, host
->dma_nents
, datasize
,
204 host
->res
->start
+ MMC_REG_BUFFER_ACCESS
,
210 imx_dma_enable(host
->dma
);
214 static int mxcmci_start_cmd(struct mxcmci_host
*host
, struct mmc_command
*cmd
,
217 WARN_ON(host
->cmd
!= NULL
);
220 switch (mmc_resp_type(cmd
)) {
221 case MMC_RSP_R1
: /* short CRC, OPCODE */
222 case MMC_RSP_R1B
:/* short CRC, OPCODE, BUSY */
223 cmdat
|= CMD_DAT_CONT_RESPONSE_48BIT_CRC
;
225 case MMC_RSP_R2
: /* long 136 bit + CRC */
226 cmdat
|= CMD_DAT_CONT_RESPONSE_136BIT
;
228 case MMC_RSP_R3
: /* short */
229 cmdat
|= CMD_DAT_CONT_RESPONSE_48BIT
;
234 dev_err(mmc_dev(host
->mmc
), "unhandled response type 0x%x\n",
236 cmd
->error
= -EINVAL
;
240 if (mxcmci_use_dma(host
))
241 writel(INT_READ_OP_EN
| INT_WRITE_OP_DONE_EN
|
243 host
->base
+ MMC_REG_INT_CNTR
);
245 writel(INT_END_CMD_RES_EN
, host
->base
+ MMC_REG_INT_CNTR
);
247 writew(cmd
->opcode
, host
->base
+ MMC_REG_CMD
);
248 writel(cmd
->arg
, host
->base
+ MMC_REG_ARG
);
249 writew(cmdat
, host
->base
+ MMC_REG_CMD_DAT_CONT
);
254 static void mxcmci_finish_request(struct mxcmci_host
*host
,
255 struct mmc_request
*req
)
257 writel(0, host
->base
+ MMC_REG_INT_CNTR
);
263 mmc_request_done(host
->mmc
, req
);
266 static int mxcmci_finish_data(struct mxcmci_host
*host
, unsigned int stat
)
268 struct mmc_data
*data
= host
->data
;
272 if (mxcmci_use_dma(host
)) {
273 imx_dma_disable(host
->dma
);
274 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, host
->dma_nents
,
279 if (stat
& STATUS_ERR_MASK
) {
280 dev_dbg(mmc_dev(host
->mmc
), "request failed. status: 0x%08x\n",
282 if (stat
& STATUS_CRC_READ_ERR
) {
283 data
->error
= -EILSEQ
;
284 } else if (stat
& STATUS_CRC_WRITE_ERR
) {
285 u32 err_code
= (stat
>> 9) & 0x3;
286 if (err_code
== 2) /* No CRC response */
287 data
->error
= -ETIMEDOUT
;
289 data
->error
= -EILSEQ
;
290 } else if (stat
& STATUS_TIME_OUT_READ
) {
291 data
->error
= -ETIMEDOUT
;
296 data
->bytes_xfered
= host
->datasize
;
299 data_error
= data
->error
;
306 static void mxcmci_read_response(struct mxcmci_host
*host
, unsigned int stat
)
308 struct mmc_command
*cmd
= host
->cmd
;
315 if (stat
& STATUS_TIME_OUT_RESP
) {
316 dev_dbg(mmc_dev(host
->mmc
), "CMD TIMEOUT\n");
317 cmd
->error
= -ETIMEDOUT
;
318 } else if (stat
& STATUS_RESP_CRC_ERR
&& cmd
->flags
& MMC_RSP_CRC
) {
319 dev_dbg(mmc_dev(host
->mmc
), "cmd crc error\n");
320 cmd
->error
= -EILSEQ
;
323 if (cmd
->flags
& MMC_RSP_PRESENT
) {
324 if (cmd
->flags
& MMC_RSP_136
) {
325 for (i
= 0; i
< 4; i
++) {
326 a
= readw(host
->base
+ MMC_REG_RES_FIFO
);
327 b
= readw(host
->base
+ MMC_REG_RES_FIFO
);
328 cmd
->resp
[i
] = a
<< 16 | b
;
331 a
= readw(host
->base
+ MMC_REG_RES_FIFO
);
332 b
= readw(host
->base
+ MMC_REG_RES_FIFO
);
333 c
= readw(host
->base
+ MMC_REG_RES_FIFO
);
334 cmd
->resp
[0] = a
<< 24 | b
<< 8 | c
>> 8;
339 static int mxcmci_poll_status(struct mxcmci_host
*host
, u32 mask
)
342 unsigned long timeout
= jiffies
+ HZ
;
345 stat
= readl(host
->base
+ MMC_REG_STATUS
);
346 if (stat
& STATUS_ERR_MASK
)
348 if (time_after(jiffies
, timeout
))
349 return STATUS_TIME_OUT_READ
;
356 static int mxcmci_pull(struct mxcmci_host
*host
, void *_buf
, int bytes
)
362 stat
= mxcmci_poll_status(host
,
363 STATUS_BUF_READ_RDY
| STATUS_READ_OP_DONE
);
366 *buf
++ = readl(host
->base
+ MMC_REG_BUFFER_ACCESS
);
374 stat
= mxcmci_poll_status(host
,
375 STATUS_BUF_READ_RDY
| STATUS_READ_OP_DONE
);
378 tmp
= readl(host
->base
+ MMC_REG_BUFFER_ACCESS
);
379 memcpy(b
, &tmp
, bytes
);
385 static int mxcmci_push(struct mxcmci_host
*host
, void *_buf
, int bytes
)
391 stat
= mxcmci_poll_status(host
, STATUS_BUF_WRITE_RDY
);
394 writel(*buf
++, host
->base
+ MMC_REG_BUFFER_ACCESS
);
402 stat
= mxcmci_poll_status(host
, STATUS_BUF_WRITE_RDY
);
406 memcpy(&tmp
, b
, bytes
);
407 writel(tmp
, host
->base
+ MMC_REG_BUFFER_ACCESS
);
410 stat
= mxcmci_poll_status(host
, STATUS_BUF_WRITE_RDY
);
417 static int mxcmci_transfer_data(struct mxcmci_host
*host
)
419 struct mmc_data
*data
= host
->req
->data
;
420 struct scatterlist
*sg
;
428 if (data
->flags
& MMC_DATA_READ
) {
429 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
430 stat
= mxcmci_pull(host
, sg_virt(sg
), sg
->length
);
433 host
->datasize
+= sg
->length
;
436 for_each_sg(data
->sg
, sg
, data
->sg_len
, i
) {
437 stat
= mxcmci_push(host
, sg_virt(sg
), sg
->length
);
440 host
->datasize
+= sg
->length
;
442 stat
= mxcmci_poll_status(host
, STATUS_WRITE_OP_DONE
);
449 static void mxcmci_datawork(struct work_struct
*work
)
451 struct mxcmci_host
*host
= container_of(work
, struct mxcmci_host
,
453 int datastat
= mxcmci_transfer_data(host
);
454 mxcmci_finish_data(host
, datastat
);
456 if (host
->req
->stop
) {
457 if (mxcmci_start_cmd(host
, host
->req
->stop
, 0)) {
458 mxcmci_finish_request(host
, host
->req
);
462 mxcmci_finish_request(host
, host
->req
);
467 static void mxcmci_data_done(struct mxcmci_host
*host
, unsigned int stat
)
469 struct mmc_data
*data
= host
->data
;
475 data_error
= mxcmci_finish_data(host
, stat
);
477 mxcmci_read_response(host
, stat
);
480 if (host
->req
->stop
) {
481 if (mxcmci_start_cmd(host
, host
->req
->stop
, 0)) {
482 mxcmci_finish_request(host
, host
->req
);
486 mxcmci_finish_request(host
, host
->req
);
491 static void mxcmci_cmd_done(struct mxcmci_host
*host
, unsigned int stat
)
493 mxcmci_read_response(host
, stat
);
496 if (!host
->data
&& host
->req
) {
497 mxcmci_finish_request(host
, host
->req
);
501 /* For the DMA case the DMA engine handles the data transfer
502 * automatically. For non DMA we have to to it ourselves.
503 * Don't do it in interrupt context though.
505 if (!mxcmci_use_dma(host
) && host
->data
)
506 schedule_work(&host
->datawork
);
510 static irqreturn_t
mxcmci_irq(int irq
, void *devid
)
512 struct mxcmci_host
*host
= devid
;
515 stat
= readl(host
->base
+ MMC_REG_STATUS
);
516 writel(stat
, host
->base
+ MMC_REG_STATUS
);
518 dev_dbg(mmc_dev(host
->mmc
), "%s: 0x%08x\n", __func__
, stat
);
520 if (stat
& STATUS_END_CMD_RESP
)
521 mxcmci_cmd_done(host
, stat
);
523 if (mxcmci_use_dma(host
) &&
524 (stat
& (STATUS_DATA_TRANS_DONE
| STATUS_WRITE_OP_DONE
)))
525 mxcmci_data_done(host
, stat
);
530 static void mxcmci_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
532 struct mxcmci_host
*host
= mmc_priv(mmc
);
533 unsigned int cmdat
= host
->cmdat
;
535 WARN_ON(host
->req
!= NULL
);
538 host
->cmdat
&= ~CMD_DAT_CONT_INIT
;
543 mxcmci_setup_data(host
, req
->data
);
545 cmdat
|= CMD_DAT_CONT_DATA_ENABLE
;
547 if (req
->data
->flags
& MMC_DATA_WRITE
)
548 cmdat
|= CMD_DAT_CONT_WRITE
;
551 if (mxcmci_start_cmd(host
, req
->cmd
, cmdat
))
552 mxcmci_finish_request(host
, req
);
555 static void mxcmci_set_clk_rate(struct mxcmci_host
*host
, unsigned int clk_ios
)
557 unsigned int divider
;
559 unsigned int clk_in
= clk_get_rate(host
->clk
);
561 while (prescaler
<= 0x800) {
562 for (divider
= 1; divider
<= 0xF; divider
++) {
565 x
= (clk_in
/ (divider
+ 1));
568 x
/= (prescaler
* 2);
582 writew((prescaler
<< 4) | divider
, host
->base
+ MMC_REG_CLK_RATE
);
584 dev_dbg(mmc_dev(host
->mmc
), "scaler: %d divider: %d in: %d out: %d\n",
585 prescaler
, divider
, clk_in
, clk_ios
);
588 static void mxcmci_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
590 struct mxcmci_host
*host
= mmc_priv(mmc
);
594 * use burstlen of 64 in 4 bit mode (--> reg value 0)
595 * use burstlen of 16 in 1 bit mode (--> reg value 16)
597 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
602 imx_dma_config_burstlen(host
->dma
, blen
);
604 if (ios
->bus_width
== MMC_BUS_WIDTH_4
)
605 host
->cmdat
|= CMD_DAT_CONT_BUS_WIDTH_4
;
607 host
->cmdat
&= ~CMD_DAT_CONT_BUS_WIDTH_4
;
609 if (host
->power_mode
!= ios
->power_mode
) {
610 if (host
->pdata
&& host
->pdata
->setpower
)
611 host
->pdata
->setpower(mmc_dev(mmc
), ios
->vdd
);
612 host
->power_mode
= ios
->power_mode
;
613 if (ios
->power_mode
== MMC_POWER_ON
)
614 host
->cmdat
|= CMD_DAT_CONT_INIT
;
618 mxcmci_set_clk_rate(host
, ios
->clock
);
619 writew(STR_STP_CLK_START_CLK
, host
->base
+ MMC_REG_STR_STP_CLK
);
621 writew(STR_STP_CLK_STOP_CLK
, host
->base
+ MMC_REG_STR_STP_CLK
);
624 host
->clock
= ios
->clock
;
627 static irqreturn_t
mxcmci_detect_irq(int irq
, void *data
)
629 struct mmc_host
*mmc
= data
;
631 dev_dbg(mmc_dev(mmc
), "%s\n", __func__
);
633 mmc_detect_change(mmc
, msecs_to_jiffies(250));
637 static int mxcmci_get_ro(struct mmc_host
*mmc
)
639 struct mxcmci_host
*host
= mmc_priv(mmc
);
641 if (host
->pdata
&& host
->pdata
->get_ro
)
642 return !!host
->pdata
->get_ro(mmc_dev(mmc
));
644 * Board doesn't support read only detection; let the mmc core
651 static const struct mmc_host_ops mxcmci_ops
= {
652 .request
= mxcmci_request
,
653 .set_ios
= mxcmci_set_ios
,
654 .get_ro
= mxcmci_get_ro
,
657 static int mxcmci_probe(struct platform_device
*pdev
)
659 struct mmc_host
*mmc
;
660 struct mxcmci_host
*host
= NULL
;
664 printk(KERN_INFO
"i.MX SDHC driver\n");
666 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
667 irq
= platform_get_irq(pdev
, 0);
671 r
= request_mem_region(r
->start
, resource_size(r
), pdev
->name
);
675 mmc
= mmc_alloc_host(sizeof(struct mxcmci_host
), &pdev
->dev
);
678 goto out_release_mem
;
681 mmc
->ops
= &mxcmci_ops
;
682 mmc
->caps
= MMC_CAP_4_BIT_DATA
;
684 /* MMC core transfer sizes tunable parameters */
685 mmc
->max_hw_segs
= 64;
686 mmc
->max_phys_segs
= 64;
687 mmc
->max_blk_size
= 2048;
688 mmc
->max_blk_count
= 65535;
689 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
690 mmc
->max_seg_size
= mmc
->max_seg_size
;
692 host
= mmc_priv(mmc
);
693 host
->base
= ioremap(r
->start
, resource_size(r
));
700 host
->pdata
= pdev
->dev
.platform_data
;
702 if (host
->pdata
&& host
->pdata
->ocr_avail
)
703 mmc
->ocr_avail
= host
->pdata
->ocr_avail
;
705 mmc
->ocr_avail
= MMC_VDD_32_33
| MMC_VDD_33_34
;
710 host
->clk
= clk_get(&pdev
->dev
, NULL
);
711 if (IS_ERR(host
->clk
)) {
712 ret
= PTR_ERR(host
->clk
);
715 clk_enable(host
->clk
);
717 mxcmci_softreset(host
);
719 host
->rev_no
= readw(host
->base
+ MMC_REG_REV_NO
);
720 if (host
->rev_no
!= 0x400) {
722 dev_err(mmc_dev(host
->mmc
), "wrong rev.no. 0x%08x. aborting.\n",
727 mmc
->f_min
= clk_get_rate(host
->clk
) >> 16;
728 if (mmc
->f_min
< 400000)
730 mmc
->f_max
= clk_get_rate(host
->clk
) >> 1;
732 /* recommended in data sheet */
733 writew(0x2db4, host
->base
+ MMC_REG_READ_TO
);
735 writel(0, host
->base
+ MMC_REG_INT_CNTR
);
738 host
->dma
= imx_dma_request_by_prio(DRIVER_NAME
, DMA_PRIO_LOW
);
740 dev_err(mmc_dev(host
->mmc
), "imx_dma_request_by_prio failed\n");
745 r
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
751 ret
= imx_dma_config_channel(host
->dma
,
752 IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_FIFO
,
753 IMX_DMA_MEMSIZE_32
| IMX_DMA_TYPE_LINEAR
,
756 dev_err(mmc_dev(host
->mmc
), "failed to config DMA channel\n");
760 INIT_WORK(&host
->datawork
, mxcmci_datawork
);
762 ret
= request_irq(host
->irq
, mxcmci_irq
, 0, DRIVER_NAME
, host
);
766 platform_set_drvdata(pdev
, mmc
);
768 if (host
->pdata
&& host
->pdata
->init
) {
769 ret
= host
->pdata
->init(&pdev
->dev
, mxcmci_detect_irq
,
780 free_irq(host
->irq
, host
);
783 imx_dma_free(host
->dma
);
786 clk_disable(host
->clk
);
793 release_mem_region(host
->res
->start
, resource_size(host
->res
));
797 static int mxcmci_remove(struct platform_device
*pdev
)
799 struct mmc_host
*mmc
= platform_get_drvdata(pdev
);
800 struct mxcmci_host
*host
= mmc_priv(mmc
);
802 platform_set_drvdata(pdev
, NULL
);
804 mmc_remove_host(mmc
);
806 if (host
->pdata
&& host
->pdata
->exit
)
807 host
->pdata
->exit(&pdev
->dev
, mmc
);
809 free_irq(host
->irq
, host
);
812 imx_dma_free(host
->dma
);
814 clk_disable(host
->clk
);
817 release_mem_region(host
->res
->start
, resource_size(host
->res
));
818 release_resource(host
->res
);
826 static int mxcmci_suspend(struct platform_device
*dev
, pm_message_t state
)
828 struct mmc_host
*mmc
= platform_get_drvdata(dev
);
832 ret
= mmc_suspend_host(mmc
, state
);
837 static int mxcmci_resume(struct platform_device
*dev
)
839 struct mmc_host
*mmc
= platform_get_drvdata(dev
);
840 struct mxcmci_host
*host
;
844 host
= mmc_priv(mmc
);
845 ret
= mmc_resume_host(mmc
);
851 #define mxcmci_suspend NULL
852 #define mxcmci_resume NULL
853 #endif /* CONFIG_PM */
855 static struct platform_driver mxcmci_driver
= {
856 .probe
= mxcmci_probe
,
857 .remove
= mxcmci_remove
,
858 .suspend
= mxcmci_suspend
,
859 .resume
= mxcmci_resume
,
862 .owner
= THIS_MODULE
,
866 static int __init
mxcmci_init(void)
868 return platform_driver_register(&mxcmci_driver
);
871 static void __exit
mxcmci_exit(void)
873 platform_driver_unregister(&mxcmci_driver
);
876 module_init(mxcmci_init
);
877 module_exit(mxcmci_exit
);
879 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
880 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
881 MODULE_LICENSE("GPL");
882 MODULE_ALIAS("platform:imx-mmc");