1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 #include <linux/pci.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
33 #include "ixgbe_common.h"
34 #include "ixgbe_phy.h"
36 static bool ixgbe_validate_phy_addr(struct ixgbe_hw
*hw
, u32 phy_addr
);
37 static enum ixgbe_phy_type
ixgbe_get_phy_type_from_id(u32 phy_id
);
38 static s32
ixgbe_get_phy_id(struct ixgbe_hw
*hw
);
41 * ixgbe_identify_phy_generic - Get physical layer module
42 * @hw: pointer to hardware structure
44 * Determines the physical layer module found on the current adapter.
46 s32
ixgbe_identify_phy_generic(struct ixgbe_hw
*hw
)
48 s32 status
= IXGBE_ERR_PHY_ADDR_INVALID
;
51 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
52 for (phy_addr
= 0; phy_addr
< IXGBE_MAX_PHY_ADDR
; phy_addr
++) {
53 if (ixgbe_validate_phy_addr(hw
, phy_addr
)) {
54 hw
->phy
.addr
= phy_addr
;
57 ixgbe_get_phy_type_from_id(hw
->phy
.id
);
70 * ixgbe_validate_phy_addr - Determines phy address is valid
71 * @hw: pointer to hardware structure
74 static bool ixgbe_validate_phy_addr(struct ixgbe_hw
*hw
, u32 phy_addr
)
79 hw
->phy
.addr
= phy_addr
;
80 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_ID_HIGH
,
81 IXGBE_MDIO_PMA_PMD_DEV_TYPE
, &phy_id
);
83 if (phy_id
!= 0xFFFF && phy_id
!= 0x0)
90 * ixgbe_get_phy_id - Get the phy type
91 * @hw: pointer to hardware structure
94 static s32
ixgbe_get_phy_id(struct ixgbe_hw
*hw
)
100 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_ID_HIGH
,
101 IXGBE_MDIO_PMA_PMD_DEV_TYPE
,
105 hw
->phy
.id
= (u32
)(phy_id_high
<< 16);
106 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_PHY_ID_LOW
,
107 IXGBE_MDIO_PMA_PMD_DEV_TYPE
,
109 hw
->phy
.id
|= (u32
)(phy_id_low
& IXGBE_PHY_REVISION_MASK
);
110 hw
->phy
.revision
= (u32
)(phy_id_low
& ~IXGBE_PHY_REVISION_MASK
);
116 * ixgbe_get_phy_type_from_id - Get the phy type
117 * @hw: pointer to hardware structure
120 static enum ixgbe_phy_type
ixgbe_get_phy_type_from_id(u32 phy_id
)
122 enum ixgbe_phy_type phy_type
;
126 phy_type
= ixgbe_phy_qt
;
129 phy_type
= ixgbe_phy_unknown
;
137 * ixgbe_reset_phy_generic - Performs a PHY reset
138 * @hw: pointer to hardware structure
140 s32
ixgbe_reset_phy_generic(struct ixgbe_hw
*hw
)
143 * Perform soft PHY reset to the PHY_XS.
144 * This will cause a soft reset to the PHY
146 return hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_PHY_XS_CONTROL
,
147 IXGBE_MDIO_PHY_XS_DEV_TYPE
,
148 IXGBE_MDIO_PHY_XS_RESET
);
152 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
153 * @hw: pointer to hardware structure
154 * @reg_addr: 32 bit address of PHY register to read
155 * @phy_data: Pointer to read data from PHY register
157 s32
ixgbe_read_phy_reg_generic(struct ixgbe_hw
*hw
, u32 reg_addr
,
158 u32 device_type
, u16
*phy_data
)
166 if (IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
)
167 gssr
= IXGBE_GSSR_PHY1_SM
;
169 gssr
= IXGBE_GSSR_PHY0_SM
;
171 if (ixgbe_acquire_swfw_sync(hw
, gssr
) != 0)
172 status
= IXGBE_ERR_SWFW_SYNC
;
175 /* Setup and write the address cycle command */
176 command
= ((reg_addr
<< IXGBE_MSCA_NP_ADDR_SHIFT
) |
177 (device_type
<< IXGBE_MSCA_DEV_TYPE_SHIFT
) |
178 (hw
->phy
.addr
<< IXGBE_MSCA_PHY_ADDR_SHIFT
) |
179 (IXGBE_MSCA_ADDR_CYCLE
| IXGBE_MSCA_MDI_COMMAND
));
181 IXGBE_WRITE_REG(hw
, IXGBE_MSCA
, command
);
184 * Check every 10 usec to see if the address cycle completed.
185 * The MDI Command bit will clear when the operation is
188 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
191 command
= IXGBE_READ_REG(hw
, IXGBE_MSCA
);
193 if ((command
& IXGBE_MSCA_MDI_COMMAND
) == 0)
197 if ((command
& IXGBE_MSCA_MDI_COMMAND
) != 0) {
198 hw_dbg(hw
, "PHY address command did not complete.\n");
199 status
= IXGBE_ERR_PHY
;
204 * Address cycle complete, setup and write the read
207 command
= ((reg_addr
<< IXGBE_MSCA_NP_ADDR_SHIFT
) |
208 (device_type
<< IXGBE_MSCA_DEV_TYPE_SHIFT
) |
209 (hw
->phy
.addr
<< IXGBE_MSCA_PHY_ADDR_SHIFT
) |
210 (IXGBE_MSCA_READ
| IXGBE_MSCA_MDI_COMMAND
));
212 IXGBE_WRITE_REG(hw
, IXGBE_MSCA
, command
);
215 * Check every 10 usec to see if the address cycle
216 * completed. The MDI Command bit will clear when the
217 * operation is complete
219 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
222 command
= IXGBE_READ_REG(hw
, IXGBE_MSCA
);
224 if ((command
& IXGBE_MSCA_MDI_COMMAND
) == 0)
228 if ((command
& IXGBE_MSCA_MDI_COMMAND
) != 0) {
229 hw_dbg(hw
, "PHY read command didn't complete\n");
230 status
= IXGBE_ERR_PHY
;
233 * Read operation is complete. Get the data
236 data
= IXGBE_READ_REG(hw
, IXGBE_MSRWD
);
237 data
>>= IXGBE_MSRWD_READ_DATA_SHIFT
;
238 *phy_data
= (u16
)(data
);
242 ixgbe_release_swfw_sync(hw
, gssr
);
249 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
250 * @hw: pointer to hardware structure
251 * @reg_addr: 32 bit PHY register to write
252 * @device_type: 5 bit device type
253 * @phy_data: Data to write to the PHY register
255 s32
ixgbe_write_phy_reg_generic(struct ixgbe_hw
*hw
, u32 reg_addr
,
256 u32 device_type
, u16 phy_data
)
263 if (IXGBE_READ_REG(hw
, IXGBE_STATUS
) & IXGBE_STATUS_LAN_ID_1
)
264 gssr
= IXGBE_GSSR_PHY1_SM
;
266 gssr
= IXGBE_GSSR_PHY0_SM
;
268 if (ixgbe_acquire_swfw_sync(hw
, gssr
) != 0)
269 status
= IXGBE_ERR_SWFW_SYNC
;
272 /* Put the data in the MDI single read and write data register*/
273 IXGBE_WRITE_REG(hw
, IXGBE_MSRWD
, (u32
)phy_data
);
275 /* Setup and write the address cycle command */
276 command
= ((reg_addr
<< IXGBE_MSCA_NP_ADDR_SHIFT
) |
277 (device_type
<< IXGBE_MSCA_DEV_TYPE_SHIFT
) |
278 (hw
->phy
.addr
<< IXGBE_MSCA_PHY_ADDR_SHIFT
) |
279 (IXGBE_MSCA_ADDR_CYCLE
| IXGBE_MSCA_MDI_COMMAND
));
281 IXGBE_WRITE_REG(hw
, IXGBE_MSCA
, command
);
284 * Check every 10 usec to see if the address cycle completed.
285 * The MDI Command bit will clear when the operation is
288 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
291 command
= IXGBE_READ_REG(hw
, IXGBE_MSCA
);
293 if ((command
& IXGBE_MSCA_MDI_COMMAND
) == 0)
297 if ((command
& IXGBE_MSCA_MDI_COMMAND
) != 0) {
298 hw_dbg(hw
, "PHY address cmd didn't complete\n");
299 status
= IXGBE_ERR_PHY
;
304 * Address cycle complete, setup and write the write
307 command
= ((reg_addr
<< IXGBE_MSCA_NP_ADDR_SHIFT
) |
308 (device_type
<< IXGBE_MSCA_DEV_TYPE_SHIFT
) |
309 (hw
->phy
.addr
<< IXGBE_MSCA_PHY_ADDR_SHIFT
) |
310 (IXGBE_MSCA_WRITE
| IXGBE_MSCA_MDI_COMMAND
));
312 IXGBE_WRITE_REG(hw
, IXGBE_MSCA
, command
);
315 * Check every 10 usec to see if the address cycle
316 * completed. The MDI Command bit will clear when the
317 * operation is complete
319 for (i
= 0; i
< IXGBE_MDIO_COMMAND_TIMEOUT
; i
++) {
322 command
= IXGBE_READ_REG(hw
, IXGBE_MSCA
);
324 if ((command
& IXGBE_MSCA_MDI_COMMAND
) == 0)
328 if ((command
& IXGBE_MSCA_MDI_COMMAND
) != 0) {
329 hw_dbg(hw
, "PHY address cmd didn't complete\n");
330 status
= IXGBE_ERR_PHY
;
334 ixgbe_release_swfw_sync(hw
, gssr
);
341 * ixgbe_setup_phy_link_generic - Set and restart autoneg
342 * @hw: pointer to hardware structure
344 * Restart autonegotiation and PHY and waits for completion.
346 s32
ixgbe_setup_phy_link_generic(struct ixgbe_hw
*hw
)
348 s32 status
= IXGBE_NOT_IMPLEMENTED
;
350 u32 max_time_out
= 10;
351 u16 autoneg_reg
= IXGBE_MII_AUTONEG_REG
;
354 * Set advertisement settings in PHY based on autoneg_advertised
355 * settings. If autoneg_advertised = 0, then advertise default values
356 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
359 hw
->phy
.ops
.read_reg(hw
, IXGBE_MII_SPEED_SELECTION_REG
,
360 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, &autoneg_reg
);
362 if (hw
->phy
.autoneg_advertised
== IXGBE_LINK_SPEED_1GB_FULL
)
363 autoneg_reg
&= 0xEFFF; /* 0 in bit 12 is 1G operation */
365 autoneg_reg
|= 0x1000; /* 1 in bit 12 is 10G/1G operation */
367 hw
->phy
.ops
.write_reg(hw
, IXGBE_MII_SPEED_SELECTION_REG
,
368 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, autoneg_reg
);
370 /* Restart PHY autonegotiation and wait for completion */
371 hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_CONTROL
,
372 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, &autoneg_reg
);
374 autoneg_reg
|= IXGBE_MII_RESTART
;
376 hw
->phy
.ops
.write_reg(hw
, IXGBE_MDIO_AUTO_NEG_CONTROL
,
377 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
, autoneg_reg
);
379 /* Wait for autonegotiation to finish */
380 for (time_out
= 0; time_out
< max_time_out
; time_out
++) {
382 /* Restart PHY autonegotiation and wait for completion */
383 status
= hw
->phy
.ops
.read_reg(hw
, IXGBE_MDIO_AUTO_NEG_STATUS
,
384 IXGBE_MDIO_AUTO_NEG_DEV_TYPE
,
387 autoneg_reg
&= IXGBE_MII_AUTONEG_COMPLETE
;
388 if (autoneg_reg
== IXGBE_MII_AUTONEG_COMPLETE
) {
394 if (time_out
== max_time_out
)
395 status
= IXGBE_ERR_LINK_SETUP
;
401 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
402 * @hw: pointer to hardware structure
403 * @speed: new link speed
404 * @autoneg: true if autonegotiation enabled
406 s32
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw
*hw
,
407 ixgbe_link_speed speed
,
409 bool autoneg_wait_to_complete
)
413 * Clear autoneg_advertised and set new values based on input link
416 hw
->phy
.autoneg_advertised
= 0;
418 if (speed
& IXGBE_LINK_SPEED_10GB_FULL
)
419 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_10GB_FULL
;
421 if (speed
& IXGBE_LINK_SPEED_1GB_FULL
)
422 hw
->phy
.autoneg_advertised
|= IXGBE_LINK_SPEED_1GB_FULL
;
424 /* Setup link based on the new speed settings */
425 hw
->phy
.ops
.setup_link(hw
);