2 * drivers/spi/amba-pl022.c
4 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
6 * Copyright (C) 2008-2009 ST-Ericsson AB
7 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
11 * Initial version inspired by:
12 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
13 * Initial adoption to PL022 by:
14 * Sachin Verma <sachin.verma@st.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
29 * - add timeout on polled transfers
32 #include <linux/init.h>
33 #include <linux/module.h>
34 #include <linux/device.h>
35 #include <linux/ioport.h>
36 #include <linux/errno.h>
37 #include <linux/interrupt.h>
38 #include <linux/spi/spi.h>
39 #include <linux/workqueue.h>
40 #include <linux/delay.h>
41 #include <linux/clk.h>
42 #include <linux/err.h>
43 #include <linux/amba/bus.h>
44 #include <linux/amba/pl022.h>
46 #include <linux/slab.h>
47 #include <linux/dmaengine.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/scatterlist.h>
52 * This macro is used to define some register default values.
53 * reg is masked with mask, the OR:ed with an (again masked)
54 * val shifted sb steps to the left.
56 #define SSP_WRITE_BITS(reg, val, mask, sb) \
57 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
60 * This macro is also used to define some default values.
61 * It will just shift val by sb steps to the left and mask
62 * the result with mask.
64 #define GEN_MASK_BITS(val, mask, sb) \
65 (((val)<<(sb)) & (mask))
68 #define DO_NOT_DRIVE_TX 1
70 #define DO_NOT_QUEUE_DMA 0
77 * Macros to access SSP Registers with their offsets
79 #define SSP_CR0(r) (r + 0x000)
80 #define SSP_CR1(r) (r + 0x004)
81 #define SSP_DR(r) (r + 0x008)
82 #define SSP_SR(r) (r + 0x00C)
83 #define SSP_CPSR(r) (r + 0x010)
84 #define SSP_IMSC(r) (r + 0x014)
85 #define SSP_RIS(r) (r + 0x018)
86 #define SSP_MIS(r) (r + 0x01C)
87 #define SSP_ICR(r) (r + 0x020)
88 #define SSP_DMACR(r) (r + 0x024)
89 #define SSP_ITCR(r) (r + 0x080)
90 #define SSP_ITIP(r) (r + 0x084)
91 #define SSP_ITOP(r) (r + 0x088)
92 #define SSP_TDR(r) (r + 0x08C)
94 #define SSP_PID0(r) (r + 0xFE0)
95 #define SSP_PID1(r) (r + 0xFE4)
96 #define SSP_PID2(r) (r + 0xFE8)
97 #define SSP_PID3(r) (r + 0xFEC)
99 #define SSP_CID0(r) (r + 0xFF0)
100 #define SSP_CID1(r) (r + 0xFF4)
101 #define SSP_CID2(r) (r + 0xFF8)
102 #define SSP_CID3(r) (r + 0xFFC)
105 * SSP Control Register 0 - SSP_CR0
107 #define SSP_CR0_MASK_DSS (0x0FUL << 0)
108 #define SSP_CR0_MASK_FRF (0x3UL << 4)
109 #define SSP_CR0_MASK_SPO (0x1UL << 6)
110 #define SSP_CR0_MASK_SPH (0x1UL << 7)
111 #define SSP_CR0_MASK_SCR (0xFFUL << 8)
114 * The ST version of this block moves som bits
115 * in SSP_CR0 and extends it to 32 bits
117 #define SSP_CR0_MASK_DSS_ST (0x1FUL << 0)
118 #define SSP_CR0_MASK_HALFDUP_ST (0x1UL << 5)
119 #define SSP_CR0_MASK_CSS_ST (0x1FUL << 16)
120 #define SSP_CR0_MASK_FRF_ST (0x3UL << 21)
124 * SSP Control Register 0 - SSP_CR1
126 #define SSP_CR1_MASK_LBM (0x1UL << 0)
127 #define SSP_CR1_MASK_SSE (0x1UL << 1)
128 #define SSP_CR1_MASK_MS (0x1UL << 2)
129 #define SSP_CR1_MASK_SOD (0x1UL << 3)
132 * The ST version of this block adds some bits
135 #define SSP_CR1_MASK_RENDN_ST (0x1UL << 4)
136 #define SSP_CR1_MASK_TENDN_ST (0x1UL << 5)
137 #define SSP_CR1_MASK_MWAIT_ST (0x1UL << 6)
138 #define SSP_CR1_MASK_RXIFLSEL_ST (0x7UL << 7)
139 #define SSP_CR1_MASK_TXIFLSEL_ST (0x7UL << 10)
140 /* This one is only in the PL023 variant */
141 #define SSP_CR1_MASK_FBCLKDEL_ST (0x7UL << 13)
144 * SSP Status Register - SSP_SR
146 #define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
147 #define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
148 #define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
149 #define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
150 #define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
153 * SSP Clock Prescale Register - SSP_CPSR
155 #define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
158 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
160 #define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
161 #define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
162 #define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
163 #define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
166 * SSP Raw Interrupt Status Register - SSP_RIS
168 /* Receive Overrun Raw Interrupt status */
169 #define SSP_RIS_MASK_RORRIS (0x1UL << 0)
170 /* Receive Timeout Raw Interrupt status */
171 #define SSP_RIS_MASK_RTRIS (0x1UL << 1)
172 /* Receive FIFO Raw Interrupt status */
173 #define SSP_RIS_MASK_RXRIS (0x1UL << 2)
174 /* Transmit FIFO Raw Interrupt status */
175 #define SSP_RIS_MASK_TXRIS (0x1UL << 3)
178 * SSP Masked Interrupt Status Register - SSP_MIS
180 /* Receive Overrun Masked Interrupt status */
181 #define SSP_MIS_MASK_RORMIS (0x1UL << 0)
182 /* Receive Timeout Masked Interrupt status */
183 #define SSP_MIS_MASK_RTMIS (0x1UL << 1)
184 /* Receive FIFO Masked Interrupt status */
185 #define SSP_MIS_MASK_RXMIS (0x1UL << 2)
186 /* Transmit FIFO Masked Interrupt status */
187 #define SSP_MIS_MASK_TXMIS (0x1UL << 3)
190 * SSP Interrupt Clear Register - SSP_ICR
192 /* Receive Overrun Raw Clear Interrupt bit */
193 #define SSP_ICR_MASK_RORIC (0x1UL << 0)
194 /* Receive Timeout Clear Interrupt bit */
195 #define SSP_ICR_MASK_RTIC (0x1UL << 1)
198 * SSP DMA Control Register - SSP_DMACR
200 /* Receive DMA Enable bit */
201 #define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
202 /* Transmit DMA Enable bit */
203 #define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
206 * SSP Integration Test control Register - SSP_ITCR
208 #define SSP_ITCR_MASK_ITEN (0x1UL << 0)
209 #define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
212 * SSP Integration Test Input Register - SSP_ITIP
214 #define ITIP_MASK_SSPRXD (0x1UL << 0)
215 #define ITIP_MASK_SSPFSSIN (0x1UL << 1)
216 #define ITIP_MASK_SSPCLKIN (0x1UL << 2)
217 #define ITIP_MASK_RXDMAC (0x1UL << 3)
218 #define ITIP_MASK_TXDMAC (0x1UL << 4)
219 #define ITIP_MASK_SSPTXDIN (0x1UL << 5)
222 * SSP Integration Test output Register - SSP_ITOP
224 #define ITOP_MASK_SSPTXD (0x1UL << 0)
225 #define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
226 #define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
227 #define ITOP_MASK_SSPOEn (0x1UL << 3)
228 #define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
229 #define ITOP_MASK_RORINTR (0x1UL << 5)
230 #define ITOP_MASK_RTINTR (0x1UL << 6)
231 #define ITOP_MASK_RXINTR (0x1UL << 7)
232 #define ITOP_MASK_TXINTR (0x1UL << 8)
233 #define ITOP_MASK_INTR (0x1UL << 9)
234 #define ITOP_MASK_RXDMABREQ (0x1UL << 10)
235 #define ITOP_MASK_RXDMASREQ (0x1UL << 11)
236 #define ITOP_MASK_TXDMABREQ (0x1UL << 12)
237 #define ITOP_MASK_TXDMASREQ (0x1UL << 13)
240 * SSP Test Data Register - SSP_TDR
242 #define TDR_MASK_TESTDATA (0xFFFFFFFF)
246 * we use the spi_message.state (void *) pointer to
247 * hold a single state value, that's why all this
248 * (void *) casting is done here.
250 #define STATE_START ((void *) 0)
251 #define STATE_RUNNING ((void *) 1)
252 #define STATE_DONE ((void *) 2)
253 #define STATE_ERROR ((void *) -1)
256 * SSP State - Whether Enabled or Disabled
258 #define SSP_DISABLED (0)
259 #define SSP_ENABLED (1)
262 * SSP DMA State - Whether DMA Enabled or Disabled
264 #define SSP_DMA_DISABLED (0)
265 #define SSP_DMA_ENABLED (1)
270 #define SSP_DEFAULT_CLKRATE 0x2
271 #define SSP_DEFAULT_PRESCALE 0x40
274 * SSP Clock Parameter ranges
276 #define CPSDVR_MIN 0x02
277 #define CPSDVR_MAX 0xFE
282 * SSP Interrupt related Macros
284 #define DEFAULT_SSP_REG_IMSC 0x0UL
285 #define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
286 #define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
288 #define CLEAR_ALL_INTERRUPTS 0x3
292 * The type of reading going on on this chip
302 * The type of writing going on on this chip
312 * struct vendor_data - vendor-specific config parameters
313 * for PL022 derivates
314 * @fifodepth: depth of FIFOs (both)
315 * @max_bpw: maximum number of bits per word
316 * @unidir: supports unidirection transfers
317 * @extended_cr: 32 bit wide control register 0 with extra
318 * features and extra features in CR1 as found in the ST variants
319 * @pl023: supports a subset of the ST extensions called "PL023"
330 * struct pl022 - This is the private SSP driver data structure
331 * @adev: AMBA device model hookup
332 * @vendor: vendor data for the IP block
333 * @phybase: the physical memory where the SSP device resides
334 * @virtbase: the virtual memory where the SSP is mapped
335 * @clk: outgoing clock "SPICLK" for the SPI bus
336 * @master: SPI framework hookup
337 * @master_info: controller-specific data from machine setup
338 * @workqueue: a workqueue on which any spi_message request is queued
339 * @pump_messages: work struct for scheduling work to the workqueue
340 * @queue_lock: spinlock to syncronise access to message queue
341 * @queue: message queue
342 * @busy: workqueue is busy
343 * @running: workqueue is running
344 * @pump_transfers: Tasklet used in Interrupt Transfer mode
345 * @cur_msg: Pointer to current spi_message being processed
346 * @cur_transfer: Pointer to current spi_transfer
347 * @cur_chip: pointer to current clients chip(assigned from controller_state)
348 * @tx: current position in TX buffer to be read
349 * @tx_end: end position in TX buffer to be read
350 * @rx: current position in RX buffer to be written
351 * @rx_end: end position in RX buffer to be written
352 * @read: the type of read currently going on
353 * @write: the type of write currently going on
354 * @exp_fifo_level: expected FIFO level
355 * @dma_rx_channel: optional channel for RX DMA
356 * @dma_tx_channel: optional channel for TX DMA
357 * @sgt_rx: scattertable for the RX transfer
358 * @sgt_tx: scattertable for the TX transfer
359 * @dummypage: a dummy page used for driving data on the bus with DMA
362 struct amba_device
*adev
;
363 struct vendor_data
*vendor
;
364 resource_size_t phybase
;
365 void __iomem
*virtbase
;
367 struct spi_master
*master
;
368 struct pl022_ssp_controller
*master_info
;
369 /* Driver message queue */
370 struct workqueue_struct
*workqueue
;
371 struct work_struct pump_messages
;
372 spinlock_t queue_lock
;
373 struct list_head queue
;
376 /* Message transfer pump */
377 struct tasklet_struct pump_transfers
;
378 struct spi_message
*cur_msg
;
379 struct spi_transfer
*cur_transfer
;
380 struct chip_data
*cur_chip
;
385 enum ssp_reading read
;
386 enum ssp_writing write
;
389 #ifdef CONFIG_DMA_ENGINE
390 struct dma_chan
*dma_rx_channel
;
391 struct dma_chan
*dma_tx_channel
;
392 struct sg_table sgt_rx
;
393 struct sg_table sgt_tx
;
399 * struct chip_data - To maintain runtime state of SSP for each client chip
400 * @cr0: Value of control register CR0 of SSP - on later ST variants this
401 * register is 32 bits wide rather than just 16
402 * @cr1: Value of control register CR1 of SSP
403 * @dmacr: Value of DMA control Register of SSP
404 * @cpsr: Value of Clock prescale register
405 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
406 * @enable_dma: Whether to enable DMA or not
407 * @read: function ptr to be used to read when doing xfer for this chip
408 * @write: function ptr to be used to write when doing xfer for this chip
409 * @cs_control: chip select callback provided by chip
410 * @xfer_type: polling/interrupt/DMA
412 * Runtime state of the SSP controller, maintained per chip,
413 * This would be set according to the current message that would be served
422 enum ssp_reading read
;
423 enum ssp_writing write
;
424 void (*cs_control
) (u32 command
);
429 * null_cs_control - Dummy chip select function
430 * @command: select/delect the chip
432 * If no chip select function is provided by client this is used as dummy
435 static void null_cs_control(u32 command
)
437 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command
);
441 * giveback - current spi_message is over, schedule next message and call
442 * callback of this message. Assumes that caller already
443 * set message->status; dma and pio irqs are blocked
444 * @pl022: SSP driver private data structure
446 static void giveback(struct pl022
*pl022
)
448 struct spi_transfer
*last_transfer
;
450 struct spi_message
*msg
;
451 void (*curr_cs_control
) (u32 command
);
454 * This local reference to the chip select function
455 * is needed because we set curr_chip to NULL
456 * as a step toward termininating the message.
458 curr_cs_control
= pl022
->cur_chip
->cs_control
;
459 spin_lock_irqsave(&pl022
->queue_lock
, flags
);
460 msg
= pl022
->cur_msg
;
461 pl022
->cur_msg
= NULL
;
462 pl022
->cur_transfer
= NULL
;
463 pl022
->cur_chip
= NULL
;
464 queue_work(pl022
->workqueue
, &pl022
->pump_messages
);
465 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
467 last_transfer
= list_entry(msg
->transfers
.prev
,
471 /* Delay if requested before any change in chip select */
472 if (last_transfer
->delay_usecs
)
474 * FIXME: This runs in interrupt context.
475 * Is this really smart?
477 udelay(last_transfer
->delay_usecs
);
480 * Drop chip select UNLESS cs_change is true or we are returning
481 * a message with an error, or next message is for another chip
483 if (!last_transfer
->cs_change
)
484 curr_cs_control(SSP_CHIP_DESELECT
);
486 struct spi_message
*next_msg
;
488 /* Holding of cs was hinted, but we need to make sure
489 * the next message is for the same chip. Don't waste
490 * time with the following tests unless this was hinted.
492 * We cannot postpone this until pump_messages, because
493 * after calling msg->complete (below) the driver that
494 * sent the current message could be unloaded, which
495 * could invalidate the cs_control() callback...
498 /* get a pointer to the next message, if any */
499 spin_lock_irqsave(&pl022
->queue_lock
, flags
);
500 if (list_empty(&pl022
->queue
))
503 next_msg
= list_entry(pl022
->queue
.next
,
504 struct spi_message
, queue
);
505 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
507 /* see if the next and current messages point
510 if (next_msg
&& next_msg
->spi
!= msg
->spi
)
512 if (!next_msg
|| msg
->state
== STATE_ERROR
)
513 curr_cs_control(SSP_CHIP_DESELECT
);
517 msg
->complete(msg
->context
);
518 /* This message is completed, so let's turn off the clocks & power */
519 clk_disable(pl022
->clk
);
520 amba_pclk_disable(pl022
->adev
);
521 amba_vcore_disable(pl022
->adev
);
525 * flush - flush the FIFO to reach a clean state
526 * @pl022: SSP driver private data structure
528 static int flush(struct pl022
*pl022
)
530 unsigned long limit
= loops_per_jiffy
<< 1;
532 dev_dbg(&pl022
->adev
->dev
, "flush\n");
534 while (readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_RNE
)
535 readw(SSP_DR(pl022
->virtbase
));
536 } while ((readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_BSY
) && limit
--);
538 pl022
->exp_fifo_level
= 0;
544 * restore_state - Load configuration of current chip
545 * @pl022: SSP driver private data structure
547 static void restore_state(struct pl022
*pl022
)
549 struct chip_data
*chip
= pl022
->cur_chip
;
551 if (pl022
->vendor
->extended_cr
)
552 writel(chip
->cr0
, SSP_CR0(pl022
->virtbase
));
554 writew(chip
->cr0
, SSP_CR0(pl022
->virtbase
));
555 writew(chip
->cr1
, SSP_CR1(pl022
->virtbase
));
556 writew(chip
->dmacr
, SSP_DMACR(pl022
->virtbase
));
557 writew(chip
->cpsr
, SSP_CPSR(pl022
->virtbase
));
558 writew(DISABLE_ALL_INTERRUPTS
, SSP_IMSC(pl022
->virtbase
));
559 writew(CLEAR_ALL_INTERRUPTS
, SSP_ICR(pl022
->virtbase
));
563 * Default SSP Register Values
565 #define DEFAULT_SSP_REG_CR0 ( \
566 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
567 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 4) | \
568 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
569 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
570 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
573 /* ST versions have slightly different bit layout */
574 #define DEFAULT_SSP_REG_CR0_ST ( \
575 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
576 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP_ST, 5) | \
577 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
578 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
579 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
580 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS_ST, 16) | \
581 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF_ST, 21) \
584 /* The PL023 version is slightly different again */
585 #define DEFAULT_SSP_REG_CR0_ST_PL023 ( \
586 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS_ST, 0) | \
587 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
588 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
589 GEN_MASK_BITS(SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) \
592 #define DEFAULT_SSP_REG_CR1 ( \
593 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
594 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
595 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
596 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) \
599 /* ST versions extend this register to use all 16 bits */
600 #define DEFAULT_SSP_REG_CR1_ST ( \
601 DEFAULT_SSP_REG_CR1 | \
602 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
603 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
604 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT_ST, 6) |\
605 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
606 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) \
610 * The PL023 variant has further differences: no loopback mode, no microwire
611 * support, and a new clock feedback delay setting.
613 #define DEFAULT_SSP_REG_CR1_ST_PL023 ( \
614 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
615 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
616 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
617 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN_ST, 4) | \
618 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN_ST, 5) | \
619 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL_ST, 7) | \
620 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL_ST, 10) | \
621 GEN_MASK_BITS(SSP_FEEDBACK_CLK_DELAY_NONE, SSP_CR1_MASK_FBCLKDEL_ST, 13) \
624 #define DEFAULT_SSP_REG_CPSR ( \
625 GEN_MASK_BITS(SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
628 #define DEFAULT_SSP_REG_DMACR (\
629 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
630 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
634 * load_ssp_default_config - Load default configuration for SSP
635 * @pl022: SSP driver private data structure
637 static void load_ssp_default_config(struct pl022
*pl022
)
639 if (pl022
->vendor
->pl023
) {
640 writel(DEFAULT_SSP_REG_CR0_ST_PL023
, SSP_CR0(pl022
->virtbase
));
641 writew(DEFAULT_SSP_REG_CR1_ST_PL023
, SSP_CR1(pl022
->virtbase
));
642 } else if (pl022
->vendor
->extended_cr
) {
643 writel(DEFAULT_SSP_REG_CR0_ST
, SSP_CR0(pl022
->virtbase
));
644 writew(DEFAULT_SSP_REG_CR1_ST
, SSP_CR1(pl022
->virtbase
));
646 writew(DEFAULT_SSP_REG_CR0
, SSP_CR0(pl022
->virtbase
));
647 writew(DEFAULT_SSP_REG_CR1
, SSP_CR1(pl022
->virtbase
));
649 writew(DEFAULT_SSP_REG_DMACR
, SSP_DMACR(pl022
->virtbase
));
650 writew(DEFAULT_SSP_REG_CPSR
, SSP_CPSR(pl022
->virtbase
));
651 writew(DISABLE_ALL_INTERRUPTS
, SSP_IMSC(pl022
->virtbase
));
652 writew(CLEAR_ALL_INTERRUPTS
, SSP_ICR(pl022
->virtbase
));
656 * This will write to TX and read from RX according to the parameters
659 static void readwriter(struct pl022
*pl022
)
663 * The FIFO depth is different inbetween primecell variants.
664 * I believe filling in too much in the FIFO might cause
665 * errons in 8bit wide transfers on ARM variants (just 8 words
666 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
668 * To prevent this issue, the TX FIFO is only filled to the
669 * unused RX FIFO fill length, regardless of what the TX
670 * FIFO status flag indicates.
672 dev_dbg(&pl022
->adev
->dev
,
673 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
674 __func__
, pl022
->rx
, pl022
->rx_end
, pl022
->tx
, pl022
->tx_end
);
676 /* Read as much as you can */
677 while ((readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_RNE
)
678 && (pl022
->rx
< pl022
->rx_end
)) {
679 switch (pl022
->read
) {
681 readw(SSP_DR(pl022
->virtbase
));
684 *(u8
*) (pl022
->rx
) =
685 readw(SSP_DR(pl022
->virtbase
)) & 0xFFU
;
688 *(u16
*) (pl022
->rx
) =
689 (u16
) readw(SSP_DR(pl022
->virtbase
));
692 *(u32
*) (pl022
->rx
) =
693 readl(SSP_DR(pl022
->virtbase
));
696 pl022
->rx
+= (pl022
->cur_chip
->n_bytes
);
697 pl022
->exp_fifo_level
--;
700 * Write as much as possible up to the RX FIFO size
702 while ((pl022
->exp_fifo_level
< pl022
->vendor
->fifodepth
)
703 && (pl022
->tx
< pl022
->tx_end
)) {
704 switch (pl022
->write
) {
706 writew(0x0, SSP_DR(pl022
->virtbase
));
709 writew(*(u8
*) (pl022
->tx
), SSP_DR(pl022
->virtbase
));
712 writew((*(u16
*) (pl022
->tx
)), SSP_DR(pl022
->virtbase
));
715 writel(*(u32
*) (pl022
->tx
), SSP_DR(pl022
->virtbase
));
718 pl022
->tx
+= (pl022
->cur_chip
->n_bytes
);
719 pl022
->exp_fifo_level
++;
721 * This inner reader takes care of things appearing in the RX
722 * FIFO as we're transmitting. This will happen a lot since the
723 * clock starts running when you put things into the TX FIFO,
724 * and then things are continously clocked into the RX FIFO.
726 while ((readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_RNE
)
727 && (pl022
->rx
< pl022
->rx_end
)) {
728 switch (pl022
->read
) {
730 readw(SSP_DR(pl022
->virtbase
));
733 *(u8
*) (pl022
->rx
) =
734 readw(SSP_DR(pl022
->virtbase
)) & 0xFFU
;
737 *(u16
*) (pl022
->rx
) =
738 (u16
) readw(SSP_DR(pl022
->virtbase
));
741 *(u32
*) (pl022
->rx
) =
742 readl(SSP_DR(pl022
->virtbase
));
745 pl022
->rx
+= (pl022
->cur_chip
->n_bytes
);
746 pl022
->exp_fifo_level
--;
750 * When we exit here the TX FIFO should be full and the RX FIFO
757 * next_transfer - Move to the Next transfer in the current spi message
758 * @pl022: SSP driver private data structure
760 * This function moves though the linked list of spi transfers in the
761 * current spi message and returns with the state of current spi
762 * message i.e whether its last transfer is done(STATE_DONE) or
763 * Next transfer is ready(STATE_RUNNING)
765 static void *next_transfer(struct pl022
*pl022
)
767 struct spi_message
*msg
= pl022
->cur_msg
;
768 struct spi_transfer
*trans
= pl022
->cur_transfer
;
770 /* Move to next transfer */
771 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
772 pl022
->cur_transfer
=
773 list_entry(trans
->transfer_list
.next
,
774 struct spi_transfer
, transfer_list
);
775 return STATE_RUNNING
;
781 * This DMA functionality is only compiled in if we have
782 * access to the generic DMA devices/DMA engine.
784 #ifdef CONFIG_DMA_ENGINE
785 static void unmap_free_dma_scatter(struct pl022
*pl022
)
787 /* Unmap and free the SG tables */
788 dma_unmap_sg(pl022
->dma_tx_channel
->device
->dev
, pl022
->sgt_tx
.sgl
,
789 pl022
->sgt_tx
.nents
, DMA_TO_DEVICE
);
790 dma_unmap_sg(pl022
->dma_rx_channel
->device
->dev
, pl022
->sgt_rx
.sgl
,
791 pl022
->sgt_rx
.nents
, DMA_FROM_DEVICE
);
792 sg_free_table(&pl022
->sgt_rx
);
793 sg_free_table(&pl022
->sgt_tx
);
796 static void dma_callback(void *data
)
798 struct pl022
*pl022
= data
;
799 struct spi_message
*msg
= pl022
->cur_msg
;
801 BUG_ON(!pl022
->sgt_rx
.sgl
);
805 * Optionally dump out buffers to inspect contents, this is
806 * good if you want to convince yourself that the loopback
807 * read/write contents are the same, when adopting to a new
811 struct scatterlist
*sg
;
814 dma_sync_sg_for_cpu(&pl022
->adev
->dev
,
819 for_each_sg(pl022
->sgt_rx
.sgl
, sg
, pl022
->sgt_rx
.nents
, i
) {
820 dev_dbg(&pl022
->adev
->dev
, "SPI RX SG ENTRY: %d", i
);
821 print_hex_dump(KERN_ERR
, "SPI RX: ",
829 for_each_sg(pl022
->sgt_tx
.sgl
, sg
, pl022
->sgt_tx
.nents
, i
) {
830 dev_dbg(&pl022
->adev
->dev
, "SPI TX SG ENTRY: %d", i
);
831 print_hex_dump(KERN_ERR
, "SPI TX: ",
842 unmap_free_dma_scatter(pl022
);
844 /* Update total bytes transfered */
845 msg
->actual_length
+= pl022
->cur_transfer
->len
;
846 if (pl022
->cur_transfer
->cs_change
)
848 cs_control(SSP_CHIP_DESELECT
);
850 /* Move to next transfer */
851 msg
->state
= next_transfer(pl022
);
852 tasklet_schedule(&pl022
->pump_transfers
);
855 static void setup_dma_scatter(struct pl022
*pl022
,
858 struct sg_table
*sgtab
)
860 struct scatterlist
*sg
;
861 int bytesleft
= length
;
867 for_each_sg(sgtab
->sgl
, sg
, sgtab
->nents
, i
) {
869 * If there are less bytes left than what fits
870 * in the current page (plus page alignment offset)
871 * we just feed in this, else we stuff in as much
874 if (bytesleft
< (PAGE_SIZE
- offset_in_page(bufp
)))
875 mapbytes
= bytesleft
;
877 mapbytes
= PAGE_SIZE
- offset_in_page(bufp
);
878 sg_set_page(sg
, virt_to_page(bufp
),
879 mapbytes
, offset_in_page(bufp
));
881 bytesleft
-= mapbytes
;
882 dev_dbg(&pl022
->adev
->dev
,
883 "set RX/TX target page @ %p, %d bytes, %d left\n",
884 bufp
, mapbytes
, bytesleft
);
887 /* Map the dummy buffer on every page */
888 for_each_sg(sgtab
->sgl
, sg
, sgtab
->nents
, i
) {
889 if (bytesleft
< PAGE_SIZE
)
890 mapbytes
= bytesleft
;
892 mapbytes
= PAGE_SIZE
;
893 sg_set_page(sg
, virt_to_page(pl022
->dummypage
),
895 bytesleft
-= mapbytes
;
896 dev_dbg(&pl022
->adev
->dev
,
897 "set RX/TX to dummy page %d bytes, %d left\n",
898 mapbytes
, bytesleft
);
906 * configure_dma - configures the channels for the next transfer
907 * @pl022: SSP driver's private data structure
909 static int configure_dma(struct pl022
*pl022
)
911 struct dma_slave_config rx_conf
= {
912 .src_addr
= SSP_DR(pl022
->phybase
),
913 .direction
= DMA_FROM_DEVICE
,
914 .src_maxburst
= pl022
->vendor
->fifodepth
>> 1,
916 struct dma_slave_config tx_conf
= {
917 .dst_addr
= SSP_DR(pl022
->phybase
),
918 .direction
= DMA_TO_DEVICE
,
919 .dst_maxburst
= pl022
->vendor
->fifodepth
>> 1,
923 int rx_sglen
, tx_sglen
;
924 struct dma_chan
*rxchan
= pl022
->dma_rx_channel
;
925 struct dma_chan
*txchan
= pl022
->dma_tx_channel
;
926 struct dma_async_tx_descriptor
*rxdesc
;
927 struct dma_async_tx_descriptor
*txdesc
;
929 /* Check that the channels are available */
930 if (!rxchan
|| !txchan
)
933 switch (pl022
->read
) {
935 /* Use the same as for writing */
936 rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_UNDEFINED
;
939 rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
942 rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
945 rx_conf
.src_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
949 switch (pl022
->write
) {
951 /* Use the same as for reading */
952 tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_UNDEFINED
;
955 tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_1_BYTE
;
958 tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_2_BYTES
;
961 tx_conf
.dst_addr_width
= DMA_SLAVE_BUSWIDTH_4_BYTES
;
965 /* SPI pecularity: we need to read and write the same width */
966 if (rx_conf
.src_addr_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
)
967 rx_conf
.src_addr_width
= tx_conf
.dst_addr_width
;
968 if (tx_conf
.dst_addr_width
== DMA_SLAVE_BUSWIDTH_UNDEFINED
)
969 tx_conf
.dst_addr_width
= rx_conf
.src_addr_width
;
970 BUG_ON(rx_conf
.src_addr_width
!= tx_conf
.dst_addr_width
);
972 dmaengine_slave_config(rxchan
, &rx_conf
);
973 dmaengine_slave_config(txchan
, &tx_conf
);
975 /* Create sglists for the transfers */
976 pages
= (pl022
->cur_transfer
->len
>> PAGE_SHIFT
) + 1;
977 dev_dbg(&pl022
->adev
->dev
, "using %d pages for transfer\n", pages
);
979 ret
= sg_alloc_table(&pl022
->sgt_rx
, pages
, GFP_KERNEL
);
981 goto err_alloc_rx_sg
;
983 ret
= sg_alloc_table(&pl022
->sgt_tx
, pages
, GFP_KERNEL
);
985 goto err_alloc_tx_sg
;
987 /* Fill in the scatterlists for the RX+TX buffers */
988 setup_dma_scatter(pl022
, pl022
->rx
,
989 pl022
->cur_transfer
->len
, &pl022
->sgt_rx
);
990 setup_dma_scatter(pl022
, pl022
->tx
,
991 pl022
->cur_transfer
->len
, &pl022
->sgt_tx
);
993 /* Map DMA buffers */
994 rx_sglen
= dma_map_sg(rxchan
->device
->dev
, pl022
->sgt_rx
.sgl
,
995 pl022
->sgt_rx
.nents
, DMA_FROM_DEVICE
);
999 tx_sglen
= dma_map_sg(txchan
->device
->dev
, pl022
->sgt_tx
.sgl
,
1000 pl022
->sgt_tx
.nents
, DMA_TO_DEVICE
);
1004 /* Send both scatterlists */
1005 rxdesc
= rxchan
->device
->device_prep_slave_sg(rxchan
,
1009 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1013 txdesc
= txchan
->device
->device_prep_slave_sg(txchan
,
1017 DMA_PREP_INTERRUPT
| DMA_CTRL_ACK
);
1021 /* Put the callback on the RX transfer only, that should finish last */
1022 rxdesc
->callback
= dma_callback
;
1023 rxdesc
->callback_param
= pl022
;
1025 /* Submit and fire RX and TX with TX last so we're ready to read! */
1026 dmaengine_submit(rxdesc
);
1027 dmaengine_submit(txdesc
);
1028 dma_async_issue_pending(rxchan
);
1029 dma_async_issue_pending(txchan
);
1034 dmaengine_terminate_all(txchan
);
1036 dmaengine_terminate_all(rxchan
);
1037 dma_unmap_sg(txchan
->device
->dev
, pl022
->sgt_tx
.sgl
,
1038 pl022
->sgt_tx
.nents
, DMA_TO_DEVICE
);
1040 dma_unmap_sg(rxchan
->device
->dev
, pl022
->sgt_rx
.sgl
,
1041 pl022
->sgt_tx
.nents
, DMA_FROM_DEVICE
);
1043 sg_free_table(&pl022
->sgt_tx
);
1045 sg_free_table(&pl022
->sgt_rx
);
1050 static int __init
pl022_dma_probe(struct pl022
*pl022
)
1052 dma_cap_mask_t mask
;
1054 /* Try to acquire a generic DMA engine slave channel */
1056 dma_cap_set(DMA_SLAVE
, mask
);
1058 * We need both RX and TX channels to do DMA, else do none
1061 pl022
->dma_rx_channel
= dma_request_channel(mask
,
1062 pl022
->master_info
->dma_filter
,
1063 pl022
->master_info
->dma_rx_param
);
1064 if (!pl022
->dma_rx_channel
) {
1065 dev_err(&pl022
->adev
->dev
, "no RX DMA channel!\n");
1069 pl022
->dma_tx_channel
= dma_request_channel(mask
,
1070 pl022
->master_info
->dma_filter
,
1071 pl022
->master_info
->dma_tx_param
);
1072 if (!pl022
->dma_tx_channel
) {
1073 dev_err(&pl022
->adev
->dev
, "no TX DMA channel!\n");
1077 pl022
->dummypage
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
1078 if (!pl022
->dummypage
) {
1079 dev_err(&pl022
->adev
->dev
, "no DMA dummypage!\n");
1080 goto err_no_dummypage
;
1083 dev_info(&pl022
->adev
->dev
, "setup for DMA on RX %s, TX %s\n",
1084 dma_chan_name(pl022
->dma_rx_channel
),
1085 dma_chan_name(pl022
->dma_tx_channel
));
1090 dma_release_channel(pl022
->dma_tx_channel
);
1092 dma_release_channel(pl022
->dma_rx_channel
);
1093 pl022
->dma_rx_channel
= NULL
;
1098 static void terminate_dma(struct pl022
*pl022
)
1100 struct dma_chan
*rxchan
= pl022
->dma_rx_channel
;
1101 struct dma_chan
*txchan
= pl022
->dma_tx_channel
;
1103 dmaengine_terminate_all(rxchan
);
1104 dmaengine_terminate_all(txchan
);
1105 unmap_free_dma_scatter(pl022
);
1108 static void pl022_dma_remove(struct pl022
*pl022
)
1111 terminate_dma(pl022
);
1112 if (pl022
->dma_tx_channel
)
1113 dma_release_channel(pl022
->dma_tx_channel
);
1114 if (pl022
->dma_rx_channel
)
1115 dma_release_channel(pl022
->dma_rx_channel
);
1116 kfree(pl022
->dummypage
);
1120 static inline int configure_dma(struct pl022
*pl022
)
1125 static inline int pl022_dma_probe(struct pl022
*pl022
)
1130 static inline void pl022_dma_remove(struct pl022
*pl022
)
1136 * pl022_interrupt_handler - Interrupt handler for SSP controller
1138 * This function handles interrupts generated for an interrupt based transfer.
1139 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
1140 * current message's state as STATE_ERROR and schedule the tasklet
1141 * pump_transfers which will do the postprocessing of the current message by
1142 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
1143 * more data, and writes data in TX FIFO till it is not full. If we complete
1144 * the transfer we move to the next transfer and schedule the tasklet.
1146 static irqreturn_t
pl022_interrupt_handler(int irq
, void *dev_id
)
1148 struct pl022
*pl022
= dev_id
;
1149 struct spi_message
*msg
= pl022
->cur_msg
;
1153 if (unlikely(!msg
)) {
1154 dev_err(&pl022
->adev
->dev
,
1155 "bad message state in interrupt handler");
1160 /* Read the Interrupt Status Register */
1161 irq_status
= readw(SSP_MIS(pl022
->virtbase
));
1163 if (unlikely(!irq_status
))
1167 * This handles the FIFO interrupts, the timeout
1168 * interrupts are flatly ignored, they cannot be
1171 if (unlikely(irq_status
& SSP_MIS_MASK_RORMIS
)) {
1173 * Overrun interrupt - bail out since our Data has been
1176 dev_err(&pl022
->adev
->dev
, "FIFO overrun\n");
1177 if (readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_RFF
)
1178 dev_err(&pl022
->adev
->dev
,
1179 "RXFIFO is full\n");
1180 if (readw(SSP_SR(pl022
->virtbase
)) & SSP_SR_MASK_TNF
)
1181 dev_err(&pl022
->adev
->dev
,
1182 "TXFIFO is full\n");
1185 * Disable and clear interrupts, disable SSP,
1186 * mark message with bad status so it can be
1189 writew(DISABLE_ALL_INTERRUPTS
,
1190 SSP_IMSC(pl022
->virtbase
));
1191 writew(CLEAR_ALL_INTERRUPTS
, SSP_ICR(pl022
->virtbase
));
1192 writew((readw(SSP_CR1(pl022
->virtbase
)) &
1193 (~SSP_CR1_MASK_SSE
)), SSP_CR1(pl022
->virtbase
));
1194 msg
->state
= STATE_ERROR
;
1196 /* Schedule message queue handler */
1197 tasklet_schedule(&pl022
->pump_transfers
);
1203 if ((pl022
->tx
== pl022
->tx_end
) && (flag
== 0)) {
1205 /* Disable Transmit interrupt */
1206 writew(readw(SSP_IMSC(pl022
->virtbase
)) &
1207 (~SSP_IMSC_MASK_TXIM
),
1208 SSP_IMSC(pl022
->virtbase
));
1212 * Since all transactions must write as much as shall be read,
1213 * we can conclude the entire transaction once RX is complete.
1214 * At this point, all TX will always be finished.
1216 if (pl022
->rx
>= pl022
->rx_end
) {
1217 writew(DISABLE_ALL_INTERRUPTS
,
1218 SSP_IMSC(pl022
->virtbase
));
1219 writew(CLEAR_ALL_INTERRUPTS
, SSP_ICR(pl022
->virtbase
));
1220 if (unlikely(pl022
->rx
> pl022
->rx_end
)) {
1221 dev_warn(&pl022
->adev
->dev
, "read %u surplus "
1222 "bytes (did you request an odd "
1223 "number of bytes on a 16bit bus?)\n",
1224 (u32
) (pl022
->rx
- pl022
->rx_end
));
1226 /* Update total bytes transfered */
1227 msg
->actual_length
+= pl022
->cur_transfer
->len
;
1228 if (pl022
->cur_transfer
->cs_change
)
1230 cs_control(SSP_CHIP_DESELECT
);
1231 /* Move to next transfer */
1232 msg
->state
= next_transfer(pl022
);
1233 tasklet_schedule(&pl022
->pump_transfers
);
1241 * This sets up the pointers to memory for the next message to
1242 * send out on the SPI bus.
1244 static int set_up_next_transfer(struct pl022
*pl022
,
1245 struct spi_transfer
*transfer
)
1249 /* Sanity check the message for this bus width */
1250 residue
= pl022
->cur_transfer
->len
% pl022
->cur_chip
->n_bytes
;
1251 if (unlikely(residue
!= 0)) {
1252 dev_err(&pl022
->adev
->dev
,
1253 "message of %u bytes to transmit but the current "
1254 "chip bus has a data width of %u bytes!\n",
1255 pl022
->cur_transfer
->len
,
1256 pl022
->cur_chip
->n_bytes
);
1257 dev_err(&pl022
->adev
->dev
, "skipping this message\n");
1260 pl022
->tx
= (void *)transfer
->tx_buf
;
1261 pl022
->tx_end
= pl022
->tx
+ pl022
->cur_transfer
->len
;
1262 pl022
->rx
= (void *)transfer
->rx_buf
;
1263 pl022
->rx_end
= pl022
->rx
+ pl022
->cur_transfer
->len
;
1265 pl022
->tx
? pl022
->cur_chip
->write
: WRITING_NULL
;
1266 pl022
->read
= pl022
->rx
? pl022
->cur_chip
->read
: READING_NULL
;
1271 * pump_transfers - Tasklet function which schedules next transfer
1272 * when running in interrupt or DMA transfer mode.
1273 * @data: SSP driver private data structure
1276 static void pump_transfers(unsigned long data
)
1278 struct pl022
*pl022
= (struct pl022
*) data
;
1279 struct spi_message
*message
= NULL
;
1280 struct spi_transfer
*transfer
= NULL
;
1281 struct spi_transfer
*previous
= NULL
;
1283 /* Get current state information */
1284 message
= pl022
->cur_msg
;
1285 transfer
= pl022
->cur_transfer
;
1287 /* Handle for abort */
1288 if (message
->state
== STATE_ERROR
) {
1289 message
->status
= -EIO
;
1294 /* Handle end of message */
1295 if (message
->state
== STATE_DONE
) {
1296 message
->status
= 0;
1301 /* Delay if requested at end of transfer before CS change */
1302 if (message
->state
== STATE_RUNNING
) {
1303 previous
= list_entry(transfer
->transfer_list
.prev
,
1304 struct spi_transfer
,
1306 if (previous
->delay_usecs
)
1308 * FIXME: This runs in interrupt context.
1309 * Is this really smart?
1311 udelay(previous
->delay_usecs
);
1313 /* Drop chip select only if cs_change is requested */
1314 if (previous
->cs_change
)
1315 pl022
->cur_chip
->cs_control(SSP_CHIP_SELECT
);
1318 message
->state
= STATE_RUNNING
;
1321 if (set_up_next_transfer(pl022
, transfer
)) {
1322 message
->state
= STATE_ERROR
;
1323 message
->status
= -EIO
;
1327 /* Flush the FIFOs and let's go! */
1330 if (pl022
->cur_chip
->enable_dma
) {
1331 if (configure_dma(pl022
)) {
1332 dev_dbg(&pl022
->adev
->dev
,
1333 "configuration of DMA failed, fall back to interrupt mode\n");
1334 goto err_config_dma
;
1340 writew(ENABLE_ALL_INTERRUPTS
, SSP_IMSC(pl022
->virtbase
));
1343 static void do_interrupt_dma_transfer(struct pl022
*pl022
)
1345 u32 irqflags
= ENABLE_ALL_INTERRUPTS
;
1347 /* Enable target chip */
1348 pl022
->cur_chip
->cs_control(SSP_CHIP_SELECT
);
1349 if (set_up_next_transfer(pl022
, pl022
->cur_transfer
)) {
1351 pl022
->cur_msg
->state
= STATE_ERROR
;
1352 pl022
->cur_msg
->status
= -EIO
;
1356 /* If we're using DMA, set up DMA here */
1357 if (pl022
->cur_chip
->enable_dma
) {
1358 /* Configure DMA transfer */
1359 if (configure_dma(pl022
)) {
1360 dev_dbg(&pl022
->adev
->dev
,
1361 "configuration of DMA failed, fall back to interrupt mode\n");
1362 goto err_config_dma
;
1364 /* Disable interrupts in DMA mode, IRQ from DMA controller */
1365 irqflags
= DISABLE_ALL_INTERRUPTS
;
1368 /* Enable SSP, turn on interrupts */
1369 writew((readw(SSP_CR1(pl022
->virtbase
)) | SSP_CR1_MASK_SSE
),
1370 SSP_CR1(pl022
->virtbase
));
1371 writew(irqflags
, SSP_IMSC(pl022
->virtbase
));
1374 static void do_polling_transfer(struct pl022
*pl022
)
1376 struct spi_message
*message
= NULL
;
1377 struct spi_transfer
*transfer
= NULL
;
1378 struct spi_transfer
*previous
= NULL
;
1379 struct chip_data
*chip
;
1381 chip
= pl022
->cur_chip
;
1382 message
= pl022
->cur_msg
;
1384 while (message
->state
!= STATE_DONE
) {
1385 /* Handle for abort */
1386 if (message
->state
== STATE_ERROR
)
1388 transfer
= pl022
->cur_transfer
;
1390 /* Delay if requested at end of transfer */
1391 if (message
->state
== STATE_RUNNING
) {
1393 list_entry(transfer
->transfer_list
.prev
,
1394 struct spi_transfer
, transfer_list
);
1395 if (previous
->delay_usecs
)
1396 udelay(previous
->delay_usecs
);
1397 if (previous
->cs_change
)
1398 pl022
->cur_chip
->cs_control(SSP_CHIP_SELECT
);
1401 message
->state
= STATE_RUNNING
;
1402 pl022
->cur_chip
->cs_control(SSP_CHIP_SELECT
);
1405 /* Configuration Changing Per Transfer */
1406 if (set_up_next_transfer(pl022
, transfer
)) {
1408 message
->state
= STATE_ERROR
;
1411 /* Flush FIFOs and enable SSP */
1413 writew((readw(SSP_CR1(pl022
->virtbase
)) | SSP_CR1_MASK_SSE
),
1414 SSP_CR1(pl022
->virtbase
));
1416 dev_dbg(&pl022
->adev
->dev
, "polling transfer ongoing ...\n");
1417 /* FIXME: insert a timeout so we don't hang here indefinately */
1418 while (pl022
->tx
< pl022
->tx_end
|| pl022
->rx
< pl022
->rx_end
)
1421 /* Update total byte transfered */
1422 message
->actual_length
+= pl022
->cur_transfer
->len
;
1423 if (pl022
->cur_transfer
->cs_change
)
1424 pl022
->cur_chip
->cs_control(SSP_CHIP_DESELECT
);
1425 /* Move to next transfer */
1426 message
->state
= next_transfer(pl022
);
1429 /* Handle end of message */
1430 if (message
->state
== STATE_DONE
)
1431 message
->status
= 0;
1433 message
->status
= -EIO
;
1440 * pump_messages - Workqueue function which processes spi message queue
1441 * @data: pointer to private data of SSP driver
1443 * This function checks if there is any spi message in the queue that
1444 * needs processing and delegate control to appropriate function
1445 * do_polling_transfer()/do_interrupt_dma_transfer()
1446 * based on the kind of the transfer
1449 static void pump_messages(struct work_struct
*work
)
1451 struct pl022
*pl022
=
1452 container_of(work
, struct pl022
, pump_messages
);
1453 unsigned long flags
;
1455 /* Lock queue and check for queue work */
1456 spin_lock_irqsave(&pl022
->queue_lock
, flags
);
1457 if (list_empty(&pl022
->queue
) || !pl022
->running
) {
1458 pl022
->busy
= false;
1459 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1462 /* Make sure we are not already running a message */
1463 if (pl022
->cur_msg
) {
1464 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1467 /* Extract head of queue */
1469 list_entry(pl022
->queue
.next
, struct spi_message
, queue
);
1471 list_del_init(&pl022
->cur_msg
->queue
);
1473 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1475 /* Initial message state */
1476 pl022
->cur_msg
->state
= STATE_START
;
1477 pl022
->cur_transfer
= list_entry(pl022
->cur_msg
->transfers
.next
,
1478 struct spi_transfer
,
1481 /* Setup the SPI using the per chip configuration */
1482 pl022
->cur_chip
= spi_get_ctldata(pl022
->cur_msg
->spi
);
1484 * We enable the core voltage and clocks here, then the clocks
1485 * and core will be disabled when giveback() is called in each method
1486 * (poll/interrupt/DMA)
1488 amba_vcore_enable(pl022
->adev
);
1489 amba_pclk_enable(pl022
->adev
);
1490 clk_enable(pl022
->clk
);
1491 restore_state(pl022
);
1494 if (pl022
->cur_chip
->xfer_type
== POLLING_TRANSFER
)
1495 do_polling_transfer(pl022
);
1497 do_interrupt_dma_transfer(pl022
);
1501 static int __init
init_queue(struct pl022
*pl022
)
1503 INIT_LIST_HEAD(&pl022
->queue
);
1504 spin_lock_init(&pl022
->queue_lock
);
1506 pl022
->running
= false;
1507 pl022
->busy
= false;
1509 tasklet_init(&pl022
->pump_transfers
,
1510 pump_transfers
, (unsigned long)pl022
);
1512 INIT_WORK(&pl022
->pump_messages
, pump_messages
);
1513 pl022
->workqueue
= create_singlethread_workqueue(
1514 dev_name(pl022
->master
->dev
.parent
));
1515 if (pl022
->workqueue
== NULL
)
1522 static int start_queue(struct pl022
*pl022
)
1524 unsigned long flags
;
1526 spin_lock_irqsave(&pl022
->queue_lock
, flags
);
1528 if (pl022
->running
|| pl022
->busy
) {
1529 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1533 pl022
->running
= true;
1534 pl022
->cur_msg
= NULL
;
1535 pl022
->cur_transfer
= NULL
;
1536 pl022
->cur_chip
= NULL
;
1537 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1539 queue_work(pl022
->workqueue
, &pl022
->pump_messages
);
1545 static int stop_queue(struct pl022
*pl022
)
1547 unsigned long flags
;
1548 unsigned limit
= 500;
1551 spin_lock_irqsave(&pl022
->queue_lock
, flags
);
1553 /* This is a bit lame, but is optimized for the common execution path.
1554 * A wait_queue on the pl022->busy could be used, but then the common
1555 * execution path (pump_messages) would be required to call wake_up or
1556 * friends on every SPI message. Do this instead */
1557 while (!list_empty(&pl022
->queue
) && pl022
->busy
&& limit
--) {
1558 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1560 spin_lock_irqsave(&pl022
->queue_lock
, flags
);
1563 if (!list_empty(&pl022
->queue
) || pl022
->busy
)
1566 pl022
->running
= false;
1568 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1573 static int destroy_queue(struct pl022
*pl022
)
1577 status
= stop_queue(pl022
);
1578 /* we are unloading the module or failing to load (only two calls
1579 * to this routine), and neither call can handle a return value.
1580 * However, destroy_workqueue calls flush_workqueue, and that will
1581 * block until all work is done. If the reason that stop_queue
1582 * timed out is that the work will never finish, then it does no
1583 * good to call destroy_workqueue, so return anyway. */
1587 destroy_workqueue(pl022
->workqueue
);
1592 static int verify_controller_parameters(struct pl022
*pl022
,
1593 struct pl022_config_chip
const *chip_info
)
1595 if ((chip_info
->iface
< SSP_INTERFACE_MOTOROLA_SPI
)
1596 || (chip_info
->iface
> SSP_INTERFACE_UNIDIRECTIONAL
)) {
1597 dev_err(&pl022
->adev
->dev
,
1598 "interface is configured incorrectly\n");
1601 if ((chip_info
->iface
== SSP_INTERFACE_UNIDIRECTIONAL
) &&
1602 (!pl022
->vendor
->unidir
)) {
1603 dev_err(&pl022
->adev
->dev
,
1604 "unidirectional mode not supported in this "
1605 "hardware version\n");
1608 if ((chip_info
->hierarchy
!= SSP_MASTER
)
1609 && (chip_info
->hierarchy
!= SSP_SLAVE
)) {
1610 dev_err(&pl022
->adev
->dev
,
1611 "hierarchy is configured incorrectly\n");
1614 if ((chip_info
->com_mode
!= INTERRUPT_TRANSFER
)
1615 && (chip_info
->com_mode
!= DMA_TRANSFER
)
1616 && (chip_info
->com_mode
!= POLLING_TRANSFER
)) {
1617 dev_err(&pl022
->adev
->dev
,
1618 "Communication mode is configured incorrectly\n");
1621 if ((chip_info
->rx_lev_trig
< SSP_RX_1_OR_MORE_ELEM
)
1622 || (chip_info
->rx_lev_trig
> SSP_RX_32_OR_MORE_ELEM
)) {
1623 dev_err(&pl022
->adev
->dev
,
1624 "RX FIFO Trigger Level is configured incorrectly\n");
1627 if ((chip_info
->tx_lev_trig
< SSP_TX_1_OR_MORE_EMPTY_LOC
)
1628 || (chip_info
->tx_lev_trig
> SSP_TX_32_OR_MORE_EMPTY_LOC
)) {
1629 dev_err(&pl022
->adev
->dev
,
1630 "TX FIFO Trigger Level is configured incorrectly\n");
1633 if (chip_info
->iface
== SSP_INTERFACE_NATIONAL_MICROWIRE
) {
1634 if ((chip_info
->ctrl_len
< SSP_BITS_4
)
1635 || (chip_info
->ctrl_len
> SSP_BITS_32
)) {
1636 dev_err(&pl022
->adev
->dev
,
1637 "CTRL LEN is configured incorrectly\n");
1640 if ((chip_info
->wait_state
!= SSP_MWIRE_WAIT_ZERO
)
1641 && (chip_info
->wait_state
!= SSP_MWIRE_WAIT_ONE
)) {
1642 dev_err(&pl022
->adev
->dev
,
1643 "Wait State is configured incorrectly\n");
1646 /* Half duplex is only available in the ST Micro version */
1647 if (pl022
->vendor
->extended_cr
) {
1648 if ((chip_info
->duplex
!=
1649 SSP_MICROWIRE_CHANNEL_FULL_DUPLEX
)
1650 && (chip_info
->duplex
!=
1651 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX
)) {
1652 dev_err(&pl022
->adev
->dev
,
1653 "Microwire duplex mode is configured incorrectly\n");
1657 if (chip_info
->duplex
!= SSP_MICROWIRE_CHANNEL_FULL_DUPLEX
)
1658 dev_err(&pl022
->adev
->dev
,
1659 "Microwire half duplex mode requested,"
1660 " but this is only available in the"
1661 " ST version of PL022\n");
1669 * pl022_transfer - transfer function registered to SPI master framework
1670 * @spi: spi device which is requesting transfer
1671 * @msg: spi message which is to handled is queued to driver queue
1673 * This function is registered to the SPI framework for this SPI master
1674 * controller. It will queue the spi_message in the queue of driver if
1675 * the queue is not stopped and return.
1677 static int pl022_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
1679 struct pl022
*pl022
= spi_master_get_devdata(spi
->master
);
1680 unsigned long flags
;
1682 spin_lock_irqsave(&pl022
->queue_lock
, flags
);
1684 if (!pl022
->running
) {
1685 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1688 msg
->actual_length
= 0;
1689 msg
->status
= -EINPROGRESS
;
1690 msg
->state
= STATE_START
;
1692 list_add_tail(&msg
->queue
, &pl022
->queue
);
1693 if (pl022
->running
&& !pl022
->busy
)
1694 queue_work(pl022
->workqueue
, &pl022
->pump_messages
);
1696 spin_unlock_irqrestore(&pl022
->queue_lock
, flags
);
1700 static int calculate_effective_freq(struct pl022
*pl022
,
1702 struct ssp_clock_params
*clk_freq
)
1704 /* Lets calculate the frequency parameters */
1707 bool freq_found
= false;
1712 rate
= clk_get_rate(pl022
->clk
);
1713 /* cpsdvscr = 2 & scr 0 */
1714 max_tclk
= (rate
/ (CPSDVR_MIN
* (1 + SCR_MIN
)));
1715 /* cpsdvsr = 254 & scr = 255 */
1716 min_tclk
= (rate
/ (CPSDVR_MAX
* (1 + SCR_MAX
)));
1718 if ((freq
<= max_tclk
) && (freq
>= min_tclk
)) {
1719 while (cpsdvsr
<= CPSDVR_MAX
&& !freq_found
) {
1720 while (scr
<= SCR_MAX
&& !freq_found
) {
1722 (cpsdvsr
* (1 + scr
))) > freq
)
1726 * This bool is made true when
1727 * effective frequency >=
1728 * target frequency is found
1732 (cpsdvsr
* (1 + scr
))) != freq
) {
1733 if (scr
== SCR_MIN
) {
1747 dev_dbg(&pl022
->adev
->dev
,
1748 "SSP Effective Frequency is %u\n",
1749 (rate
/ (cpsdvsr
* (1 + scr
))));
1750 clk_freq
->cpsdvsr
= (u8
) (cpsdvsr
& 0xFF);
1751 clk_freq
->scr
= (u8
) (scr
& 0xFF);
1752 dev_dbg(&pl022
->adev
->dev
,
1753 "SSP cpsdvsr = %d, scr = %d\n",
1754 clk_freq
->cpsdvsr
, clk_freq
->scr
);
1757 dev_err(&pl022
->adev
->dev
,
1758 "controller data is incorrect: out of range frequency");
1766 * A piece of default chip info unless the platform
1769 static const struct pl022_config_chip pl022_default_chip_info
= {
1770 .com_mode
= POLLING_TRANSFER
,
1771 .iface
= SSP_INTERFACE_MOTOROLA_SPI
,
1772 .hierarchy
= SSP_SLAVE
,
1773 .slave_tx_disable
= DO_NOT_DRIVE_TX
,
1774 .rx_lev_trig
= SSP_RX_1_OR_MORE_ELEM
,
1775 .tx_lev_trig
= SSP_TX_1_OR_MORE_EMPTY_LOC
,
1776 .ctrl_len
= SSP_BITS_8
,
1777 .wait_state
= SSP_MWIRE_WAIT_ZERO
,
1778 .duplex
= SSP_MICROWIRE_CHANNEL_FULL_DUPLEX
,
1779 .cs_control
= null_cs_control
,
1784 * pl022_setup - setup function registered to SPI master framework
1785 * @spi: spi device which is requesting setup
1787 * This function is registered to the SPI framework for this SPI master
1788 * controller. If it is the first time when setup is called by this device,
1789 * this function will initialize the runtime state for this chip and save
1790 * the same in the device structure. Else it will update the runtime info
1791 * with the updated chip info. Nothing is really being written to the
1792 * controller hardware here, that is not done until the actual transfer
1795 static int pl022_setup(struct spi_device
*spi
)
1797 struct pl022_config_chip
const *chip_info
;
1798 struct chip_data
*chip
;
1799 struct ssp_clock_params clk_freq
= {0, };
1801 struct pl022
*pl022
= spi_master_get_devdata(spi
->master
);
1802 unsigned int bits
= spi
->bits_per_word
;
1805 if (!spi
->max_speed_hz
)
1808 /* Get controller_state if one is supplied */
1809 chip
= spi_get_ctldata(spi
);
1812 chip
= kzalloc(sizeof(struct chip_data
), GFP_KERNEL
);
1815 "cannot allocate controller state\n");
1819 "allocated memory for controller's runtime state\n");
1822 /* Get controller data if one is supplied */
1823 chip_info
= spi
->controller_data
;
1825 if (chip_info
== NULL
) {
1826 chip_info
= &pl022_default_chip_info
;
1827 /* spi_board_info.controller_data not is supplied */
1829 "using default controller_data settings\n");
1832 "using user supplied controller_data settings\n");
1835 * We can override with custom divisors, else we use the board
1838 if ((0 == chip_info
->clk_freq
.cpsdvsr
)
1839 && (0 == chip_info
->clk_freq
.scr
)) {
1840 status
= calculate_effective_freq(pl022
,
1844 goto err_config_params
;
1846 memcpy(&clk_freq
, &chip_info
->clk_freq
, sizeof(clk_freq
));
1847 if ((clk_freq
.cpsdvsr
% 2) != 0)
1849 clk_freq
.cpsdvsr
- 1;
1851 if ((clk_freq
.cpsdvsr
< CPSDVR_MIN
)
1852 || (clk_freq
.cpsdvsr
> CPSDVR_MAX
)) {
1854 "cpsdvsr is configured incorrectly\n");
1855 goto err_config_params
;
1859 status
= verify_controller_parameters(pl022
, chip_info
);
1861 dev_err(&spi
->dev
, "controller data is incorrect");
1862 goto err_config_params
;
1865 /* Now set controller state based on controller data */
1866 chip
->xfer_type
= chip_info
->com_mode
;
1867 if (!chip_info
->cs_control
) {
1868 chip
->cs_control
= null_cs_control
;
1870 "chip select function is NULL for this chip\n");
1872 chip
->cs_control
= chip_info
->cs_control
;
1875 /* PL022 doesn't support less than 4-bits */
1877 goto err_config_params
;
1878 } else if (bits
<= 8) {
1879 dev_dbg(&spi
->dev
, "4 <= n <=8 bits per word\n");
1881 chip
->read
= READING_U8
;
1882 chip
->write
= WRITING_U8
;
1883 } else if (bits
<= 16) {
1884 dev_dbg(&spi
->dev
, "9 <= n <= 16 bits per word\n");
1886 chip
->read
= READING_U16
;
1887 chip
->write
= WRITING_U16
;
1889 if (pl022
->vendor
->max_bpw
>= 32) {
1890 dev_dbg(&spi
->dev
, "17 <= n <= 32 bits per word\n");
1892 chip
->read
= READING_U32
;
1893 chip
->write
= WRITING_U32
;
1896 "illegal data size for this controller!\n");
1898 "a standard pl022 can only handle "
1899 "1 <= n <= 16 bit words\n");
1901 goto err_config_params
;
1905 /* Now Initialize all register settings required for this chip */
1910 if ((chip_info
->com_mode
== DMA_TRANSFER
)
1911 && ((pl022
->master_info
)->enable_dma
)) {
1912 chip
->enable_dma
= true;
1913 dev_dbg(&spi
->dev
, "DMA mode set in controller state\n");
1914 SSP_WRITE_BITS(chip
->dmacr
, SSP_DMA_ENABLED
,
1915 SSP_DMACR_MASK_RXDMAE
, 0);
1916 SSP_WRITE_BITS(chip
->dmacr
, SSP_DMA_ENABLED
,
1917 SSP_DMACR_MASK_TXDMAE
, 1);
1919 chip
->enable_dma
= false;
1920 dev_dbg(&spi
->dev
, "DMA mode NOT set in controller state\n");
1921 SSP_WRITE_BITS(chip
->dmacr
, SSP_DMA_DISABLED
,
1922 SSP_DMACR_MASK_RXDMAE
, 0);
1923 SSP_WRITE_BITS(chip
->dmacr
, SSP_DMA_DISABLED
,
1924 SSP_DMACR_MASK_TXDMAE
, 1);
1927 chip
->cpsr
= clk_freq
.cpsdvsr
;
1929 /* Special setup for the ST micro extended control registers */
1930 if (pl022
->vendor
->extended_cr
) {
1933 if (pl022
->vendor
->pl023
) {
1934 /* These bits are only in the PL023 */
1935 SSP_WRITE_BITS(chip
->cr1
, chip_info
->clkdelay
,
1936 SSP_CR1_MASK_FBCLKDEL_ST
, 13);
1938 /* These bits are in the PL022 but not PL023 */
1939 SSP_WRITE_BITS(chip
->cr0
, chip_info
->duplex
,
1940 SSP_CR0_MASK_HALFDUP_ST
, 5);
1941 SSP_WRITE_BITS(chip
->cr0
, chip_info
->ctrl_len
,
1942 SSP_CR0_MASK_CSS_ST
, 16);
1943 SSP_WRITE_BITS(chip
->cr0
, chip_info
->iface
,
1944 SSP_CR0_MASK_FRF_ST
, 21);
1945 SSP_WRITE_BITS(chip
->cr1
, chip_info
->wait_state
,
1946 SSP_CR1_MASK_MWAIT_ST
, 6);
1948 SSP_WRITE_BITS(chip
->cr0
, bits
- 1,
1949 SSP_CR0_MASK_DSS_ST
, 0);
1951 if (spi
->mode
& SPI_LSB_FIRST
) {
1958 SSP_WRITE_BITS(chip
->cr1
, tmp
, SSP_CR1_MASK_RENDN_ST
, 4);
1959 SSP_WRITE_BITS(chip
->cr1
, etx
, SSP_CR1_MASK_TENDN_ST
, 5);
1960 SSP_WRITE_BITS(chip
->cr1
, chip_info
->rx_lev_trig
,
1961 SSP_CR1_MASK_RXIFLSEL_ST
, 7);
1962 SSP_WRITE_BITS(chip
->cr1
, chip_info
->tx_lev_trig
,
1963 SSP_CR1_MASK_TXIFLSEL_ST
, 10);
1965 SSP_WRITE_BITS(chip
->cr0
, bits
- 1,
1966 SSP_CR0_MASK_DSS
, 0);
1967 SSP_WRITE_BITS(chip
->cr0
, chip_info
->iface
,
1968 SSP_CR0_MASK_FRF
, 4);
1971 /* Stuff that is common for all versions */
1972 if (spi
->mode
& SPI_CPOL
)
1973 tmp
= SSP_CLK_POL_IDLE_HIGH
;
1975 tmp
= SSP_CLK_POL_IDLE_LOW
;
1976 SSP_WRITE_BITS(chip
->cr0
, tmp
, SSP_CR0_MASK_SPO
, 6);
1978 if (spi
->mode
& SPI_CPHA
)
1979 tmp
= SSP_CLK_SECOND_EDGE
;
1981 tmp
= SSP_CLK_FIRST_EDGE
;
1982 SSP_WRITE_BITS(chip
->cr0
, tmp
, SSP_CR0_MASK_SPH
, 7);
1984 SSP_WRITE_BITS(chip
->cr0
, clk_freq
.scr
, SSP_CR0_MASK_SCR
, 8);
1985 /* Loopback is available on all versions except PL023 */
1986 if (!pl022
->vendor
->pl023
) {
1987 if (spi
->mode
& SPI_LOOP
)
1988 tmp
= LOOPBACK_ENABLED
;
1990 tmp
= LOOPBACK_DISABLED
;
1991 SSP_WRITE_BITS(chip
->cr1
, tmp
, SSP_CR1_MASK_LBM
, 0);
1993 SSP_WRITE_BITS(chip
->cr1
, SSP_DISABLED
, SSP_CR1_MASK_SSE
, 1);
1994 SSP_WRITE_BITS(chip
->cr1
, chip_info
->hierarchy
, SSP_CR1_MASK_MS
, 2);
1995 SSP_WRITE_BITS(chip
->cr1
, chip_info
->slave_tx_disable
, SSP_CR1_MASK_SOD
, 3);
1997 /* Save controller_state */
1998 spi_set_ctldata(spi
, chip
);
2001 spi_set_ctldata(spi
, NULL
);
2007 * pl022_cleanup - cleanup function registered to SPI master framework
2008 * @spi: spi device which is requesting cleanup
2010 * This function is registered to the SPI framework for this SPI master
2011 * controller. It will free the runtime state of chip.
2013 static void pl022_cleanup(struct spi_device
*spi
)
2015 struct chip_data
*chip
= spi_get_ctldata(spi
);
2017 spi_set_ctldata(spi
, NULL
);
2022 static int __devinit
2023 pl022_probe(struct amba_device
*adev
, struct amba_id
*id
)
2025 struct device
*dev
= &adev
->dev
;
2026 struct pl022_ssp_controller
*platform_info
= adev
->dev
.platform_data
;
2027 struct spi_master
*master
;
2028 struct pl022
*pl022
= NULL
; /*Data for this driver */
2031 dev_info(&adev
->dev
,
2032 "ARM PL022 driver, device ID: 0x%08x\n", adev
->periphid
);
2033 if (platform_info
== NULL
) {
2034 dev_err(&adev
->dev
, "probe - no platform data supplied\n");
2039 /* Allocate master with space for data */
2040 master
= spi_alloc_master(dev
, sizeof(struct pl022
));
2041 if (master
== NULL
) {
2042 dev_err(&adev
->dev
, "probe - cannot alloc SPI master\n");
2047 pl022
= spi_master_get_devdata(master
);
2048 pl022
->master
= master
;
2049 pl022
->master_info
= platform_info
;
2051 pl022
->vendor
= id
->data
;
2054 * Bus Number Which has been Assigned to this SSP controller
2057 master
->bus_num
= platform_info
->bus_id
;
2058 master
->num_chipselect
= platform_info
->num_chipselect
;
2059 master
->cleanup
= pl022_cleanup
;
2060 master
->setup
= pl022_setup
;
2061 master
->transfer
= pl022_transfer
;
2064 * Supports mode 0-3, loopback, and active low CS. Transfers are
2065 * always MS bit first on the original pl022.
2067 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_CS_HIGH
| SPI_LOOP
;
2068 if (pl022
->vendor
->extended_cr
)
2069 master
->mode_bits
|= SPI_LSB_FIRST
;
2071 dev_dbg(&adev
->dev
, "BUSNO: %d\n", master
->bus_num
);
2073 status
= amba_request_regions(adev
, NULL
);
2075 goto err_no_ioregion
;
2077 pl022
->phybase
= adev
->res
.start
;
2078 pl022
->virtbase
= ioremap(adev
->res
.start
, resource_size(&adev
->res
));
2079 if (pl022
->virtbase
== NULL
) {
2081 goto err_no_ioremap
;
2083 printk(KERN_INFO
"pl022: mapped registers from 0x%08x to %p\n",
2084 adev
->res
.start
, pl022
->virtbase
);
2086 pl022
->clk
= clk_get(&adev
->dev
, NULL
);
2087 if (IS_ERR(pl022
->clk
)) {
2088 status
= PTR_ERR(pl022
->clk
);
2089 dev_err(&adev
->dev
, "could not retrieve SSP/SPI bus clock\n");
2094 writew((readw(SSP_CR1(pl022
->virtbase
)) & (~SSP_CR1_MASK_SSE
)),
2095 SSP_CR1(pl022
->virtbase
));
2096 load_ssp_default_config(pl022
);
2098 status
= request_irq(adev
->irq
[0], pl022_interrupt_handler
, 0, "pl022",
2101 dev_err(&adev
->dev
, "probe - cannot get IRQ (%d)\n", status
);
2105 /* Get DMA channels */
2106 if (platform_info
->enable_dma
) {
2107 status
= pl022_dma_probe(pl022
);
2112 /* Initialize and start queue */
2113 status
= init_queue(pl022
);
2115 dev_err(&adev
->dev
, "probe - problem initializing queue\n");
2116 goto err_init_queue
;
2118 status
= start_queue(pl022
);
2120 dev_err(&adev
->dev
, "probe - problem starting queue\n");
2121 goto err_start_queue
;
2123 /* Register with the SPI framework */
2124 amba_set_drvdata(adev
, pl022
);
2125 status
= spi_register_master(master
);
2128 "probe - problem registering spi master\n");
2129 goto err_spi_register
;
2131 dev_dbg(dev
, "probe succeded\n");
2133 * Disable the silicon block pclk and any voltage domain and just
2134 * power it up and clock it when it's needed
2136 amba_pclk_disable(adev
);
2137 amba_vcore_disable(adev
);
2143 destroy_queue(pl022
);
2144 pl022_dma_remove(pl022
);
2146 free_irq(adev
->irq
[0], pl022
);
2148 clk_put(pl022
->clk
);
2150 iounmap(pl022
->virtbase
);
2152 amba_release_regions(adev
);
2154 spi_master_put(master
);
2160 static int __devexit
2161 pl022_remove(struct amba_device
*adev
)
2163 struct pl022
*pl022
= amba_get_drvdata(adev
);
2168 /* Remove the queue */
2169 status
= destroy_queue(pl022
);
2172 "queue remove failed (%d)\n", status
);
2175 load_ssp_default_config(pl022
);
2176 pl022_dma_remove(pl022
);
2177 free_irq(adev
->irq
[0], pl022
);
2178 clk_disable(pl022
->clk
);
2179 clk_put(pl022
->clk
);
2180 iounmap(pl022
->virtbase
);
2181 amba_release_regions(adev
);
2182 tasklet_disable(&pl022
->pump_transfers
);
2183 spi_unregister_master(pl022
->master
);
2184 spi_master_put(pl022
->master
);
2185 amba_set_drvdata(adev
, NULL
);
2186 dev_dbg(&adev
->dev
, "remove succeded\n");
2191 static int pl022_suspend(struct amba_device
*adev
, pm_message_t state
)
2193 struct pl022
*pl022
= amba_get_drvdata(adev
);
2196 status
= stop_queue(pl022
);
2198 dev_warn(&adev
->dev
, "suspend cannot stop queue\n");
2202 amba_vcore_enable(adev
);
2203 amba_pclk_enable(adev
);
2204 load_ssp_default_config(pl022
);
2205 amba_pclk_disable(adev
);
2206 amba_vcore_disable(adev
);
2207 dev_dbg(&adev
->dev
, "suspended\n");
2211 static int pl022_resume(struct amba_device
*adev
)
2213 struct pl022
*pl022
= amba_get_drvdata(adev
);
2216 /* Start the queue running */
2217 status
= start_queue(pl022
);
2219 dev_err(&adev
->dev
, "problem starting queue (%d)\n", status
);
2221 dev_dbg(&adev
->dev
, "resumed\n");
2226 #define pl022_suspend NULL
2227 #define pl022_resume NULL
2228 #endif /* CONFIG_PM */
2230 static struct vendor_data vendor_arm
= {
2234 .extended_cr
= false,
2239 static struct vendor_data vendor_st
= {
2243 .extended_cr
= true,
2247 static struct vendor_data vendor_st_pl023
= {
2251 .extended_cr
= true,
2255 static struct amba_id pl022_ids
[] = {
2258 * ARM PL022 variant, this has a 16bit wide
2259 * and 8 locations deep TX/RX FIFO
2263 .data
= &vendor_arm
,
2267 * ST Micro derivative, this has 32bit wide
2268 * and 32 locations deep TX/RX FIFO
2276 * ST-Ericsson derivative "PL023" (this is not
2277 * an official ARM number), this is a PL022 SSP block
2278 * stripped to SPI mode only, it has 32bit wide
2279 * and 32 locations deep TX/RX FIFO but no extended
2284 .data
= &vendor_st_pl023
,
2289 static struct amba_driver pl022_driver
= {
2291 .name
= "ssp-pl022",
2293 .id_table
= pl022_ids
,
2294 .probe
= pl022_probe
,
2295 .remove
= __devexit_p(pl022_remove
),
2296 .suspend
= pl022_suspend
,
2297 .resume
= pl022_resume
,
2301 static int __init
pl022_init(void)
2303 return amba_driver_register(&pl022_driver
);
2306 subsys_initcall(pl022_init
);
2308 static void __exit
pl022_exit(void)
2310 amba_driver_unregister(&pl022_driver
);
2313 module_exit(pl022_exit
);
2315 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
2316 MODULE_DESCRIPTION("PL022 SSP Controller Driver");
2317 MODULE_LICENSE("GPL");