arch/arm/mach-imx/mm-imx3.c

   1 /*
   2  *  Copyright (C) 1999,2000 Arm Limited
   3  *  Copyright (C) 2000 Deep Blue Solutions Ltd
   4  *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   5  *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   6  *    - add MX31 specific definitions
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/mm.h>
  20 #include <linux/init.h>
  21 #include <linux/err.h>
  22
  23 #include <asm/pgtable.h>
  24 #include <asm/hardware/cache-l2x0.h>
  25 #include <asm/mach/map.h>
  26
  27 #include <mach/common.h>
  28 #include <mach/devices-common.h>
  29 #include <mach/hardware.h>
  30 #include <mach/iomux-v3.h>
  31 #include <mach/irqs.h>
  32
  33 static void imx3_idle(void)
  34 {
  35         unsigned long reg = 0;
  36
  37         __asm__ __volatile__(
  38                 /* disable I and D cache */
  39                 "mrc p15, 0, %0, c1, c0, 0\n"
  40                 "bic %0, %0, #0x00001000\n"
  41                 "bic %0, %0, #0x00000004\n"
  42                 "mcr p15, 0, %0, c1, c0, 0\n"
  43                 /* invalidate I cache */
  44                 "mov %0, #0\n"
  45                 "mcr p15, 0, %0, c7, c5, 0\n"
  46                 /* clear and invalidate D cache */
  47                 "mov %0, #0\n"
  48                 "mcr p15, 0, %0, c7, c14, 0\n"
  49                 /* WFI */
  50                 "mov %0, #0\n"
  51                 "mcr p15, 0, %0, c7, c0, 4\n"
  52                 "nop\n" "nop\n" "nop\n" "nop\n"
  53                 "nop\n" "nop\n" "nop\n"
  54                 /* enable I and D cache */
  55                 "mrc p15, 0, %0, c1, c0, 0\n"
  56                 "orr %0, %0, #0x00001000\n"
  57                 "orr %0, %0, #0x00000004\n"
  58                 "mcr p15, 0, %0, c1, c0, 0\n"
  59                 : "=r" (reg));
  60 }
  61
  62 static void __iomem *imx3_ioremap_caller(unsigned long phys_addr, size_t size,
  63                                          unsigned int mtype, void *caller)
  64 {
  65         if (mtype == MT_DEVICE) {
  66                 /*
  67                  * Access all peripherals below 0x80000000 as nonshared device
  68                  * on mx3, but leave l2cc alone.  Otherwise cache corruptions
  69                  * can occur.
  70                  */
  71                 if (phys_addr < 0x80000000 &&
  72                                 !addr_in_module(phys_addr, MX3x_L2CC))
  73                         mtype = MT_DEVICE_NONSHARED;
  74         }
  75
  76         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
  77 }
  78
  79 void imx3_init_l2x0(void)
  80 {
  81         void __iomem *l2x0_base;
  82         void __iomem *clkctl_base;
  83
  84 /*
  85  * First of all, we must repair broken chip settings. There are some
  86  * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
  87  * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
  88  * Workaraound is to setup the correct register setting prior enabling the
  89  * L2 cache. This should not hurt already working CPUs, as they are using the
  90  * same value.
  91  */
  92 #define L2_MEM_VAL 0x10
  93
  94         clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
  95         if (clkctl_base != NULL) {
  96                 writel(0x00000515, clkctl_base + L2_MEM_VAL);
  97                 iounmap(clkctl_base);
  98         } else {
  99                 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
 100         }
 101
 102         l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
 103         if (IS_ERR(l2x0_base)) {
 104                 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
 105                                 PTR_ERR(l2x0_base));
 106                 return;
 107         }
 108
 109         l2x0_init(l2x0_base, 0x00030024, 0x00000000);
 110 }
 111
 112 #ifdef CONFIG_SOC_IMX31
 113 static struct map_desc mx31_io_desc[] __initdata = {
 114         imx_map_entry(MX31, X_MEMC, MT_DEVICE),
 115         imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
 116         imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
 117         imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
 118         imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
 119 };
 120
 121 /*
 122  * This function initializes the memory map. It is called during the
 123  * system startup to create static physical to virtual memory mappings
 124  * for the IO modules.
 125  */
 126 void __init mx31_map_io(void)
 127 {
 128         iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
 129 }
 130
 131 void __init imx31_init_early(void)
 132 {
 133         mxc_set_cpu_type(MXC_CPU_MX31);
 134         mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 135         arch_ioremap_caller = imx3_ioremap_caller;
 136         arm_pm_idle = imx3_idle;
 137 }
 138
 139 void __init mx31_init_irq(void)
 140 {
 141         mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
 142 }
 143
 144 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
 145         .per_2_per_addr = 1677,
 146 };
 147
 148 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
 149         .ap_2_ap_addr = 423,
 150         .ap_2_bp_addr = 829,
 151         .bp_2_ap_addr = 1029,
 152 };
 153
 154 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
 155         .fw_name = "sdma-imx31-to2.bin",
 156         .script_addrs = &imx31_to2_sdma_script,
 157 };
 158
 159 void __init imx31_soc_init(void)
 160 {
 161         int to_version = mx31_revision() >> 4;
 162
 163         imx3_init_l2x0();
 164
 165         mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
 166         mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
 167         mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
 168
 169         if (to_version == 1) {
 170                 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
 171                         strlen(imx31_sdma_pdata.fw_name));
 172                 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
 173         }
 174
 175         imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
 176 }
 177 #endif /* ifdef CONFIG_SOC_IMX31 */
 178
 179 #ifdef CONFIG_SOC_IMX35
 180 static struct map_desc mx35_io_desc[] __initdata = {
 181         imx_map_entry(MX35, X_MEMC, MT_DEVICE),
 182         imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
 183         imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
 184         imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
 185         imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
 186 };
 187
 188 void __init mx35_map_io(void)
 189 {
 190         iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
 191 }
 192
 193 void __init imx35_init_early(void)
 194 {
 195         mxc_set_cpu_type(MXC_CPU_MX35);
 196         mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
 197         mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 198         arm_pm_idle = imx3_idle;
 199         arch_ioremap_caller = imx3_ioremap_caller;
 200 }
 201
 202 void __init mx35_init_irq(void)
 203 {
 204         mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
 205 }
 206
 207 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
 208         .ap_2_ap_addr = 642,
 209         .uart_2_mcu_addr = 817,
 210         .mcu_2_app_addr = 747,
 211         .uartsh_2_mcu_addr = 1183,
 212         .per_2_shp_addr = 1033,
 213         .mcu_2_shp_addr = 961,
 214         .ata_2_mcu_addr = 1333,
 215         .mcu_2_ata_addr = 1252,
 216         .app_2_mcu_addr = 683,
 217         .shp_2_per_addr = 1111,
 218         .shp_2_mcu_addr = 892,
 219 };
 220
 221 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
 222         .ap_2_ap_addr = 729,
 223         .uart_2_mcu_addr = 904,
 224         .per_2_app_addr = 1597,
 225         .mcu_2_app_addr = 834,
 226         .uartsh_2_mcu_addr = 1270,
 227         .per_2_shp_addr = 1120,
 228         .mcu_2_shp_addr = 1048,
 229         .ata_2_mcu_addr = 1429,
 230         .mcu_2_ata_addr = 1339,
 231         .app_2_per_addr = 1531,
 232         .app_2_mcu_addr = 770,
 233         .shp_2_per_addr = 1198,
 234         .shp_2_mcu_addr = 979,
 235 };
 236
 237 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
 238         .fw_name = "sdma-imx35-to2.bin",
 239         .script_addrs = &imx35_to2_sdma_script,
 240 };
 241
 242 void __init imx35_soc_init(void)
 243 {
 244         int to_version = mx35_revision() >> 4;
 245
 246         imx3_init_l2x0();
 247
 248         /* i.mx35 has the i.mx31 type gpio */
 249         mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
 250         mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
 251         mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
 252
 253         if (to_version == 1) {
 254                 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
 255                         strlen(imx35_sdma_pdata.fw_name));
 256                 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
 257         }
 258
 259         imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
 260 }
 261 #endif /* ifdef CONFIG_SOC_IMX35 */