arch/arm/mach-imx/mach-cpuimx51sd.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/i2c.h>
  20 #include <linux/i2c/tsc2007.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/i2c-gpio.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/can/platform/mcp251x.h>
  28
  29 #include <mach/eukrea-baseboards.h>
  30 #include <mach/common.h>
  31 #include <mach/hardware.h>
  32 #include <mach/iomux-mx51.h>
  33
  34 #include <asm/setup.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/arch.h>
  37 #include <asm/mach/time.h>
  38
  39 #include "devices-imx51.h"
  40 #include "cpu_op-mx51.h"
  41
  42 #define USBH1_RST               IMX_GPIO_NR(2, 28)
  43 #define ETH_RST                 IMX_GPIO_NR(2, 31)
  44 #define TSC2007_IRQGPIO_REV2    IMX_GPIO_NR(3, 12)
  45 #define TSC2007_IRQGPIO_REV3    IMX_GPIO_NR(4, 0)
  46 #define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
  47 #define CAN_RST                 IMX_GPIO_NR(4, 15)
  48 #define CAN_NCS                 IMX_GPIO_NR(4, 24)
  49 #define CAN_RXOBF_REV2          IMX_GPIO_NR(1, 4)
  50 #define CAN_RXOBF_REV3          IMX_GPIO_NR(3, 12)
  51 #define CAN_RX1BF               IMX_GPIO_NR(1, 6)
  52 #define CAN_TXORTS              IMX_GPIO_NR(1, 7)
  53 #define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
  54 #define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
  55 #define I2C_SCL                 IMX_GPIO_NR(4, 16)
  56 #define I2C_SDA                 IMX_GPIO_NR(4, 17)
  57
  58 /* USB_CTRL_1 */
  59 #define MX51_USB_CTRL_1_OFFSET          0x10
  60 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  61
  62 #define MX51_USB_PLLDIV_12_MHZ          0x00
  63 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  64 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  65
  66 static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
  67         /* UART1 */
  68         MX51_PAD_UART1_RXD__UART1_RXD,
  69         MX51_PAD_UART1_TXD__UART1_TXD,
  70         MX51_PAD_UART1_RTS__UART1_RTS,
  71         MX51_PAD_UART1_CTS__UART1_CTS,
  72
  73         /* USB HOST1 */
  74         MX51_PAD_USBH1_CLK__USBH1_CLK,
  75         MX51_PAD_USBH1_DIR__USBH1_DIR,
  76         MX51_PAD_USBH1_NXT__USBH1_NXT,
  77         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  78         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  79         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  80         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  81         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  82         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  83         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  84         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  85         MX51_PAD_USBH1_STP__USBH1_STP,
  86         MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
  87
  88         /* FEC */
  89         MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
  90
  91         /* HSI2C */
  92         MX51_PAD_I2C1_CLK__GPIO4_16,
  93         MX51_PAD_I2C1_DAT__GPIO4_17,
  94
  95         /* I2C1 */
  96         MX51_PAD_SD2_CMD__I2C1_SCL,
  97         MX51_PAD_SD2_CLK__I2C1_SDA,
  98
  99         /* CAN */
 100         MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
 101         MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
 102         MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
 103         MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
 104         MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
 105         MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
 106         MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
 107         MX51_PAD_GPIO1_6__GPIO1_6,
 108         MX51_PAD_GPIO1_7__GPIO1_7,
 109         MX51_PAD_GPIO1_8__GPIO1_8,
 110         MX51_PAD_GPIO1_9__GPIO1_9,
 111
 112         /* Touchscreen */
 113         /* IRQ */
 114         NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
 115                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 116                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 117         NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
 118                         PAD_CTL_PKE | PAD_CTL_SRE_FAST |
 119                         PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
 120 };
 121
 122 static const struct imxuart_platform_data uart_pdata __initconst = {
 123         .flags = IMXUART_HAVE_RTSCTS,
 124 };
 125
 126 static int tsc2007_get_pendown_state(void)
 127 {
 128         if (mx51_revision() < IMX_CHIP_REVISION_3_0)
 129                 return !gpio_get_value(TSC2007_IRQGPIO_REV2);
 130         else
 131                 return !gpio_get_value(TSC2007_IRQGPIO_REV3);
 132 }
 133
 134 static struct tsc2007_platform_data tsc2007_info = {
 135         .model                  = 2007,
 136         .x_plate_ohms           = 180,
 137         .get_pendown_state      = tsc2007_get_pendown_state,
 138 };
 139
 140 static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
 141         {
 142                 I2C_BOARD_INFO("pcf8563", 0x51),
 143         }, {
 144                 I2C_BOARD_INFO("tsc2007", 0x49),
 145                 .type           = "tsc2007",
 146                 .platform_data  = &tsc2007_info,
 147         },
 148 };
 149
 150 static const struct mxc_nand_platform_data
 151                 eukrea_cpuimx51sd_nand_board_info __initconst = {
 152         .width          = 1,
 153         .hw_ecc         = 1,
 154         .flash_bbt      = 1,
 155 };
 156
 157 /* This function is board specific as the bit mask for the plldiv will also
 158 be different for other Freescale SoCs, thus a common bitmask is not
 159 possible and cannot get place in /plat-mxc/ehci.c.*/
 160 static int initialize_otg_port(struct platform_device *pdev)
 161 {
 162         u32 v;
 163         void __iomem *usb_base;
 164         void __iomem *usbother_base;
 165
 166         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 167         if (!usb_base)
 168                 return -ENOMEM;
 169         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 170
 171         /* Set the PHY clock to 19.2MHz */
 172         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 173         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 174         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 175         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 176         iounmap(usb_base);
 177
 178         mdelay(10);
 179
 180         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 181 }
 182
 183 static int initialize_usbh1_port(struct platform_device *pdev)
 184 {
 185         u32 v;
 186         void __iomem *usb_base;
 187         void __iomem *usbother_base;
 188
 189         usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
 190         if (!usb_base)
 191                 return -ENOMEM;
 192         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 193
 194         /* The clock for the USBH1 ULPI port will come from the PHY. */
 195         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 196         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
 197                         usbother_base + MX51_USB_CTRL_1_OFFSET);
 198         iounmap(usb_base);
 199
 200         mdelay(10);
 201
 202         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 203                         MXC_EHCI_ITC_NO_THRESHOLD);
 204 }
 205
 206 static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
 207         .init           = initialize_otg_port,
 208         .portsc = MXC_EHCI_UTMI_16BIT,
 209 };
 210
 211 static const struct fsl_usb2_platform_data usb_pdata __initconst = {
 212         .operating_mode = FSL_USB2_DR_DEVICE,
 213         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 214 };
 215
 216 static const struct mxc_usbh_platform_data usbh1_config __initconst = {
 217         .init           = initialize_usbh1_port,
 218         .portsc = MXC_EHCI_MODE_ULPI,
 219 };
 220
 221 static int otg_mode_host;
 222
 223 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
 224 {
 225         if (!strcmp(options, "host"))
 226                 otg_mode_host = 1;
 227         else if (!strcmp(options, "device"))
 228                 otg_mode_host = 0;
 229         else
 230                 pr_info("otg_mode neither \"host\" nor \"device\". "
 231                         "Defaulting to device\n");
 232         return 0;
 233 }
 234 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
 235
 236 static struct i2c_gpio_platform_data pdata = {
 237         .sda_pin                = I2C_SDA,
 238         .sda_is_open_drain      = 0,
 239         .scl_pin                = I2C_SCL,
 240         .scl_is_open_drain      = 0,
 241         .udelay                 = 2,
 242 };
 243
 244 static struct platform_device hsi2c_gpio_device = {
 245         .name                   = "i2c-gpio",
 246         .id                     = 0,
 247         .dev.platform_data      = &pdata,
 248 };
 249
 250 static struct mcp251x_platform_data mcp251x_info = {
 251         .oscillator_frequency = 24E6,
 252 };
 253
 254 static struct spi_board_info cpuimx51sd_spi_device[] = {
 255         {
 256                 .modalias        = "mcp2515",
 257                 .max_speed_hz    = 10000000,
 258                 .bus_num         = 0,
 259                 .mode           = SPI_MODE_0,
 260                 .chip_select     = 0,
 261                 .platform_data   = &mcp251x_info,
 262                 .irq             = IMX_GPIO_TO_IRQ(CAN_IRQGPIO)
 263         },
 264 };
 265
 266 static int cpuimx51sd_spi1_cs[] = {
 267         CAN_NCS,
 268 };
 269
 270 static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
 271         .chipselect     = cpuimx51sd_spi1_cs,
 272         .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
 273 };
 274
 275 static struct platform_device *rev2_platform_devices[] __initdata = {
 276         &hsi2c_gpio_device,
 277 };
 278
 279 static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
 280         .bitrate = 100000,
 281 };
 282
 283 static void __init eukrea_cpuimx51sd_init(void)
 284 {
 285         imx51_soc_init();
 286
 287         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
 288                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 289
 290 #if defined(CONFIG_CPU_FREQ_IMX)
 291         get_cpu_op = mx51_get_cpu_op;
 292 #endif
 293
 294         imx51_add_imx_uart(0, &uart_pdata);
 295         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
 296         imx51_add_imx2_wdt(0, NULL);
 297
 298         gpio_request(ETH_RST, "eth_rst");
 299         gpio_set_value(ETH_RST, 1);
 300         imx51_add_fec(NULL);
 301
 302         gpio_request(CAN_IRQGPIO, "can_irq");
 303         gpio_direction_input(CAN_IRQGPIO);
 304         gpio_free(CAN_IRQGPIO);
 305         gpio_request(CAN_NCS, "can_ncs");
 306         gpio_direction_output(CAN_NCS, 1);
 307         gpio_free(CAN_NCS);
 308         gpio_request(CAN_RST, "can_rst");
 309         gpio_direction_output(CAN_RST, 0);
 310         msleep(20);
 311         gpio_set_value(CAN_RST, 1);
 312         imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
 313         spi_register_board_info(cpuimx51sd_spi_device,
 314                                 ARRAY_SIZE(cpuimx51sd_spi_device));
 315
 316         if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
 317                 eukrea_cpuimx51sd_i2c_devices[1].irq =
 318                         gpio_to_irq(TSC2007_IRQGPIO_REV2),
 319                 platform_add_devices(rev2_platform_devices,
 320                         ARRAY_SIZE(rev2_platform_devices));
 321                 gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
 322                 gpio_direction_input(TSC2007_IRQGPIO_REV2);
 323                 gpio_free(TSC2007_IRQGPIO_REV2);
 324         } else {
 325                 eukrea_cpuimx51sd_i2c_devices[1].irq =
 326                         gpio_to_irq(TSC2007_IRQGPIO_REV3),
 327                 imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
 328                 gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
 329                 gpio_direction_input(TSC2007_IRQGPIO_REV3);
 330                 gpio_free(TSC2007_IRQGPIO_REV3);
 331         }
 332
 333         i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
 334                         ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
 335
 336         if (otg_mode_host)
 337                 imx51_add_mxc_ehci_otg(&dr_utmi_config);
 338         else {
 339                 initialize_otg_port(NULL);
 340                 imx51_add_fsl_usb2_udc(&usb_pdata);
 341         }
 342
 343         gpio_request(USBH1_RST, "usb_rst");
 344         gpio_direction_output(USBH1_RST, 0);
 345         msleep(20);
 346         gpio_set_value(USBH1_RST, 1);
 347         imx51_add_mxc_ehci_hs(1, &usbh1_config);
 348
 349 #ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
 350         eukrea_mbimxsd51_baseboard_init();
 351 #endif
 352 }
 353
 354 static void __init eukrea_cpuimx51sd_timer_init(void)
 355 {
 356         mx51_clocks_init(32768, 24000000, 22579200, 0);
 357 }
 358
 359 static struct sys_timer mxc_timer = {
 360         .init   = eukrea_cpuimx51sd_timer_init,
 361 };
 362
 363 MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
 364         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 365         .atag_offset = 0x100,
 366         .map_io = mx51_map_io,
 367         .init_early = imx51_init_early,
 368         .init_irq = mx51_init_irq,
 369         .handle_irq = imx51_handle_irq,
 370         .timer = &mxc_timer,
 371         .init_machine = eukrea_cpuimx51sd_init,
 372         .init_late      = imx51_init_late,
 373         .restart        = mxc_restart,
 374 MACHINE_END