drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <asm/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72
  73 #include "radeon_family.h"
  74 #include "radeon_mode.h"
  75 #include "radeon_reg.h"
  76
  77 /*
  78  * Modules parameters.
  79  */
  80 extern int radeon_no_wb;
  81 extern int radeon_modeset;
  82 extern int radeon_dynclks;
  83 extern int radeon_r4xx_atom;
  84 extern int radeon_agpmode;
  85 extern int radeon_vram_limit;
  86 extern int radeon_gart_size;
  87 extern int radeon_benchmarking;
  88 extern int radeon_testing;
  89 extern int radeon_connector_table;
  90 extern int radeon_tv;
  91 extern int radeon_new_pll;
  92 extern int radeon_dynpm;
  93 extern int radeon_audio;
  94 extern int radeon_disp_priority;
  95 extern int radeon_hw_i2c;
  96
  97 /*
  98  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  99  * symbol;
 100  */
 101 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
 102 #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
 103 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 104 #define RADEON_IB_POOL_SIZE             16
 105 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
 106 #define RADEONFB_CONN_LIMIT             4
 107 #define RADEON_BIOS_NUM_SCRATCH         8
 108
 109 /*
 110  * Errata workarounds.
 111  */
 112 enum radeon_pll_errata {
 113         CHIP_ERRATA_R300_CG             = 0x00000001,
 114         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 115         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 116 };
 117
 118
 119 struct radeon_device;
 120
 121
 122 /*
 123  * BIOS.
 124  */
 125 #define ATRM_BIOS_PAGE 4096
 126
 127 #if defined(CONFIG_VGA_SWITCHEROO)
 128 bool radeon_atrm_supported(struct pci_dev *pdev);
 129 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 130 #else
 131 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 132 {
 133         return false;
 134 }
 135
 136 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 137         return -EINVAL;
 138 }
 139 #endif
 140 bool radeon_get_bios(struct radeon_device *rdev);
 141
 142
 143 /*
 144  * Dummy page
 145  */
 146 struct radeon_dummy_page {
 147         struct page     *page;
 148         dma_addr_t      addr;
 149 };
 150 int radeon_dummy_page_init(struct radeon_device *rdev);
 151 void radeon_dummy_page_fini(struct radeon_device *rdev);
 152
 153
 154 /*
 155  * Clocks
 156  */
 157 struct radeon_clock {
 158         struct radeon_pll p1pll;
 159         struct radeon_pll p2pll;
 160         struct radeon_pll dcpll;
 161         struct radeon_pll spll;
 162         struct radeon_pll mpll;
 163         /* 10 Khz units */
 164         uint32_t default_mclk;
 165         uint32_t default_sclk;
 166         uint32_t default_dispclk;
 167         uint32_t dp_extclk;
 168 };
 169
 170 /*
 171  * Power management
 172  */
 173 int radeon_pm_init(struct radeon_device *rdev);
 174 void radeon_pm_fini(struct radeon_device *rdev);
 175 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 176 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 177 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 178 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
 179 void radeon_sync_with_vblank(struct radeon_device *rdev);
 180
 181 /*
 182  * Fences.
 183  */
 184 struct radeon_fence_driver {
 185         uint32_t                        scratch_reg;
 186         atomic_t                        seq;
 187         uint32_t                        last_seq;
 188         unsigned long                   last_jiffies;
 189         unsigned long                   last_timeout;
 190         wait_queue_head_t               queue;
 191         rwlock_t                        lock;
 192         struct list_head                created;
 193         struct list_head                emited;
 194         struct list_head                signaled;
 195         bool                            initialized;
 196 };
 197
 198 struct radeon_fence {
 199         struct radeon_device            *rdev;
 200         struct kref                     kref;
 201         struct list_head                list;
 202         /* protected by radeon_fence.lock */
 203         uint32_t                        seq;
 204         bool                            emited;
 205         bool                            signaled;
 206 };
 207
 208 int radeon_fence_driver_init(struct radeon_device *rdev);
 209 void radeon_fence_driver_fini(struct radeon_device *rdev);
 210 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 211 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 212 void radeon_fence_process(struct radeon_device *rdev);
 213 bool radeon_fence_signaled(struct radeon_fence *fence);
 214 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 215 int radeon_fence_wait_next(struct radeon_device *rdev);
 216 int radeon_fence_wait_last(struct radeon_device *rdev);
 217 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 218 void radeon_fence_unref(struct radeon_fence **fence);
 219
 220 /*
 221  * Tiling registers
 222  */
 223 struct radeon_surface_reg {
 224         struct radeon_bo *bo;
 225 };
 226
 227 #define RADEON_GEM_MAX_SURFACES 8
 228
 229 /*
 230  * TTM.
 231  */
 232 struct radeon_mman {
 233         struct ttm_bo_global_ref        bo_global_ref;
 234         struct ttm_global_reference     mem_global_ref;
 235         struct ttm_bo_device            bdev;
 236         bool                            mem_global_referenced;
 237         bool                            initialized;
 238 };
 239
 240 struct radeon_bo {
 241         /* Protected by gem.mutex */
 242         struct list_head                list;
 243         /* Protected by tbo.reserved */
 244         u32                             placements[3];
 245         struct ttm_placement            placement;
 246         struct ttm_buffer_object        tbo;
 247         struct ttm_bo_kmap_obj          kmap;
 248         unsigned                        pin_count;
 249         void                            *kptr;
 250         u32                             tiling_flags;
 251         u32                             pitch;
 252         int                             surface_reg;
 253         /* Constant after initialization */
 254         struct radeon_device            *rdev;
 255         struct drm_gem_object           *gobj;
 256 };
 257
 258 struct radeon_bo_list {
 259         struct list_head        list;
 260         struct radeon_bo        *bo;
 261         uint64_t                gpu_offset;
 262         unsigned                rdomain;
 263         unsigned                wdomain;
 264         u32                     tiling_flags;
 265 };
 266
 267 /*
 268  * GEM objects.
 269  */
 270 struct radeon_gem {
 271         struct mutex            mutex;
 272         struct list_head        objects;
 273 };
 274
 275 int radeon_gem_init(struct radeon_device *rdev);
 276 void radeon_gem_fini(struct radeon_device *rdev);
 277 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 278                                 int alignment, int initial_domain,
 279                                 bool discardable, bool kernel,
 280                                 struct drm_gem_object **obj);
 281 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 282                           uint64_t *gpu_addr);
 283 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 284
 285
 286 /*
 287  * GART structures, functions & helpers
 288  */
 289 struct radeon_mc;
 290
 291 struct radeon_gart_table_ram {
 292         volatile uint32_t               *ptr;
 293 };
 294
 295 struct radeon_gart_table_vram {
 296         struct radeon_bo                *robj;
 297         volatile uint32_t               *ptr;
 298 };
 299
 300 union radeon_gart_table {
 301         struct radeon_gart_table_ram    ram;
 302         struct radeon_gart_table_vram   vram;
 303 };
 304
 305 #define RADEON_GPU_PAGE_SIZE 4096
 306 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 307
 308 struct radeon_gart {
 309         dma_addr_t                      table_addr;
 310         unsigned                        num_gpu_pages;
 311         unsigned                        num_cpu_pages;
 312         unsigned                        table_size;
 313         union radeon_gart_table         table;
 314         struct page                     **pages;
 315         dma_addr_t                      *pages_addr;
 316         bool                            ready;
 317 };
 318
 319 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 320 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 321 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 322 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 323 int radeon_gart_init(struct radeon_device *rdev);
 324 void radeon_gart_fini(struct radeon_device *rdev);
 325 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 326                         int pages);
 327 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 328                      int pages, struct page **pagelist);
 329
 330
 331 /*
 332  * GPU MC structures, functions & helpers
 333  */
 334 struct radeon_mc {
 335         resource_size_t         aper_size;
 336         resource_size_t         aper_base;
 337         resource_size_t         agp_base;
 338         /* for some chips with <= 32MB we need to lie
 339          * about vram size near mc fb location */
 340         u64                     mc_vram_size;
 341         u64                     visible_vram_size;
 342         u64                     gtt_size;
 343         u64                     gtt_start;
 344         u64                     gtt_end;
 345         u64                     vram_start;
 346         u64                     vram_end;
 347         unsigned                vram_width;
 348         u64                     real_vram_size;
 349         int                     vram_mtrr;
 350         bool                    vram_is_ddr;
 351         bool                    igp_sideport_enabled;
 352 };
 353
 354 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 355 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 356
 357 /*
 358  * GPU scratch registers structures, functions & helpers
 359  */
 360 struct radeon_scratch {
 361         unsigned                num_reg;
 362         bool                    free[32];
 363         uint32_t                reg[32];
 364 };
 365
 366 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 367 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 368
 369
 370 /*
 371  * IRQS.
 372  */
 373 struct radeon_irq {
 374         bool            installed;
 375         bool            sw_int;
 376         /* FIXME: use a define max crtc rather than hardcode it */
 377         bool            crtc_vblank_int[6];
 378         wait_queue_head_t       vblank_queue;
 379         /* FIXME: use defines for max hpd/dacs */
 380         bool            hpd[6];
 381         bool            gui_idle;
 382         bool            gui_idle_acked;
 383         wait_queue_head_t       idle_queue;
 384         /* FIXME: use defines for max HDMI blocks */
 385         bool            hdmi[2];
 386         spinlock_t sw_lock;
 387         int sw_refcount;
 388 };
 389
 390 int radeon_irq_kms_init(struct radeon_device *rdev);
 391 void radeon_irq_kms_fini(struct radeon_device *rdev);
 392 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 393 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 394
 395 /*
 396  * CP & ring.
 397  */
 398 struct radeon_ib {
 399         struct list_head        list;
 400         unsigned                idx;
 401         uint64_t                gpu_addr;
 402         struct radeon_fence     *fence;
 403         uint32_t                *ptr;
 404         uint32_t                length_dw;
 405         bool                    free;
 406 };
 407
 408 /*
 409  * locking -
 410  * mutex protects scheduled_ibs, ready, alloc_bm
 411  */
 412 struct radeon_ib_pool {
 413         struct mutex            mutex;
 414         struct radeon_bo        *robj;
 415         struct list_head        bogus_ib;
 416         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 417         bool                    ready;
 418         unsigned                head_id;
 419 };
 420
 421 struct radeon_cp {
 422         struct radeon_bo        *ring_obj;
 423         volatile uint32_t       *ring;
 424         unsigned                rptr;
 425         unsigned                wptr;
 426         unsigned                wptr_old;
 427         unsigned                ring_size;
 428         unsigned                ring_free_dw;
 429         int                     count_dw;
 430         uint64_t                gpu_addr;
 431         uint32_t                align_mask;
 432         uint32_t                ptr_mask;
 433         struct mutex            mutex;
 434         bool                    ready;
 435 };
 436
 437 /*
 438  * R6xx+ IH ring
 439  */
 440 struct r600_ih {
 441         struct radeon_bo        *ring_obj;
 442         volatile uint32_t       *ring;
 443         unsigned                rptr;
 444         unsigned                wptr;
 445         unsigned                wptr_old;
 446         unsigned                ring_size;
 447         uint64_t                gpu_addr;
 448         uint32_t                ptr_mask;
 449         spinlock_t              lock;
 450         bool                    enabled;
 451 };
 452
 453 struct r600_blit {
 454         struct mutex            mutex;
 455         struct radeon_bo        *shader_obj;
 456         u64 shader_gpu_addr;
 457         u32 vs_offset, ps_offset;
 458         u32 state_offset;
 459         u32 state_len;
 460         u32 vb_used, vb_total;
 461         struct radeon_ib *vb_ib;
 462 };
 463
 464 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 465 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 466 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 467 int radeon_ib_pool_init(struct radeon_device *rdev);
 468 void radeon_ib_pool_fini(struct radeon_device *rdev);
 469 int radeon_ib_test(struct radeon_device *rdev);
 470 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
 471 /* Ring access between begin & end cannot sleep */
 472 void radeon_ring_free_size(struct radeon_device *rdev);
 473 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 474 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 475 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 476 int radeon_ring_test(struct radeon_device *rdev);
 477 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 478 void radeon_ring_fini(struct radeon_device *rdev);
 479
 480
 481 /*
 482  * CS.
 483  */
 484 struct radeon_cs_reloc {
 485         struct drm_gem_object           *gobj;
 486         struct radeon_bo                *robj;
 487         struct radeon_bo_list           lobj;
 488         uint32_t                        handle;
 489         uint32_t                        flags;
 490 };
 491
 492 struct radeon_cs_chunk {
 493         uint32_t                chunk_id;
 494         uint32_t                length_dw;
 495         int kpage_idx[2];
 496         uint32_t                *kpage[2];
 497         uint32_t                *kdata;
 498         void __user *user_ptr;
 499         int last_copied_page;
 500         int last_page_index;
 501 };
 502
 503 struct radeon_cs_parser {
 504         struct device           *dev;
 505         struct radeon_device    *rdev;
 506         struct drm_file         *filp;
 507         /* chunks */
 508         unsigned                nchunks;
 509         struct radeon_cs_chunk  *chunks;
 510         uint64_t                *chunks_array;
 511         /* IB */
 512         unsigned                idx;
 513         /* relocations */
 514         unsigned                nrelocs;
 515         struct radeon_cs_reloc  *relocs;
 516         struct radeon_cs_reloc  **relocs_ptr;
 517         struct list_head        validated;
 518         /* indices of various chunks */
 519         int                     chunk_ib_idx;
 520         int                     chunk_relocs_idx;
 521         struct radeon_ib        *ib;
 522         void                    *track;
 523         unsigned                family;
 524         int parser_error;
 525 };
 526
 527 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 528 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 529
 530
 531 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 532 {
 533         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 534         u32 pg_idx, pg_offset;
 535         u32 idx_value = 0;
 536         int new_page;
 537
 538         pg_idx = (idx * 4) / PAGE_SIZE;
 539         pg_offset = (idx * 4) % PAGE_SIZE;
 540
 541         if (ibc->kpage_idx[0] == pg_idx)
 542                 return ibc->kpage[0][pg_offset/4];
 543         if (ibc->kpage_idx[1] == pg_idx)
 544                 return ibc->kpage[1][pg_offset/4];
 545
 546         new_page = radeon_cs_update_pages(p, pg_idx);
 547         if (new_page < 0) {
 548                 p->parser_error = new_page;
 549                 return 0;
 550         }
 551
 552         idx_value = ibc->kpage[new_page][pg_offset/4];
 553         return idx_value;
 554 }
 555
 556 struct radeon_cs_packet {
 557         unsigned        idx;
 558         unsigned        type;
 559         unsigned        reg;
 560         unsigned        opcode;
 561         int             count;
 562         unsigned        one_reg_wr;
 563 };
 564
 565 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 566                                       struct radeon_cs_packet *pkt,
 567                                       unsigned idx, unsigned reg);
 568 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 569                                       struct radeon_cs_packet *pkt);
 570
 571
 572 /*
 573  * AGP
 574  */
 575 int radeon_agp_init(struct radeon_device *rdev);
 576 void radeon_agp_resume(struct radeon_device *rdev);
 577 void radeon_agp_fini(struct radeon_device *rdev);
 578
 579
 580 /*
 581  * Writeback
 582  */
 583 struct radeon_wb {
 584         struct radeon_bo        *wb_obj;
 585         volatile uint32_t       *wb;
 586         uint64_t                gpu_addr;
 587 };
 588
 589 /**
 590  * struct radeon_pm - power management datas
 591  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 592  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 593  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 594  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 595  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 596  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 597  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 598  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 599  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 600  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 601  * @needed_bandwidth:   current bandwidth needs
 602  *
 603  * It keeps track of various data needed to take powermanagement decision.
 604  * Bandwith need is used to determine minimun clock of the GPU and memory.
 605  * Equation between gpu/memory clock and available bandwidth is hw dependent
 606  * (type of memory, bus size, efficiency, ...)
 607  */
 608 enum radeon_pm_state {
 609         PM_STATE_DISABLED,
 610         PM_STATE_MINIMUM,
 611         PM_STATE_PAUSED,
 612         PM_STATE_ACTIVE
 613 };
 614 enum radeon_pm_action {
 615         PM_ACTION_NONE,
 616         PM_ACTION_MINIMUM,
 617         PM_ACTION_DOWNCLOCK,
 618         PM_ACTION_UPCLOCK
 619 };
 620
 621 enum radeon_voltage_type {
 622         VOLTAGE_NONE = 0,
 623         VOLTAGE_GPIO,
 624         VOLTAGE_VDDC,
 625         VOLTAGE_SW
 626 };
 627
 628 enum radeon_pm_state_type {
 629         POWER_STATE_TYPE_DEFAULT,
 630         POWER_STATE_TYPE_POWERSAVE,
 631         POWER_STATE_TYPE_BATTERY,
 632         POWER_STATE_TYPE_BALANCED,
 633         POWER_STATE_TYPE_PERFORMANCE,
 634 };
 635
 636 enum radeon_pm_clock_mode_type {
 637         POWER_MODE_TYPE_DEFAULT,
 638         POWER_MODE_TYPE_LOW,
 639         POWER_MODE_TYPE_MID,
 640         POWER_MODE_TYPE_HIGH,
 641 };
 642
 643 struct radeon_voltage {
 644         enum radeon_voltage_type type;
 645         /* gpio voltage */
 646         struct radeon_gpio_rec gpio;
 647         u32 delay; /* delay in usec from voltage drop to sclk change */
 648         bool active_high; /* voltage drop is active when bit is high */
 649         /* VDDC voltage */
 650         u8 vddc_id; /* index into vddc voltage table */
 651         u8 vddci_id; /* index into vddci voltage table */
 652         bool vddci_enabled;
 653         /* r6xx+ sw */
 654         u32 voltage;
 655 };
 656
 657 struct radeon_pm_non_clock_info {
 658         /* pcie lanes */
 659         int pcie_lanes;
 660         /* standardized non-clock flags */
 661         u32 flags;
 662 };
 663
 664 struct radeon_pm_clock_info {
 665         /* memory clock */
 666         u32 mclk;
 667         /* engine clock */
 668         u32 sclk;
 669         /* voltage info */
 670         struct radeon_voltage voltage;
 671         /* standardized clock flags - not sure we'll need these */
 672         u32 flags;
 673 };
 674
 675 struct radeon_power_state {
 676         enum radeon_pm_state_type type;
 677         /* XXX: use a define for num clock modes */
 678         struct radeon_pm_clock_info clock_info[8];
 679         /* number of valid clock modes in this power state */
 680         int num_clock_modes;
 681         struct radeon_pm_clock_info *default_clock_mode;
 682         /* non clock info about this state */
 683         struct radeon_pm_non_clock_info non_clock_info;
 684         bool voltage_drop_active;
 685 };
 686
 687 /*
 688  * Some modes are overclocked by very low value, accept them
 689  */
 690 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
 691
 692 struct radeon_pm {
 693         struct mutex            mutex;
 694         struct delayed_work     idle_work;
 695         enum radeon_pm_state    state;
 696         enum radeon_pm_action   planned_action;
 697         unsigned long           action_timeout;
 698         bool                    downclocked;
 699         int                     active_crtcs;
 700         int                     req_vblank;
 701         bool                    vblank_sync;
 702         bool                    gui_idle;
 703         fixed20_12              max_bandwidth;
 704         fixed20_12              igp_sideport_mclk;
 705         fixed20_12              igp_system_mclk;
 706         fixed20_12              igp_ht_link_clk;
 707         fixed20_12              igp_ht_link_width;
 708         fixed20_12              k8_bandwidth;
 709         fixed20_12              sideport_bandwidth;
 710         fixed20_12              ht_bandwidth;
 711         fixed20_12              core_bandwidth;
 712         fixed20_12              sclk;
 713         fixed20_12              mclk;
 714         fixed20_12              needed_bandwidth;
 715         /* XXX: use a define for num power modes */
 716         struct radeon_power_state power_state[8];
 717         /* number of valid power states */
 718         int                     num_power_states;
 719         struct radeon_power_state *current_power_state;
 720         struct radeon_pm_clock_info *current_clock_mode;
 721         struct radeon_power_state *requested_power_state;
 722         struct radeon_pm_clock_info *requested_clock_mode;
 723         struct radeon_power_state *default_power_state;
 724         struct radeon_i2c_chan *i2c_bus;
 725 };
 726
 727
 728 /*
 729  * Benchmarking
 730  */
 731 void radeon_benchmark(struct radeon_device *rdev);
 732
 733
 734 /*
 735  * Testing
 736  */
 737 void radeon_test_moves(struct radeon_device *rdev);
 738
 739
 740 /*
 741  * Debugfs
 742  */
 743 int radeon_debugfs_add_files(struct radeon_device *rdev,
 744                              struct drm_info_list *files,
 745                              unsigned nfiles);
 746 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 747
 748
 749 /*
 750  * ASIC specific functions.
 751  */
 752 struct radeon_asic {
 753         int (*init)(struct radeon_device *rdev);
 754         void (*fini)(struct radeon_device *rdev);
 755         int (*resume)(struct radeon_device *rdev);
 756         int (*suspend)(struct radeon_device *rdev);
 757         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 758         bool (*gpu_is_lockup)(struct radeon_device *rdev);
 759         int (*asic_reset)(struct radeon_device *rdev);
 760         void (*gart_tlb_flush)(struct radeon_device *rdev);
 761         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 762         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 763         void (*cp_fini)(struct radeon_device *rdev);
 764         void (*cp_disable)(struct radeon_device *rdev);
 765         void (*cp_commit)(struct radeon_device *rdev);
 766         void (*ring_start)(struct radeon_device *rdev);
 767         int (*ring_test)(struct radeon_device *rdev);
 768         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 769         int (*irq_set)(struct radeon_device *rdev);
 770         int (*irq_process)(struct radeon_device *rdev);
 771         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 772         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 773         int (*cs_parse)(struct radeon_cs_parser *p);
 774         int (*copy_blit)(struct radeon_device *rdev,
 775                          uint64_t src_offset,
 776                          uint64_t dst_offset,
 777                          unsigned num_pages,
 778                          struct radeon_fence *fence);
 779         int (*copy_dma)(struct radeon_device *rdev,
 780                         uint64_t src_offset,
 781                         uint64_t dst_offset,
 782                         unsigned num_pages,
 783                         struct radeon_fence *fence);
 784         int (*copy)(struct radeon_device *rdev,
 785                     uint64_t src_offset,
 786                     uint64_t dst_offset,
 787                     unsigned num_pages,
 788                     struct radeon_fence *fence);
 789         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
 790         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 791         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
 792         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 793         int (*get_pcie_lanes)(struct radeon_device *rdev);
 794         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 795         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 796         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 797                                uint32_t tiling_flags, uint32_t pitch,
 798                                uint32_t offset, uint32_t obj_size);
 799         void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 800         void (*bandwidth_update)(struct radeon_device *rdev);
 801         void (*hpd_init)(struct radeon_device *rdev);
 802         void (*hpd_fini)(struct radeon_device *rdev);
 803         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 804         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 805         /* ioctl hw specific callback. Some hw might want to perform special
 806          * operation on specific ioctl. For instance on wait idle some hw
 807          * might want to perform and HDP flush through MMIO as it seems that
 808          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
 809          * through ring.
 810          */
 811         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
 812         bool (*gui_idle)(struct radeon_device *rdev);
 813         void (*set_power_state)(struct radeon_device *rdev);
 814 };
 815
 816 /*
 817  * Asic structures
 818  */
 819 struct r100_gpu_lockup {
 820         unsigned long   last_jiffies;
 821         u32             last_cp_rptr;
 822 };
 823
 824 struct r100_asic {
 825         const unsigned          *reg_safe_bm;
 826         unsigned                reg_safe_bm_size;
 827         u32                     hdp_cntl;
 828         struct r100_gpu_lockup  lockup;
 829 };
 830
 831 struct r300_asic {
 832         const unsigned          *reg_safe_bm;
 833         unsigned                reg_safe_bm_size;
 834         u32                     resync_scratch;
 835         u32                     hdp_cntl;
 836         struct r100_gpu_lockup  lockup;
 837 };
 838
 839 struct r600_asic {
 840         unsigned                max_pipes;
 841         unsigned                max_tile_pipes;
 842         unsigned                max_simds;
 843         unsigned                max_backends;
 844         unsigned                max_gprs;
 845         unsigned                max_threads;
 846         unsigned                max_stack_entries;
 847         unsigned                max_hw_contexts;
 848         unsigned                max_gs_threads;
 849         unsigned                sx_max_export_size;
 850         unsigned                sx_max_export_pos_size;
 851         unsigned                sx_max_export_smx_size;
 852         unsigned                sq_num_cf_insts;
 853         unsigned                tiling_nbanks;
 854         unsigned                tiling_npipes;
 855         unsigned                tiling_group_size;
 856         struct r100_gpu_lockup  lockup;
 857 };
 858
 859 struct rv770_asic {
 860         unsigned                max_pipes;
 861         unsigned                max_tile_pipes;
 862         unsigned                max_simds;
 863         unsigned                max_backends;
 864         unsigned                max_gprs;
 865         unsigned                max_threads;
 866         unsigned                max_stack_entries;
 867         unsigned                max_hw_contexts;
 868         unsigned                max_gs_threads;
 869         unsigned                sx_max_export_size;
 870         unsigned                sx_max_export_pos_size;
 871         unsigned                sx_max_export_smx_size;
 872         unsigned                sq_num_cf_insts;
 873         unsigned                sx_num_of_sets;
 874         unsigned                sc_prim_fifo_size;
 875         unsigned                sc_hiz_tile_fifo_size;
 876         unsigned                sc_earlyz_tile_fifo_fize;
 877         unsigned                tiling_nbanks;
 878         unsigned                tiling_npipes;
 879         unsigned                tiling_group_size;
 880         struct r100_gpu_lockup  lockup;
 881 };
 882
 883 struct evergreen_asic {
 884         unsigned num_ses;
 885         unsigned max_pipes;
 886         unsigned max_tile_pipes;
 887         unsigned max_simds;
 888         unsigned max_backends;
 889         unsigned max_gprs;
 890         unsigned max_threads;
 891         unsigned max_stack_entries;
 892         unsigned max_hw_contexts;
 893         unsigned max_gs_threads;
 894         unsigned sx_max_export_size;
 895         unsigned sx_max_export_pos_size;
 896         unsigned sx_max_export_smx_size;
 897         unsigned sq_num_cf_insts;
 898         unsigned sx_num_of_sets;
 899         unsigned sc_prim_fifo_size;
 900         unsigned sc_hiz_tile_fifo_size;
 901         unsigned sc_earlyz_tile_fifo_size;
 902         unsigned tiling_nbanks;
 903         unsigned tiling_npipes;
 904         unsigned tiling_group_size;
 905 };
 906
 907 union radeon_asic_config {
 908         struct r300_asic        r300;
 909         struct r100_asic        r100;
 910         struct r600_asic        r600;
 911         struct rv770_asic       rv770;
 912         struct evergreen_asic   evergreen;
 913 };
 914
 915 /*
 916  * asic initizalization from radeon_asic.c
 917  */
 918 void radeon_agp_disable(struct radeon_device *rdev);
 919 int radeon_asic_init(struct radeon_device *rdev);
 920
 921
 922 /*
 923  * IOCTL.
 924  */
 925 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
 926                           struct drm_file *filp);
 927 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
 928                             struct drm_file *filp);
 929 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
 930                          struct drm_file *file_priv);
 931 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
 932                            struct drm_file *file_priv);
 933 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 934                             struct drm_file *file_priv);
 935 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
 936                            struct drm_file *file_priv);
 937 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 938                                 struct drm_file *filp);
 939 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
 940                           struct drm_file *filp);
 941 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
 942                           struct drm_file *filp);
 943 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
 944                               struct drm_file *filp);
 945 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
 946 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
 947                                 struct drm_file *filp);
 948 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
 949                                 struct drm_file *filp);
 950
 951
 952 /*
 953  * Core structure, functions and helpers.
 954  */
 955 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
 956 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
 957
 958 struct radeon_device {
 959         struct device                   *dev;
 960         struct drm_device               *ddev;
 961         struct pci_dev                  *pdev;
 962         /* ASIC */
 963         union radeon_asic_config        config;
 964         enum radeon_family              family;
 965         unsigned long                   flags;
 966         int                             usec_timeout;
 967         enum radeon_pll_errata          pll_errata;
 968         int                             num_gb_pipes;
 969         int                             num_z_pipes;
 970         int                             disp_priority;
 971         /* BIOS */
 972         uint8_t                         *bios;
 973         bool                            is_atom_bios;
 974         uint16_t                        bios_header_start;
 975         struct radeon_bo                *stollen_vga_memory;
 976         /* Register mmio */
 977         resource_size_t                 rmmio_base;
 978         resource_size_t                 rmmio_size;
 979         void                            *rmmio;
 980         radeon_rreg_t                   mc_rreg;
 981         radeon_wreg_t                   mc_wreg;
 982         radeon_rreg_t                   pll_rreg;
 983         radeon_wreg_t                   pll_wreg;
 984         uint32_t                        pcie_reg_mask;
 985         radeon_rreg_t                   pciep_rreg;
 986         radeon_wreg_t                   pciep_wreg;
 987         struct radeon_clock             clock;
 988         struct radeon_mc                mc;
 989         struct radeon_gart              gart;
 990         struct radeon_mode_info         mode_info;
 991         struct radeon_scratch           scratch;
 992         struct radeon_mman              mman;
 993         struct radeon_fence_driver      fence_drv;
 994         struct radeon_cp                cp;
 995         struct radeon_ib_pool           ib_pool;
 996         struct radeon_irq               irq;
 997         struct radeon_asic              *asic;
 998         struct radeon_gem               gem;
 999         struct radeon_pm                pm;
1000         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1001         struct mutex                    cs_mutex;
1002         struct radeon_wb                wb;
1003         struct radeon_dummy_page        dummy_page;
1004         bool                            gpu_lockup;
1005         bool                            shutdown;
1006         bool                            suspend;
1007         bool                            need_dma32;
1008         bool                            accel_working;
1009         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1010         const struct firmware *me_fw;   /* all family ME firmware */
1011         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1012         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1013         struct r600_blit r600_blit;
1014         int msi_enabled; /* msi enabled */
1015         struct r600_ih ih; /* r6/700 interrupt ring */
1016         struct workqueue_struct *wq;
1017         struct work_struct hotplug_work;
1018         int num_crtc; /* number of crtcs */
1019         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1020
1021         /* audio stuff */
1022         struct timer_list       audio_timer;
1023         int                     audio_channels;
1024         int                     audio_rate;
1025         int                     audio_bits_per_sample;
1026         uint8_t                 audio_status_bits;
1027         uint8_t                 audio_category_code;
1028
1029         bool powered_down;
1030 };
1031
1032 int radeon_device_init(struct radeon_device *rdev,
1033                        struct drm_device *ddev,
1034                        struct pci_dev *pdev,
1035                        uint32_t flags);
1036 void radeon_device_fini(struct radeon_device *rdev);
1037 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1038
1039 /* r600 blit */
1040 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1041 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1042 void r600_kms_blit_copy(struct radeon_device *rdev,
1043                         u64 src_gpu_addr, u64 dst_gpu_addr,
1044                         int size_bytes);
1045
1046 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1047 {
1048         if (reg < rdev->rmmio_size)
1049                 return readl(((void __iomem *)rdev->rmmio) + reg);
1050         else {
1051                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1052                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1053         }
1054 }
1055
1056 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1057 {
1058         if (reg < rdev->rmmio_size)
1059                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1060         else {
1061                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1062                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1063         }
1064 }
1065
1066 /*
1067  * Cast helper
1068  */
1069 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1070
1071 /*
1072  * Registers read & write functions.
1073  */
1074 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1075 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1076 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1077 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1078 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1079 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1080 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1081 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1082 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1083 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1084 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1085 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1086 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1087 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1088 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1089 #define WREG32_P(reg, val, mask)                                \
1090         do {                                                    \
1091                 uint32_t tmp_ = RREG32(reg);                    \
1092                 tmp_ &= (mask);                                 \
1093                 tmp_ |= ((val) & ~(mask));                      \
1094                 WREG32(reg, tmp_);                              \
1095         } while (0)
1096 #define WREG32_PLL_P(reg, val, mask)                            \
1097         do {                                                    \
1098                 uint32_t tmp_ = RREG32_PLL(reg);                \
1099                 tmp_ &= (mask);                                 \
1100                 tmp_ |= ((val) & ~(mask));                      \
1101                 WREG32_PLL(reg, tmp_);                          \
1102         } while (0)
1103 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1104
1105 /*
1106  * Indirect registers accessor
1107  */
1108 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1109 {
1110         uint32_t r;
1111
1112         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1113         r = RREG32(RADEON_PCIE_DATA);
1114         return r;
1115 }
1116
1117 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1118 {
1119         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1120         WREG32(RADEON_PCIE_DATA, (v));
1121 }
1122
1123 void r100_pll_errata_after_index(struct radeon_device *rdev);
1124
1125
1126 /*
1127  * ASICs helpers.
1128  */
1129 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1130                             (rdev->pdev->device == 0x5969))
1131 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1132                 (rdev->family == CHIP_RV200) || \
1133                 (rdev->family == CHIP_RS100) || \
1134                 (rdev->family == CHIP_RS200) || \
1135                 (rdev->family == CHIP_RV250) || \
1136                 (rdev->family == CHIP_RV280) || \
1137                 (rdev->family == CHIP_RS300))
1138 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1139                 (rdev->family == CHIP_RV350) ||                 \
1140                 (rdev->family == CHIP_R350)  ||                 \
1141                 (rdev->family == CHIP_RV380) ||                 \
1142                 (rdev->family == CHIP_R420)  ||                 \
1143                 (rdev->family == CHIP_R423)  ||                 \
1144                 (rdev->family == CHIP_RV410) ||                 \
1145                 (rdev->family == CHIP_RS400) ||                 \
1146                 (rdev->family == CHIP_RS480))
1147 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1148 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1149 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1150 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1151
1152 /*
1153  * BIOS helpers.
1154  */
1155 #define RBIOS8(i) (rdev->bios[i])
1156 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1157 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1158
1159 int radeon_combios_init(struct radeon_device *rdev);
1160 void radeon_combios_fini(struct radeon_device *rdev);
1161 int radeon_atombios_init(struct radeon_device *rdev);
1162 void radeon_atombios_fini(struct radeon_device *rdev);
1163
1164
1165 /*
1166  * RING helpers.
1167  */
1168 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1169 {
1170 #if DRM_DEBUG_CODE
1171         if (rdev->cp.count_dw <= 0) {
1172                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1173         }
1174 #endif
1175         rdev->cp.ring[rdev->cp.wptr++] = v;
1176         rdev->cp.wptr &= rdev->cp.ptr_mask;
1177         rdev->cp.count_dw--;
1178         rdev->cp.ring_free_dw--;
1179 }
1180
1181
1182 /*
1183  * ASICs macro.
1184  */
1185 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1186 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1187 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1188 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1189 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1190 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1191 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1192 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1193 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1194 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1195 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1196 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1197 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1198 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1199 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1200 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1201 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1202 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1203 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1204 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1205 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1206 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1207 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1208 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1209 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1210 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1211 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1212 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1213 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1214 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1215 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1216 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1217 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1218 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1219 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1220 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1221 #define radeon_set_power_state(rdev) (rdev)->asic->set_power_state((rdev))
1222
1223 /* Common functions */
1224 /* AGP */
1225 extern int radeon_gpu_reset(struct radeon_device *rdev);
1226 extern void radeon_agp_disable(struct radeon_device *rdev);
1227 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1228 extern void radeon_gart_restore(struct radeon_device *rdev);
1229 extern int radeon_modeset_init(struct radeon_device *rdev);
1230 extern void radeon_modeset_fini(struct radeon_device *rdev);
1231 extern bool radeon_card_posted(struct radeon_device *rdev);
1232 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1233 extern void radeon_update_display_priority(struct radeon_device *rdev);
1234 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1235 extern int radeon_clocks_init(struct radeon_device *rdev);
1236 extern void radeon_clocks_fini(struct radeon_device *rdev);
1237 extern void radeon_scratch_init(struct radeon_device *rdev);
1238 extern void radeon_surface_init(struct radeon_device *rdev);
1239 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1240 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1241 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1242 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1243 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1244 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1245 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1246 extern int radeon_resume_kms(struct drm_device *dev);
1247 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1248
1249 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1250 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1251 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1252
1253 /* rv200,rv250,rv280 */
1254 extern void r200_set_safe_registers(struct radeon_device *rdev);
1255
1256 /* r300,r350,rv350,rv370,rv380 */
1257 extern void r300_set_reg_safe(struct radeon_device *rdev);
1258 extern void r300_mc_program(struct radeon_device *rdev);
1259 extern void r300_mc_init(struct radeon_device *rdev);
1260 extern void r300_clock_startup(struct radeon_device *rdev);
1261 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1262 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1263 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1264 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1265 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1266
1267 /* r420,r423,rv410 */
1268 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1269 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1270 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1271 extern void r420_pipes_init(struct radeon_device *rdev);
1272
1273 /* rv515 */
1274 struct rv515_mc_save {
1275         u32 d1vga_control;
1276         u32 d2vga_control;
1277         u32 vga_render_control;
1278         u32 vga_hdp_control;
1279         u32 d1crtc_control;
1280         u32 d2crtc_control;
1281 };
1282 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1283 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1284 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1285 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1286 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1287 extern void rv515_clock_startup(struct radeon_device *rdev);
1288 extern void rv515_debugfs(struct radeon_device *rdev);
1289 extern int rv515_suspend(struct radeon_device *rdev);
1290
1291 /* rs400 */
1292 extern int rs400_gart_init(struct radeon_device *rdev);
1293 extern int rs400_gart_enable(struct radeon_device *rdev);
1294 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1295 extern void rs400_gart_disable(struct radeon_device *rdev);
1296 extern void rs400_gart_fini(struct radeon_device *rdev);
1297
1298 /* rs600 */
1299 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1300 extern int rs600_irq_set(struct radeon_device *rdev);
1301 extern void rs600_irq_disable(struct radeon_device *rdev);
1302
1303 /* rs690, rs740 */
1304 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1305                                         struct drm_display_mode *mode1,
1306                                         struct drm_display_mode *mode2);
1307
1308 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1309 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1310 extern bool r600_card_posted(struct radeon_device *rdev);
1311 extern void r600_cp_stop(struct radeon_device *rdev);
1312 extern int r600_cp_start(struct radeon_device *rdev);
1313 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1314 extern int r600_cp_resume(struct radeon_device *rdev);
1315 extern void r600_cp_fini(struct radeon_device *rdev);
1316 extern int r600_count_pipe_bits(uint32_t val);
1317 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1318 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1319 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1320 extern int r600_ib_test(struct radeon_device *rdev);
1321 extern int r600_ring_test(struct radeon_device *rdev);
1322 extern void r600_wb_fini(struct radeon_device *rdev);
1323 extern int r600_wb_enable(struct radeon_device *rdev);
1324 extern void r600_wb_disable(struct radeon_device *rdev);
1325 extern void r600_scratch_init(struct radeon_device *rdev);
1326 extern int r600_blit_init(struct radeon_device *rdev);
1327 extern void r600_blit_fini(struct radeon_device *rdev);
1328 extern int r600_init_microcode(struct radeon_device *rdev);
1329 extern int r600_asic_reset(struct radeon_device *rdev);
1330 /* r600 irq */
1331 extern int r600_irq_init(struct radeon_device *rdev);
1332 extern void r600_irq_fini(struct radeon_device *rdev);
1333 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1334 extern int r600_irq_set(struct radeon_device *rdev);
1335 extern void r600_irq_suspend(struct radeon_device *rdev);
1336 extern void r600_disable_interrupts(struct radeon_device *rdev);
1337 extern void r600_rlc_stop(struct radeon_device *rdev);
1338 /* r600 audio */
1339 extern int r600_audio_init(struct radeon_device *rdev);
1340 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1341 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1342 extern int r600_audio_channels(struct radeon_device *rdev);
1343 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1344 extern int r600_audio_rate(struct radeon_device *rdev);
1345 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1346 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1347 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1348 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1349 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1350 extern void r600_audio_fini(struct radeon_device *rdev);
1351 extern void r600_hdmi_init(struct drm_encoder *encoder);
1352 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1353 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1354 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1355 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1356 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1357
1358 extern void r700_cp_stop(struct radeon_device *rdev);
1359 extern void r700_cp_fini(struct radeon_device *rdev);
1360 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1361 extern int evergreen_irq_set(struct radeon_device *rdev);
1362
1363 /* evergreen */
1364 struct evergreen_mc_save {
1365         u32 vga_control[6];
1366         u32 vga_render_control;
1367         u32 vga_hdp_control;
1368         u32 crtc_control[6];
1369 };
1370
1371 #include "radeon_object.h"
1372
1373 #endif