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[PATCH] inode-diet: Eliminate i_blksize from the inode structure
[linux-2.6/libata-dev.git] / drivers / infiniband / hw / ipath / ipath_iba6110.c
blob5c9b509e40e449c24645c72b1418057a5b0d9c00
1 /*
2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 /*
35 * This file contains all of the code that is specific to the InfiniPath
36 * HT chip.
37 */
38
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41
42 #include "ipath_kernel.h"
43 #include "ipath_registers.h"
44
45 /*
46 * This lists the InfiniPath registers, in the actual chip layout.
47 * This structure should never be directly accessed.
48 *
49 * The names are in InterCap form because they're taken straight from
50 * the chip specification. Since they're only used in this file, they
51 * don't pollute the rest of the source.
52 */
53
54 struct _infinipath_do_not_use_kernel_regs {
55 unsigned long long Revision;
56 unsigned long long Control;
57 unsigned long long PageAlign;
58 unsigned long long PortCnt;
59 unsigned long long DebugPortSelect;
60 unsigned long long DebugPort;
61 unsigned long long SendRegBase;
62 unsigned long long UserRegBase;
63 unsigned long long CounterRegBase;
64 unsigned long long Scratch;
65 unsigned long long ReservedMisc1;
66 unsigned long long InterruptConfig;
67 unsigned long long IntBlocked;
68 unsigned long long IntMask;
69 unsigned long long IntStatus;
70 unsigned long long IntClear;
71 unsigned long long ErrorMask;
72 unsigned long long ErrorStatus;
73 unsigned long long ErrorClear;
74 unsigned long long HwErrMask;
75 unsigned long long HwErrStatus;
76 unsigned long long HwErrClear;
77 unsigned long long HwDiagCtrl;
78 unsigned long long MDIO;
79 unsigned long long IBCStatus;
80 unsigned long long IBCCtrl;
81 unsigned long long ExtStatus;
82 unsigned long long ExtCtrl;
83 unsigned long long GPIOOut;
84 unsigned long long GPIOMask;
85 unsigned long long GPIOStatus;
86 unsigned long long GPIOClear;
87 unsigned long long RcvCtrl;
88 unsigned long long RcvBTHQP;
89 unsigned long long RcvHdrSize;
90 unsigned long long RcvHdrCnt;
91 unsigned long long RcvHdrEntSize;
92 unsigned long long RcvTIDBase;
93 unsigned long long RcvTIDCnt;
94 unsigned long long RcvEgrBase;
95 unsigned long long RcvEgrCnt;
96 unsigned long long RcvBufBase;
97 unsigned long long RcvBufSize;
98 unsigned long long RxIntMemBase;
99 unsigned long long RxIntMemSize;
100 unsigned long long RcvPartitionKey;
101 unsigned long long ReservedRcv[10];
102 unsigned long long SendCtrl;
103 unsigned long long SendPIOBufBase;
104 unsigned long long SendPIOSize;
105 unsigned long long SendPIOBufCnt;
106 unsigned long long SendPIOAvailAddr;
107 unsigned long long TxIntMemBase;
108 unsigned long long TxIntMemSize;
109 unsigned long long ReservedSend[9];
110 unsigned long long SendBufferError;
111 unsigned long long SendBufferErrorCONT1;
112 unsigned long long SendBufferErrorCONT2;
113 unsigned long long SendBufferErrorCONT3;
114 unsigned long long ReservedSBE[4];
115 unsigned long long RcvHdrAddr0;
116 unsigned long long RcvHdrAddr1;
117 unsigned long long RcvHdrAddr2;
118 unsigned long long RcvHdrAddr3;
119 unsigned long long RcvHdrAddr4;
120 unsigned long long RcvHdrAddr5;
121 unsigned long long RcvHdrAddr6;
122 unsigned long long RcvHdrAddr7;
123 unsigned long long RcvHdrAddr8;
124 unsigned long long ReservedRHA[7];
125 unsigned long long RcvHdrTailAddr0;
126 unsigned long long RcvHdrTailAddr1;
127 unsigned long long RcvHdrTailAddr2;
128 unsigned long long RcvHdrTailAddr3;
129 unsigned long long RcvHdrTailAddr4;
130 unsigned long long RcvHdrTailAddr5;
131 unsigned long long RcvHdrTailAddr6;
132 unsigned long long RcvHdrTailAddr7;
133 unsigned long long RcvHdrTailAddr8;
134 unsigned long long ReservedRHTA[7];
135 unsigned long long Sync; /* Software only */
136 unsigned long long Dump; /* Software only */
137 unsigned long long SimVer; /* Software only */
138 unsigned long long ReservedSW[5];
139 unsigned long long SerdesConfig0;
140 unsigned long long SerdesConfig1;
141 unsigned long long SerdesStatus;
142 unsigned long long XGXSConfig;
143 unsigned long long ReservedSW2[4];
144 };
145
146 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
147 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
148 #define IPATH_CREG_OFFSET(field) (offsetof( \
149 struct infinipath_counters, field) / sizeof(u64))
150
151 static const struct ipath_kregs ipath_ht_kregs = {
152 .kr_control = IPATH_KREG_OFFSET(Control),
153 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
154 .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
155 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
156 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
157 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
158 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
159 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
160 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
161 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
162 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
163 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
164 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
165 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
166 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
167 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
168 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
169 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
170 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
171 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
172 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
173 .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
174 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
175 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
176 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
177 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
178 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
179 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
180 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
181 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
182 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
183 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
184 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
185 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
186 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
187 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
188 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
189 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
190 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
191 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
192 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
193 .kr_revision = IPATH_KREG_OFFSET(Revision),
194 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
195 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
196 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
197 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
198 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
199 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
200 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
201 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
202 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
203 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
204 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
205 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
206 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
207 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
208 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
209 /*
210 * These should not be used directly via ipath_read_kreg64(),
211 * use them with ipath_read_kreg64_port(),
212 */
213 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
214 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
215 };
216
217 static const struct ipath_cregs ipath_ht_cregs = {
218 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
219 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
220 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
221 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
222 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
223 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
224 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
225 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
226 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
227 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
228 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
229 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
230 /* calc from Reg_CounterRegBase + offset */
231 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
232 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
233 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
234 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
235 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
236 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
237 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
238 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
239 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
240 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
241 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
242 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
243 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
244 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
245 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
246 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
247 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
248 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
249 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
250 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
251 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
252 };
253
254 /* kr_intstatus, kr_intclear, kr_intmask bits */
255 #define INFINIPATH_I_RCVURG_MASK 0x1FF
256 #define INFINIPATH_I_RCVAVAIL_MASK 0x1FF
257
258 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
259 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
260 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
261 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR 0x0000000000800000ULL
262 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR 0x0000000001000000ULL
263 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR 0x0000000002000000ULL
264 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR 0x0000000004000000ULL
265 #define INFINIPATH_HWE_HTCMISCERR4 0x0000000008000000ULL
266 #define INFINIPATH_HWE_HTCMISCERR5 0x0000000010000000ULL
267 #define INFINIPATH_HWE_HTCMISCERR6 0x0000000020000000ULL
268 #define INFINIPATH_HWE_HTCMISCERR7 0x0000000040000000ULL
269 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR 0x0000000080000000ULL
270 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
271 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR 0x0000000200000000ULL
272 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
273 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
274 #define INFINIPATH_HWE_HTBPLL_FBSLIP 0x0200000000000000ULL
275 #define INFINIPATH_HWE_HTBPLL_RFSLIP 0x0400000000000000ULL
276 #define INFINIPATH_HWE_HTAPLL_FBSLIP 0x0800000000000000ULL
277 #define INFINIPATH_HWE_HTAPLL_RFSLIP 0x1000000000000000ULL
278 #define INFINIPATH_HWE_SERDESPLLFAILED 0x2000000000000000ULL
279
280 /* kr_extstatus bits */
281 #define INFINIPATH_EXTS_FREQSEL 0x2
282 #define INFINIPATH_EXTS_SERDESSEL 0x4
283 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
284 #define INFINIPATH_EXTS_MEMBIST_CORRECT 0x0000000000008000
285
286 /*
287 * masks and bits that are different in different chips, or present only
288 * in one
289 */
290 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
291 INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
292 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
293 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
294
295 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
296 INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
297 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
298 INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
299 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
300 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
301 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
302 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
303
304 #define _IPATH_GPIO_SDA_NUM 1
305 #define _IPATH_GPIO_SCL_NUM 0
306
307 #define IPATH_GPIO_SDA \
308 (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
309 #define IPATH_GPIO_SCL \
310 (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
311
312 /* keep the code below somewhat more readonable; not used elsewhere */
313 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
314 infinipath_hwe_htclnkabyte1crcerr)
315 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr | \
316 infinipath_hwe_htclnkbbyte1crcerr)
317 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
318 infinipath_hwe_htclnkbbyte0crcerr)
319 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr | \
320 infinipath_hwe_htclnkbbyte1crcerr)
321
322 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
323 char *msg, size_t msgl)
324 {
325 char bitsmsg[64];
326 ipath_err_t crcbits = hwerrs &
327 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
328 /* don't check if 8bit HT */
329 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
330 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
331 /* don't check if 8bit HT */
332 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
333 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
334 /*
335 * we'll want to ignore link errors on link that is
336 * not in use, if any. For now, complain about both
337 */
338 if (crcbits) {
339 u16 ctrl0, ctrl1;
340 snprintf(bitsmsg, sizeof bitsmsg,
341 "[HT%s lane %s CRC (%llx); ignore till reload]",
342 !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
343 "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
344 ? "1 (B)" : "0+1 (A+B)"),
345 !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
346 : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
347 "0+1"), (unsigned long long) crcbits);
348 strlcat(msg, bitsmsg, msgl);
349
350 /*
351 * print extra info for debugging. slave/primary
352 * config word 4, 8 (link control 0, 1)
353 */
354
355 if (pci_read_config_word(dd->pcidev,
356 dd->ipath_ht_slave_off + 0x4,
357 &ctrl0))
358 dev_info(&dd->pcidev->dev, "Couldn't read "
359 "linkctrl0 of slave/primary "
360 "config block\n");
361 else if (!(ctrl0 & 1 << 6))
362 /* not if EOC bit set */
363 ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
364 ((ctrl0 >> 8) & 7) ? " CRC" : "",
365 ((ctrl0 >> 4) & 1) ? "linkfail" :
366 "");
367 if (pci_read_config_word(dd->pcidev,
368 dd->ipath_ht_slave_off + 0x8,
369 &ctrl1))
370 dev_info(&dd->pcidev->dev, "Couldn't read "
371 "linkctrl1 of slave/primary "
372 "config block\n");
373 else if (!(ctrl1 & 1 << 6))
374 /* not if EOC bit set */
375 ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
376 ((ctrl1 >> 8) & 7) ? " CRC" : "",
377 ((ctrl1 >> 4) & 1) ? "linkfail" :
378 "");
379
380 /* disable until driver reloaded */
381 dd->ipath_hwerrmask &= ~crcbits;
382 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
383 dd->ipath_hwerrmask);
384 ipath_dbg("HT crc errs: %s\n", msg);
385 } else
386 ipath_dbg("ignoring HT crc errors 0x%llx, "
387 "not in use\n", (unsigned long long)
388 (hwerrs & (_IPATH_HTLINK0_CRCBITS |
389 _IPATH_HTLINK1_CRCBITS)));
390 }
391
392 /**
393 * ipath_ht_handle_hwerrors - display hardware errors
394 * @dd: the infinipath device
395 * @msg: the output buffer
396 * @msgl: the size of the output buffer
397 *
398 * Use same msg buffer as regular errors to avoid
399 * excessive stack use. Most hardware errors are catastrophic, but for
400 * right now, we'll print them and continue.
401 * We reuse the same message buffer as ipath_handle_errors() to avoid
402 * excessive stack usage.
403 */
404 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
405 size_t msgl)
406 {
407 ipath_err_t hwerrs;
408 u32 bits, ctrl;
409 int isfatal = 0;
410 char bitsmsg[64];
411
412 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
413
414 if (!hwerrs) {
415 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
416 /*
417 * better than printing cofusing messages
418 * This seems to be related to clearing the crc error, or
419 * the pll error during init.
420 */
421 goto bail;
422 } else if (hwerrs == -1LL) {
423 ipath_dev_err(dd, "Read of hardware error status failed "
424 "(all bits set); ignoring\n");
425 goto bail;
426 }
427 ipath_stats.sps_hwerrs++;
428
429 /* Always clear the error status register, except MEMBISTFAIL,
430 * regardless of whether we continue or stop using the chip.
431 * We want that set so we know it failed, even across driver reload.
432 * We'll still ignore it in the hwerrmask. We do this partly for
433 * diagnostics, but also for support */
434 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
435 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
436
437 hwerrs &= dd->ipath_hwerrmask;
438
439 /*
440 * make sure we get this much out, unless told to be quiet,
441 * or it's occurred within the last 5 seconds
442 */
443 if ((hwerrs & ~dd->ipath_lasthwerror) ||
444 (ipath_debug & __IPATH_VERBDBG))
445 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
446 "(cleared)\n", (unsigned long long) hwerrs);
447 dd->ipath_lasthwerror |= hwerrs;
448
449 if (hwerrs & ~infinipath_hwe_bitsextant)
450 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
451 "%llx set\n", (unsigned long long)
452 (hwerrs & ~infinipath_hwe_bitsextant));
453
454 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
455 if (ctrl & INFINIPATH_C_FREEZEMODE) {
456 if (hwerrs) {
457 /*
458 * if any set that we aren't ignoring; only
459 * make the complaint once, in case it's stuck
460 * or recurring, and we get here multiple
461 * times.
462 */
463 if (dd->ipath_flags & IPATH_INITTED) {
464 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
465 "mode), no longer usable, SN %.16s\n",
466 dd->ipath_serial);
467 isfatal = 1;
468 }
469 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
470 /* mark as having had error */
471 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
472 /*
473 * mark as not usable, at a minimum until driver
474 * is reloaded, probably until reboot, since no
475 * other reset is possible.
476 */
477 dd->ipath_flags &= ~IPATH_INITTED;
478 } else {
479 ipath_dbg("Clearing freezemode on ignored hardware "
480 "error\n");
481 ctrl &= ~INFINIPATH_C_FREEZEMODE;
482 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
483 ctrl);
484 }
485 }
486
487 *msg = '\0';
488
489 /*
490 * may someday want to decode into which bits are which
491 * functional area for parity errors, etc.
492 */
493 if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
494 << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
495 bits = (u32) ((hwerrs >>
496 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
497 INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
498 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
499 bits);
500 strlcat(msg, bitsmsg, msgl);
501 }
502 if (hwerrs & (INFINIPATH_HWE_RXEMEMPARITYERR_MASK
503 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)) {
504 bits = (u32) ((hwerrs >>
505 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) &
506 INFINIPATH_HWE_RXEMEMPARITYERR_MASK);
507 snprintf(bitsmsg, sizeof bitsmsg, "[RXE Parity Errs %x] ",
508 bits);
509 strlcat(msg, bitsmsg, msgl);
510 }
511 if (hwerrs & (INFINIPATH_HWE_TXEMEMPARITYERR_MASK
512 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)) {
513 bits = (u32) ((hwerrs >>
514 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) &
515 INFINIPATH_HWE_TXEMEMPARITYERR_MASK);
516 snprintf(bitsmsg, sizeof bitsmsg, "[TXE Parity Errs %x] ",
517 bits);
518 strlcat(msg, bitsmsg, msgl);
519 }
520 if (hwerrs & INFINIPATH_HWE_IBCBUSTOSPCPARITYERR)
521 strlcat(msg, "[IB2IPATH Parity]", msgl);
522 if (hwerrs & INFINIPATH_HWE_IBCBUSFRSPCPARITYERR)
523 strlcat(msg, "[IPATH2IB Parity]", msgl);
524 if (hwerrs & INFINIPATH_HWE_HTCBUSIREQPARITYERR)
525 strlcat(msg, "[HTC Ireq Parity]", msgl);
526 if (hwerrs & INFINIPATH_HWE_HTCBUSTREQPARITYERR)
527 strlcat(msg, "[HTC Treq Parity]", msgl);
528 if (hwerrs & INFINIPATH_HWE_HTCBUSTRESPPARITYERR)
529 strlcat(msg, "[HTC Tresp Parity]", msgl);
530
531 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
532 hwerr_crcbits(dd, hwerrs, msg, msgl);
533
534 if (hwerrs & INFINIPATH_HWE_HTCMISCERR5)
535 strlcat(msg, "[HT core Misc5]", msgl);
536 if (hwerrs & INFINIPATH_HWE_HTCMISCERR6)
537 strlcat(msg, "[HT core Misc6]", msgl);
538 if (hwerrs & INFINIPATH_HWE_HTCMISCERR7)
539 strlcat(msg, "[HT core Misc7]", msgl);
540 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
541 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
542 msgl);
543 /* ignore from now on, so disable until driver reloaded */
544 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
545 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
546 dd->ipath_hwerrmask);
547 }
548 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
549 INFINIPATH_HWE_COREPLL_RFSLIP | \
550 INFINIPATH_HWE_HTBPLL_FBSLIP | \
551 INFINIPATH_HWE_HTBPLL_RFSLIP | \
552 INFINIPATH_HWE_HTAPLL_FBSLIP | \
553 INFINIPATH_HWE_HTAPLL_RFSLIP)
554
555 if (hwerrs & _IPATH_PLL_FAIL) {
556 snprintf(bitsmsg, sizeof bitsmsg,
557 "[PLL failed (%llx), InfiniPath hardware unusable]",
558 (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
559 strlcat(msg, bitsmsg, msgl);
560 /* ignore from now on, so disable until driver reloaded */
561 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
562 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
563 dd->ipath_hwerrmask);
564 }
565
566 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
567 /*
568 * If it occurs, it is left masked since the eternal
569 * interface is unused
570 */
571 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
572 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
573 dd->ipath_hwerrmask);
574 }
575
576 if (hwerrs & INFINIPATH_HWE_RXDSYNCMEMPARITYERR)
577 strlcat(msg, "[Rx Dsync]", msgl);
578 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED)
579 strlcat(msg, "[SerDes PLL]", msgl);
580
581 ipath_dev_err(dd, "%s hardware error\n", msg);
582 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
583 /*
584 * for status file; if no trailing brace is copied,
585 * we'll know it was truncated.
586 */
587 snprintf(dd->ipath_freezemsg,
588 dd->ipath_freezelen, "{%s}", msg);
589
590 bail:;
591 }
592
593 /**
594 * ipath_ht_boardname - fill in the board name
595 * @dd: the infinipath device
596 * @name: the output buffer
597 * @namelen: the size of the output buffer
598 *
599 * fill in the board name, based on the board revision register
600 */
601 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
602 size_t namelen)
603 {
604 char *n = NULL;
605 u8 boardrev = dd->ipath_boardrev;
606 int ret;
607
608 switch (boardrev) {
609 case 4: /* Ponderosa is one of the bringup boards */
610 n = "Ponderosa";
611 break;
612 case 5:
613 /*
614 * original production board; two production levels, with
615 * different serial number ranges. See ipath_ht_early_init() for
616 * case where we enable IPATH_GPIO_INTR for later serial # range.
617 */
618 n = "InfiniPath_QHT7040";
619 break;
620 case 6:
621 n = "OEM_Board_3";
622 break;
623 case 7:
624 /* small form factor production board */
625 n = "InfiniPath_QHT7140";
626 break;
627 case 8:
628 n = "LS/X-1";
629 break;
630 case 9: /* Comstock bringup test board */
631 n = "Comstock";
632 break;
633 case 10:
634 n = "OEM_Board_2";
635 break;
636 case 11:
637 n = "InfiniPath_HT-470"; /* obsoleted */
638 break;
639 case 12:
640 n = "OEM_Board_4";
641 break;
642 default: /* don't know, just print the number */
643 ipath_dev_err(dd, "Don't yet know about board "
644 "with ID %u\n", boardrev);
645 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
646 boardrev);
647 break;
648 }
649 if (n)
650 snprintf(name, namelen, "%s", n);
651
652 if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 || dd->ipath_minrev > 3)) {
653 /*
654 * This version of the driver only supports Rev 3.2 and 3.3
655 */
656 ipath_dev_err(dd,
657 "Unsupported InfiniPath hardware revision %u.%u!\n",
658 dd->ipath_majrev, dd->ipath_minrev);
659 ret = 1;
660 goto bail;
661 }
662 /*
663 * pkt/word counters are 32 bit, and therefore wrap fast enough
664 * that we snapshot them from a timer, and maintain 64 bit shadow
665 * copies
666 */
667 dd->ipath_flags |= IPATH_32BITCOUNTERS;
668 if (dd->ipath_htspeed != 800)
669 ipath_dev_err(dd,
670 "Incorrectly configured for HT @ %uMHz\n",
671 dd->ipath_htspeed);
672 if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
673 dd->ipath_boardrev == 6)
674 dd->ipath_flags |= IPATH_GPIO_INTR;
675 else
676 dd->ipath_flags |= IPATH_POLL_RX_INTR;
677 if (dd->ipath_boardrev == 8) { /* LS/X-1 */
678 u64 val;
679 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
680 if (val & INFINIPATH_EXTS_SERDESSEL) {
681 /*
682 * hardware disabled
683 *
684 * This means that the chip is hardware disabled,
685 * and will not be able to bring up the link,
686 * in any case. We special case this and abort
687 * early, to avoid later messages. We also set
688 * the DISABLED status bit
689 */
690 ipath_dbg("Unit %u is hardware-disabled\n",
691 dd->ipath_unit);
692 *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
693 /* this value is handled differently */
694 ret = 2;
695 goto bail;
696 }
697 }
698 ret = 0;
699
700 bail:
701 return ret;
702 }
703
704 static void ipath_check_htlink(struct ipath_devdata *dd)
705 {
706 u8 linkerr, link_off, i;
707
708 for (i = 0; i < 2; i++) {
709 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
710 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
711 dev_info(&dd->pcidev->dev, "Couldn't read "
712 "linkerror%d of HT slave/primary block\n",
713 i);
714 else if (linkerr & 0xf0) {
715 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
716 "clearing\n", linkerr >> 4, i);
717 /*
718 * writing the linkerr bits that are set should
719 * clear them
720 */
721 if (pci_write_config_byte(dd->pcidev, link_off,
722 linkerr))
723 ipath_dbg("Failed write to clear HT "
724 "linkerror%d\n", i);
725 if (pci_read_config_byte(dd->pcidev, link_off,
726 &linkerr))
727 dev_info(&dd->pcidev->dev,
728 "Couldn't reread linkerror%d of "
729 "HT slave/primary block\n", i);
730 else if (linkerr & 0xf0)
731 dev_info(&dd->pcidev->dev,
732 "HT linkerror%d bits 0x%x "
733 "couldn't be cleared\n",
734 i, linkerr >> 4);
735 }
736 }
737 }
738
739 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
740 {
741 ipath_dbg("No reset possible for this InfiniPath hardware\n");
742 return 0;
743 }
744
745 #define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */
746 #define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */
747
748 /*
749 * Bits 13-15 of command==0 is slave/primary block. Clear any HT CRC
750 * errors. We only bother to do this at load time, because it's OK if
751 * it happened before we were loaded (first time after boot/reset),
752 * but any time after that, it's fatal anyway. Also need to not check
753 * for for upper byte errors if we are in 8 bit mode, so figure out
754 * our width. For now, at least, also complain if it's 8 bit.
755 */
756 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
757 int pos, u8 cap_type)
758 {
759 u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
760 u16 linkctrl = 0;
761 int i;
762
763 dd->ipath_ht_slave_off = pos;
764 /* command word, master_host bit */
765 /* master host || slave */
766 if ((cap_type >> 2) & 1)
767 link_a_b_off = 4;
768 else
769 link_a_b_off = 0;
770 ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
771 link_a_b_off ? 1 : 0,
772 link_a_b_off ? 'B' : 'A');
773
774 link_a_b_off += pos;
775
776 /*
777 * check both link control registers; clear both HT CRC sets if
778 * necessary.
779 */
780 for (i = 0; i < 2; i++) {
781 link_off = pos + i * 4 + 0x4;
782 if (pci_read_config_word(pdev, link_off, &linkctrl))
783 ipath_dev_err(dd, "Couldn't read HT link control%d "
784 "register\n", i);
785 else if (linkctrl & (0xf << 8)) {
786 ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
787 "bits %x\n", i, linkctrl & (0xf << 8));
788 /*
789 * now write them back to clear the error.
790 */
791 pci_write_config_byte(pdev, link_off,
792 linkctrl & (0xf << 8));
793 }
794 }
795
796 /*
797 * As with HT CRC bits, same for protocol errors that might occur
798 * during boot.
799 */
800 for (i = 0; i < 2; i++) {
801 link_off = pos + i * 4 + 0xd;
802 if (pci_read_config_byte(pdev, link_off, &linkerr))
803 dev_info(&pdev->dev, "Couldn't read linkerror%d "
804 "of HT slave/primary block\n", i);
805 else if (linkerr & 0xf0) {
806 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
807 "clearing\n", linkerr >> 4, i);
808 /*
809 * writing the linkerr bits that are set will clear
810 * them
811 */
812 if (pci_write_config_byte
813 (pdev, link_off, linkerr))
814 ipath_dbg("Failed write to clear HT "
815 "linkerror%d\n", i);
816 if (pci_read_config_byte(pdev, link_off, &linkerr))
817 dev_info(&pdev->dev, "Couldn't reread "
818 "linkerror%d of HT slave/primary "
819 "block\n", i);
820 else if (linkerr & 0xf0)
821 dev_info(&pdev->dev, "HT linkerror%d bits "
822 "0x%x couldn't be cleared\n",
823 i, linkerr >> 4);
824 }
825 }
826
827 /*
828 * this is just for our link to the host, not devices connected
829 * through tunnel.
830 */
831
832 if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
833 ipath_dev_err(dd, "Couldn't read HT link width "
834 "config register\n");
835 else {
836 u32 width;
837 switch (linkwidth & 7) {
838 case 5:
839 width = 4;
840 break;
841 case 4:
842 width = 2;
843 break;
844 case 3:
845 width = 32;
846 break;
847 case 1:
848 width = 16;
849 break;
850 case 0:
851 default: /* if wrong, assume 8 bit */
852 width = 8;
853 break;
854 }
855
856 dd->ipath_htwidth = width;
857
858 if (linkwidth != 0x11) {
859 ipath_dev_err(dd, "Not configured for 16 bit HT "
860 "(%x)\n", linkwidth);
861 if (!(linkwidth & 0xf)) {
862 ipath_dbg("Will ignore HT lane1 errors\n");
863 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
864 }
865 }
866 }
867
868 /*
869 * this is just for our link to the host, not devices connected
870 * through tunnel.
871 */
872 if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
873 ipath_dev_err(dd, "Couldn't read HT link frequency "
874 "config register\n");
875 else {
876 u32 speed;
877 switch (linkwidth & 0xf) {
878 case 6:
879 speed = 1000;
880 break;
881 case 5:
882 speed = 800;
883 break;
884 case 4:
885 speed = 600;
886 break;
887 case 3:
888 speed = 500;
889 break;
890 case 2:
891 speed = 400;
892 break;
893 case 1:
894 speed = 300;
895 break;
896 default:
897 /*
898 * assume reserved and vendor-specific are 200...
899 */
900 case 0:
901 speed = 200;
902 break;
903 }
904 dd->ipath_htspeed = speed;
905 }
906 }
907
908 static int set_int_handler(struct ipath_devdata *dd, struct pci_dev *pdev,
909 int pos)
910 {
911 u32 int_handler_addr_lower;
912 u32 int_handler_addr_upper;
913 u64 ihandler;
914 u32 intvec;
915
916 /* use indirection register to get the intr handler */
917 pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x10);
918 pci_read_config_dword(pdev, pos + 4, &int_handler_addr_lower);
919 pci_write_config_byte(pdev, pos + HT_INTR_REG_INDEX, 0x11);
920 pci_read_config_dword(pdev, pos + 4, &int_handler_addr_upper);
921
922 ihandler = (u64) int_handler_addr_lower |
923 ((u64) int_handler_addr_upper << 32);
924
925 /*
926 * kernels with CONFIG_PCI_MSI set the vector in the irq field of
927 * struct pci_device, so we use that to program the internal
928 * interrupt register (not config space) with that value. The BIOS
929 * must still have done the basic MSI setup.
930 */
931 intvec = pdev->irq;
932 /*
933 * clear any vector bits there; normally not set but we'll overload
934 * this for some debug purposes (setting the HTC debug register
935 * value from software, rather than GPIOs), so it might be set on a
936 * driver reload.
937 */
938 ihandler &= ~0xff0000;
939 /* x86 vector goes in intrinfo[23:16] */
940 ihandler |= intvec << 16;
941 ipath_cdbg(VERBOSE, "ihandler lower %x, upper %x, intvec %x, "
942 "interruptconfig %llx\n", int_handler_addr_lower,
943 int_handler_addr_upper, intvec,
944 (unsigned long long) ihandler);
945
946 /* can't program yet, so save for interrupt setup */
947 dd->ipath_intconfig = ihandler;
948 /* keep going, so we find link control stuff also */
949
950 return ihandler != 0;
951 }
952
953 /**
954 * ipath_setup_ht_config - setup the interruptconfig register
955 * @dd: the infinipath device
956 * @pdev: the PCI device
957 *
958 * setup the interruptconfig register from the HT config info.
959 * Also clear CRC errors in HT linkcontrol, if necessary.
960 * This is done only for the real hardware. It is done before
961 * chip address space is initted, so can't touch infinipath registers
962 */
963 static int ipath_setup_ht_config(struct ipath_devdata *dd,
964 struct pci_dev *pdev)
965 {
966 int pos, ret = 0;
967 int ihandler = 0;
968
969 /*
970 * Read the capability info to find the interrupt info, and also
971 * handle clearing CRC errors in linkctrl register if necessary. We
972 * do this early, before we ever enable errors or hardware errors,
973 * mostly to avoid causing the chip to enter freeze mode.
974 */
975 pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
976 if (!pos) {
977 ipath_dev_err(dd, "Couldn't find HyperTransport "
978 "capability; no interrupts\n");
979 ret = -ENODEV;
980 goto bail;
981 }
982 do {
983 u8 cap_type;
984
985 /* the HT capability type byte is 3 bytes after the
986 * capability byte.
987 */
988 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
989 dev_info(&pdev->dev, "Couldn't read config "
990 "command @ %d\n", pos);
991 continue;
992 }
993 if (!(cap_type & 0xE0))
994 slave_or_pri_blk(dd, pdev, pos, cap_type);
995 else if (cap_type == HT_INTR_DISC_CONFIG)
996 ihandler = set_int_handler(dd, pdev, pos);
997 } while ((pos = pci_find_next_capability(pdev, pos,
998 PCI_CAP_ID_HT)));
999
1000 if (!ihandler) {
1001 ipath_dev_err(dd, "Couldn't find interrupt handler in "
1002 "config space\n");
1003 ret = -ENODEV;
1004 }
1005
1006 bail:
1007 return ret;
1008 }
1009
1010 /**
1011 * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1012 * @dd: the infinipath device
1013 *
1014 * Called during driver unload.
1015 * This is currently a nop for the HT chip, not for all chips
1016 */
1017 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1018 {
1019 }
1020
1021 /**
1022 * ipath_setup_ht_setextled - set the state of the two external LEDs
1023 * @dd: the infinipath device
1024 * @lst: the L state
1025 * @ltst: the LT state
1026 *
1027 * Set the state of the two external LEDs, to indicate physical and
1028 * logical state of IB link. For this chip (at least with recommended
1029 * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1030 * (logical state)
1031 *
1032 * Note: We try to match the Mellanox HCA LED behavior as best
1033 * we can. Green indicates physical link state is OK (something is
1034 * plugged in, and we can train).
1035 * Amber indicates the link is logically up (ACTIVE).
1036 * Mellanox further blinks the amber LED to indicate data packet
1037 * activity, but we have no hardware support for that, so it would
1038 * require waking up every 10-20 msecs and checking the counters
1039 * on the chip, and then turning the LED off if appropriate. That's
1040 * visible overhead, so not something we will do.
1041 *
1042 */
1043 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1044 u64 lst, u64 ltst)
1045 {
1046 u64 extctl;
1047
1048 /* the diags use the LED to indicate diag info, so we leave
1049 * the external LED alone when the diags are running */
1050 if (ipath_diag_inuse)
1051 return;
1052
1053 /*
1054 * start by setting both LED control bits to off, then turn
1055 * on the appropriate bit(s).
1056 */
1057 if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1058 /*
1059 * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1060 * is inverted, because it is normally used to indicate
1061 * a hardware fault at reset, if there were errors
1062 */
1063 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1064 | INFINIPATH_EXTC_LEDGBLERR_OFF;
1065 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1066 extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1067 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1068 extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1069 }
1070 else {
1071 extctl = dd->ipath_extctrl &
1072 ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1073 INFINIPATH_EXTC_LED2PRIPORT_ON);
1074 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1075 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1076 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1077 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1078 }
1079 dd->ipath_extctrl = extctl;
1080 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1081 }
1082
1083 static void ipath_init_ht_variables(void)
1084 {
1085 ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1086 ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1087 ipath_gpio_sda = IPATH_GPIO_SDA;
1088 ipath_gpio_scl = IPATH_GPIO_SCL;
1089
1090 infinipath_i_bitsextant =
1091 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1092 (INFINIPATH_I_RCVAVAIL_MASK <<
1093 INFINIPATH_I_RCVAVAIL_SHIFT) |
1094 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1095 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1096
1097 infinipath_e_bitsextant =
1098 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1099 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1100 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1101 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1102 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1103 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1104 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1105 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1106 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1107 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1108 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1109 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1110 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1111 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1112 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1113 INFINIPATH_E_HARDWARE;
1114
1115 infinipath_hwe_bitsextant =
1116 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1117 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1118 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1119 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1120 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1121 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1122 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1123 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1124 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1125 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1126 INFINIPATH_HWE_HTCMISCERR4 |
1127 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1128 INFINIPATH_HWE_HTCMISCERR7 |
1129 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1130 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1131 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1132 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1133 INFINIPATH_HWE_MEMBISTFAILED |
1134 INFINIPATH_HWE_COREPLL_FBSLIP |
1135 INFINIPATH_HWE_COREPLL_RFSLIP |
1136 INFINIPATH_HWE_HTBPLL_FBSLIP |
1137 INFINIPATH_HWE_HTBPLL_RFSLIP |
1138 INFINIPATH_HWE_HTAPLL_FBSLIP |
1139 INFINIPATH_HWE_HTAPLL_RFSLIP |
1140 INFINIPATH_HWE_SERDESPLLFAILED |
1141 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1142 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1143
1144 infinipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1145 infinipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1146 }
1147
1148 /**
1149 * ipath_ht_init_hwerrors - enable hardware errors
1150 * @dd: the infinipath device
1151 *
1152 * now that we have finished initializing everything that might reasonably
1153 * cause a hardware error, and cleared those errors bits as they occur,
1154 * we can enable hardware errors in the mask (potentially enabling
1155 * freeze mode), and enable hardware errors as errors (along with
1156 * everything else) in errormask
1157 */
1158 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1159 {
1160 ipath_err_t val;
1161 u64 extsval;
1162
1163 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1164
1165 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1166 ipath_dev_err(dd, "MemBIST did not complete!\n");
1167
1168 ipath_check_htlink(dd);
1169
1170 /* barring bugs, all hwerrors become interrupts, which can */
1171 val = -1LL;
1172 /* don't look at crc lane1 if 8 bit */
1173 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1174 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1175 /* don't look at crc lane1 if 8 bit */
1176 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1177 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1178
1179 /*
1180 * disable RXDSYNCMEMPARITY because external serdes is unused,
1181 * and therefore the logic will never be used or initialized,
1182 * and uninitialized state will normally result in this error
1183 * being asserted. Similarly for the external serdess pll
1184 * lock signal.
1185 */
1186 val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1187 INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1188
1189 /*
1190 * Disable MISCERR4 because of an inversion in the HT core
1191 * logic checking for errors that cause this bit to be set.
1192 * The errata can also cause the protocol error bit to be set
1193 * in the HT config space linkerror register(s).
1194 */
1195 val &= ~INFINIPATH_HWE_HTCMISCERR4;
1196
1197 /*
1198 * PLL ignored because MDIO interface has a logic problem
1199 * for reads, on Comstock and Ponderosa. BRINGUP
1200 */
1201 if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1202 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1203 dd->ipath_hwerrmask = val;
1204 }
1205
1206 /**
1207 * ipath_ht_bringup_serdes - bring up the serdes
1208 * @dd: the infinipath device
1209 */
1210 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1211 {
1212 u64 val, config1;
1213 int ret = 0, change = 0;
1214
1215 ipath_dbg("Trying to bringup serdes\n");
1216
1217 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1218 INFINIPATH_HWE_SERDESPLLFAILED)
1219 {
1220 ipath_dbg("At start, serdes PLL failed bit set in "
1221 "hwerrstatus, clearing and continuing\n");
1222 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1223 INFINIPATH_HWE_SERDESPLLFAILED);
1224 }
1225
1226 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1227 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1228
1229 ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1230 "config1=%llx, sstatus=%llx xgxs %llx\n",
1231 (unsigned long long) val, (unsigned long long) config1,
1232 (unsigned long long)
1233 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1234 (unsigned long long)
1235 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1236
1237 /* force reset on */
1238 val |= INFINIPATH_SERDC0_RESET_PLL
1239 /* | INFINIPATH_SERDC0_RESET_MASK */
1240 ;
1241 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1242 udelay(15); /* need pll reset set at least for a bit */
1243
1244 if (val & INFINIPATH_SERDC0_RESET_PLL) {
1245 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1246 /* set lane resets, and tx idle, during pll reset */
1247 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1248 INFINIPATH_SERDC0_TXIDLE;
1249 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1250 "%llx)\n", (unsigned long long) val2);
1251 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1252 val2);
1253 /*
1254 * be sure chip saw it
1255 */
1256 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1257 /*
1258 * need pll reset clear at least 11 usec before lane
1259 * resets cleared; give it a few more
1260 */
1261 udelay(15);
1262 val = val2; /* for check below */
1263 }
1264
1265 if (val & (INFINIPATH_SERDC0_RESET_PLL |
1266 INFINIPATH_SERDC0_RESET_MASK |
1267 INFINIPATH_SERDC0_TXIDLE)) {
1268 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1269 INFINIPATH_SERDC0_RESET_MASK |
1270 INFINIPATH_SERDC0_TXIDLE);
1271 /* clear them */
1272 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1273 val);
1274 }
1275
1276 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1277 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1278 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1279 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1280 INFINIPATH_XGXS_MDIOADDR_SHIFT);
1281 /*
1282 * we use address 3
1283 */
1284 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1285 change = 1;
1286 }
1287 if (val & INFINIPATH_XGXS_RESET) {
1288 /* normally true after boot */
1289 val &= ~INFINIPATH_XGXS_RESET;
1290 change = 1;
1291 }
1292 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1293 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1294 /* need to compensate for Tx inversion in partner */
1295 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1296 INFINIPATH_XGXS_RX_POL_SHIFT);
1297 val |= dd->ipath_rx_pol_inv <<
1298 INFINIPATH_XGXS_RX_POL_SHIFT;
1299 change = 1;
1300 }
1301 if (change)
1302 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1303
1304 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1305
1306 /* clear current and de-emphasis bits */
1307 config1 &= ~0x0ffffffff00ULL;
1308 /* set current to 20ma */
1309 config1 |= 0x00000000000ULL;
1310 /* set de-emphasis to -5.68dB */
1311 config1 |= 0x0cccc000000ULL;
1312 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1313
1314 ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1315 "config1=%llx, sstatus=%llx xgxs %llx\n",
1316 (unsigned long long) val, (unsigned long long) config1,
1317 (unsigned long long)
1318 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1319 (unsigned long long)
1320 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1321
1322 if (!ipath_waitfor_mdio_cmdready(dd)) {
1323 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1324 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1325 IPATH_MDIO_CTRL_XGXS_REG_8,
1326 0));
1327 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1328 IPATH_MDIO_DATAVALID, &val))
1329 ipath_dbg("Never got MDIO data for XGXS status "
1330 "read\n");
1331 else
1332 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1333 "'bank' 31 %x\n", (u32) val);
1334 } else
1335 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1336
1337 return ret; /* for now, say we always succeeded */
1338 }
1339
1340 /**
1341 * ipath_ht_quiet_serdes - set serdes to txidle
1342 * @dd: the infinipath device
1343 * driver is being unloaded
1344 */
1345 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1346 {
1347 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1348
1349 val |= INFINIPATH_SERDC0_TXIDLE;
1350 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1351 (unsigned long long) val);
1352 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1353 }
1354
1355 static int ipath_ht_intconfig(struct ipath_devdata *dd)
1356 {
1357 int ret;
1358
1359 if (!dd->ipath_intconfig) {
1360 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
1361 "interrupt address\n");
1362 ret = 1;
1363 goto bail;
1364 }
1365
1366 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
1367 dd->ipath_intconfig); /* interrupt address */
1368 ret = 0;
1369
1370 bail:
1371 return ret;
1372 }
1373
1374 /**
1375 * ipath_pe_put_tid - write a TID in chip
1376 * @dd: the infinipath device
1377 * @tidptr: pointer to the expected TID (in chip) to udpate
1378 * @tidtype: 0 for eager, 1 for expected
1379 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1380 *
1381 * This exists as a separate routine to allow for special locking etc.
1382 * It's used for both the full cleanup on exit, as well as the normal
1383 * setup and teardown.
1384 */
1385 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1386 u64 __iomem *tidptr, u32 type,
1387 unsigned long pa)
1388 {
1389 if (pa != dd->ipath_tidinvalid) {
1390 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1391 dev_info(&dd->pcidev->dev,
1392 "physaddr %lx has more than "
1393 "40 bits, using only 40!!!\n", pa);
1394 pa &= INFINIPATH_RT_ADDR_MASK;
1395 }
1396 if (type == 0)
1397 pa |= dd->ipath_tidtemplate;
1398 else {
1399 /* in words (fixed, full page). */
1400 u64 lenvalid = PAGE_SIZE >> 2;
1401 lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1402 pa |= lenvalid | INFINIPATH_RT_VALID;
1403 }
1404 }
1405 if (dd->ipath_kregbase)
1406 writeq(pa, tidptr);
1407 }
1408
1409 /**
1410 * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1411 * @dd: the infinipath device
1412 * @port: the port
1413 *
1414 * Used from ipath_close(), and at chip initialization.
1415 */
1416 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1417 {
1418 u64 __iomem *tidbase;
1419 int i;
1420
1421 if (!dd->ipath_kregbase)
1422 return;
1423
1424 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1425
1426 /*
1427 * need to invalidate all of the expected TID entries for this
1428 * port, so we don't have valid entries that might somehow get
1429 * used (early in next use of this port, or through some bug)
1430 */
1431 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1432 dd->ipath_rcvtidbase +
1433 port * dd->ipath_rcvtidcnt *
1434 sizeof(*tidbase));
1435 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1436 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1437
1438 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1439 dd->ipath_rcvegrbase +
1440 port * dd->ipath_rcvegrcnt *
1441 sizeof(*tidbase));
1442
1443 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1444 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1445 }
1446
1447 /**
1448 * ipath_ht_tidtemplate - setup constants for TID updates
1449 * @dd: the infinipath device
1450 *
1451 * We setup stuff that we use a lot, to avoid calculating each time
1452 */
1453 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1454 {
1455 dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1456 dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1457 dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1458
1459 /*
1460 * work around chip errata bug 7358, by marking invalid tids
1461 * as having max length
1462 */
1463 dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1464 INFINIPATH_RT_BUFSIZE_SHIFT;
1465 }
1466
1467 static int ipath_ht_early_init(struct ipath_devdata *dd)
1468 {
1469 u32 __iomem *piobuf;
1470 u32 pioincr, val32, egrsize;
1471 int i;
1472
1473 /*
1474 * one cache line; long IB headers will spill over into received
1475 * buffer
1476 */
1477 dd->ipath_rcvhdrentsize = 16;
1478 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1479
1480 /*
1481 * For HT, we allocate a somewhat overly large eager buffer,
1482 * such that we can guarantee that we can receive the largest
1483 * packet that we can send out. To truly support a 4KB MTU,
1484 * we need to bump this to a large value. To date, other than
1485 * testing, we have never encountered an HCA that can really
1486 * send 4KB MTU packets, so we do not handle that (we'll get
1487 * errors interrupts if we ever see one).
1488 */
1489 dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1490 egrsize = dd->ipath_rcvegrbufsize;
1491
1492 /*
1493 * the min() check here is currently a nop, but it may not
1494 * always be, depending on just how we do ipath_rcvegrbufsize
1495 */
1496 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1497 dd->ipath_rcvegrbufsize);
1498 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1499 ipath_ht_tidtemplate(dd);
1500
1501 /*
1502 * zero all the TID entries at startup. We do this for sanity,
1503 * in case of a previous driver crash of some kind, and also
1504 * because the chip powers up with these memories in an unknown
1505 * state. Use portcnt, not cfgports, since this is for the
1506 * full chip, not for current (possibly different) configuration
1507 * value.
1508 * Chip Errata bug 6447
1509 */
1510 for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1511 ipath_ht_clear_tids(dd, val32);
1512
1513 /*
1514 * write the pbc of each buffer, to be sure it's initialized, then
1515 * cancel all the buffers, and also abort any packets that might
1516 * have been in flight for some reason (the latter is for driver
1517 * unload/reload, but isn't a bad idea at first init). PIO send
1518 * isn't enabled at this point, so there is no danger of sending
1519 * these out on the wire.
1520 * Chip Errata bug 6610
1521 */
1522 piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1523 dd->ipath_piobufbase);
1524 pioincr = dd->ipath_palign / sizeof(*piobuf);
1525 for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1526 /*
1527 * reasonable word count, just to init pbc
1528 */
1529 writel(16, piobuf);
1530 piobuf += pioincr;
1531 }
1532 /*
1533 * self-clearing
1534 */
1535 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1536 INFINIPATH_S_ABORT);
1537
1538 ipath_get_eeprom_info(dd);
1539 if(dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1540 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1541 /*
1542 * Later production QHT7040 has same changes as QHT7140, so
1543 * can use GPIO interrupts. They have serial #'s starting
1544 * with 128, rather than 112.
1545 */
1546 dd->ipath_flags |= IPATH_GPIO_INTR;
1547 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1548 }
1549 return 0;
1550 }
1551
1552 /**
1553 * ipath_init_ht_get_base_info - set chip-specific flags for user code
1554 * @dd: the infinipath device
1555 * @kbase: ipath_base_info pointer
1556 *
1557 * We set the PCIE flag because the lower bandwidth on PCIe vs
1558 * HyperTransport can affect some user packet algorithims.
1559 */
1560 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1561 {
1562 struct ipath_base_info *kinfo = kbase;
1563
1564 kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1565 IPATH_RUNTIME_RCVHDR_COPY;
1566
1567 return 0;
1568 }
1569
1570 /**
1571 * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1572 * @dd: the infinipath device
1573 *
1574 * This is global, and is called directly at init to set up the
1575 * chip-specific function pointers for later use.
1576 */
1577 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1578 {
1579 dd->ipath_f_intrsetup = ipath_ht_intconfig;
1580 dd->ipath_f_bus = ipath_setup_ht_config;
1581 dd->ipath_f_reset = ipath_setup_ht_reset;
1582 dd->ipath_f_get_boardname = ipath_ht_boardname;
1583 dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1584 dd->ipath_f_early_init = ipath_ht_early_init;
1585 dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1586 dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1587 dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1588 dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1589 dd->ipath_f_put_tid = ipath_ht_put_tid;
1590 dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1591 dd->ipath_f_setextled = ipath_setup_ht_setextled;
1592 dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1593
1594 /*
1595 * initialize chip-specific variables
1596 */
1597 dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1598
1599 /*
1600 * setup the register offsets, since they are different for each
1601 * chip
1602 */
1603 dd->ipath_kregs = &ipath_ht_kregs;
1604 dd->ipath_cregs = &ipath_ht_cregs;
1605
1606 /*
1607 * do very early init that is needed before ipath_f_bus is
1608 * called
1609 */
1610 ipath_init_ht_variables();
1611 }
Linux 2.6 libata-dev (mirror)