2 * Copyright (c) 2006 QLogic, Inc. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/delay.h>
35 #include <linux/pci.h>
36 #include <linux/vmalloc.h>
38 #include "ipath_kernel.h"
41 * InfiniPath I2C driver for a serial eeprom. This is not a generic
42 * I2C interface. For a start, the device we're using (Atmel AT24C11)
43 * doesn't work like a regular I2C device. It looks like one
44 * electrically, but not logically. Normal I2C devices have a single
45 * 7-bit or 10-bit I2C address that they respond to. Valid 7-bit
46 * addresses range from 0x03 to 0x77. Addresses 0x00 to 0x02 and 0x78
47 * to 0x7F are special reserved addresses (e.g. 0x00 is the "general
48 * call" address.) The Atmel device, on the other hand, responds to ALL
49 * 7-bit addresses. It's designed to be the only device on a given I2C
50 * bus. A 7-bit address corresponds to the memory address within the
51 * Atmel device itself.
53 * Also, the timing requirements mean more than simple software
54 * bitbanging, with readbacks from chip to ensure timing (simple udelay
57 * This all means that accessing the device is specialized enough
58 * that using the standard kernel I2C bitbanging interface would be
59 * impossible. For example, the core I2C eeprom driver expects to find
60 * a device at one or more of a limited set of addresses only. It doesn't
61 * allow writing to an eeprom. It also doesn't provide any means of
62 * accessing eeprom contents from within the kernel, only via sysfs.
78 static int eeprom_init
;
81 * The gpioval manipulation really should be protected by spinlocks
82 * or be converted to use atomic operations.
86 * i2c_gpio_set - set a GPIO line
87 * @dd: the infinipath device
88 * @line: the line to set
89 * @new_line_state: the state to set
91 * Returns 0 if the line was set to the new state successfully, non-zero
94 static int i2c_gpio_set(struct ipath_devdata
*dd
,
96 enum i2c_state new_line_state
)
98 u64 read_val
, write_val
, mask
, *gpioval
;
100 gpioval
= &dd
->ipath_gpio_out
;
101 read_val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_extctrl
);
102 if (line
== i2c_line_scl
)
103 mask
= ipath_gpio_scl
;
105 mask
= ipath_gpio_sda
;
107 if (new_line_state
== i2c_line_high
)
108 /* tri-state the output rather than force high */
109 write_val
= read_val
& ~mask
;
111 /* config line to be an output */
112 write_val
= read_val
| mask
;
113 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_extctrl
, write_val
);
115 /* set high and verify */
116 if (new_line_state
== i2c_line_high
)
121 if (line
== i2c_line_scl
) {
122 write_val
<<= ipath_gpio_scl_num
;
123 *gpioval
= *gpioval
& ~(1UL << ipath_gpio_scl_num
);
124 *gpioval
|= write_val
;
126 write_val
<<= ipath_gpio_sda_num
;
127 *gpioval
= *gpioval
& ~(1UL << ipath_gpio_sda_num
);
128 *gpioval
|= write_val
;
130 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_gpio_out
, *gpioval
);
136 * i2c_gpio_get - get a GPIO line state
137 * @dd: the infinipath device
138 * @line: the line to get
139 * @curr_statep: where to put the line state
141 * Returns 0 if the line was set to the new state successfully, non-zero
142 * on error. curr_state is not set on error.
144 static int i2c_gpio_get(struct ipath_devdata
*dd
,
146 enum i2c_state
*curr_statep
)
148 u64 read_val
, write_val
, mask
;
152 if (curr_statep
== NULL
) {
157 read_val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_extctrl
);
158 /* config line to be an input */
159 if (line
== i2c_line_scl
)
160 mask
= ipath_gpio_scl
;
162 mask
= ipath_gpio_sda
;
163 write_val
= read_val
& ~mask
;
164 ipath_write_kreg(dd
, dd
->ipath_kregs
->kr_extctrl
, write_val
);
165 read_val
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_extstatus
);
168 *curr_statep
= i2c_line_high
;
170 *curr_statep
= i2c_line_low
;
179 * i2c_wait_for_writes - wait for a write
180 * @dd: the infinipath device
182 * We use this instead of udelay directly, so we can make sure
183 * that previous register writes have been flushed all the way
184 * to the chip. Since we are delaying anyway, the cost doesn't
185 * hurt, and makes the bit twiddling more regular
187 static void i2c_wait_for_writes(struct ipath_devdata
*dd
)
189 (void)ipath_read_kreg32(dd
, dd
->ipath_kregs
->kr_scratch
);
192 static void scl_out(struct ipath_devdata
*dd
, u8 bit
)
194 i2c_gpio_set(dd
, i2c_line_scl
, bit
? i2c_line_high
: i2c_line_low
);
196 i2c_wait_for_writes(dd
);
199 static void sda_out(struct ipath_devdata
*dd
, u8 bit
)
201 i2c_gpio_set(dd
, i2c_line_sda
, bit
? i2c_line_high
: i2c_line_low
);
203 i2c_wait_for_writes(dd
);
206 static u8
sda_in(struct ipath_devdata
*dd
, int wait
)
210 if (i2c_gpio_get(dd
, i2c_line_sda
, &bit
))
211 ipath_dbg("get bit failed!\n");
214 i2c_wait_for_writes(dd
);
216 return bit
== i2c_line_high
? 1U : 0;
220 * i2c_ackrcv - see if ack following write is true
221 * @dd: the infinipath device
223 static int i2c_ackrcv(struct ipath_devdata
*dd
)
227 /* AT ENTRY SCL = LOW */
228 /* change direction, ignore data */
229 ack_received
= sda_in(dd
, 1);
230 scl_out(dd
, i2c_line_high
);
231 ack_received
= sda_in(dd
, 1) == 0;
232 scl_out(dd
, i2c_line_low
);
237 * wr_byte - write a byte, one bit at a time
238 * @dd: the infinipath device
239 * @data: the byte to write
241 * Returns 0 if we got the following ack, otherwise 1
243 static int wr_byte(struct ipath_devdata
*dd
, u8 data
)
248 for (bit_cntr
= 7; bit_cntr
>= 0; bit_cntr
--) {
249 bit
= (data
>> bit_cntr
) & 1;
251 scl_out(dd
, i2c_line_high
);
252 scl_out(dd
, i2c_line_low
);
254 return (!i2c_ackrcv(dd
)) ? 1 : 0;
257 static void send_ack(struct ipath_devdata
*dd
)
259 sda_out(dd
, i2c_line_low
);
260 scl_out(dd
, i2c_line_high
);
261 scl_out(dd
, i2c_line_low
);
262 sda_out(dd
, i2c_line_high
);
266 * i2c_startcmd - transmit the start condition, followed by address/cmd
267 * @dd: the infinipath device
268 * @offset_dir: direction byte
270 * (both clock/data high, clock high, data low while clock is high)
272 static int i2c_startcmd(struct ipath_devdata
*dd
, u8 offset_dir
)
276 /* issue start sequence */
277 sda_out(dd
, i2c_line_high
);
278 scl_out(dd
, i2c_line_high
);
279 sda_out(dd
, i2c_line_low
);
280 scl_out(dd
, i2c_line_low
);
282 /* issue length and direction byte */
283 res
= wr_byte(dd
, offset_dir
);
286 ipath_cdbg(VERBOSE
, "No ack to complete start\n");
292 * stop_cmd - transmit the stop condition
293 * @dd: the infinipath device
295 * (both clock/data low, clock high, data high while clock is high)
297 static void stop_cmd(struct ipath_devdata
*dd
)
299 scl_out(dd
, i2c_line_low
);
300 sda_out(dd
, i2c_line_low
);
301 scl_out(dd
, i2c_line_high
);
302 sda_out(dd
, i2c_line_high
);
307 * eeprom_reset - reset I2C communication
308 * @dd: the infinipath device
311 static int eeprom_reset(struct ipath_devdata
*dd
)
313 int clock_cycles_left
= 9;
314 u64
*gpioval
= &dd
->ipath_gpio_out
;
318 *gpioval
= ipath_read_kreg64(dd
, dd
->ipath_kregs
->kr_gpio_out
);
319 ipath_cdbg(VERBOSE
, "Resetting i2c eeprom; initial gpioout reg "
320 "is %llx\n", (unsigned long long) *gpioval
);
323 * This is to get the i2c into a known state, by first going low,
324 * then tristate sda (and then tristate scl as first thing
327 scl_out(dd
, i2c_line_low
);
328 sda_out(dd
, i2c_line_high
);
330 while (clock_cycles_left
--) {
331 scl_out(dd
, i2c_line_high
);
334 sda_out(dd
, i2c_line_low
);
335 scl_out(dd
, i2c_line_low
);
340 scl_out(dd
, i2c_line_low
);
350 * ipath_eeprom_read - receives bytes from the eeprom via I2C
351 * @dd: the infinipath device
352 * @eeprom_offset: address to read from
353 * @buffer: where to store result
354 * @len: number of bytes to receive
357 int ipath_eeprom_read(struct ipath_devdata
*dd
, u8 eeprom_offset
,
358 void *buffer
, int len
)
360 /* compiler complains unless initialized */
368 eeprom_offset
= (eeprom_offset
<< 1) | READ_CMD
;
370 if (i2c_startcmd(dd
, eeprom_offset
)) {
371 ipath_dbg("Failed startcmd\n");
378 * eeprom keeps clocking data out as long as we ack, automatically
379 * incrementing the address.
384 for (bit_cntr
= 8; bit_cntr
; bit_cntr
--) {
386 scl_out(dd
, i2c_line_high
);
388 single_byte
|= bit
<< (bit_cntr
- 1);
389 scl_out(dd
, i2c_line_low
);
392 /* send ack if not the last byte */
396 *((u8
*) buffer
) = single_byte
;
409 * ipath_eeprom_write - writes data to the eeprom via I2C
410 * @dd: the infinipath device
411 * @eeprom_offset: where to place data
412 * @buffer: data to write
413 * @len: number of bytes to write
415 int ipath_eeprom_write(struct ipath_devdata
*dd
, u8 eeprom_offset
,
416 const void *buffer
, int len
)
420 const u8
*bp
= buffer
;
421 int max_wait_time
, i
;
428 if (i2c_startcmd(dd
, (eeprom_offset
<< 1) | WRITE_CMD
)) {
429 ipath_dbg("Failed to start cmd offset %u\n",
434 sub_len
= min(len
, 4);
435 eeprom_offset
+= sub_len
;
438 for (i
= 0; i
< sub_len
; i
++) {
439 if (wr_byte(dd
, *bp
++)) {
440 ipath_dbg("no ack after byte %u/%u (%u "
441 "total remain)\n", i
, sub_len
,
450 * wait for write complete by waiting for a successful
451 * read (the chip replies with a zero after the write
452 * cmd completes, and before it writes to the eeprom.
453 * The startcmd for the read will fail the ack until
454 * the writes have completed. We do this inline to avoid
455 * the debug prints that are in the real read routine
456 * if the startcmd fails.
459 while (i2c_startcmd(dd
, READ_CMD
)) {
461 if (!--max_wait_time
) {
462 ipath_dbg("Did not get successful read to "
467 /* now read the zero byte */
468 for (i
= single_byte
= 0; i
< 8; i
++) {
470 scl_out(dd
, i2c_line_high
);
472 scl_out(dd
, i2c_line_low
);
490 static u8
flash_csum(struct ipath_flash
*ifp
, int adjust
)
495 for (len
= 0; len
< ifp
->if_length
; len
++)
497 csum
-= ifp
->if_csum
;
506 * ipath_get_guid - get the GUID from the i2c device
507 * @dd: the infinipath device
509 * We have the capability to use the ipath_nguid field, and get
510 * the guid from the first chip's flash, to use for all of them.
512 void ipath_get_eeprom_info(struct ipath_devdata
*dd
)
515 struct ipath_flash
*ifp
;
519 int t
= dd
->ipath_unit
;
520 struct ipath_devdata
*dd0
= ipath_lookup(0);
522 if (t
&& dd0
->ipath_nguid
> 1 && t
<= dd0
->ipath_nguid
) {
524 dd
->ipath_guid
= dd0
->ipath_guid
;
525 bguid
= (u8
*) & dd
->ipath_guid
;
529 if (oguid
> bguid
[7]) {
530 if (bguid
[6] == 0xff) {
531 if (bguid
[5] == 0xff) {
534 "Can't set %s GUID from "
535 "base, wraps to OUI!\n",
536 ipath_get_unit_name(t
));
546 ipath_dbg("nguid %u, so adding %u to device 0 guid, "
549 (unsigned long long) be64_to_cpu(dd
->ipath_guid
));
553 len
= offsetof(struct ipath_flash
, if_future
);
556 ipath_dev_err(dd
, "Couldn't allocate memory to read %u "
557 "bytes from eeprom for GUID\n", len
);
561 if (ipath_eeprom_read(dd
, 0, buf
, len
)) {
562 ipath_dev_err(dd
, "Failed reading GUID from eeprom\n");
565 ifp
= (struct ipath_flash
*)buf
;
567 csum
= flash_csum(ifp
, 0);
568 if (csum
!= ifp
->if_csum
) {
569 dev_info(&dd
->pcidev
->dev
, "Bad I2C flash checksum: "
570 "0x%x, not 0x%x\n", csum
, ifp
->if_csum
);
573 if (*(__be64
*) ifp
->if_guid
== 0ULL ||
574 *(__be64
*) ifp
->if_guid
== __constant_cpu_to_be64(-1LL)) {
575 ipath_dev_err(dd
, "Invalid GUID %llx from flash; "
577 *(unsigned long long *) ifp
->if_guid
);
578 /* don't allow GUID if all 0 or all 1's */
582 /* complain, but allow it */
583 if (*(u64
*) ifp
->if_guid
== 0x100007511000000ULL
)
584 dev_info(&dd
->pcidev
->dev
, "Warning, GUID %llx is "
585 "default, probably not correct!\n",
586 *(unsigned long long *) ifp
->if_guid
);
588 bguid
= ifp
->if_guid
;
589 if (!bguid
[0] && !bguid
[1] && !bguid
[2]) {
590 /* original incorrect GUID format in flash; fix in
591 * core copy, by shifting up 2 octets; don't need to
592 * change top octet, since both it and shifted are
596 bguid
[3] = bguid
[4] = 0;
597 guid
= *(__be64
*) ifp
->if_guid
;
598 ipath_cdbg(VERBOSE
, "Old GUID format in flash, top 3 zero, "
599 "shifting 2 octets\n");
601 guid
= *(__be64
*) ifp
->if_guid
;
602 dd
->ipath_guid
= guid
;
603 dd
->ipath_nguid
= ifp
->if_numguid
;
605 * Things are slightly complicated by the desire to transparently
606 * support both the Pathscale 10-digit serial number and the QLogic
607 * 13-character version.
609 if ((ifp
->if_fversion
> 1) && ifp
->if_sprefix
[0]
610 && ((u8
*)ifp
->if_sprefix
)[0] != 0xFF) {
611 /* This board has a Serial-prefix, which is stored
612 * elsewhere for backward-compatibility.
614 char *snp
= dd
->ipath_serial
;
616 memcpy(snp
, ifp
->if_sprefix
, sizeof ifp
->if_sprefix
);
617 snp
[sizeof ifp
->if_sprefix
] = '\0';
620 len
= (sizeof dd
->ipath_serial
) - len
;
621 if (len
> sizeof ifp
->if_serial
) {
622 len
= sizeof ifp
->if_serial
;
624 memcpy(snp
, ifp
->if_serial
, len
);
626 memcpy(dd
->ipath_serial
, ifp
->if_serial
,
627 sizeof ifp
->if_serial
);
629 ipath_cdbg(VERBOSE
, "Initted GUID to %llx from eeprom\n",
630 (unsigned long long) be64_to_cpu(dd
->ipath_guid
));