drivers/net/netxen/netxen_nic_hw.c

   1 /*
   2  * Copyright (C) 2003 - 2006 NetXen, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called LICENSE.
  22  *
  23  * Contact Information:
  24  *    info@netxen.com
  25  * NetXen,
  26  * 3965 Freedom Circle, Fourth floor,
  27  * Santa Clara, CA 95054
  28  *
  29  *
  30  * Source file for NIC routines to access the Phantom hardware
  31  *
  32  */
  33
  34 #include "netxen_nic.h"
  35 #include "netxen_nic_hw.h"
  36 #include "netxen_nic_phan_reg.h"
  37
  38 /*  PCI Windowing for DDR regions.  */
  39
  40 #define ADDR_IN_RANGE(addr, low, high)  \
  41         (((addr) <= (high)) && ((addr) >= (low)))
  42
  43 #define NETXEN_FLASH_BASE       (BOOTLD_START)
  44 #define NETXEN_PHANTOM_MEM_BASE (NETXEN_FLASH_BASE)
  45 #define NETXEN_MAX_MTU          8000 + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE
  46 #define NETXEN_MIN_MTU          64
  47 #define NETXEN_ETH_FCS_SIZE     4
  48 #define NETXEN_ENET_HEADER_SIZE 14
  49 #define NETXEN_WINDOW_ONE       0x2000000       /*CRB Window: bit 25 of CRB address */
  50 #define NETXEN_FIRMWARE_LEN     ((16 * 1024) / 4)
  51 #define NETXEN_NIU_HDRSIZE      (0x1 << 6)
  52 #define NETXEN_NIU_TLRSIZE      (0x1 << 5)
  53
  54 #define lower32(x)              ((u32)((x) & 0xffffffff))
  55 #define upper32(x)                      \
  56         ((u32)(((unsigned long long)(x) >> 32) & 0xffffffff))
  57
  58 #define NETXEN_NIC_ZERO_PAUSE_ADDR     0ULL
  59 #define NETXEN_NIC_UNIT_PAUSE_ADDR     0x200ULL
  60 #define NETXEN_NIC_EPG_PAUSE_ADDR1     0x2200010000c28001ULL
  61 #define NETXEN_NIC_EPG_PAUSE_ADDR2     0x0100088866554433ULL
  62
  63 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
  64
  65 unsigned long netxen_nic_pci_set_window(struct netxen_adapter *adapter,
  66                                         unsigned long long addr);
  67 void netxen_free_hw_resources(struct netxen_adapter *adapter);
  68
  69 int netxen_nic_set_mac(struct net_device *netdev, void *p)
  70 {
  71         struct netxen_port *port = netdev_priv(netdev);
  72         struct netxen_adapter *adapter = port->adapter;
  73         struct sockaddr *addr = p;
  74
  75         if (netif_running(netdev))
  76                 return -EBUSY;
  77
  78         if (!is_valid_ether_addr(addr->sa_data))
  79                 return -EADDRNOTAVAIL;
  80
  81         DPRINTK(INFO, "valid ether addr\n");
  82         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  83
  84         if (adapter->macaddr_set)
  85                 adapter->macaddr_set(port, addr->sa_data);
  86
  87         return 0;
  88 }
  89
  90 /*
  91  * netxen_nic_set_multi - Multicast
  92  */
  93 void netxen_nic_set_multi(struct net_device *netdev)
  94 {
  95         struct netxen_port *port = netdev_priv(netdev);
  96         struct netxen_adapter *adapter = port->adapter;
  97         struct dev_mc_list *mc_ptr;
  98         __u32 netxen_mac_addr_cntl_data = 0;
  99
 100         mc_ptr = netdev->mc_list;
 101         if (netdev->flags & IFF_PROMISC) {
 102                 if (adapter->set_promisc)
 103                         adapter->set_promisc(adapter,
 104                                              port->portnum,
 105                                              NETXEN_NIU_PROMISC_MODE);
 106         } else {
 107                 if (adapter->unset_promisc &&
 108                     adapter->ahw.boardcfg.board_type
 109                     != NETXEN_BRDTYPE_P2_SB31_10G_IMEZ)
 110                         adapter->unset_promisc(adapter,
 111                                                port->portnum,
 112                                                NETXEN_NIU_NON_PROMISC_MODE);
 113         }
 114         if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
 115                 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x03);
 116                 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
 117                 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x00);
 118                 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x00);
 119                 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x00);
 120                 netxen_nic_mcr_set_enable_xtnd0(netxen_mac_addr_cntl_data);
 121                 netxen_nic_mcr_set_enable_xtnd1(netxen_mac_addr_cntl_data);
 122                 netxen_nic_mcr_set_enable_xtnd2(netxen_mac_addr_cntl_data);
 123                 netxen_nic_mcr_set_enable_xtnd3(netxen_mac_addr_cntl_data);
 124         } else {
 125                 netxen_nic_mcr_set_mode_select(netxen_mac_addr_cntl_data, 0x00);
 126                 netxen_nic_mcr_set_id_pool0(netxen_mac_addr_cntl_data, 0x00);
 127                 netxen_nic_mcr_set_id_pool1(netxen_mac_addr_cntl_data, 0x01);
 128                 netxen_nic_mcr_set_id_pool2(netxen_mac_addr_cntl_data, 0x02);
 129                 netxen_nic_mcr_set_id_pool3(netxen_mac_addr_cntl_data, 0x03);
 130         }
 131         writel(netxen_mac_addr_cntl_data,
 132                NETXEN_CRB_NORMALIZE(adapter, NETXEN_MAC_ADDR_CNTL_REG));
 133         if (adapter->ahw.board_type == NETXEN_NIC_XGBE) {
 134                 writel(netxen_mac_addr_cntl_data,
 135                        NETXEN_CRB_NORMALIZE(adapter,
 136                                             NETXEN_MULTICAST_ADDR_HI_0));
 137         } else {
 138                 writel(netxen_mac_addr_cntl_data,
 139                        NETXEN_CRB_NORMALIZE(adapter,
 140                                             NETXEN_MULTICAST_ADDR_HI_1));
 141         }
 142         netxen_mac_addr_cntl_data = 0;
 143         writel(netxen_mac_addr_cntl_data,
 144                NETXEN_CRB_NORMALIZE(adapter, NETXEN_NIU_GB_DROP_WRONGADDR));
 145 }
 146
 147 /*
 148  * netxen_nic_change_mtu - Change the Maximum Transfer Unit
 149  * @returns 0 on success, negative on failure
 150  */
 151 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
 152 {
 153         struct netxen_port *port = netdev_priv(netdev);
 154         struct netxen_adapter *adapter = port->adapter;
 155         int eff_mtu = mtu + NETXEN_ENET_HEADER_SIZE + NETXEN_ETH_FCS_SIZE;
 156
 157         if ((eff_mtu > NETXEN_MAX_MTU) || (eff_mtu < NETXEN_MIN_MTU)) {
 158                 printk(KERN_ERR "%s: %s %d is not supported.\n",
 159                        netxen_nic_driver_name, netdev->name, mtu);
 160                 return -EINVAL;
 161         }
 162
 163         if (adapter->set_mtu)
 164                 adapter->set_mtu(port, mtu);
 165         netdev->mtu = mtu;
 166
 167         return 0;
 168 }
 169
 170 /*
 171  * check if the firmware has been downloaded and ready to run  and
 172  * setup the address for the descriptors in the adapter
 173  */
 174 int netxen_nic_hw_resources(struct netxen_adapter *adapter)
 175 {
 176         struct netxen_hardware_context *hw = &adapter->ahw;
 177         u32 state = 0;
 178         void *addr;
 179         int loops = 0, err = 0;
 180         int ctx, ring;
 181         u32 card_cmdring = 0;
 182         struct netxen_recv_context *recv_ctx;
 183         struct netxen_rcv_desc_ctx *rcv_desc;
 184
 185         DPRINTK(INFO, "crb_base: %lx %x", NETXEN_PCI_CRBSPACE,
 186                 PCI_OFFSET_SECOND_RANGE(adapter, NETXEN_PCI_CRBSPACE));
 187         DPRINTK(INFO, "cam base: %lx %x", NETXEN_CRB_CAM,
 188                 pci_base_offset(adapter, NETXEN_CRB_CAM));
 189         DPRINTK(INFO, "cam RAM: %lx %x", NETXEN_CAM_RAM_BASE,
 190                 pci_base_offset(adapter, NETXEN_CAM_RAM_BASE));
 191
 192         /* Window 1 call */
 193         card_cmdring = readl(NETXEN_CRB_NORMALIZE(adapter, CRB_CMDPEG_CMDRING));
 194
 195         DPRINTK(INFO, "Command Peg sends 0x%x for cmdring base\n",
 196                 card_cmdring);
 197
 198         for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
 199                 DPRINTK(INFO, "Command Peg ready..waiting for rcv peg\n");
 200                 loops = 0;
 201                 state = 0;
 202                 /* Window 1 call */
 203                 state = readl(NETXEN_CRB_NORMALIZE(adapter,
 204                                                    recv_crb_registers[ctx].
 205                                                    crb_rcvpeg_state));
 206                 while (state != PHAN_PEG_RCV_INITIALIZED && loops < 20) {
 207                         udelay(100);
 208                         /* Window 1 call */
 209                         state = readl(NETXEN_CRB_NORMALIZE(adapter,
 210                                                            recv_crb_registers
 211                                                            [ctx].
 212                                                            crb_rcvpeg_state));
 213                         loops++;
 214                 }
 215                 if (loops >= 20) {
 216                         printk(KERN_ERR "Rcv Peg initialization not complete:"
 217                                "%x.\n", state);
 218                         err = -EIO;
 219                         return err;
 220                 }
 221         }
 222         DPRINTK(INFO, "Recieve Peg ready too. starting stuff\n");
 223
 224         addr = netxen_alloc(adapter->ahw.pdev,
 225                             sizeof(struct netxen_ring_ctx) +
 226                             sizeof(uint32_t),
 227                             (dma_addr_t *) & adapter->ctx_desc_phys_addr,
 228                             &adapter->ctx_desc_pdev);
 229
 230         printk("ctx_desc_phys_addr: 0x%llx\n",
 231                (unsigned long long) adapter->ctx_desc_phys_addr);
 232         if (addr == NULL) {
 233                 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
 234                 err = -ENOMEM;
 235                 return err;
 236         }
 237         memset(addr, 0, sizeof(struct netxen_ring_ctx));
 238         adapter->ctx_desc = (struct netxen_ring_ctx *)addr;
 239         adapter->ctx_desc->cmd_consumer_offset =
 240             cpu_to_le64(adapter->ctx_desc_phys_addr +
 241                         sizeof(struct netxen_ring_ctx));
 242         adapter->cmd_consumer = (uint32_t *) (((char *)addr) +
 243                                               sizeof(struct netxen_ring_ctx));
 244
 245         addr = netxen_alloc(adapter->ahw.pdev,
 246                             sizeof(struct cmd_desc_type0) *
 247                             adapter->max_tx_desc_count,
 248                             (dma_addr_t *) & hw->cmd_desc_phys_addr,
 249                             &adapter->ahw.cmd_desc_pdev);
 250         printk("cmd_desc_phys_addr: 0x%llx\n",
 251                (unsigned long long) hw->cmd_desc_phys_addr);
 252
 253         if (addr == NULL) {
 254                 DPRINTK(ERR, "bad return from pci_alloc_consistent\n");
 255                 netxen_free_hw_resources(adapter);
 256                 return -ENOMEM;
 257         }
 258
 259         adapter->ctx_desc->cmd_ring_addr =
 260                 cpu_to_le64(hw->cmd_desc_phys_addr);
 261         adapter->ctx_desc->cmd_ring_size =
 262                 cpu_to_le32(adapter->max_tx_desc_count);
 263
 264         hw->cmd_desc_head = (struct cmd_desc_type0 *)addr;
 265
 266         for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
 267                 recv_ctx = &adapter->recv_ctx[ctx];
 268
 269                 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
 270                         rcv_desc = &recv_ctx->rcv_desc[ring];
 271                         addr = netxen_alloc(adapter->ahw.pdev,
 272                                             RCV_DESC_RINGSIZE,
 273                                             &rcv_desc->phys_addr,
 274                                             &rcv_desc->phys_pdev);
 275                         if (addr == NULL) {
 276                                 DPRINTK(ERR, "bad return from "
 277                                         "pci_alloc_consistent\n");
 278                                 netxen_free_hw_resources(adapter);
 279                                 err = -ENOMEM;
 280                                 return err;
 281                         }
 282                         rcv_desc->desc_head = (struct rcv_desc *)addr;
 283                         adapter->ctx_desc->rcv_ctx[ring].rcv_ring_addr =
 284                             cpu_to_le64(rcv_desc->phys_addr);
 285                         adapter->ctx_desc->rcv_ctx[ring].rcv_ring_size =
 286                             cpu_to_le32(rcv_desc->max_rx_desc_count);
 287                 }
 288
 289                 addr = netxen_alloc(adapter->ahw.pdev, STATUS_DESC_RINGSIZE,
 290                                     &recv_ctx->rcv_status_desc_phys_addr,
 291                                     &recv_ctx->rcv_status_desc_pdev);
 292                 if (addr == NULL) {
 293                         DPRINTK(ERR, "bad return from"
 294                                 " pci_alloc_consistent\n");
 295                         netxen_free_hw_resources(adapter);
 296                         err = -ENOMEM;
 297                         return err;
 298                 }
 299                 recv_ctx->rcv_status_desc_head = (struct status_desc *)addr;
 300                 adapter->ctx_desc->sts_ring_addr =
 301                     cpu_to_le64(recv_ctx->rcv_status_desc_phys_addr);
 302                 adapter->ctx_desc->sts_ring_size =
 303                     cpu_to_le32(adapter->max_rx_desc_count);
 304
 305         }
 306         /* Window = 1 */
 307
 308         writel(lower32(adapter->ctx_desc_phys_addr),
 309                NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_LO));
 310         writel(upper32(adapter->ctx_desc_phys_addr),
 311                NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_ADDR_REG_HI));
 312         writel(NETXEN_CTX_SIGNATURE,
 313                NETXEN_CRB_NORMALIZE(adapter, CRB_CTX_SIGNATURE_REG));
 314         return err;
 315 }
 316
 317 void netxen_free_hw_resources(struct netxen_adapter *adapter)
 318 {
 319         struct netxen_recv_context *recv_ctx;
 320         struct netxen_rcv_desc_ctx *rcv_desc;
 321         int ctx, ring;
 322
 323         if (adapter->ctx_desc != NULL) {
 324                 pci_free_consistent(adapter->ctx_desc_pdev,
 325                                     sizeof(struct netxen_ring_ctx) +
 326                                     sizeof(uint32_t),
 327                                     adapter->ctx_desc,
 328                                     adapter->ctx_desc_phys_addr);
 329                 adapter->ctx_desc = NULL;
 330         }
 331
 332         if (adapter->ahw.cmd_desc_head != NULL) {
 333                 pci_free_consistent(adapter->ahw.cmd_desc_pdev,
 334                                     sizeof(struct cmd_desc_type0) *
 335                                     adapter->max_tx_desc_count,
 336                                     adapter->ahw.cmd_desc_head,
 337                                     adapter->ahw.cmd_desc_phys_addr);
 338                 adapter->ahw.cmd_desc_head = NULL;
 339         }
 340         /* Special handling: there are 2 ports on this board */
 341         if (adapter->ahw.boardcfg.board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) {
 342                 adapter->ahw.max_ports = 2;
 343         }
 344
 345         for (ctx = 0; ctx < MAX_RCV_CTX; ++ctx) {
 346                 recv_ctx = &adapter->recv_ctx[ctx];
 347                 for (ring = 0; ring < NUM_RCV_DESC_RINGS; ring++) {
 348                         rcv_desc = &recv_ctx->rcv_desc[ring];
 349
 350                         if (rcv_desc->desc_head != NULL) {
 351                                 pci_free_consistent(rcv_desc->phys_pdev,
 352                                                     RCV_DESC_RINGSIZE,
 353                                                     rcv_desc->desc_head,
 354                                                     rcv_desc->phys_addr);
 355                                 rcv_desc->desc_head = NULL;
 356                         }
 357                 }
 358
 359                 if (recv_ctx->rcv_status_desc_head != NULL) {
 360                         pci_free_consistent(recv_ctx->rcv_status_desc_pdev,
 361                                             STATUS_DESC_RINGSIZE,
 362                                             recv_ctx->rcv_status_desc_head,
 363                                             recv_ctx->
 364                                             rcv_status_desc_phys_addr);
 365                         recv_ctx->rcv_status_desc_head = NULL;
 366                 }
 367         }
 368 }
 369
 370 void netxen_tso_check(struct netxen_adapter *adapter,
 371                       struct cmd_desc_type0 *desc, struct sk_buff *skb)
 372 {
 373         if (desc->mss) {
 374                 desc->total_hdr_length = sizeof(struct ethhdr) +
 375                     ((skb->nh.iph)->ihl * sizeof(u32)) +
 376                     ((skb->h.th)->doff * sizeof(u32));
 377                 netxen_set_cmd_desc_opcode(desc, TX_TCP_LSO);
 378         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
 379                 if (skb->nh.iph->protocol == IPPROTO_TCP) {
 380                         netxen_set_cmd_desc_opcode(desc, TX_TCP_PKT);
 381                 } else if (skb->nh.iph->protocol == IPPROTO_UDP) {
 382                         netxen_set_cmd_desc_opcode(desc, TX_UDP_PKT);
 383                 } else {
 384                         return;
 385                 }
 386         }
 387         adapter->stats.xmitcsummed++;
 388         desc->tcp_hdr_offset = skb->h.raw - skb->data;
 389         desc->ip_hdr_offset = skb->nh.raw - skb->data;
 390 }
 391
 392 int netxen_is_flash_supported(struct netxen_adapter *adapter)
 393 {
 394         const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
 395         int addr, val01, val02, i, j;
 396
 397         /* if the flash size less than 4Mb, make huge war cry and die */
 398         for (j = 1; j < 4; j++) {
 399                 addr = j * NETXEN_NIC_WINDOW_MARGIN;
 400                 for (i = 0; i < (sizeof(locs) / sizeof(locs[0])); i++) {
 401                         if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
 402                             && netxen_rom_fast_read(adapter, (addr + locs[i]),
 403                                                     &val02) == 0) {
 404                                 if (val01 == val02)
 405                                         return -1;
 406                         } else
 407                                 return -1;
 408                 }
 409         }
 410
 411         return 0;
 412 }
 413
 414 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
 415                                   int size, u32 * buf)
 416 {
 417         int i, addr;
 418         u32 *ptr32;
 419
 420         addr = base;
 421         ptr32 = buf;
 422         for (i = 0; i < size / sizeof(u32); i++) {
 423                 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1)
 424                         return -1;
 425                 *ptr32 = cpu_to_le32(*ptr32);
 426                 ptr32++;
 427                 addr += sizeof(u32);
 428         }
 429         if ((char *)buf + size > (char *)ptr32) {
 430                 u32 local;
 431
 432                 if (netxen_rom_fast_read(adapter, addr, &local) == -1)
 433                         return -1;
 434                 local = cpu_to_le32(local);
 435                 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
 436         }
 437
 438         return 0;
 439 }
 440
 441 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 mac[])
 442 {
 443         u32 *pmac = (u32 *) & mac[0];
 444
 445         if (netxen_get_flash_block(adapter,
 446                                    USER_START +
 447                                    offsetof(struct netxen_new_user_info,
 448                                             mac_addr),
 449                                    FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
 450                 return -1;
 451         }
 452         if (*mac == ~0ULL) {
 453                 if (netxen_get_flash_block(adapter,
 454                                            USER_START_OLD +
 455                                            offsetof(struct netxen_user_old_info,
 456                                                     mac_addr),
 457                                            FLASH_NUM_PORTS * sizeof(u64),
 458                                            pmac) == -1)
 459                         return -1;
 460                 if (*mac == ~0ULL)
 461                         return -1;
 462         }
 463         return 0;
 464 }
 465
 466 /*
 467  * Changes the CRB window to the specified window.
 468  */
 469 void netxen_nic_pci_change_crbwindow(struct netxen_adapter *adapter, u32 wndw)
 470 {
 471         void __iomem *offset;
 472         u32 tmp;
 473         int count = 0;
 474
 475         if (adapter->curr_window == wndw)
 476                 return;
 477
 478         /*
 479          * Move the CRB window.
 480          * We need to write to the "direct access" region of PCI
 481          * to avoid a race condition where the window register has
 482          * not been successfully written across CRB before the target
 483          * register address is received by PCI. The direct region bypasses
 484          * the CRB bus.
 485          */
 486         offset =
 487             PCI_OFFSET_SECOND_RANGE(adapter,
 488                                     NETXEN_PCIX_PH_REG(PCIX_CRB_WINDOW));
 489
 490         if (wndw & 0x1)
 491                 wndw = NETXEN_WINDOW_ONE;
 492
 493         writel(wndw, offset);
 494
 495         /* MUST make sure window is set before we forge on... */
 496         while ((tmp = readl(offset)) != wndw) {
 497                 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
 498                        "registered properly: 0x%08x.\n",
 499                        netxen_nic_driver_name, __FUNCTION__, tmp);
 500                 mdelay(1);
 501                 if (count >= 10)
 502                         break;
 503                 count++;
 504         }
 505
 506         adapter->curr_window = wndw;
 507 }
 508
 509 void netxen_load_firmware(struct netxen_adapter *adapter)
 510 {
 511         int i;
 512         u32 data, size = 0;
 513         u32 flashaddr = NETXEN_FLASH_BASE, memaddr = NETXEN_PHANTOM_MEM_BASE;
 514         u64 off;
 515         void __iomem *addr;
 516
 517         size = NETXEN_FIRMWARE_LEN;
 518         writel(1, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
 519
 520         for (i = 0; i < size; i++) {
 521                 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0) {
 522                         DPRINTK(ERR,
 523                                 "Error in netxen_rom_fast_read(). Will skip"
 524                                 "loading flash image\n");
 525                         return;
 526                 }
 527                 off = netxen_nic_pci_set_window(adapter, memaddr);
 528                 addr = pci_base_offset(adapter, off);
 529                 writel(data, addr);
 530                 flashaddr += 4;
 531                 memaddr += 4;
 532         }
 533         udelay(100);
 534         /* make sure Casper is powered on */
 535         writel(0x3fff,
 536                NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL));
 537         writel(0, NETXEN_CRB_NORMALIZE(adapter, NETXEN_ROMUSB_GLB_CAS_RST));
 538
 539         udelay(100);
 540 }
 541
 542 int
 543 netxen_nic_hw_write_wx(struct netxen_adapter *adapter, u64 off, void *data,
 544                        int len)
 545 {
 546         void __iomem *addr;
 547
 548         if (ADDR_IN_WINDOW1(off)) {
 549                 addr = NETXEN_CRB_NORMALIZE(adapter, off);
 550         } else {                /* Window 0 */
 551                 addr = pci_base_offset(adapter, off);
 552                 netxen_nic_pci_change_crbwindow(adapter, 0);
 553         }
 554
 555         DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
 556                 " data %llx len %d\n",
 557                 pci_base(adapter, off), off, addr,
 558                 *(unsigned long long *)data, len);
 559         if (!addr) {
 560                 netxen_nic_pci_change_crbwindow(adapter, 1);
 561                 return 1;
 562         }
 563
 564         switch (len) {
 565         case 1:
 566                 writeb(*(u8 *) data, addr);
 567                 break;
 568         case 2:
 569                 writew(*(u16 *) data, addr);
 570                 break;
 571         case 4:
 572                 writel(*(u32 *) data, addr);
 573                 break;
 574         case 8:
 575                 writeq(*(u64 *) data, addr);
 576                 break;
 577         default:
 578                 DPRINTK(INFO,
 579                         "writing data %lx to offset %llx, num words=%d\n",
 580                         *(unsigned long *)data, off, (len >> 3));
 581
 582                 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
 583                                             (len >> 3));
 584                 break;
 585         }
 586         if (!ADDR_IN_WINDOW1(off))
 587                 netxen_nic_pci_change_crbwindow(adapter, 1);
 588
 589         return 0;
 590 }
 591
 592 int
 593 netxen_nic_hw_read_wx(struct netxen_adapter *adapter, u64 off, void *data,
 594                       int len)
 595 {
 596         void __iomem *addr;
 597
 598         if (ADDR_IN_WINDOW1(off)) {     /* Window 1 */
 599                 addr = NETXEN_CRB_NORMALIZE(adapter, off);
 600         } else {                /* Window 0 */
 601                 addr = pci_base_offset(adapter, off);
 602                 netxen_nic_pci_change_crbwindow(adapter, 0);
 603         }
 604
 605         DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
 606                 pci_base(adapter, off), off, addr);
 607         if (!addr) {
 608                 netxen_nic_pci_change_crbwindow(adapter, 1);
 609                 return 1;
 610         }
 611         switch (len) {
 612         case 1:
 613                 *(u8 *) data = readb(addr);
 614                 break;
 615         case 2:
 616                 *(u16 *) data = readw(addr);
 617                 break;
 618         case 4:
 619                 *(u32 *) data = readl(addr);
 620                 break;
 621         case 8:
 622                 *(u64 *) data = readq(addr);
 623                 break;
 624         default:
 625                 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
 626                                            (len >> 3));
 627                 break;
 628         }
 629         DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
 630
 631         if (!ADDR_IN_WINDOW1(off))
 632                 netxen_nic_pci_change_crbwindow(adapter, 1);
 633
 634         return 0;
 635 }
 636
 637 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
 638 {                               /* Only for window 1 */
 639         void __iomem *addr;
 640
 641         addr = NETXEN_CRB_NORMALIZE(adapter, off);
 642         DPRINTK(INFO, "writing to base %lx offset %llx addr %p data %x\n",
 643                 pci_base(adapter, off), off, addr, val);
 644         writel(val, addr);
 645
 646 }
 647
 648 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
 649 {                               /* Only for window 1 */
 650         void __iomem *addr;
 651         int val;
 652
 653         addr = NETXEN_CRB_NORMALIZE(adapter, off);
 654         DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
 655                 pci_base(adapter, off), off, addr);
 656         val = readl(addr);
 657         writel(val, addr);
 658
 659         return val;
 660 }
 661
 662 /* Change the window to 0, write and change back to window 1. */
 663 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
 664 {
 665         void __iomem *addr;
 666
 667         netxen_nic_pci_change_crbwindow(adapter, 0);
 668         addr = pci_base_offset(adapter, index);
 669         writel(value, addr);
 670         netxen_nic_pci_change_crbwindow(adapter, 1);
 671 }
 672
 673 /* Change the window to 0, read and change back to window 1. */
 674 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 * value)
 675 {
 676         void __iomem *addr;
 677
 678         addr = pci_base_offset(adapter, index);
 679
 680         netxen_nic_pci_change_crbwindow(adapter, 0);
 681         *value = readl(addr);
 682         netxen_nic_pci_change_crbwindow(adapter, 1);
 683 }
 684
 685 int netxen_pci_set_window_warning_count = 0;
 686
 687 unsigned long
 688 netxen_nic_pci_set_window(struct netxen_adapter *adapter,
 689                           unsigned long long addr)
 690 {
 691         static int ddr_mn_window = -1;
 692         static int qdr_sn_window = -1;
 693         int window;
 694
 695         if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
 696                 /* DDR network side */
 697                 addr -= NETXEN_ADDR_DDR_NET;
 698                 window = (addr >> 25) & 0x3ff;
 699                 if (ddr_mn_window != window) {
 700                         ddr_mn_window = window;
 701                         writel(window, PCI_OFFSET_SECOND_RANGE(adapter,
 702                                                                NETXEN_PCIX_PH_REG
 703                                                                (PCIX_MN_WINDOW)));
 704                         /* MUST make sure window is set before we forge on... */
 705                         readl(PCI_OFFSET_SECOND_RANGE(adapter,
 706                                                       NETXEN_PCIX_PH_REG
 707                                                       (PCIX_MN_WINDOW)));
 708                 }
 709                 addr -= (window * NETXEN_WINDOW_ONE);
 710                 addr += NETXEN_PCI_DDR_NET;
 711         } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
 712                 addr -= NETXEN_ADDR_OCM0;
 713                 addr += NETXEN_PCI_OCM0;
 714         } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
 715                 addr -= NETXEN_ADDR_OCM1;
 716                 addr += NETXEN_PCI_OCM1;
 717         } else
 718             if (ADDR_IN_RANGE
 719                 (addr, NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX)) {
 720                 /* QDR network side */
 721                 addr -= NETXEN_ADDR_QDR_NET;
 722                 window = (addr >> 22) & 0x3f;
 723                 if (qdr_sn_window != window) {
 724                         qdr_sn_window = window;
 725                         writel((window << 22),
 726                                PCI_OFFSET_SECOND_RANGE(adapter,
 727                                                        NETXEN_PCIX_PH_REG
 728                                                        (PCIX_SN_WINDOW)));
 729                         /* MUST make sure window is set before we forge on... */
 730                         readl(PCI_OFFSET_SECOND_RANGE(adapter,
 731                                                       NETXEN_PCIX_PH_REG
 732                                                       (PCIX_SN_WINDOW)));
 733                 }
 734                 addr -= (window * 0x400000);
 735                 addr += NETXEN_PCI_QDR_NET;
 736         } else {
 737                 /*
 738                  * peg gdb frequently accesses memory that doesn't exist,
 739                  * this limits the chit chat so debugging isn't slowed down.
 740                  */
 741                 if ((netxen_pci_set_window_warning_count++ < 8)
 742                     || (netxen_pci_set_window_warning_count % 64 == 0))
 743                         printk("%s: Warning:netxen_nic_pci_set_window()"
 744                                " Unknown address range!\n",
 745                                netxen_nic_driver_name);
 746
 747         }
 748         return addr;
 749 }
 750
 751 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
 752 {
 753         int rv = 0;
 754         int addr = BRDCFG_START;
 755         struct netxen_board_info *boardinfo;
 756         int index;
 757         u32 *ptr32;
 758
 759         boardinfo = &adapter->ahw.boardcfg;
 760         ptr32 = (u32 *) boardinfo;
 761
 762         for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
 763              index++) {
 764                 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
 765                         return -EIO;
 766                 }
 767                 ptr32++;
 768                 addr += sizeof(u32);
 769         }
 770         if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
 771                 printk("%s: ERROR reading %s board config."
 772                        " Read %x, expected %x\n", netxen_nic_driver_name,
 773                        netxen_nic_driver_name,
 774                        boardinfo->magic, NETXEN_BDINFO_MAGIC);
 775                 rv = -1;
 776         }
 777         if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
 778                 printk("%s: Unknown board config version."
 779                        " Read %x, expected %x\n", netxen_nic_driver_name,
 780                        boardinfo->header_version, NETXEN_BDINFO_VERSION);
 781                 rv = -1;
 782         }
 783
 784         DPRINTK(INFO, "Discovered board type:0x%x  ", boardinfo->board_type);
 785         switch ((netxen_brdtype_t) boardinfo->board_type) {
 786         case NETXEN_BRDTYPE_P2_SB35_4G:
 787                 adapter->ahw.board_type = NETXEN_NIC_GBE;
 788                 break;
 789         case NETXEN_BRDTYPE_P2_SB31_10G:
 790         case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
 791         case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
 792         case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
 793                 adapter->ahw.board_type = NETXEN_NIC_XGBE;
 794                 break;
 795         case NETXEN_BRDTYPE_P1_BD:
 796         case NETXEN_BRDTYPE_P1_SB:
 797         case NETXEN_BRDTYPE_P1_SMAX:
 798         case NETXEN_BRDTYPE_P1_SOCK:
 799                 adapter->ahw.board_type = NETXEN_NIC_GBE;
 800                 break;
 801         default:
 802                 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
 803                        boardinfo->board_type);
 804                 break;
 805         }
 806
 807         return rv;
 808 }
 809
 810 /* NIU access sections */
 811
 812 int netxen_nic_set_mtu_gb(struct netxen_port *port, int new_mtu)
 813 {
 814         struct netxen_adapter *adapter = port->adapter;
 815         netxen_nic_write_w0(adapter,
 816                             NETXEN_NIU_GB_MAX_FRAME_SIZE(port->portnum),
 817                             new_mtu);
 818         return 0;
 819 }
 820
 821 int netxen_nic_set_mtu_xgb(struct netxen_port *port, int new_mtu)
 822 {
 823         struct netxen_adapter *adapter = port->adapter;
 824         new_mtu += NETXEN_NIU_HDRSIZE + NETXEN_NIU_TLRSIZE;
 825         netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
 826         return 0;
 827 }
 828
 829 void netxen_nic_init_niu_gb(struct netxen_adapter *adapter)
 830 {
 831         int portno;
 832         for (portno = 0; portno < NETXEN_NIU_MAX_GBE_PORTS; portno++)
 833                 netxen_niu_gbe_init_port(adapter, portno);
 834 }
 835
 836 void netxen_nic_stop_all_ports(struct netxen_adapter *adapter)
 837 {
 838         int port_nr;
 839         struct netxen_port *port;
 840
 841         for (port_nr = 0; port_nr < adapter->ahw.max_ports; port_nr++) {
 842                 port = adapter->port[port_nr];
 843                 if (adapter->stop_port)
 844                         adapter->stop_port(adapter, port->portnum);
 845         }
 846 }
 847
 848 void
 849 netxen_crb_writelit_adapter(struct netxen_adapter *adapter, unsigned long off,
 850                             int data)
 851 {
 852         void __iomem *addr;
 853
 854         if (ADDR_IN_WINDOW1(off)) {
 855                 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
 856         } else {
 857                 netxen_nic_pci_change_crbwindow(adapter, 0);
 858                 addr = pci_base_offset(adapter, off);
 859                 writel(data, addr);
 860                 netxen_nic_pci_change_crbwindow(adapter, 1);
 861         }
 862 }
 863
 864 void netxen_nic_set_link_parameters(struct netxen_port *port)
 865 {
 866         struct netxen_adapter *adapter = port->adapter;
 867         __u32 status;
 868         __u32 autoneg;
 869         __u32 mode;
 870
 871         netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
 872         if (netxen_get_niu_enable_ge(mode)) {   /* Gb 10/100/1000 Mbps mode */
 873                 if (adapter->phy_read
 874                     && adapter->
 875                     phy_read(adapter, port->portnum,
 876                              NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
 877                              &status) == 0) {
 878                         if (netxen_get_phy_link(status)) {
 879                                 switch (netxen_get_phy_speed(status)) {
 880                                 case 0:
 881                                         port->link_speed = SPEED_10;
 882                                         break;
 883                                 case 1:
 884                                         port->link_speed = SPEED_100;
 885                                         break;
 886                                 case 2:
 887                                         port->link_speed = SPEED_1000;
 888                                         break;
 889                                 default:
 890                                         port->link_speed = -1;
 891                                         break;
 892                                 }
 893                                 switch (netxen_get_phy_duplex(status)) {
 894                                 case 0:
 895                                         port->link_duplex = DUPLEX_HALF;
 896                                         break;
 897                                 case 1:
 898                                         port->link_duplex = DUPLEX_FULL;
 899                                         break;
 900                                 default:
 901                                         port->link_duplex = -1;
 902                                         break;
 903                                 }
 904                                 if (adapter->phy_read
 905                                     && adapter->
 906                                     phy_read(adapter, port->portnum,
 907                                              NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
 908                                              &autoneg) != 0)
 909                                         port->link_autoneg = autoneg;
 910                         } else
 911                                 goto link_down;
 912                 } else {
 913                       link_down:
 914                         port->link_speed = -1;
 915                         port->link_duplex = -1;
 916                 }
 917         }
 918 }
 919
 920 void netxen_nic_flash_print(struct netxen_adapter *adapter)
 921 {
 922         int valid = 1;
 923         u32 fw_major = 0;
 924         u32 fw_minor = 0;
 925         u32 fw_build = 0;
 926         char brd_name[NETXEN_MAX_SHORT_NAME];
 927         struct netxen_new_user_info user_info;
 928         int i, addr = USER_START;
 929         u32 *ptr32;
 930
 931         struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
 932         if (board_info->magic != NETXEN_BDINFO_MAGIC) {
 933                 printk
 934                     ("NetXen Unknown board config, Read 0x%x expected as 0x%x\n",
 935                      board_info->magic, NETXEN_BDINFO_MAGIC);
 936                 valid = 0;
 937         }
 938         if (board_info->header_version != NETXEN_BDINFO_VERSION) {
 939                 printk("NetXen Unknown board config version."
 940                        " Read %x, expected %x\n",
 941                        board_info->header_version, NETXEN_BDINFO_VERSION);
 942                 valid = 0;
 943         }
 944         if (valid) {
 945                 ptr32 = (u32 *) & user_info;
 946                 for (i = 0;
 947                      i < sizeof(struct netxen_new_user_info) / sizeof(u32);
 948                      i++) {
 949                         if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
 950                                 printk("%s: ERROR reading %s board userarea.\n",
 951                                        netxen_nic_driver_name,
 952                                        netxen_nic_driver_name);
 953                                 return;
 954                         }
 955                         *ptr32 = le32_to_cpu(*ptr32);
 956                         ptr32++;
 957                         addr += sizeof(u32);
 958                 }
 959                 get_brd_name_by_type(board_info->board_type, brd_name);
 960
 961                 printk("NetXen %s Board S/N %s  Chip id 0x%x\n",
 962                        brd_name, user_info.serial_num, board_info->chip_id);
 963
 964                 printk("NetXen %s Board #%d, Chip id 0x%x\n",
 965                        board_info->board_type == 0x0b ? "XGB" : "GBE",
 966                        board_info->board_num, board_info->chip_id);
 967                 fw_major = readl(NETXEN_CRB_NORMALIZE(adapter,
 968                                                       NETXEN_FW_VERSION_MAJOR));
 969                 fw_minor = readl(NETXEN_CRB_NORMALIZE(adapter,
 970                                                       NETXEN_FW_VERSION_MINOR));
 971                 fw_build =
 972                     readl(NETXEN_CRB_NORMALIZE(adapter, NETXEN_FW_VERSION_SUB));
 973
 974                 printk("NetXen Firmware version %d.%d.%d\n", fw_major, fw_minor,
 975                        fw_build);
 976         }
 977         if (fw_major != _NETXEN_NIC_LINUX_MAJOR) {
 978                 printk(KERN_ERR "The mismatch in driver version and firmware "
 979                        "version major number\n"
 980                        "Driver version major number = %d \t"
 981                        "Firmware version major number = %d \n",
 982                        _NETXEN_NIC_LINUX_MAJOR, fw_major);
 983                 adapter->driver_mismatch = 1;
 984         }
 985         if (fw_minor != _NETXEN_NIC_LINUX_MINOR &&
 986                         fw_minor != (_NETXEN_NIC_LINUX_MINOR + 1)) {
 987                 printk(KERN_ERR "The mismatch in driver version and firmware "
 988                        "version minor number\n"
 989                        "Driver version minor number = %d \t"
 990                        "Firmware version minor number = %d \n",
 991                        _NETXEN_NIC_LINUX_MINOR, fw_minor);
 992                 adapter->driver_mismatch = 1;
 993         }
 994         if (adapter->driver_mismatch)
 995                 printk(KERN_INFO "Use the driver with version no %d.%d.xxx\n",
 996                        fw_major, fw_minor);
 997 }
 998