2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
8 * See MAINTAINERS file for support contact information.
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
27 #include <asm/system.h>
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
36 #define assert(expr) \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work
= 20;
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit
= 32;
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
64 #define MAX_READ_REQUEST_SHIFT 12
65 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
68 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
69 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73 #define R8169_REGS_SIZE 256
74 #define R8169_NAPI_WEIGHT 64
75 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82 #define RTL8169_PHY_TIMEOUT (10*HZ)
84 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
86 #define RTL_EEPROM_SIG_ADDR 0x0000
88 /* write/read MMIO register */
89 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92 #define RTL_R8(reg) readb (ioaddr + (reg))
93 #define RTL_R16(reg) readw (ioaddr + (reg))
94 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
97 RTL_GIGA_MAC_VER_01
= 0x01, // 8169
98 RTL_GIGA_MAC_VER_02
= 0x02, // 8169S
99 RTL_GIGA_MAC_VER_03
= 0x03, // 8110S
100 RTL_GIGA_MAC_VER_04
= 0x04, // 8169SB
101 RTL_GIGA_MAC_VER_05
= 0x05, // 8110SCd
102 RTL_GIGA_MAC_VER_06
= 0x06, // 8110SCe
103 RTL_GIGA_MAC_VER_07
= 0x07, // 8102e
104 RTL_GIGA_MAC_VER_08
= 0x08, // 8102e
105 RTL_GIGA_MAC_VER_09
= 0x09, // 8102e
106 RTL_GIGA_MAC_VER_10
= 0x0a, // 8101e
107 RTL_GIGA_MAC_VER_11
= 0x0b, // 8168Bb
108 RTL_GIGA_MAC_VER_12
= 0x0c, // 8168Be
109 RTL_GIGA_MAC_VER_13
= 0x0d, // 8101Eb
110 RTL_GIGA_MAC_VER_14
= 0x0e, // 8101 ?
111 RTL_GIGA_MAC_VER_15
= 0x0f, // 8101 ?
112 RTL_GIGA_MAC_VER_16
= 0x11, // 8101Ec
113 RTL_GIGA_MAC_VER_17
= 0x10, // 8168Bf
114 RTL_GIGA_MAC_VER_18
= 0x12, // 8168CP
115 RTL_GIGA_MAC_VER_19
= 0x13, // 8168C
116 RTL_GIGA_MAC_VER_20
= 0x14, // 8168C
117 RTL_GIGA_MAC_VER_21
= 0x15, // 8168C
118 RTL_GIGA_MAC_VER_22
= 0x16, // 8168C
119 RTL_GIGA_MAC_VER_23
= 0x17, // 8168CP
120 RTL_GIGA_MAC_VER_24
= 0x18, // 8168CP
121 RTL_GIGA_MAC_VER_25
= 0x19 // 8168D
124 #define _R(NAME,MAC,MASK) \
125 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
127 static const struct {
130 u32 RxConfigMask
; /* Clears the bits supported by this chip */
131 } rtl_chip_info
[] = {
132 _R("RTL8169", RTL_GIGA_MAC_VER_01
, 0xff7e1880), // 8169
133 _R("RTL8169s", RTL_GIGA_MAC_VER_02
, 0xff7e1880), // 8169S
134 _R("RTL8110s", RTL_GIGA_MAC_VER_03
, 0xff7e1880), // 8110S
135 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04
, 0xff7e1880), // 8169SB
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05
, 0xff7e1880), // 8110SCd
137 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06
, 0xff7e1880), // 8110SCe
138 _R("RTL8102e", RTL_GIGA_MAC_VER_07
, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_08
, 0xff7e1880), // PCI-E
140 _R("RTL8102e", RTL_GIGA_MAC_VER_09
, 0xff7e1880), // PCI-E
141 _R("RTL8101e", RTL_GIGA_MAC_VER_10
, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11
, 0xff7e1880), // PCI-E
143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12
, 0xff7e1880), // PCI-E
144 _R("RTL8101e", RTL_GIGA_MAC_VER_13
, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_14
, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_15
, 0xff7e1880), // PCI-E 8139
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17
, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_16
, 0xff7e1880), // PCI-E
149 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18
, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19
, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20
, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21
, 0xff7e1880), // PCI-E
153 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22
, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23
, 0xff7e1880), // PCI-E
155 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24
, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25
, 0xff7e1880) // PCI-E
166 static void rtl_hw_start_8169(struct net_device
*);
167 static void rtl_hw_start_8168(struct net_device
*);
168 static void rtl_hw_start_8101(struct net_device
*);
170 static struct pci_device_id rtl8169_pci_tbl
[] = {
171 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8129), 0, 0, RTL_CFG_0
},
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8136), 0, 0, RTL_CFG_2
},
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8167), 0, 0, RTL_CFG_0
},
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8168), 0, 0, RTL_CFG_1
},
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK
, 0x8169), 0, 0, RTL_CFG_0
},
176 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4300), 0, 0, RTL_CFG_0
},
177 { PCI_DEVICE(PCI_VENDOR_ID_AT
, 0xc107), 0, 0, RTL_CFG_0
},
178 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0
},
179 { PCI_VENDOR_ID_LINKSYS
, 0x1032,
180 PCI_ANY_ID
, 0x0024, 0, 0, RTL_CFG_0
},
182 PCI_ANY_ID
, 0x2410, 0, 0, RTL_CFG_2
},
186 MODULE_DEVICE_TABLE(pci
, rtl8169_pci_tbl
);
188 static int rx_copybreak
= 200;
195 MAC0
= 0, /* Ethernet hardware address. */
197 MAR0
= 8, /* Multicast filter. */
198 CounterAddrLow
= 0x10,
199 CounterAddrHigh
= 0x14,
200 TxDescStartAddrLow
= 0x20,
201 TxDescStartAddrHigh
= 0x24,
202 TxHDescStartAddrLow
= 0x28,
203 TxHDescStartAddrHigh
= 0x2c,
226 RxDescAddrLow
= 0xe4,
227 RxDescAddrHigh
= 0xe8,
230 FuncEventMask
= 0xf4,
231 FuncPresetState
= 0xf8,
232 FuncForceEvent
= 0xfc,
235 enum rtl8110_registers
{
241 enum rtl8168_8101_registers
{
244 #define CSIAR_FLAG 0x80000000
245 #define CSIAR_WRITE_CMD 0x80000000
246 #define CSIAR_BYTE_ENABLE 0x0f
247 #define CSIAR_BYTE_ENABLE_SHIFT 12
248 #define CSIAR_ADDR_MASK 0x0fff
251 #define EPHYAR_FLAG 0x80000000
252 #define EPHYAR_WRITE_CMD 0x80000000
253 #define EPHYAR_REG_MASK 0x1f
254 #define EPHYAR_REG_SHIFT 16
255 #define EPHYAR_DATA_MASK 0xffff
257 #define FIX_NAK_1 (1 << 4)
258 #define FIX_NAK_2 (1 << 3)
261 enum rtl_register_content
{
262 /* InterruptStatusBits */
266 TxDescUnavail
= 0x0080,
288 /* TXPoll register p.5 */
289 HPQ
= 0x80, /* Poll cmd on the high prio queue */
290 NPQ
= 0x40, /* Poll cmd on the low prio queue */
291 FSWInt
= 0x01, /* Forced software interrupt */
295 Cfg9346_Unlock
= 0xc0,
300 AcceptBroadcast
= 0x08,
301 AcceptMulticast
= 0x04,
303 AcceptAllPhys
= 0x01,
310 TxInterFrameGapShift
= 24,
311 TxDMAShift
= 8, /* DMA burst value (0-7) is shift this many bits */
313 /* Config1 register p.24 */
316 MSIEnable
= (1 << 5), /* Enable Message Signaled Interrupt */
317 Speed_down
= (1 << 4),
321 PMEnable
= (1 << 0), /* Power Management Enable */
323 /* Config2 register p. 25 */
324 PCI_Clock_66MHz
= 0x01,
325 PCI_Clock_33MHz
= 0x00,
327 /* Config3 register p.25 */
328 MagicPacket
= (1 << 5), /* Wake up when receives a Magic Packet */
329 LinkUp
= (1 << 4), /* Wake up when the cable connection is re-established */
330 Beacon_en
= (1 << 0), /* 8168 only. Reserved in the 8168b */
332 /* Config5 register p.27 */
333 BWF
= (1 << 6), /* Accept Broadcast wakeup frame */
334 MWF
= (1 << 5), /* Accept Multicast wakeup frame */
335 UWF
= (1 << 4), /* Accept Unicast wakeup frame */
336 LanWake
= (1 << 1), /* LanWake enable/disable */
337 PMEStatus
= (1 << 0), /* PME status can be reset by PCI RST# */
340 TBIReset
= 0x80000000,
341 TBILoopback
= 0x40000000,
342 TBINwEnable
= 0x20000000,
343 TBINwRestart
= 0x10000000,
344 TBILinkOk
= 0x02000000,
345 TBINwComplete
= 0x01000000,
348 EnableBist
= (1 << 15), // 8168 8101
349 Mac_dbgo_oe
= (1 << 14), // 8168 8101
350 Normal_mode
= (1 << 13), // unused
351 Force_half_dup
= (1 << 12), // 8168 8101
352 Force_rxflow_en
= (1 << 11), // 8168 8101
353 Force_txflow_en
= (1 << 10), // 8168 8101
354 Cxpl_dbg_sel
= (1 << 9), // 8168 8101
355 ASF
= (1 << 8), // 8168 8101
356 PktCntrDisable
= (1 << 7), // 8168 8101
357 Mac_dbgo_sel
= 0x001c, // 8168
362 INTT_0
= 0x0000, // 8168
363 INTT_1
= 0x0001, // 8168
364 INTT_2
= 0x0002, // 8168
365 INTT_3
= 0x0003, // 8168
367 /* rtl8169_PHYstatus */
378 TBILinkOK
= 0x02000000,
380 /* DumpCounterCommand */
384 enum desc_status_bit
{
385 DescOwn
= (1 << 31), /* Descriptor is owned by NIC */
386 RingEnd
= (1 << 30), /* End of descriptor ring */
387 FirstFrag
= (1 << 29), /* First segment of a packet */
388 LastFrag
= (1 << 28), /* Final segment of a packet */
391 LargeSend
= (1 << 27), /* TCP Large Send Offload (TSO) */
392 MSSShift
= 16, /* MSS value position */
393 MSSMask
= 0xfff, /* MSS value + LargeSend bit: 12 bits */
394 IPCS
= (1 << 18), /* Calculate IP checksum */
395 UDPCS
= (1 << 17), /* Calculate UDP/IP checksum */
396 TCPCS
= (1 << 16), /* Calculate TCP/IP checksum */
397 TxVlanTag
= (1 << 17), /* Add VLAN tag */
400 PID1
= (1 << 18), /* Protocol ID bit 1/2 */
401 PID0
= (1 << 17), /* Protocol ID bit 2/2 */
403 #define RxProtoUDP (PID1)
404 #define RxProtoTCP (PID0)
405 #define RxProtoIP (PID1 | PID0)
406 #define RxProtoMask RxProtoIP
408 IPFail
= (1 << 16), /* IP checksum failed */
409 UDPFail
= (1 << 15), /* UDP/IP checksum failed */
410 TCPFail
= (1 << 14), /* TCP/IP checksum failed */
411 RxVlanTag
= (1 << 16), /* VLAN tag available */
414 #define RsvdMask 0x3fffc000
431 u8 __pad
[sizeof(void *) - sizeof(u32
)];
435 RTL_FEATURE_WOL
= (1 << 0),
436 RTL_FEATURE_MSI
= (1 << 1),
437 RTL_FEATURE_GMII
= (1 << 2),
440 struct rtl8169_private
{
441 void __iomem
*mmio_addr
; /* memory map physical address */
442 struct pci_dev
*pci_dev
; /* Index of PCI device */
443 struct net_device
*dev
;
444 struct napi_struct napi
;
445 spinlock_t lock
; /* spin lock flag */
449 u32 cur_rx
; /* Index into the Rx descriptor buffer of next Rx pkt. */
450 u32 cur_tx
; /* Index into the Tx descriptor buffer of next Rx pkt. */
453 struct TxDesc
*TxDescArray
; /* 256-aligned Tx descriptor ring */
454 struct RxDesc
*RxDescArray
; /* 256-aligned Rx descriptor ring */
455 dma_addr_t TxPhyAddr
;
456 dma_addr_t RxPhyAddr
;
457 struct sk_buff
*Rx_skbuff
[NUM_RX_DESC
]; /* Rx data buffers */
458 struct ring_info tx_skb
[NUM_TX_DESC
]; /* Tx data buffers */
461 struct timer_list timer
;
466 int phy_auto_nego_reg
;
467 int phy_1000_ctrl_reg
;
468 #ifdef CONFIG_R8169_VLAN
469 struct vlan_group
*vlgrp
;
471 int (*set_speed
)(struct net_device
*, u8 autoneg
, u16 speed
, u8 duplex
);
472 int (*get_settings
)(struct net_device
*, struct ethtool_cmd
*);
473 void (*phy_reset_enable
)(void __iomem
*);
474 void (*hw_start
)(struct net_device
*);
475 unsigned int (*phy_reset_pending
)(void __iomem
*);
476 unsigned int (*link_ok
)(void __iomem
*);
478 struct delayed_work task
;
481 struct mii_if_info mii
;
484 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
485 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
486 module_param(rx_copybreak
, int, 0);
487 MODULE_PARM_DESC(rx_copybreak
, "Copy breakpoint for copy-only-tiny-frames");
488 module_param(use_dac
, int, 0);
489 MODULE_PARM_DESC(use_dac
, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
490 module_param_named(debug
, debug
.msg_enable
, int, 0);
491 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 16=all)");
492 MODULE_LICENSE("GPL");
493 MODULE_VERSION(RTL8169_VERSION
);
495 static int rtl8169_open(struct net_device
*dev
);
496 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
497 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
);
498 static int rtl8169_init_ring(struct net_device
*dev
);
499 static void rtl_hw_start(struct net_device
*dev
);
500 static int rtl8169_close(struct net_device
*dev
);
501 static void rtl_set_rx_mode(struct net_device
*dev
);
502 static void rtl8169_tx_timeout(struct net_device
*dev
);
503 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
);
504 static int rtl8169_rx_interrupt(struct net_device
*, struct rtl8169_private
*,
505 void __iomem
*, u32 budget
);
506 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
);
507 static void rtl8169_down(struct net_device
*dev
);
508 static void rtl8169_rx_clear(struct rtl8169_private
*tp
);
509 static int rtl8169_poll(struct napi_struct
*napi
, int budget
);
511 static const unsigned int rtl8169_rx_config
=
512 (RX_FIFO_THRESH
<< RxCfgFIFOShift
) | (RX_DMA_BURST
<< RxCfgDMAShift
);
514 static void mdio_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
518 RTL_W32(PHYAR
, 0x80000000 | (reg_addr
& 0x1f) << 16 | (value
& 0xffff));
520 for (i
= 20; i
> 0; i
--) {
522 * Check if the RTL8169 has completed writing to the specified
525 if (!(RTL_R32(PHYAR
) & 0x80000000))
531 static int mdio_read(void __iomem
*ioaddr
, int reg_addr
)
535 RTL_W32(PHYAR
, 0x0 | (reg_addr
& 0x1f) << 16);
537 for (i
= 20; i
> 0; i
--) {
539 * Check if the RTL8169 has completed retrieving data from
540 * the specified MII register.
542 if (RTL_R32(PHYAR
) & 0x80000000) {
543 value
= RTL_R32(PHYAR
) & 0xffff;
551 static void mdio_patch(void __iomem
*ioaddr
, int reg_addr
, int value
)
553 mdio_write(ioaddr
, reg_addr
, mdio_read(ioaddr
, reg_addr
) | value
);
556 static void rtl_mdio_write(struct net_device
*dev
, int phy_id
, int location
,
559 struct rtl8169_private
*tp
= netdev_priv(dev
);
560 void __iomem
*ioaddr
= tp
->mmio_addr
;
562 mdio_write(ioaddr
, location
, val
);
565 static int rtl_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
567 struct rtl8169_private
*tp
= netdev_priv(dev
);
568 void __iomem
*ioaddr
= tp
->mmio_addr
;
570 return mdio_read(ioaddr
, location
);
573 static void rtl_ephy_write(void __iomem
*ioaddr
, int reg_addr
, int value
)
577 RTL_W32(EPHYAR
, EPHYAR_WRITE_CMD
| (value
& EPHYAR_DATA_MASK
) |
578 (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
580 for (i
= 0; i
< 100; i
++) {
581 if (!(RTL_R32(EPHYAR
) & EPHYAR_FLAG
))
587 static u16
rtl_ephy_read(void __iomem
*ioaddr
, int reg_addr
)
592 RTL_W32(EPHYAR
, (reg_addr
& EPHYAR_REG_MASK
) << EPHYAR_REG_SHIFT
);
594 for (i
= 0; i
< 100; i
++) {
595 if (RTL_R32(EPHYAR
) & EPHYAR_FLAG
) {
596 value
= RTL_R32(EPHYAR
) & EPHYAR_DATA_MASK
;
605 static void rtl_csi_write(void __iomem
*ioaddr
, int addr
, int value
)
609 RTL_W32(CSIDR
, value
);
610 RTL_W32(CSIAR
, CSIAR_WRITE_CMD
| (addr
& CSIAR_ADDR_MASK
) |
611 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
613 for (i
= 0; i
< 100; i
++) {
614 if (!(RTL_R32(CSIAR
) & CSIAR_FLAG
))
620 static u32
rtl_csi_read(void __iomem
*ioaddr
, int addr
)
625 RTL_W32(CSIAR
, (addr
& CSIAR_ADDR_MASK
) |
626 CSIAR_BYTE_ENABLE
<< CSIAR_BYTE_ENABLE_SHIFT
);
628 for (i
= 0; i
< 100; i
++) {
629 if (RTL_R32(CSIAR
) & CSIAR_FLAG
) {
630 value
= RTL_R32(CSIDR
);
639 static void rtl8169_irq_mask_and_ack(void __iomem
*ioaddr
)
641 RTL_W16(IntrMask
, 0x0000);
643 RTL_W16(IntrStatus
, 0xffff);
646 static void rtl8169_asic_down(void __iomem
*ioaddr
)
648 RTL_W8(ChipCmd
, 0x00);
649 rtl8169_irq_mask_and_ack(ioaddr
);
653 static unsigned int rtl8169_tbi_reset_pending(void __iomem
*ioaddr
)
655 return RTL_R32(TBICSR
) & TBIReset
;
658 static unsigned int rtl8169_xmii_reset_pending(void __iomem
*ioaddr
)
660 return mdio_read(ioaddr
, MII_BMCR
) & BMCR_RESET
;
663 static unsigned int rtl8169_tbi_link_ok(void __iomem
*ioaddr
)
665 return RTL_R32(TBICSR
) & TBILinkOk
;
668 static unsigned int rtl8169_xmii_link_ok(void __iomem
*ioaddr
)
670 return RTL_R8(PHYstatus
) & LinkStatus
;
673 static void rtl8169_tbi_reset_enable(void __iomem
*ioaddr
)
675 RTL_W32(TBICSR
, RTL_R32(TBICSR
) | TBIReset
);
678 static void rtl8169_xmii_reset_enable(void __iomem
*ioaddr
)
682 val
= mdio_read(ioaddr
, MII_BMCR
) | BMCR_RESET
;
683 mdio_write(ioaddr
, MII_BMCR
, val
& 0xffff);
686 static void rtl8169_check_link_status(struct net_device
*dev
,
687 struct rtl8169_private
*tp
,
688 void __iomem
*ioaddr
)
692 spin_lock_irqsave(&tp
->lock
, flags
);
693 if (tp
->link_ok(ioaddr
)) {
694 netif_carrier_on(dev
);
695 if (netif_msg_ifup(tp
))
696 printk(KERN_INFO PFX
"%s: link up\n", dev
->name
);
698 if (netif_msg_ifdown(tp
))
699 printk(KERN_INFO PFX
"%s: link down\n", dev
->name
);
700 netif_carrier_off(dev
);
702 spin_unlock_irqrestore(&tp
->lock
, flags
);
705 static void rtl8169_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
707 struct rtl8169_private
*tp
= netdev_priv(dev
);
708 void __iomem
*ioaddr
= tp
->mmio_addr
;
713 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
714 wol
->supported
= WAKE_ANY
;
716 spin_lock_irq(&tp
->lock
);
718 options
= RTL_R8(Config1
);
719 if (!(options
& PMEnable
))
722 options
= RTL_R8(Config3
);
723 if (options
& LinkUp
)
724 wol
->wolopts
|= WAKE_PHY
;
725 if (options
& MagicPacket
)
726 wol
->wolopts
|= WAKE_MAGIC
;
728 options
= RTL_R8(Config5
);
730 wol
->wolopts
|= WAKE_UCAST
;
732 wol
->wolopts
|= WAKE_BCAST
;
734 wol
->wolopts
|= WAKE_MCAST
;
737 spin_unlock_irq(&tp
->lock
);
740 static int rtl8169_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
742 struct rtl8169_private
*tp
= netdev_priv(dev
);
743 void __iomem
*ioaddr
= tp
->mmio_addr
;
750 { WAKE_ANY
, Config1
, PMEnable
},
751 { WAKE_PHY
, Config3
, LinkUp
},
752 { WAKE_MAGIC
, Config3
, MagicPacket
},
753 { WAKE_UCAST
, Config5
, UWF
},
754 { WAKE_BCAST
, Config5
, BWF
},
755 { WAKE_MCAST
, Config5
, MWF
},
756 { WAKE_ANY
, Config5
, LanWake
}
759 spin_lock_irq(&tp
->lock
);
761 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
763 for (i
= 0; i
< ARRAY_SIZE(cfg
); i
++) {
764 u8 options
= RTL_R8(cfg
[i
].reg
) & ~cfg
[i
].mask
;
765 if (wol
->wolopts
& cfg
[i
].opt
)
766 options
|= cfg
[i
].mask
;
767 RTL_W8(cfg
[i
].reg
, options
);
770 RTL_W8(Cfg9346
, Cfg9346_Lock
);
773 tp
->features
|= RTL_FEATURE_WOL
;
775 tp
->features
&= ~RTL_FEATURE_WOL
;
776 device_set_wakeup_enable(&tp
->pci_dev
->dev
, wol
->wolopts
);
778 spin_unlock_irq(&tp
->lock
);
783 static void rtl8169_get_drvinfo(struct net_device
*dev
,
784 struct ethtool_drvinfo
*info
)
786 struct rtl8169_private
*tp
= netdev_priv(dev
);
788 strcpy(info
->driver
, MODULENAME
);
789 strcpy(info
->version
, RTL8169_VERSION
);
790 strcpy(info
->bus_info
, pci_name(tp
->pci_dev
));
793 static int rtl8169_get_regs_len(struct net_device
*dev
)
795 return R8169_REGS_SIZE
;
798 static int rtl8169_set_speed_tbi(struct net_device
*dev
,
799 u8 autoneg
, u16 speed
, u8 duplex
)
801 struct rtl8169_private
*tp
= netdev_priv(dev
);
802 void __iomem
*ioaddr
= tp
->mmio_addr
;
806 reg
= RTL_R32(TBICSR
);
807 if ((autoneg
== AUTONEG_DISABLE
) && (speed
== SPEED_1000
) &&
808 (duplex
== DUPLEX_FULL
)) {
809 RTL_W32(TBICSR
, reg
& ~(TBINwEnable
| TBINwRestart
));
810 } else if (autoneg
== AUTONEG_ENABLE
)
811 RTL_W32(TBICSR
, reg
| TBINwEnable
| TBINwRestart
);
813 if (netif_msg_link(tp
)) {
814 printk(KERN_WARNING
"%s: "
815 "incorrect speed setting refused in TBI mode\n",
824 static int rtl8169_set_speed_xmii(struct net_device
*dev
,
825 u8 autoneg
, u16 speed
, u8 duplex
)
827 struct rtl8169_private
*tp
= netdev_priv(dev
);
828 void __iomem
*ioaddr
= tp
->mmio_addr
;
829 int auto_nego
, giga_ctrl
;
831 auto_nego
= mdio_read(ioaddr
, MII_ADVERTISE
);
832 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_10FULL
|
833 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
834 giga_ctrl
= mdio_read(ioaddr
, MII_CTRL1000
);
835 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
837 if (autoneg
== AUTONEG_ENABLE
) {
838 auto_nego
|= (ADVERTISE_10HALF
| ADVERTISE_10FULL
|
839 ADVERTISE_100HALF
| ADVERTISE_100FULL
);
840 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
842 if (speed
== SPEED_10
)
843 auto_nego
|= ADVERTISE_10HALF
| ADVERTISE_10FULL
;
844 else if (speed
== SPEED_100
)
845 auto_nego
|= ADVERTISE_100HALF
| ADVERTISE_100FULL
;
846 else if (speed
== SPEED_1000
)
847 giga_ctrl
|= ADVERTISE_1000FULL
| ADVERTISE_1000HALF
;
849 if (duplex
== DUPLEX_HALF
)
850 auto_nego
&= ~(ADVERTISE_10FULL
| ADVERTISE_100FULL
);
852 if (duplex
== DUPLEX_FULL
)
853 auto_nego
&= ~(ADVERTISE_10HALF
| ADVERTISE_100HALF
);
855 /* This tweak comes straight from Realtek's driver. */
856 if ((speed
== SPEED_100
) && (duplex
== DUPLEX_HALF
) &&
857 ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
858 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
))) {
859 auto_nego
= ADVERTISE_100HALF
| ADVERTISE_CSMA
;
863 /* The 8100e/8101e/8102e do Fast Ethernet only. */
864 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_07
) ||
865 (tp
->mac_version
== RTL_GIGA_MAC_VER_08
) ||
866 (tp
->mac_version
== RTL_GIGA_MAC_VER_09
) ||
867 (tp
->mac_version
== RTL_GIGA_MAC_VER_10
) ||
868 (tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
869 (tp
->mac_version
== RTL_GIGA_MAC_VER_14
) ||
870 (tp
->mac_version
== RTL_GIGA_MAC_VER_15
) ||
871 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
872 if ((giga_ctrl
& (ADVERTISE_1000FULL
| ADVERTISE_1000HALF
)) &&
873 netif_msg_link(tp
)) {
874 printk(KERN_INFO
"%s: PHY does not support 1000Mbps.\n",
877 giga_ctrl
&= ~(ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
880 auto_nego
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
882 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_11
) ||
883 (tp
->mac_version
== RTL_GIGA_MAC_VER_12
) ||
884 (tp
->mac_version
>= RTL_GIGA_MAC_VER_17
)) {
887 * Vendor specific (0x1f) and reserved (0x0e) MII registers.
889 mdio_write(ioaddr
, 0x1f, 0x0000);
890 mdio_write(ioaddr
, 0x0e, 0x0000);
893 tp
->phy_auto_nego_reg
= auto_nego
;
894 tp
->phy_1000_ctrl_reg
= giga_ctrl
;
896 mdio_write(ioaddr
, MII_ADVERTISE
, auto_nego
);
897 mdio_write(ioaddr
, MII_CTRL1000
, giga_ctrl
);
898 mdio_write(ioaddr
, MII_BMCR
, BMCR_ANENABLE
| BMCR_ANRESTART
);
902 static int rtl8169_set_speed(struct net_device
*dev
,
903 u8 autoneg
, u16 speed
, u8 duplex
)
905 struct rtl8169_private
*tp
= netdev_priv(dev
);
908 ret
= tp
->set_speed(dev
, autoneg
, speed
, duplex
);
910 if (netif_running(dev
) && (tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
911 mod_timer(&tp
->timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
916 static int rtl8169_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
918 struct rtl8169_private
*tp
= netdev_priv(dev
);
922 spin_lock_irqsave(&tp
->lock
, flags
);
923 ret
= rtl8169_set_speed(dev
, cmd
->autoneg
, cmd
->speed
, cmd
->duplex
);
924 spin_unlock_irqrestore(&tp
->lock
, flags
);
929 static u32
rtl8169_get_rx_csum(struct net_device
*dev
)
931 struct rtl8169_private
*tp
= netdev_priv(dev
);
933 return tp
->cp_cmd
& RxChkSum
;
936 static int rtl8169_set_rx_csum(struct net_device
*dev
, u32 data
)
938 struct rtl8169_private
*tp
= netdev_priv(dev
);
939 void __iomem
*ioaddr
= tp
->mmio_addr
;
942 spin_lock_irqsave(&tp
->lock
, flags
);
945 tp
->cp_cmd
|= RxChkSum
;
947 tp
->cp_cmd
&= ~RxChkSum
;
949 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
952 spin_unlock_irqrestore(&tp
->lock
, flags
);
957 #ifdef CONFIG_R8169_VLAN
959 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
962 return (tp
->vlgrp
&& vlan_tx_tag_present(skb
)) ?
963 TxVlanTag
| swab16(vlan_tx_tag_get(skb
)) : 0x00;
966 static void rtl8169_vlan_rx_register(struct net_device
*dev
,
967 struct vlan_group
*grp
)
969 struct rtl8169_private
*tp
= netdev_priv(dev
);
970 void __iomem
*ioaddr
= tp
->mmio_addr
;
973 spin_lock_irqsave(&tp
->lock
, flags
);
976 tp
->cp_cmd
|= RxVlan
;
978 tp
->cp_cmd
&= ~RxVlan
;
979 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
981 spin_unlock_irqrestore(&tp
->lock
, flags
);
984 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
987 u32 opts2
= le32_to_cpu(desc
->opts2
);
988 struct vlan_group
*vlgrp
= tp
->vlgrp
;
991 if (vlgrp
&& (opts2
& RxVlanTag
)) {
992 vlan_hwaccel_receive_skb(skb
, vlgrp
, swab16(opts2
& 0xffff));
1000 #else /* !CONFIG_R8169_VLAN */
1002 static inline u32
rtl8169_tx_vlan_tag(struct rtl8169_private
*tp
,
1003 struct sk_buff
*skb
)
1008 static int rtl8169_rx_vlan_skb(struct rtl8169_private
*tp
, struct RxDesc
*desc
,
1009 struct sk_buff
*skb
)
1016 static int rtl8169_gset_tbi(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1018 struct rtl8169_private
*tp
= netdev_priv(dev
);
1019 void __iomem
*ioaddr
= tp
->mmio_addr
;
1023 SUPPORTED_1000baseT_Full
| SUPPORTED_Autoneg
| SUPPORTED_FIBRE
;
1024 cmd
->port
= PORT_FIBRE
;
1025 cmd
->transceiver
= XCVR_INTERNAL
;
1027 status
= RTL_R32(TBICSR
);
1028 cmd
->advertising
= (status
& TBINwEnable
) ? ADVERTISED_Autoneg
: 0;
1029 cmd
->autoneg
= !!(status
& TBINwEnable
);
1031 cmd
->speed
= SPEED_1000
;
1032 cmd
->duplex
= DUPLEX_FULL
; /* Always set */
1037 static int rtl8169_gset_xmii(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1039 struct rtl8169_private
*tp
= netdev_priv(dev
);
1041 return mii_ethtool_gset(&tp
->mii
, cmd
);
1044 static int rtl8169_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1046 struct rtl8169_private
*tp
= netdev_priv(dev
);
1047 unsigned long flags
;
1050 spin_lock_irqsave(&tp
->lock
, flags
);
1052 rc
= tp
->get_settings(dev
, cmd
);
1054 spin_unlock_irqrestore(&tp
->lock
, flags
);
1058 static void rtl8169_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1061 struct rtl8169_private
*tp
= netdev_priv(dev
);
1062 unsigned long flags
;
1064 if (regs
->len
> R8169_REGS_SIZE
)
1065 regs
->len
= R8169_REGS_SIZE
;
1067 spin_lock_irqsave(&tp
->lock
, flags
);
1068 memcpy_fromio(p
, tp
->mmio_addr
, regs
->len
);
1069 spin_unlock_irqrestore(&tp
->lock
, flags
);
1072 static u32
rtl8169_get_msglevel(struct net_device
*dev
)
1074 struct rtl8169_private
*tp
= netdev_priv(dev
);
1076 return tp
->msg_enable
;
1079 static void rtl8169_set_msglevel(struct net_device
*dev
, u32 value
)
1081 struct rtl8169_private
*tp
= netdev_priv(dev
);
1083 tp
->msg_enable
= value
;
1086 static const char rtl8169_gstrings
[][ETH_GSTRING_LEN
] = {
1093 "tx_single_collisions",
1094 "tx_multi_collisions",
1102 struct rtl8169_counters
{
1108 __le16 align_errors
;
1109 __le32 tx_one_collision
;
1110 __le32 tx_multi_collision
;
1112 __le64 rx_broadcast
;
1113 __le32 rx_multicast
;
1118 static int rtl8169_get_sset_count(struct net_device
*dev
, int sset
)
1122 return ARRAY_SIZE(rtl8169_gstrings
);
1128 static void rtl8169_get_ethtool_stats(struct net_device
*dev
,
1129 struct ethtool_stats
*stats
, u64
*data
)
1131 struct rtl8169_private
*tp
= netdev_priv(dev
);
1132 void __iomem
*ioaddr
= tp
->mmio_addr
;
1133 struct rtl8169_counters
*counters
;
1139 counters
= pci_alloc_consistent(tp
->pci_dev
, sizeof(*counters
), &paddr
);
1143 RTL_W32(CounterAddrHigh
, (u64
)paddr
>> 32);
1144 cmd
= (u64
)paddr
& DMA_32BIT_MASK
;
1145 RTL_W32(CounterAddrLow
, cmd
);
1146 RTL_W32(CounterAddrLow
, cmd
| CounterDump
);
1148 while (RTL_R32(CounterAddrLow
) & CounterDump
) {
1149 if (msleep_interruptible(1))
1153 RTL_W32(CounterAddrLow
, 0);
1154 RTL_W32(CounterAddrHigh
, 0);
1156 data
[0] = le64_to_cpu(counters
->tx_packets
);
1157 data
[1] = le64_to_cpu(counters
->rx_packets
);
1158 data
[2] = le64_to_cpu(counters
->tx_errors
);
1159 data
[3] = le32_to_cpu(counters
->rx_errors
);
1160 data
[4] = le16_to_cpu(counters
->rx_missed
);
1161 data
[5] = le16_to_cpu(counters
->align_errors
);
1162 data
[6] = le32_to_cpu(counters
->tx_one_collision
);
1163 data
[7] = le32_to_cpu(counters
->tx_multi_collision
);
1164 data
[8] = le64_to_cpu(counters
->rx_unicast
);
1165 data
[9] = le64_to_cpu(counters
->rx_broadcast
);
1166 data
[10] = le32_to_cpu(counters
->rx_multicast
);
1167 data
[11] = le16_to_cpu(counters
->tx_aborted
);
1168 data
[12] = le16_to_cpu(counters
->tx_underun
);
1170 pci_free_consistent(tp
->pci_dev
, sizeof(*counters
), counters
, paddr
);
1173 static void rtl8169_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1177 memcpy(data
, *rtl8169_gstrings
, sizeof(rtl8169_gstrings
));
1182 static const struct ethtool_ops rtl8169_ethtool_ops
= {
1183 .get_drvinfo
= rtl8169_get_drvinfo
,
1184 .get_regs_len
= rtl8169_get_regs_len
,
1185 .get_link
= ethtool_op_get_link
,
1186 .get_settings
= rtl8169_get_settings
,
1187 .set_settings
= rtl8169_set_settings
,
1188 .get_msglevel
= rtl8169_get_msglevel
,
1189 .set_msglevel
= rtl8169_set_msglevel
,
1190 .get_rx_csum
= rtl8169_get_rx_csum
,
1191 .set_rx_csum
= rtl8169_set_rx_csum
,
1192 .set_tx_csum
= ethtool_op_set_tx_csum
,
1193 .set_sg
= ethtool_op_set_sg
,
1194 .set_tso
= ethtool_op_set_tso
,
1195 .get_regs
= rtl8169_get_regs
,
1196 .get_wol
= rtl8169_get_wol
,
1197 .set_wol
= rtl8169_set_wol
,
1198 .get_strings
= rtl8169_get_strings
,
1199 .get_sset_count
= rtl8169_get_sset_count
,
1200 .get_ethtool_stats
= rtl8169_get_ethtool_stats
,
1203 static void rtl8169_write_gmii_reg_bit(void __iomem
*ioaddr
, int reg
,
1204 int bitnum
, int bitval
)
1208 val
= mdio_read(ioaddr
, reg
);
1209 val
= (bitval
== 1) ?
1210 val
| (bitval
<< bitnum
) : val
& ~(0x0001 << bitnum
);
1211 mdio_write(ioaddr
, reg
, val
& 0xffff);
1214 static void rtl8169_get_mac_version(struct rtl8169_private
*tp
,
1215 void __iomem
*ioaddr
)
1218 * The driver currently handles the 8168Bf and the 8168Be identically
1219 * but they can be identified more specifically through the test below
1222 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1224 * Same thing for the 8101Eb and the 8101Ec:
1226 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1234 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25
},
1237 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24
},
1238 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23
},
1239 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18
},
1240 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24
},
1241 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19
},
1242 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20
},
1243 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21
},
1244 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22
},
1245 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22
},
1248 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12
},
1249 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17
},
1250 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17
},
1251 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11
},
1254 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09
},
1255 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09
},
1256 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08
},
1257 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08
},
1258 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07
},
1259 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07
},
1260 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13
},
1261 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10
},
1262 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16
},
1263 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09
},
1264 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09
},
1265 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16
},
1266 /* FIXME: where did these entries come from ? -- FR */
1267 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15
},
1268 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14
},
1271 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06
},
1272 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05
},
1273 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04
},
1274 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03
},
1275 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02
},
1276 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01
},
1278 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01
} /* Catch-all */
1282 reg
= RTL_R32(TxConfig
);
1283 while ((reg
& p
->mask
) != p
->val
)
1285 tp
->mac_version
= p
->mac_version
;
1287 if (p
->mask
== 0x00000000) {
1288 struct pci_dev
*pdev
= tp
->pci_dev
;
1290 dev_info(&pdev
->dev
, "unknown MAC (%08x)\n", reg
);
1294 static void rtl8169_print_mac_version(struct rtl8169_private
*tp
)
1296 dprintk("mac_version = 0x%02x\n", tp
->mac_version
);
1304 static void rtl_phy_write(void __iomem
*ioaddr
, struct phy_reg
*regs
, int len
)
1307 mdio_write(ioaddr
, regs
->reg
, regs
->val
);
1312 static void rtl8169s_hw_phy_config(void __iomem
*ioaddr
)
1315 u16 regs
[5]; /* Beware of bit-sign propagation */
1316 } phy_magic
[5] = { {
1317 { 0x0000, //w 4 15 12 0
1318 0x00a1, //w 3 15 0 00a1
1319 0x0008, //w 2 15 0 0008
1320 0x1020, //w 1 15 0 1020
1321 0x1000 } },{ //w 0 15 0 1000
1322 { 0x7000, //w 4 15 12 7
1323 0xff41, //w 3 15 0 ff41
1324 0xde60, //w 2 15 0 de60
1325 0x0140, //w 1 15 0 0140
1326 0x0077 } },{ //w 0 15 0 0077
1327 { 0xa000, //w 4 15 12 a
1328 0xdf01, //w 3 15 0 df01
1329 0xdf20, //w 2 15 0 df20
1330 0xff95, //w 1 15 0 ff95
1331 0xfa00 } },{ //w 0 15 0 fa00
1332 { 0xb000, //w 4 15 12 b
1333 0xff41, //w 3 15 0 ff41
1334 0xde20, //w 2 15 0 de20
1335 0x0140, //w 1 15 0 0140
1336 0x00bb } },{ //w 0 15 0 00bb
1337 { 0xf000, //w 4 15 12 f
1338 0xdf01, //w 3 15 0 df01
1339 0xdf20, //w 2 15 0 df20
1340 0xff95, //w 1 15 0 ff95
1341 0xbf00 } //w 0 15 0 bf00
1346 mdio_write(ioaddr
, 0x1f, 0x0001); //w 31 2 0 1
1347 mdio_write(ioaddr
, 0x15, 0x1000); //w 21 15 0 1000
1348 mdio_write(ioaddr
, 0x18, 0x65c7); //w 24 15 0 65c7
1349 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1351 for (i
= 0; i
< ARRAY_SIZE(phy_magic
); i
++, p
++) {
1354 val
= (mdio_read(ioaddr
, pos
) & 0x0fff) | (p
->regs
[0] & 0xffff);
1355 mdio_write(ioaddr
, pos
, val
);
1357 mdio_write(ioaddr
, pos
, p
->regs
[4 - pos
] & 0xffff);
1358 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 1); //w 4 11 11 1
1359 rtl8169_write_gmii_reg_bit(ioaddr
, 4, 11, 0); //w 4 11 11 0
1361 mdio_write(ioaddr
, 0x1f, 0x0000); //w 31 2 0 0
1364 static void rtl8169sb_hw_phy_config(void __iomem
*ioaddr
)
1366 struct phy_reg phy_reg_init
[] = {
1372 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1375 static void rtl8168bb_hw_phy_config(void __iomem
*ioaddr
)
1377 struct phy_reg phy_reg_init
[] = {
1382 mdio_write(ioaddr
, 0x1f, 0x0001);
1383 mdio_patch(ioaddr
, 0x16, 1 << 0);
1385 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1388 static void rtl8168bef_hw_phy_config(void __iomem
*ioaddr
)
1390 struct phy_reg phy_reg_init
[] = {
1396 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1399 static void rtl8168cp_1_hw_phy_config(void __iomem
*ioaddr
)
1401 struct phy_reg phy_reg_init
[] = {
1409 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1412 static void rtl8168cp_2_hw_phy_config(void __iomem
*ioaddr
)
1414 struct phy_reg phy_reg_init
[] = {
1420 mdio_write(ioaddr
, 0x1f, 0x0000);
1421 mdio_patch(ioaddr
, 0x14, 1 << 5);
1422 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1424 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1427 static void rtl8168c_1_hw_phy_config(void __iomem
*ioaddr
)
1429 struct phy_reg phy_reg_init
[] = {
1449 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1451 mdio_patch(ioaddr
, 0x14, 1 << 5);
1452 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1453 mdio_write(ioaddr
, 0x1f, 0x0000);
1456 static void rtl8168c_2_hw_phy_config(void __iomem
*ioaddr
)
1458 struct phy_reg phy_reg_init
[] = {
1476 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1478 mdio_patch(ioaddr
, 0x16, 1 << 0);
1479 mdio_patch(ioaddr
, 0x14, 1 << 5);
1480 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1481 mdio_write(ioaddr
, 0x1f, 0x0000);
1484 static void rtl8168c_3_hw_phy_config(void __iomem
*ioaddr
)
1486 struct phy_reg phy_reg_init
[] = {
1498 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1500 mdio_patch(ioaddr
, 0x16, 1 << 0);
1501 mdio_patch(ioaddr
, 0x14, 1 << 5);
1502 mdio_patch(ioaddr
, 0x0d, 1 << 5);
1503 mdio_write(ioaddr
, 0x1f, 0x0000);
1506 static void rtl8168c_4_hw_phy_config(void __iomem
*ioaddr
)
1508 rtl8168c_3_hw_phy_config(ioaddr
);
1511 static void rtl8168d_hw_phy_config(void __iomem
*ioaddr
)
1513 struct phy_reg phy_reg_init_0
[] = {
1539 rtl_phy_write(ioaddr
, phy_reg_init_0
, ARRAY_SIZE(phy_reg_init_0
));
1541 if (mdio_read(ioaddr
, 0x06) == 0xc400) {
1542 struct phy_reg phy_reg_init_1
[] = {
1574 rtl_phy_write(ioaddr
, phy_reg_init_1
,
1575 ARRAY_SIZE(phy_reg_init_1
));
1578 mdio_write(ioaddr
, 0x1f, 0x0000);
1581 static void rtl8102e_hw_phy_config(void __iomem
*ioaddr
)
1583 struct phy_reg phy_reg_init
[] = {
1590 mdio_write(ioaddr
, 0x1f, 0x0000);
1591 mdio_patch(ioaddr
, 0x11, 1 << 12);
1592 mdio_patch(ioaddr
, 0x19, 1 << 13);
1594 rtl_phy_write(ioaddr
, phy_reg_init
, ARRAY_SIZE(phy_reg_init
));
1597 static void rtl_hw_phy_config(struct net_device
*dev
)
1599 struct rtl8169_private
*tp
= netdev_priv(dev
);
1600 void __iomem
*ioaddr
= tp
->mmio_addr
;
1602 rtl8169_print_mac_version(tp
);
1604 switch (tp
->mac_version
) {
1605 case RTL_GIGA_MAC_VER_01
:
1607 case RTL_GIGA_MAC_VER_02
:
1608 case RTL_GIGA_MAC_VER_03
:
1609 rtl8169s_hw_phy_config(ioaddr
);
1611 case RTL_GIGA_MAC_VER_04
:
1612 rtl8169sb_hw_phy_config(ioaddr
);
1614 case RTL_GIGA_MAC_VER_07
:
1615 case RTL_GIGA_MAC_VER_08
:
1616 case RTL_GIGA_MAC_VER_09
:
1617 rtl8102e_hw_phy_config(ioaddr
);
1619 case RTL_GIGA_MAC_VER_11
:
1620 rtl8168bb_hw_phy_config(ioaddr
);
1622 case RTL_GIGA_MAC_VER_12
:
1623 rtl8168bef_hw_phy_config(ioaddr
);
1625 case RTL_GIGA_MAC_VER_17
:
1626 rtl8168bef_hw_phy_config(ioaddr
);
1628 case RTL_GIGA_MAC_VER_18
:
1629 rtl8168cp_1_hw_phy_config(ioaddr
);
1631 case RTL_GIGA_MAC_VER_19
:
1632 rtl8168c_1_hw_phy_config(ioaddr
);
1634 case RTL_GIGA_MAC_VER_20
:
1635 rtl8168c_2_hw_phy_config(ioaddr
);
1637 case RTL_GIGA_MAC_VER_21
:
1638 rtl8168c_3_hw_phy_config(ioaddr
);
1640 case RTL_GIGA_MAC_VER_22
:
1641 rtl8168c_4_hw_phy_config(ioaddr
);
1643 case RTL_GIGA_MAC_VER_23
:
1644 case RTL_GIGA_MAC_VER_24
:
1645 rtl8168cp_2_hw_phy_config(ioaddr
);
1647 case RTL_GIGA_MAC_VER_25
:
1648 rtl8168d_hw_phy_config(ioaddr
);
1656 static void rtl8169_phy_timer(unsigned long __opaque
)
1658 struct net_device
*dev
= (struct net_device
*)__opaque
;
1659 struct rtl8169_private
*tp
= netdev_priv(dev
);
1660 struct timer_list
*timer
= &tp
->timer
;
1661 void __iomem
*ioaddr
= tp
->mmio_addr
;
1662 unsigned long timeout
= RTL8169_PHY_TIMEOUT
;
1664 assert(tp
->mac_version
> RTL_GIGA_MAC_VER_01
);
1666 if (!(tp
->phy_1000_ctrl_reg
& ADVERTISE_1000FULL
))
1669 spin_lock_irq(&tp
->lock
);
1671 if (tp
->phy_reset_pending(ioaddr
)) {
1673 * A busy loop could burn quite a few cycles on nowadays CPU.
1674 * Let's delay the execution of the timer for a few ticks.
1680 if (tp
->link_ok(ioaddr
))
1683 if (netif_msg_link(tp
))
1684 printk(KERN_WARNING
"%s: PHY reset until link up\n", dev
->name
);
1686 tp
->phy_reset_enable(ioaddr
);
1689 mod_timer(timer
, jiffies
+ timeout
);
1691 spin_unlock_irq(&tp
->lock
);
1694 static inline void rtl8169_delete_timer(struct net_device
*dev
)
1696 struct rtl8169_private
*tp
= netdev_priv(dev
);
1697 struct timer_list
*timer
= &tp
->timer
;
1699 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1702 del_timer_sync(timer
);
1705 static inline void rtl8169_request_timer(struct net_device
*dev
)
1707 struct rtl8169_private
*tp
= netdev_priv(dev
);
1708 struct timer_list
*timer
= &tp
->timer
;
1710 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_01
)
1713 mod_timer(timer
, jiffies
+ RTL8169_PHY_TIMEOUT
);
1716 #ifdef CONFIG_NET_POLL_CONTROLLER
1718 * Polling 'interrupt' - used by things like netconsole to send skbs
1719 * without having to re-enable interrupts. It's not called while
1720 * the interrupt routine is executing.
1722 static void rtl8169_netpoll(struct net_device
*dev
)
1724 struct rtl8169_private
*tp
= netdev_priv(dev
);
1725 struct pci_dev
*pdev
= tp
->pci_dev
;
1727 disable_irq(pdev
->irq
);
1728 rtl8169_interrupt(pdev
->irq
, dev
);
1729 enable_irq(pdev
->irq
);
1733 static void rtl8169_release_board(struct pci_dev
*pdev
, struct net_device
*dev
,
1734 void __iomem
*ioaddr
)
1737 pci_release_regions(pdev
);
1738 pci_disable_device(pdev
);
1742 static void rtl8169_phy_reset(struct net_device
*dev
,
1743 struct rtl8169_private
*tp
)
1745 void __iomem
*ioaddr
= tp
->mmio_addr
;
1748 tp
->phy_reset_enable(ioaddr
);
1749 for (i
= 0; i
< 100; i
++) {
1750 if (!tp
->phy_reset_pending(ioaddr
))
1754 if (netif_msg_link(tp
))
1755 printk(KERN_ERR
"%s: PHY reset failed.\n", dev
->name
);
1758 static void rtl8169_init_phy(struct net_device
*dev
, struct rtl8169_private
*tp
)
1760 void __iomem
*ioaddr
= tp
->mmio_addr
;
1762 rtl_hw_phy_config(dev
);
1764 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) {
1765 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1769 pci_write_config_byte(tp
->pci_dev
, PCI_LATENCY_TIMER
, 0x40);
1771 if (tp
->mac_version
<= RTL_GIGA_MAC_VER_06
)
1772 pci_write_config_byte(tp
->pci_dev
, PCI_CACHE_LINE_SIZE
, 0x08);
1774 if (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) {
1775 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1777 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1778 mdio_write(ioaddr
, 0x0b, 0x0000); //w 0x0b 15 0 0
1781 rtl8169_phy_reset(dev
, tp
);
1784 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1785 * only 8101. Don't panic.
1787 rtl8169_set_speed(dev
, AUTONEG_ENABLE
, SPEED_1000
, DUPLEX_FULL
);
1789 if ((RTL_R8(PHYstatus
) & TBI_Enable
) && netif_msg_link(tp
))
1790 printk(KERN_INFO PFX
"%s: TBI auto-negotiating\n", dev
->name
);
1793 static void rtl_rar_set(struct rtl8169_private
*tp
, u8
*addr
)
1795 void __iomem
*ioaddr
= tp
->mmio_addr
;
1799 low
= addr
[0] | (addr
[1] << 8) | (addr
[2] << 16) | (addr
[3] << 24);
1800 high
= addr
[4] | (addr
[5] << 8);
1802 spin_lock_irq(&tp
->lock
);
1804 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1806 RTL_W32(MAC4
, high
);
1807 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1809 spin_unlock_irq(&tp
->lock
);
1812 static int rtl_set_mac_address(struct net_device
*dev
, void *p
)
1814 struct rtl8169_private
*tp
= netdev_priv(dev
);
1815 struct sockaddr
*addr
= p
;
1817 if (!is_valid_ether_addr(addr
->sa_data
))
1818 return -EADDRNOTAVAIL
;
1820 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1822 rtl_rar_set(tp
, dev
->dev_addr
);
1827 static int rtl8169_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1829 struct rtl8169_private
*tp
= netdev_priv(dev
);
1830 struct mii_ioctl_data
*data
= if_mii(ifr
);
1832 if (!netif_running(dev
))
1837 data
->phy_id
= 32; /* Internal PHY */
1841 data
->val_out
= mdio_read(tp
->mmio_addr
, data
->reg_num
& 0x1f);
1845 if (!capable(CAP_NET_ADMIN
))
1847 mdio_write(tp
->mmio_addr
, data
->reg_num
& 0x1f, data
->val_in
);
1853 static const struct rtl_cfg_info
{
1854 void (*hw_start
)(struct net_device
*);
1855 unsigned int region
;
1860 } rtl_cfg_infos
[] = {
1862 .hw_start
= rtl_hw_start_8169
,
1865 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1866 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1867 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1868 .features
= RTL_FEATURE_GMII
1871 .hw_start
= rtl_hw_start_8168
,
1874 .intr_event
= SYSErr
| LinkChg
| RxOverflow
|
1875 TxErr
| TxOK
| RxOK
| RxErr
,
1876 .napi_event
= TxErr
| TxOK
| RxOK
| RxOverflow
,
1877 .features
= RTL_FEATURE_GMII
| RTL_FEATURE_MSI
1880 .hw_start
= rtl_hw_start_8101
,
1883 .intr_event
= SYSErr
| LinkChg
| RxOverflow
| PCSTimeout
|
1884 RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxErr
,
1885 .napi_event
= RxFIFOOver
| TxErr
| TxOK
| RxOK
| RxOverflow
,
1886 .features
= RTL_FEATURE_MSI
1890 /* Cfg9346_Unlock assumed. */
1891 static unsigned rtl_try_msi(struct pci_dev
*pdev
, void __iomem
*ioaddr
,
1892 const struct rtl_cfg_info
*cfg
)
1897 cfg2
= RTL_R8(Config2
) & ~MSIEnable
;
1898 if (cfg
->features
& RTL_FEATURE_MSI
) {
1899 if (pci_enable_msi(pdev
)) {
1900 dev_info(&pdev
->dev
, "no MSI. Back to INTx.\n");
1903 msi
= RTL_FEATURE_MSI
;
1906 RTL_W8(Config2
, cfg2
);
1910 static void rtl_disable_msi(struct pci_dev
*pdev
, struct rtl8169_private
*tp
)
1912 if (tp
->features
& RTL_FEATURE_MSI
) {
1913 pci_disable_msi(pdev
);
1914 tp
->features
&= ~RTL_FEATURE_MSI
;
1918 static int rtl_eeprom_read(struct pci_dev
*pdev
, int cap
, int addr
, __le32
*val
)
1920 int ret
, count
= 100;
1924 ret
= pci_write_config_word(pdev
, cap
+ PCI_VPD_ADDR
, addr
);
1930 ret
= pci_read_config_word(pdev
, cap
+ PCI_VPD_ADDR
, &status
);
1933 } while (!(status
& PCI_VPD_ADDR_F
) && --count
);
1935 if (!(status
& PCI_VPD_ADDR_F
))
1938 ret
= pci_read_config_dword(pdev
, cap
+ PCI_VPD_DATA
, &value
);
1942 *val
= cpu_to_le32(value
);
1947 static void rtl_init_mac_address(struct rtl8169_private
*tp
,
1948 void __iomem
*ioaddr
)
1950 struct pci_dev
*pdev
= tp
->pci_dev
;
1956 cfg1
= RTL_R8(Config1
);
1957 if (!(cfg1
& VPD
)) {
1958 if (netif_msg_probe(tp
))
1959 dev_info(&pdev
->dev
, "VPD access disabled, enabling\n");
1960 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
1961 RTL_W8(Config1
, cfg1
| VPD
);
1962 RTL_W8(Cfg9346
, Cfg9346_Lock
);
1965 vpd_cap
= pci_find_capability(pdev
, PCI_CAP_ID_VPD
);
1969 if (rtl_eeprom_read(pdev
, vpd_cap
, RTL_EEPROM_SIG_ADDR
, &sig
) < 0)
1972 if ((sig
& RTL_EEPROM_SIG_MASK
) != RTL_EEPROM_SIG
) {
1973 dev_info(&pdev
->dev
, "Missing EEPROM signature: %08x\n", sig
);
1978 * MAC address is stored in EEPROM at offset 0x0e
1979 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1980 * address as defined in the PCI 2.2 Specifications, but the VPD data
1981 * is always consecutive 4-byte data starting from the VPD address
1984 if (rtl_eeprom_read(pdev
, vpd_cap
, 0x000e, (__le32
*)&mac
[0]) < 0 ||
1985 rtl_eeprom_read(pdev
, vpd_cap
, 0x0012, (__le32
*)&mac
[4]) < 0) {
1986 if (netif_msg_probe(tp
)) {
1987 dev_warn(&pdev
->dev
,
1988 "reading MAC address from EEPROM failed\n");
1993 if (netif_msg_probe(tp
)) {
1994 DECLARE_MAC_BUF(buf
);
1996 dev_info(&pdev
->dev
, "MAC address found in EEPROM: %s\n",
1997 print_mac(buf
, mac
));
2000 if (is_valid_ether_addr(mac
))
2001 rtl_rar_set(tp
, mac
);
2004 static int __devinit
2005 rtl8169_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
2007 const struct rtl_cfg_info
*cfg
= rtl_cfg_infos
+ ent
->driver_data
;
2008 const unsigned int region
= cfg
->region
;
2009 struct rtl8169_private
*tp
;
2010 struct mii_if_info
*mii
;
2011 struct net_device
*dev
;
2012 void __iomem
*ioaddr
;
2016 if (netif_msg_drv(&debug
)) {
2017 printk(KERN_INFO
"%s Gigabit Ethernet driver %s loaded\n",
2018 MODULENAME
, RTL8169_VERSION
);
2021 dev
= alloc_etherdev(sizeof (*tp
));
2023 if (netif_msg_drv(&debug
))
2024 dev_err(&pdev
->dev
, "unable to alloc new ethernet\n");
2029 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2030 tp
= netdev_priv(dev
);
2033 tp
->msg_enable
= netif_msg_init(debug
.msg_enable
, R8169_MSG_DEFAULT
);
2037 mii
->mdio_read
= rtl_mdio_read
;
2038 mii
->mdio_write
= rtl_mdio_write
;
2039 mii
->phy_id_mask
= 0x1f;
2040 mii
->reg_num_mask
= 0x1f;
2041 mii
->supports_gmii
= !!(cfg
->features
& RTL_FEATURE_GMII
);
2043 /* enable device (incl. PCI PM wakeup and hotplug setup) */
2044 rc
= pci_enable_device(pdev
);
2046 if (netif_msg_probe(tp
))
2047 dev_err(&pdev
->dev
, "enable failure\n");
2048 goto err_out_free_dev_1
;
2051 rc
= pci_set_mwi(pdev
);
2053 goto err_out_disable_2
;
2055 /* make sure PCI base addr 1 is MMIO */
2056 if (!(pci_resource_flags(pdev
, region
) & IORESOURCE_MEM
)) {
2057 if (netif_msg_probe(tp
)) {
2059 "region #%d not an MMIO resource, aborting\n",
2066 /* check for weird/broken PCI region reporting */
2067 if (pci_resource_len(pdev
, region
) < R8169_REGS_SIZE
) {
2068 if (netif_msg_probe(tp
)) {
2070 "Invalid PCI region size(s), aborting\n");
2076 rc
= pci_request_regions(pdev
, MODULENAME
);
2078 if (netif_msg_probe(tp
))
2079 dev_err(&pdev
->dev
, "could not request regions.\n");
2083 tp
->cp_cmd
= PCIMulRW
| RxChkSum
;
2085 if ((sizeof(dma_addr_t
) > 4) &&
2086 !pci_set_dma_mask(pdev
, DMA_64BIT_MASK
) && use_dac
) {
2087 tp
->cp_cmd
|= PCIDAC
;
2088 dev
->features
|= NETIF_F_HIGHDMA
;
2090 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
2092 if (netif_msg_probe(tp
)) {
2094 "DMA configuration failed.\n");
2096 goto err_out_free_res_4
;
2100 pci_set_master(pdev
);
2102 /* ioremap MMIO region */
2103 ioaddr
= ioremap(pci_resource_start(pdev
, region
), R8169_REGS_SIZE
);
2105 if (netif_msg_probe(tp
))
2106 dev_err(&pdev
->dev
, "cannot remap MMIO, aborting\n");
2108 goto err_out_free_res_4
;
2111 tp
->pcie_cap
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
2112 if (!tp
->pcie_cap
&& netif_msg_probe(tp
))
2113 dev_info(&pdev
->dev
, "no PCI Express capability\n");
2115 /* Unneeded ? Don't mess with Mrs. Murphy. */
2116 rtl8169_irq_mask_and_ack(ioaddr
);
2118 /* Soft reset the chip. */
2119 RTL_W8(ChipCmd
, CmdReset
);
2121 /* Check that the chip has finished the reset. */
2122 for (i
= 0; i
< 100; i
++) {
2123 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2125 msleep_interruptible(1);
2128 /* Identify chip attached to board */
2129 rtl8169_get_mac_version(tp
, ioaddr
);
2131 rtl8169_print_mac_version(tp
);
2133 for (i
= 0; i
< ARRAY_SIZE(rtl_chip_info
); i
++) {
2134 if (tp
->mac_version
== rtl_chip_info
[i
].mac_version
)
2137 if (i
== ARRAY_SIZE(rtl_chip_info
)) {
2138 /* Unknown chip: assume array element #0, original RTL-8169 */
2139 if (netif_msg_probe(tp
)) {
2140 dev_printk(KERN_DEBUG
, &pdev
->dev
,
2141 "unknown chip version, assuming %s\n",
2142 rtl_chip_info
[0].name
);
2148 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2149 RTL_W8(Config1
, RTL_R8(Config1
) | PMEnable
);
2150 RTL_W8(Config5
, RTL_R8(Config5
) & PMEStatus
);
2151 if ((RTL_R8(Config3
) & (LinkUp
| MagicPacket
)) != 0)
2152 tp
->features
|= RTL_FEATURE_WOL
;
2153 if ((RTL_R8(Config5
) & (UWF
| BWF
| MWF
)) != 0)
2154 tp
->features
|= RTL_FEATURE_WOL
;
2155 tp
->features
|= rtl_try_msi(pdev
, ioaddr
, cfg
);
2156 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2158 if ((tp
->mac_version
<= RTL_GIGA_MAC_VER_06
) &&
2159 (RTL_R8(PHYstatus
) & TBI_Enable
)) {
2160 tp
->set_speed
= rtl8169_set_speed_tbi
;
2161 tp
->get_settings
= rtl8169_gset_tbi
;
2162 tp
->phy_reset_enable
= rtl8169_tbi_reset_enable
;
2163 tp
->phy_reset_pending
= rtl8169_tbi_reset_pending
;
2164 tp
->link_ok
= rtl8169_tbi_link_ok
;
2166 tp
->phy_1000_ctrl_reg
= ADVERTISE_1000FULL
; /* Implied by TBI */
2168 tp
->set_speed
= rtl8169_set_speed_xmii
;
2169 tp
->get_settings
= rtl8169_gset_xmii
;
2170 tp
->phy_reset_enable
= rtl8169_xmii_reset_enable
;
2171 tp
->phy_reset_pending
= rtl8169_xmii_reset_pending
;
2172 tp
->link_ok
= rtl8169_xmii_link_ok
;
2174 dev
->do_ioctl
= rtl8169_ioctl
;
2177 spin_lock_init(&tp
->lock
);
2179 tp
->mmio_addr
= ioaddr
;
2181 rtl_init_mac_address(tp
, ioaddr
);
2183 /* Get MAC address */
2184 for (i
= 0; i
< MAC_ADDR_LEN
; i
++)
2185 dev
->dev_addr
[i
] = RTL_R8(MAC0
+ i
);
2186 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
2188 dev
->open
= rtl8169_open
;
2189 dev
->hard_start_xmit
= rtl8169_start_xmit
;
2190 dev
->get_stats
= rtl8169_get_stats
;
2191 SET_ETHTOOL_OPS(dev
, &rtl8169_ethtool_ops
);
2192 dev
->stop
= rtl8169_close
;
2193 dev
->tx_timeout
= rtl8169_tx_timeout
;
2194 dev
->set_multicast_list
= rtl_set_rx_mode
;
2195 dev
->watchdog_timeo
= RTL8169_TX_TIMEOUT
;
2196 dev
->irq
= pdev
->irq
;
2197 dev
->base_addr
= (unsigned long) ioaddr
;
2198 dev
->change_mtu
= rtl8169_change_mtu
;
2199 dev
->set_mac_address
= rtl_set_mac_address
;
2201 netif_napi_add(dev
, &tp
->napi
, rtl8169_poll
, R8169_NAPI_WEIGHT
);
2203 #ifdef CONFIG_R8169_VLAN
2204 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
2205 dev
->vlan_rx_register
= rtl8169_vlan_rx_register
;
2208 #ifdef CONFIG_NET_POLL_CONTROLLER
2209 dev
->poll_controller
= rtl8169_netpoll
;
2212 tp
->intr_mask
= 0xffff;
2213 tp
->align
= cfg
->align
;
2214 tp
->hw_start
= cfg
->hw_start
;
2215 tp
->intr_event
= cfg
->intr_event
;
2216 tp
->napi_event
= cfg
->napi_event
;
2218 init_timer(&tp
->timer
);
2219 tp
->timer
.data
= (unsigned long) dev
;
2220 tp
->timer
.function
= rtl8169_phy_timer
;
2222 rc
= register_netdev(dev
);
2226 pci_set_drvdata(pdev
, dev
);
2228 if (netif_msg_probe(tp
)) {
2229 u32 xid
= RTL_R32(TxConfig
) & 0x7cf0f8ff;
2231 printk(KERN_INFO
"%s: %s at 0x%lx, "
2232 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2233 "XID %08x IRQ %d\n",
2235 rtl_chip_info
[tp
->chipset
].name
,
2237 dev
->dev_addr
[0], dev
->dev_addr
[1],
2238 dev
->dev_addr
[2], dev
->dev_addr
[3],
2239 dev
->dev_addr
[4], dev
->dev_addr
[5], xid
, dev
->irq
);
2242 rtl8169_init_phy(dev
, tp
);
2243 device_set_wakeup_enable(&pdev
->dev
, tp
->features
& RTL_FEATURE_WOL
);
2249 rtl_disable_msi(pdev
, tp
);
2252 pci_release_regions(pdev
);
2254 pci_clear_mwi(pdev
);
2256 pci_disable_device(pdev
);
2262 static void __devexit
rtl8169_remove_one(struct pci_dev
*pdev
)
2264 struct net_device
*dev
= pci_get_drvdata(pdev
);
2265 struct rtl8169_private
*tp
= netdev_priv(dev
);
2267 flush_scheduled_work();
2269 unregister_netdev(dev
);
2270 rtl_disable_msi(pdev
, tp
);
2271 rtl8169_release_board(pdev
, dev
, tp
->mmio_addr
);
2272 pci_set_drvdata(pdev
, NULL
);
2275 static void rtl8169_set_rxbufsize(struct rtl8169_private
*tp
,
2276 struct net_device
*dev
)
2278 unsigned int mtu
= dev
->mtu
;
2280 tp
->rx_buf_sz
= (mtu
> RX_BUF_SIZE
) ? mtu
+ ETH_HLEN
+ 8 : RX_BUF_SIZE
;
2283 static int rtl8169_open(struct net_device
*dev
)
2285 struct rtl8169_private
*tp
= netdev_priv(dev
);
2286 struct pci_dev
*pdev
= tp
->pci_dev
;
2287 int retval
= -ENOMEM
;
2290 rtl8169_set_rxbufsize(tp
, dev
);
2293 * Rx and Tx desscriptors needs 256 bytes alignment.
2294 * pci_alloc_consistent provides more.
2296 tp
->TxDescArray
= pci_alloc_consistent(pdev
, R8169_TX_RING_BYTES
,
2298 if (!tp
->TxDescArray
)
2301 tp
->RxDescArray
= pci_alloc_consistent(pdev
, R8169_RX_RING_BYTES
,
2303 if (!tp
->RxDescArray
)
2306 retval
= rtl8169_init_ring(dev
);
2310 INIT_DELAYED_WORK(&tp
->task
, NULL
);
2314 retval
= request_irq(dev
->irq
, rtl8169_interrupt
,
2315 (tp
->features
& RTL_FEATURE_MSI
) ? 0 : IRQF_SHARED
,
2318 goto err_release_ring_2
;
2320 napi_enable(&tp
->napi
);
2324 rtl8169_request_timer(dev
);
2326 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
2331 rtl8169_rx_clear(tp
);
2333 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
2336 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
2341 static void rtl8169_hw_reset(void __iomem
*ioaddr
)
2343 /* Disable interrupts */
2344 rtl8169_irq_mask_and_ack(ioaddr
);
2346 /* Reset the chipset */
2347 RTL_W8(ChipCmd
, CmdReset
);
2353 static void rtl_set_rx_tx_config_registers(struct rtl8169_private
*tp
)
2355 void __iomem
*ioaddr
= tp
->mmio_addr
;
2356 u32 cfg
= rtl8169_rx_config
;
2358 cfg
|= (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
2359 RTL_W32(RxConfig
, cfg
);
2361 /* Set DMA burst size and Interframe Gap Time */
2362 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2363 (InterFrameGap
<< TxInterFrameGapShift
));
2366 static void rtl_hw_start(struct net_device
*dev
)
2368 struct rtl8169_private
*tp
= netdev_priv(dev
);
2369 void __iomem
*ioaddr
= tp
->mmio_addr
;
2372 /* Soft reset the chip. */
2373 RTL_W8(ChipCmd
, CmdReset
);
2375 /* Check that the chip has finished the reset. */
2376 for (i
= 0; i
< 100; i
++) {
2377 if ((RTL_R8(ChipCmd
) & CmdReset
) == 0)
2379 msleep_interruptible(1);
2384 netif_start_queue(dev
);
2388 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private
*tp
,
2389 void __iomem
*ioaddr
)
2392 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2393 * register to be written before TxDescAddrLow to work.
2394 * Switching from MMIO to I/O access fixes the issue as well.
2396 RTL_W32(TxDescStartAddrHigh
, ((u64
) tp
->TxPhyAddr
) >> 32);
2397 RTL_W32(TxDescStartAddrLow
, ((u64
) tp
->TxPhyAddr
) & DMA_32BIT_MASK
);
2398 RTL_W32(RxDescAddrHigh
, ((u64
) tp
->RxPhyAddr
) >> 32);
2399 RTL_W32(RxDescAddrLow
, ((u64
) tp
->RxPhyAddr
) & DMA_32BIT_MASK
);
2402 static u16
rtl_rw_cpluscmd(void __iomem
*ioaddr
)
2406 cmd
= RTL_R16(CPlusCmd
);
2407 RTL_W16(CPlusCmd
, cmd
);
2411 static void rtl_set_rx_max_size(void __iomem
*ioaddr
)
2413 /* Low hurts. Let's disable the filtering. */
2414 RTL_W16(RxMaxSize
, 16383);
2417 static void rtl8169_set_magic_reg(void __iomem
*ioaddr
, unsigned mac_version
)
2424 { RTL_GIGA_MAC_VER_05
, PCI_Clock_33MHz
, 0x000fff00 }, // 8110SCd
2425 { RTL_GIGA_MAC_VER_05
, PCI_Clock_66MHz
, 0x000fffff },
2426 { RTL_GIGA_MAC_VER_06
, PCI_Clock_33MHz
, 0x00ffff00 }, // 8110SCe
2427 { RTL_GIGA_MAC_VER_06
, PCI_Clock_66MHz
, 0x00ffffff }
2432 clk
= RTL_R8(Config2
) & PCI_Clock_66MHz
;
2433 for (i
= 0; i
< ARRAY_SIZE(cfg2_info
); i
++, p
++) {
2434 if ((p
->mac_version
== mac_version
) && (p
->clk
== clk
)) {
2435 RTL_W32(0x7c, p
->val
);
2441 static void rtl_hw_start_8169(struct net_device
*dev
)
2443 struct rtl8169_private
*tp
= netdev_priv(dev
);
2444 void __iomem
*ioaddr
= tp
->mmio_addr
;
2445 struct pci_dev
*pdev
= tp
->pci_dev
;
2447 if (tp
->mac_version
== RTL_GIGA_MAC_VER_05
) {
2448 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) | PCIMulRW
);
2449 pci_write_config_byte(pdev
, PCI_CACHE_LINE_SIZE
, 0x08);
2452 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2453 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2454 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2455 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2456 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2457 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2459 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2461 rtl_set_rx_max_size(ioaddr
);
2463 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_01
) ||
2464 (tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2465 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
) ||
2466 (tp
->mac_version
== RTL_GIGA_MAC_VER_04
))
2467 rtl_set_rx_tx_config_registers(tp
);
2469 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2471 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_02
) ||
2472 (tp
->mac_version
== RTL_GIGA_MAC_VER_03
)) {
2473 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2474 "Bit-3 and bit-14 MUST be 1\n");
2475 tp
->cp_cmd
|= (1 << 14);
2478 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2480 rtl8169_set_magic_reg(ioaddr
, tp
->mac_version
);
2483 * Undocumented corner. Supposedly:
2484 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2486 RTL_W16(IntrMitigate
, 0x0000);
2488 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2490 if ((tp
->mac_version
!= RTL_GIGA_MAC_VER_01
) &&
2491 (tp
->mac_version
!= RTL_GIGA_MAC_VER_02
) &&
2492 (tp
->mac_version
!= RTL_GIGA_MAC_VER_03
) &&
2493 (tp
->mac_version
!= RTL_GIGA_MAC_VER_04
)) {
2494 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2495 rtl_set_rx_tx_config_registers(tp
);
2498 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2500 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2503 RTL_W32(RxMissed
, 0);
2505 rtl_set_rx_mode(dev
);
2507 /* no early-rx interrupts */
2508 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2510 /* Enable all known interrupts by setting the interrupt mask. */
2511 RTL_W16(IntrMask
, tp
->intr_event
);
2514 static void rtl_tx_performance_tweak(struct pci_dev
*pdev
, u16 force
)
2516 struct net_device
*dev
= pci_get_drvdata(pdev
);
2517 struct rtl8169_private
*tp
= netdev_priv(dev
);
2518 int cap
= tp
->pcie_cap
;
2523 pci_read_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2524 ctl
= (ctl
& ~PCI_EXP_DEVCTL_READRQ
) | force
;
2525 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2529 static void rtl_csi_access_enable(void __iomem
*ioaddr
)
2533 csi
= rtl_csi_read(ioaddr
, 0x070c) & 0x00ffffff;
2534 rtl_csi_write(ioaddr
, 0x070c, csi
| 0x27000000);
2538 unsigned int offset
;
2543 static void rtl_ephy_init(void __iomem
*ioaddr
, struct ephy_info
*e
, int len
)
2548 w
= (rtl_ephy_read(ioaddr
, e
->offset
) & ~e
->mask
) | e
->bits
;
2549 rtl_ephy_write(ioaddr
, e
->offset
, w
);
2554 static void rtl_disable_clock_request(struct pci_dev
*pdev
)
2556 struct net_device
*dev
= pci_get_drvdata(pdev
);
2557 struct rtl8169_private
*tp
= netdev_priv(dev
);
2558 int cap
= tp
->pcie_cap
;
2563 pci_read_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, &ctl
);
2564 ctl
&= ~PCI_EXP_LNKCTL_CLKREQ_EN
;
2565 pci_write_config_word(pdev
, cap
+ PCI_EXP_LNKCTL
, ctl
);
2569 #define R8168_CPCMD_QUIRK_MASK (\
2580 static void rtl_hw_start_8168bb(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2582 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2584 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2586 rtl_tx_performance_tweak(pdev
,
2587 (0x5 << MAX_READ_REQUEST_SHIFT
) | PCI_EXP_DEVCTL_NOSNOOP_EN
);
2590 static void rtl_hw_start_8168bef(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2592 rtl_hw_start_8168bb(ioaddr
, pdev
);
2594 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2596 RTL_W8(Config4
, RTL_R8(Config4
) & ~(1 << 0));
2599 static void __rtl_hw_start_8168cp(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2601 RTL_W8(Config1
, RTL_R8(Config1
) | Speed_down
);
2603 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2605 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2607 rtl_disable_clock_request(pdev
);
2609 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2612 static void rtl_hw_start_8168cp_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2614 static struct ephy_info e_info_8168cp
[] = {
2615 { 0x01, 0, 0x0001 },
2616 { 0x02, 0x0800, 0x1000 },
2617 { 0x03, 0, 0x0042 },
2618 { 0x06, 0x0080, 0x0000 },
2622 rtl_csi_access_enable(ioaddr
);
2624 rtl_ephy_init(ioaddr
, e_info_8168cp
, ARRAY_SIZE(e_info_8168cp
));
2626 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2629 static void rtl_hw_start_8168cp_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2631 rtl_csi_access_enable(ioaddr
);
2633 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2635 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2637 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2640 static void rtl_hw_start_8168cp_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2642 rtl_csi_access_enable(ioaddr
);
2644 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2647 RTL_W8(DBG_REG
, 0x20);
2649 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2651 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2653 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2656 static void rtl_hw_start_8168c_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2658 static struct ephy_info e_info_8168c_1
[] = {
2659 { 0x02, 0x0800, 0x1000 },
2660 { 0x03, 0, 0x0002 },
2661 { 0x06, 0x0080, 0x0000 }
2664 rtl_csi_access_enable(ioaddr
);
2666 RTL_W8(DBG_REG
, 0x06 | FIX_NAK_1
| FIX_NAK_2
);
2668 rtl_ephy_init(ioaddr
, e_info_8168c_1
, ARRAY_SIZE(e_info_8168c_1
));
2670 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2673 static void rtl_hw_start_8168c_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2675 static struct ephy_info e_info_8168c_2
[] = {
2676 { 0x01, 0, 0x0001 },
2677 { 0x03, 0x0400, 0x0220 }
2680 rtl_csi_access_enable(ioaddr
);
2682 rtl_ephy_init(ioaddr
, e_info_8168c_2
, ARRAY_SIZE(e_info_8168c_2
));
2684 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2687 static void rtl_hw_start_8168c_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2689 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2692 static void rtl_hw_start_8168c_4(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2694 rtl_csi_access_enable(ioaddr
);
2696 __rtl_hw_start_8168cp(ioaddr
, pdev
);
2699 static void rtl_hw_start_8168d(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2701 rtl_csi_access_enable(ioaddr
);
2703 rtl_disable_clock_request(pdev
);
2705 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2707 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2709 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R8168_CPCMD_QUIRK_MASK
);
2712 static void rtl_hw_start_8168(struct net_device
*dev
)
2714 struct rtl8169_private
*tp
= netdev_priv(dev
);
2715 void __iomem
*ioaddr
= tp
->mmio_addr
;
2716 struct pci_dev
*pdev
= tp
->pci_dev
;
2718 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2720 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2722 rtl_set_rx_max_size(ioaddr
);
2724 tp
->cp_cmd
|= RTL_R16(CPlusCmd
) | PktCntrDisable
| INTT_1
;
2726 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2728 RTL_W16(IntrMitigate
, 0x5151);
2730 /* Work around for RxFIFO overflow. */
2731 if (tp
->mac_version
== RTL_GIGA_MAC_VER_11
) {
2732 tp
->intr_event
|= RxFIFOOver
| PCSTimeout
;
2733 tp
->intr_event
&= ~RxOverflow
;
2736 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2738 rtl_set_rx_mode(dev
);
2740 RTL_W32(TxConfig
, (TX_DMA_BURST
<< TxDMAShift
) |
2741 (InterFrameGap
<< TxInterFrameGapShift
));
2745 switch (tp
->mac_version
) {
2746 case RTL_GIGA_MAC_VER_11
:
2747 rtl_hw_start_8168bb(ioaddr
, pdev
);
2750 case RTL_GIGA_MAC_VER_12
:
2751 case RTL_GIGA_MAC_VER_17
:
2752 rtl_hw_start_8168bef(ioaddr
, pdev
);
2755 case RTL_GIGA_MAC_VER_18
:
2756 rtl_hw_start_8168cp_1(ioaddr
, pdev
);
2759 case RTL_GIGA_MAC_VER_19
:
2760 rtl_hw_start_8168c_1(ioaddr
, pdev
);
2763 case RTL_GIGA_MAC_VER_20
:
2764 rtl_hw_start_8168c_2(ioaddr
, pdev
);
2767 case RTL_GIGA_MAC_VER_21
:
2768 rtl_hw_start_8168c_3(ioaddr
, pdev
);
2771 case RTL_GIGA_MAC_VER_22
:
2772 rtl_hw_start_8168c_4(ioaddr
, pdev
);
2775 case RTL_GIGA_MAC_VER_23
:
2776 rtl_hw_start_8168cp_2(ioaddr
, pdev
);
2779 case RTL_GIGA_MAC_VER_24
:
2780 rtl_hw_start_8168cp_3(ioaddr
, pdev
);
2783 case RTL_GIGA_MAC_VER_25
:
2784 rtl_hw_start_8168d(ioaddr
, pdev
);
2788 printk(KERN_ERR PFX
"%s: unknown chipset (mac_version = %d).\n",
2789 dev
->name
, tp
->mac_version
);
2793 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2795 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2797 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xF000);
2799 RTL_W16(IntrMask
, tp
->intr_event
);
2802 #define R810X_CPCMD_QUIRK_MASK (\
2814 static void rtl_hw_start_8102e_1(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2816 static struct ephy_info e_info_8102e_1
[] = {
2817 { 0x01, 0, 0x6e65 },
2818 { 0x02, 0, 0x091f },
2819 { 0x03, 0, 0xc2f9 },
2820 { 0x06, 0, 0xafb5 },
2821 { 0x07, 0, 0x0e00 },
2822 { 0x19, 0, 0xec80 },
2823 { 0x01, 0, 0x2e65 },
2828 rtl_csi_access_enable(ioaddr
);
2830 RTL_W8(DBG_REG
, FIX_NAK_1
);
2832 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2835 LEDS1
| LEDS0
| Speed_down
| MEMMAP
| IOMAP
| VPD
| PMEnable
);
2836 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2838 cfg1
= RTL_R8(Config1
);
2839 if ((cfg1
& LEDS0
) && (cfg1
& LEDS1
))
2840 RTL_W8(Config1
, cfg1
& ~LEDS0
);
2842 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2844 rtl_ephy_init(ioaddr
, e_info_8102e_1
, ARRAY_SIZE(e_info_8102e_1
));
2847 static void rtl_hw_start_8102e_2(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2849 rtl_csi_access_enable(ioaddr
);
2851 rtl_tx_performance_tweak(pdev
, 0x5 << MAX_READ_REQUEST_SHIFT
);
2853 RTL_W8(Config1
, MEMMAP
| IOMAP
| VPD
| PMEnable
);
2854 RTL_W8(Config3
, RTL_R8(Config3
) & ~Beacon_en
);
2856 RTL_W16(CPlusCmd
, RTL_R16(CPlusCmd
) & ~R810X_CPCMD_QUIRK_MASK
);
2859 static void rtl_hw_start_8102e_3(void __iomem
*ioaddr
, struct pci_dev
*pdev
)
2861 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2863 rtl_ephy_write(ioaddr
, 0x03, 0xc2f9);
2866 static void rtl_hw_start_8101(struct net_device
*dev
)
2868 struct rtl8169_private
*tp
= netdev_priv(dev
);
2869 void __iomem
*ioaddr
= tp
->mmio_addr
;
2870 struct pci_dev
*pdev
= tp
->pci_dev
;
2872 if ((tp
->mac_version
== RTL_GIGA_MAC_VER_13
) ||
2873 (tp
->mac_version
== RTL_GIGA_MAC_VER_16
)) {
2874 int cap
= tp
->pcie_cap
;
2877 pci_write_config_word(pdev
, cap
+ PCI_EXP_DEVCTL
,
2878 PCI_EXP_DEVCTL_NOSNOOP_EN
);
2882 switch (tp
->mac_version
) {
2883 case RTL_GIGA_MAC_VER_07
:
2884 rtl_hw_start_8102e_1(ioaddr
, pdev
);
2887 case RTL_GIGA_MAC_VER_08
:
2888 rtl_hw_start_8102e_3(ioaddr
, pdev
);
2891 case RTL_GIGA_MAC_VER_09
:
2892 rtl_hw_start_8102e_2(ioaddr
, pdev
);
2896 RTL_W8(Cfg9346
, Cfg9346_Unlock
);
2898 RTL_W8(EarlyTxThres
, EarlyTxThld
);
2900 rtl_set_rx_max_size(ioaddr
);
2902 tp
->cp_cmd
|= rtl_rw_cpluscmd(ioaddr
) | PCIMulRW
;
2904 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
2906 RTL_W16(IntrMitigate
, 0x0000);
2908 rtl_set_rx_tx_desc_registers(tp
, ioaddr
);
2910 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2911 rtl_set_rx_tx_config_registers(tp
);
2913 RTL_W8(Cfg9346
, Cfg9346_Lock
);
2917 rtl_set_rx_mode(dev
);
2919 RTL_W8(ChipCmd
, CmdTxEnb
| CmdRxEnb
);
2921 RTL_W16(MultiIntr
, RTL_R16(MultiIntr
) & 0xf000);
2923 RTL_W16(IntrMask
, tp
->intr_event
);
2926 static int rtl8169_change_mtu(struct net_device
*dev
, int new_mtu
)
2928 struct rtl8169_private
*tp
= netdev_priv(dev
);
2931 if (new_mtu
< ETH_ZLEN
|| new_mtu
> SafeMtu
)
2936 if (!netif_running(dev
))
2941 rtl8169_set_rxbufsize(tp
, dev
);
2943 ret
= rtl8169_init_ring(dev
);
2947 napi_enable(&tp
->napi
);
2951 rtl8169_request_timer(dev
);
2957 static inline void rtl8169_make_unusable_by_asic(struct RxDesc
*desc
)
2959 desc
->addr
= cpu_to_le64(0x0badbadbadbadbadull
);
2960 desc
->opts1
&= ~cpu_to_le32(DescOwn
| RsvdMask
);
2963 static void rtl8169_free_rx_skb(struct rtl8169_private
*tp
,
2964 struct sk_buff
**sk_buff
, struct RxDesc
*desc
)
2966 struct pci_dev
*pdev
= tp
->pci_dev
;
2968 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), tp
->rx_buf_sz
,
2969 PCI_DMA_FROMDEVICE
);
2970 dev_kfree_skb(*sk_buff
);
2972 rtl8169_make_unusable_by_asic(desc
);
2975 static inline void rtl8169_mark_to_asic(struct RxDesc
*desc
, u32 rx_buf_sz
)
2977 u32 eor
= le32_to_cpu(desc
->opts1
) & RingEnd
;
2979 desc
->opts1
= cpu_to_le32(DescOwn
| eor
| rx_buf_sz
);
2982 static inline void rtl8169_map_to_asic(struct RxDesc
*desc
, dma_addr_t mapping
,
2985 desc
->addr
= cpu_to_le64(mapping
);
2987 rtl8169_mark_to_asic(desc
, rx_buf_sz
);
2990 static struct sk_buff
*rtl8169_alloc_rx_skb(struct pci_dev
*pdev
,
2991 struct net_device
*dev
,
2992 struct RxDesc
*desc
, int rx_buf_sz
,
2995 struct sk_buff
*skb
;
2999 pad
= align
? align
: NET_IP_ALIGN
;
3001 skb
= netdev_alloc_skb(dev
, rx_buf_sz
+ pad
);
3005 skb_reserve(skb
, align
? ((pad
- 1) & (unsigned long)skb
->data
) : pad
);
3007 mapping
= pci_map_single(pdev
, skb
->data
, rx_buf_sz
,
3008 PCI_DMA_FROMDEVICE
);
3010 rtl8169_map_to_asic(desc
, mapping
, rx_buf_sz
);
3015 rtl8169_make_unusable_by_asic(desc
);
3019 static void rtl8169_rx_clear(struct rtl8169_private
*tp
)
3023 for (i
= 0; i
< NUM_RX_DESC
; i
++) {
3024 if (tp
->Rx_skbuff
[i
]) {
3025 rtl8169_free_rx_skb(tp
, tp
->Rx_skbuff
+ i
,
3026 tp
->RxDescArray
+ i
);
3031 static u32
rtl8169_rx_fill(struct rtl8169_private
*tp
, struct net_device
*dev
,
3036 for (cur
= start
; end
- cur
!= 0; cur
++) {
3037 struct sk_buff
*skb
;
3038 unsigned int i
= cur
% NUM_RX_DESC
;
3040 WARN_ON((s32
)(end
- cur
) < 0);
3042 if (tp
->Rx_skbuff
[i
])
3045 skb
= rtl8169_alloc_rx_skb(tp
->pci_dev
, dev
,
3046 tp
->RxDescArray
+ i
,
3047 tp
->rx_buf_sz
, tp
->align
);
3051 tp
->Rx_skbuff
[i
] = skb
;
3056 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc
*desc
)
3058 desc
->opts1
|= cpu_to_le32(RingEnd
);
3061 static void rtl8169_init_ring_indexes(struct rtl8169_private
*tp
)
3063 tp
->dirty_tx
= tp
->dirty_rx
= tp
->cur_tx
= tp
->cur_rx
= 0;
3066 static int rtl8169_init_ring(struct net_device
*dev
)
3068 struct rtl8169_private
*tp
= netdev_priv(dev
);
3070 rtl8169_init_ring_indexes(tp
);
3072 memset(tp
->tx_skb
, 0x0, NUM_TX_DESC
* sizeof(struct ring_info
));
3073 memset(tp
->Rx_skbuff
, 0x0, NUM_RX_DESC
* sizeof(struct sk_buff
*));
3075 if (rtl8169_rx_fill(tp
, dev
, 0, NUM_RX_DESC
) != NUM_RX_DESC
)
3078 rtl8169_mark_as_last_descriptor(tp
->RxDescArray
+ NUM_RX_DESC
- 1);
3083 rtl8169_rx_clear(tp
);
3087 static void rtl8169_unmap_tx_skb(struct pci_dev
*pdev
, struct ring_info
*tx_skb
,
3088 struct TxDesc
*desc
)
3090 unsigned int len
= tx_skb
->len
;
3092 pci_unmap_single(pdev
, le64_to_cpu(desc
->addr
), len
, PCI_DMA_TODEVICE
);
3099 static void rtl8169_tx_clear(struct rtl8169_private
*tp
)
3103 for (i
= tp
->dirty_tx
; i
< tp
->dirty_tx
+ NUM_TX_DESC
; i
++) {
3104 unsigned int entry
= i
% NUM_TX_DESC
;
3105 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3106 unsigned int len
= tx_skb
->len
;
3109 struct sk_buff
*skb
= tx_skb
->skb
;
3111 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
,
3112 tp
->TxDescArray
+ entry
);
3117 tp
->dev
->stats
.tx_dropped
++;
3120 tp
->cur_tx
= tp
->dirty_tx
= 0;
3123 static void rtl8169_schedule_work(struct net_device
*dev
, work_func_t task
)
3125 struct rtl8169_private
*tp
= netdev_priv(dev
);
3127 PREPARE_DELAYED_WORK(&tp
->task
, task
);
3128 schedule_delayed_work(&tp
->task
, 4);
3131 static void rtl8169_wait_for_quiescence(struct net_device
*dev
)
3133 struct rtl8169_private
*tp
= netdev_priv(dev
);
3134 void __iomem
*ioaddr
= tp
->mmio_addr
;
3136 synchronize_irq(dev
->irq
);
3138 /* Wait for any pending NAPI task to complete */
3139 napi_disable(&tp
->napi
);
3141 rtl8169_irq_mask_and_ack(ioaddr
);
3143 tp
->intr_mask
= 0xffff;
3144 RTL_W16(IntrMask
, tp
->intr_event
);
3145 napi_enable(&tp
->napi
);
3148 static void rtl8169_reinit_task(struct work_struct
*work
)
3150 struct rtl8169_private
*tp
=
3151 container_of(work
, struct rtl8169_private
, task
.work
);
3152 struct net_device
*dev
= tp
->dev
;
3157 if (!netif_running(dev
))
3160 rtl8169_wait_for_quiescence(dev
);
3163 ret
= rtl8169_open(dev
);
3164 if (unlikely(ret
< 0)) {
3165 if (net_ratelimit() && netif_msg_drv(tp
)) {
3166 printk(KERN_ERR PFX
"%s: reinit failure (status = %d)."
3167 " Rescheduling.\n", dev
->name
, ret
);
3169 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3176 static void rtl8169_reset_task(struct work_struct
*work
)
3178 struct rtl8169_private
*tp
=
3179 container_of(work
, struct rtl8169_private
, task
.work
);
3180 struct net_device
*dev
= tp
->dev
;
3184 if (!netif_running(dev
))
3187 rtl8169_wait_for_quiescence(dev
);
3189 rtl8169_rx_interrupt(dev
, tp
, tp
->mmio_addr
, ~(u32
)0);
3190 rtl8169_tx_clear(tp
);
3192 if (tp
->dirty_rx
== tp
->cur_rx
) {
3193 rtl8169_init_ring_indexes(tp
);
3195 netif_wake_queue(dev
);
3196 rtl8169_check_link_status(dev
, tp
, tp
->mmio_addr
);
3198 if (net_ratelimit() && netif_msg_intr(tp
)) {
3199 printk(KERN_EMERG PFX
"%s: Rx buffers shortage\n",
3202 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3209 static void rtl8169_tx_timeout(struct net_device
*dev
)
3211 struct rtl8169_private
*tp
= netdev_priv(dev
);
3213 rtl8169_hw_reset(tp
->mmio_addr
);
3215 /* Let's wait a bit while any (async) irq lands on */
3216 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3219 static int rtl8169_xmit_frags(struct rtl8169_private
*tp
, struct sk_buff
*skb
,
3222 struct skb_shared_info
*info
= skb_shinfo(skb
);
3223 unsigned int cur_frag
, entry
;
3224 struct TxDesc
* uninitialized_var(txd
);
3227 for (cur_frag
= 0; cur_frag
< info
->nr_frags
; cur_frag
++) {
3228 skb_frag_t
*frag
= info
->frags
+ cur_frag
;
3233 entry
= (entry
+ 1) % NUM_TX_DESC
;
3235 txd
= tp
->TxDescArray
+ entry
;
3237 addr
= ((void *) page_address(frag
->page
)) + frag
->page_offset
;
3238 mapping
= pci_map_single(tp
->pci_dev
, addr
, len
, PCI_DMA_TODEVICE
);
3240 /* anti gcc 2.95.3 bugware (sic) */
3241 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3243 txd
->opts1
= cpu_to_le32(status
);
3244 txd
->addr
= cpu_to_le64(mapping
);
3246 tp
->tx_skb
[entry
].len
= len
;
3250 tp
->tx_skb
[entry
].skb
= skb
;
3251 txd
->opts1
|= cpu_to_le32(LastFrag
);
3257 static inline u32
rtl8169_tso_csum(struct sk_buff
*skb
, struct net_device
*dev
)
3259 if (dev
->features
& NETIF_F_TSO
) {
3260 u32 mss
= skb_shinfo(skb
)->gso_size
;
3263 return LargeSend
| ((mss
& MSSMask
) << MSSShift
);
3265 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
3266 const struct iphdr
*ip
= ip_hdr(skb
);
3268 if (ip
->protocol
== IPPROTO_TCP
)
3269 return IPCS
| TCPCS
;
3270 else if (ip
->protocol
== IPPROTO_UDP
)
3271 return IPCS
| UDPCS
;
3272 WARN_ON(1); /* we need a WARN() */
3277 static int rtl8169_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3279 struct rtl8169_private
*tp
= netdev_priv(dev
);
3280 unsigned int frags
, entry
= tp
->cur_tx
% NUM_TX_DESC
;
3281 struct TxDesc
*txd
= tp
->TxDescArray
+ entry
;
3282 void __iomem
*ioaddr
= tp
->mmio_addr
;
3286 int ret
= NETDEV_TX_OK
;
3288 if (unlikely(TX_BUFFS_AVAIL(tp
) < skb_shinfo(skb
)->nr_frags
)) {
3289 if (netif_msg_drv(tp
)) {
3291 "%s: BUG! Tx Ring full when queue awake!\n",
3297 if (unlikely(le32_to_cpu(txd
->opts1
) & DescOwn
))
3300 opts1
= DescOwn
| rtl8169_tso_csum(skb
, dev
);
3302 frags
= rtl8169_xmit_frags(tp
, skb
, opts1
);
3304 len
= skb_headlen(skb
);
3309 if (unlikely(len
< ETH_ZLEN
)) {
3310 if (skb_padto(skb
, ETH_ZLEN
))
3311 goto err_update_stats
;
3315 opts1
|= FirstFrag
| LastFrag
;
3316 tp
->tx_skb
[entry
].skb
= skb
;
3319 mapping
= pci_map_single(tp
->pci_dev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
3321 tp
->tx_skb
[entry
].len
= len
;
3322 txd
->addr
= cpu_to_le64(mapping
);
3323 txd
->opts2
= cpu_to_le32(rtl8169_tx_vlan_tag(tp
, skb
));
3327 /* anti gcc 2.95.3 bugware (sic) */
3328 status
= opts1
| len
| (RingEnd
* !((entry
+ 1) % NUM_TX_DESC
));
3329 txd
->opts1
= cpu_to_le32(status
);
3331 dev
->trans_start
= jiffies
;
3333 tp
->cur_tx
+= frags
+ 1;
3337 RTL_W8(TxPoll
, NPQ
); /* set polling bit */
3339 if (TX_BUFFS_AVAIL(tp
) < MAX_SKB_FRAGS
) {
3340 netif_stop_queue(dev
);
3342 if (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)
3343 netif_wake_queue(dev
);
3350 netif_stop_queue(dev
);
3351 ret
= NETDEV_TX_BUSY
;
3353 dev
->stats
.tx_dropped
++;
3357 static void rtl8169_pcierr_interrupt(struct net_device
*dev
)
3359 struct rtl8169_private
*tp
= netdev_priv(dev
);
3360 struct pci_dev
*pdev
= tp
->pci_dev
;
3361 void __iomem
*ioaddr
= tp
->mmio_addr
;
3362 u16 pci_status
, pci_cmd
;
3364 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
3365 pci_read_config_word(pdev
, PCI_STATUS
, &pci_status
);
3367 if (netif_msg_intr(tp
)) {
3369 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3370 dev
->name
, pci_cmd
, pci_status
);
3374 * The recovery sequence below admits a very elaborated explanation:
3375 * - it seems to work;
3376 * - I did not see what else could be done;
3377 * - it makes iop3xx happy.
3379 * Feel free to adjust to your needs.
3381 if (pdev
->broken_parity_status
)
3382 pci_cmd
&= ~PCI_COMMAND_PARITY
;
3384 pci_cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
;
3386 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
3388 pci_write_config_word(pdev
, PCI_STATUS
,
3389 pci_status
& (PCI_STATUS_DETECTED_PARITY
|
3390 PCI_STATUS_SIG_SYSTEM_ERROR
| PCI_STATUS_REC_MASTER_ABORT
|
3391 PCI_STATUS_REC_TARGET_ABORT
| PCI_STATUS_SIG_TARGET_ABORT
));
3393 /* The infamous DAC f*ckup only happens at boot time */
3394 if ((tp
->cp_cmd
& PCIDAC
) && !tp
->dirty_rx
&& !tp
->cur_rx
) {
3395 if (netif_msg_intr(tp
))
3396 printk(KERN_INFO
"%s: disabling PCI DAC.\n", dev
->name
);
3397 tp
->cp_cmd
&= ~PCIDAC
;
3398 RTL_W16(CPlusCmd
, tp
->cp_cmd
);
3399 dev
->features
&= ~NETIF_F_HIGHDMA
;
3402 rtl8169_hw_reset(ioaddr
);
3404 rtl8169_schedule_work(dev
, rtl8169_reinit_task
);
3407 static void rtl8169_tx_interrupt(struct net_device
*dev
,
3408 struct rtl8169_private
*tp
,
3409 void __iomem
*ioaddr
)
3411 unsigned int dirty_tx
, tx_left
;
3413 dirty_tx
= tp
->dirty_tx
;
3415 tx_left
= tp
->cur_tx
- dirty_tx
;
3417 while (tx_left
> 0) {
3418 unsigned int entry
= dirty_tx
% NUM_TX_DESC
;
3419 struct ring_info
*tx_skb
= tp
->tx_skb
+ entry
;
3420 u32 len
= tx_skb
->len
;
3424 status
= le32_to_cpu(tp
->TxDescArray
[entry
].opts1
);
3425 if (status
& DescOwn
)
3428 dev
->stats
.tx_bytes
+= len
;
3429 dev
->stats
.tx_packets
++;
3431 rtl8169_unmap_tx_skb(tp
->pci_dev
, tx_skb
, tp
->TxDescArray
+ entry
);
3433 if (status
& LastFrag
) {
3434 dev_kfree_skb_irq(tx_skb
->skb
);
3441 if (tp
->dirty_tx
!= dirty_tx
) {
3442 tp
->dirty_tx
= dirty_tx
;
3444 if (netif_queue_stopped(dev
) &&
3445 (TX_BUFFS_AVAIL(tp
) >= MAX_SKB_FRAGS
)) {
3446 netif_wake_queue(dev
);
3449 * 8168 hack: TxPoll requests are lost when the Tx packets are
3450 * too close. Let's kick an extra TxPoll request when a burst
3451 * of start_xmit activity is detected (if it is not detected,
3452 * it is slow enough). -- FR
3455 if (tp
->cur_tx
!= dirty_tx
)
3456 RTL_W8(TxPoll
, NPQ
);
3460 static inline int rtl8169_fragmented_frame(u32 status
)
3462 return (status
& (FirstFrag
| LastFrag
)) != (FirstFrag
| LastFrag
);
3465 static inline void rtl8169_rx_csum(struct sk_buff
*skb
, struct RxDesc
*desc
)
3467 u32 opts1
= le32_to_cpu(desc
->opts1
);
3468 u32 status
= opts1
& RxProtoMask
;
3470 if (((status
== RxProtoTCP
) && !(opts1
& TCPFail
)) ||
3471 ((status
== RxProtoUDP
) && !(opts1
& UDPFail
)) ||
3472 ((status
== RxProtoIP
) && !(opts1
& IPFail
)))
3473 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3475 skb
->ip_summed
= CHECKSUM_NONE
;
3478 static inline bool rtl8169_try_rx_copy(struct sk_buff
**sk_buff
,
3479 struct rtl8169_private
*tp
, int pkt_size
,
3482 struct sk_buff
*skb
;
3485 if (pkt_size
>= rx_copybreak
)
3488 skb
= netdev_alloc_skb(tp
->dev
, pkt_size
+ NET_IP_ALIGN
);
3492 pci_dma_sync_single_for_cpu(tp
->pci_dev
, addr
, pkt_size
,
3493 PCI_DMA_FROMDEVICE
);
3494 skb_reserve(skb
, NET_IP_ALIGN
);
3495 skb_copy_from_linear_data(*sk_buff
, skb
->data
, pkt_size
);
3502 static int rtl8169_rx_interrupt(struct net_device
*dev
,
3503 struct rtl8169_private
*tp
,
3504 void __iomem
*ioaddr
, u32 budget
)
3506 unsigned int cur_rx
, rx_left
;
3507 unsigned int delta
, count
;
3509 cur_rx
= tp
->cur_rx
;
3510 rx_left
= NUM_RX_DESC
+ tp
->dirty_rx
- cur_rx
;
3511 rx_left
= min(rx_left
, budget
);
3513 for (; rx_left
> 0; rx_left
--, cur_rx
++) {
3514 unsigned int entry
= cur_rx
% NUM_RX_DESC
;
3515 struct RxDesc
*desc
= tp
->RxDescArray
+ entry
;
3519 status
= le32_to_cpu(desc
->opts1
);
3521 if (status
& DescOwn
)
3523 if (unlikely(status
& RxRES
)) {
3524 if (netif_msg_rx_err(tp
)) {
3526 "%s: Rx ERROR. status = %08x\n",
3529 dev
->stats
.rx_errors
++;
3530 if (status
& (RxRWT
| RxRUNT
))
3531 dev
->stats
.rx_length_errors
++;
3533 dev
->stats
.rx_crc_errors
++;
3534 if (status
& RxFOVF
) {
3535 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3536 dev
->stats
.rx_fifo_errors
++;
3538 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3540 struct sk_buff
*skb
= tp
->Rx_skbuff
[entry
];
3541 dma_addr_t addr
= le64_to_cpu(desc
->addr
);
3542 int pkt_size
= (status
& 0x00001FFF) - 4;
3543 struct pci_dev
*pdev
= tp
->pci_dev
;
3546 * The driver does not support incoming fragmented
3547 * frames. They are seen as a symptom of over-mtu
3550 if (unlikely(rtl8169_fragmented_frame(status
))) {
3551 dev
->stats
.rx_dropped
++;
3552 dev
->stats
.rx_length_errors
++;
3553 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3557 rtl8169_rx_csum(skb
, desc
);
3559 if (rtl8169_try_rx_copy(&skb
, tp
, pkt_size
, addr
)) {
3560 pci_dma_sync_single_for_device(pdev
, addr
,
3561 pkt_size
, PCI_DMA_FROMDEVICE
);
3562 rtl8169_mark_to_asic(desc
, tp
->rx_buf_sz
);
3564 pci_unmap_single(pdev
, addr
, tp
->rx_buf_sz
,
3565 PCI_DMA_FROMDEVICE
);
3566 tp
->Rx_skbuff
[entry
] = NULL
;
3569 skb_put(skb
, pkt_size
);
3570 skb
->protocol
= eth_type_trans(skb
, dev
);
3572 if (rtl8169_rx_vlan_skb(tp
, desc
, skb
) < 0)
3573 netif_receive_skb(skb
);
3575 dev
->last_rx
= jiffies
;
3576 dev
->stats
.rx_bytes
+= pkt_size
;
3577 dev
->stats
.rx_packets
++;
3580 /* Work around for AMD plateform. */
3581 if ((desc
->opts2
& cpu_to_le32(0xfffe000)) &&
3582 (tp
->mac_version
== RTL_GIGA_MAC_VER_05
)) {
3588 count
= cur_rx
- tp
->cur_rx
;
3589 tp
->cur_rx
= cur_rx
;
3591 delta
= rtl8169_rx_fill(tp
, dev
, tp
->dirty_rx
, tp
->cur_rx
);
3592 if (!delta
&& count
&& netif_msg_intr(tp
))
3593 printk(KERN_INFO
"%s: no Rx buffer allocated\n", dev
->name
);
3594 tp
->dirty_rx
+= delta
;
3597 * FIXME: until there is periodic timer to try and refill the ring,
3598 * a temporary shortage may definitely kill the Rx process.
3599 * - disable the asic to try and avoid an overflow and kick it again
3601 * - how do others driver handle this condition (Uh oh...).
3603 if ((tp
->dirty_rx
+ NUM_RX_DESC
== tp
->cur_rx
) && netif_msg_intr(tp
))
3604 printk(KERN_EMERG
"%s: Rx buffers exhausted\n", dev
->name
);
3609 static irqreturn_t
rtl8169_interrupt(int irq
, void *dev_instance
)
3611 struct net_device
*dev
= dev_instance
;
3612 struct rtl8169_private
*tp
= netdev_priv(dev
);
3613 void __iomem
*ioaddr
= tp
->mmio_addr
;
3617 status
= RTL_R16(IntrStatus
);
3619 /* hotplug/major error/no more work/shared irq */
3620 if ((status
== 0xffff) || !status
)
3625 if (unlikely(!netif_running(dev
))) {
3626 rtl8169_asic_down(ioaddr
);
3630 status
&= tp
->intr_mask
;
3632 (status
& RxFIFOOver
) ? (status
| RxOverflow
) : status
);
3634 if (!(status
& tp
->intr_event
))
3637 /* Work around for rx fifo overflow */
3638 if (unlikely(status
& RxFIFOOver
) &&
3639 (tp
->mac_version
== RTL_GIGA_MAC_VER_11
)) {
3640 netif_stop_queue(dev
);
3641 rtl8169_tx_timeout(dev
);
3645 if (unlikely(status
& SYSErr
)) {
3646 rtl8169_pcierr_interrupt(dev
);
3650 if (status
& LinkChg
)
3651 rtl8169_check_link_status(dev
, tp
, ioaddr
);
3653 if (status
& tp
->napi_event
) {
3654 RTL_W16(IntrMask
, tp
->intr_event
& ~tp
->napi_event
);
3655 tp
->intr_mask
= ~tp
->napi_event
;
3657 if (likely(netif_rx_schedule_prep(dev
, &tp
->napi
)))
3658 __netif_rx_schedule(dev
, &tp
->napi
);
3659 else if (netif_msg_intr(tp
)) {
3660 printk(KERN_INFO
"%s: interrupt %04x in poll\n",
3665 return IRQ_RETVAL(handled
);
3668 static int rtl8169_poll(struct napi_struct
*napi
, int budget
)
3670 struct rtl8169_private
*tp
= container_of(napi
, struct rtl8169_private
, napi
);
3671 struct net_device
*dev
= tp
->dev
;
3672 void __iomem
*ioaddr
= tp
->mmio_addr
;
3675 work_done
= rtl8169_rx_interrupt(dev
, tp
, ioaddr
, (u32
) budget
);
3676 rtl8169_tx_interrupt(dev
, tp
, ioaddr
);
3678 if (work_done
< budget
) {
3679 netif_rx_complete(dev
, napi
);
3680 tp
->intr_mask
= 0xffff;
3682 * 20040426: the barrier is not strictly required but the
3683 * behavior of the irq handler could be less predictable
3684 * without it. Btw, the lack of flush for the posted pci
3685 * write is safe - FR
3688 RTL_W16(IntrMask
, tp
->intr_event
);
3694 static void rtl8169_rx_missed(struct net_device
*dev
, void __iomem
*ioaddr
)
3696 struct rtl8169_private
*tp
= netdev_priv(dev
);
3698 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
)
3701 dev
->stats
.rx_missed_errors
+= (RTL_R32(RxMissed
) & 0xffffff);
3702 RTL_W32(RxMissed
, 0);
3705 static void rtl8169_down(struct net_device
*dev
)
3707 struct rtl8169_private
*tp
= netdev_priv(dev
);
3708 void __iomem
*ioaddr
= tp
->mmio_addr
;
3709 unsigned int intrmask
;
3711 rtl8169_delete_timer(dev
);
3713 netif_stop_queue(dev
);
3715 napi_disable(&tp
->napi
);
3718 spin_lock_irq(&tp
->lock
);
3720 rtl8169_asic_down(ioaddr
);
3722 rtl8169_rx_missed(dev
, ioaddr
);
3724 spin_unlock_irq(&tp
->lock
);
3726 synchronize_irq(dev
->irq
);
3728 /* Give a racing hard_start_xmit a few cycles to complete. */
3729 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
3732 * And now for the 50k$ question: are IRQ disabled or not ?
3734 * Two paths lead here:
3736 * -> netif_running() is available to sync the current code and the
3737 * IRQ handler. See rtl8169_interrupt for details.
3738 * 2) dev->change_mtu
3739 * -> rtl8169_poll can not be issued again and re-enable the
3740 * interruptions. Let's simply issue the IRQ down sequence again.
3742 * No loop if hotpluged or major error (0xffff).
3744 intrmask
= RTL_R16(IntrMask
);
3745 if (intrmask
&& (intrmask
!= 0xffff))
3748 rtl8169_tx_clear(tp
);
3750 rtl8169_rx_clear(tp
);
3753 static int rtl8169_close(struct net_device
*dev
)
3755 struct rtl8169_private
*tp
= netdev_priv(dev
);
3756 struct pci_dev
*pdev
= tp
->pci_dev
;
3760 free_irq(dev
->irq
, dev
);
3762 pci_free_consistent(pdev
, R8169_RX_RING_BYTES
, tp
->RxDescArray
,
3764 pci_free_consistent(pdev
, R8169_TX_RING_BYTES
, tp
->TxDescArray
,
3766 tp
->TxDescArray
= NULL
;
3767 tp
->RxDescArray
= NULL
;
3772 static void rtl_set_rx_mode(struct net_device
*dev
)
3774 struct rtl8169_private
*tp
= netdev_priv(dev
);
3775 void __iomem
*ioaddr
= tp
->mmio_addr
;
3776 unsigned long flags
;
3777 u32 mc_filter
[2]; /* Multicast hash filter */
3781 if (dev
->flags
& IFF_PROMISC
) {
3782 /* Unconditionally log net taps. */
3783 if (netif_msg_link(tp
)) {
3784 printk(KERN_NOTICE
"%s: Promiscuous mode enabled.\n",
3788 AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
|
3790 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3791 } else if ((dev
->mc_count
> multicast_filter_limit
)
3792 || (dev
->flags
& IFF_ALLMULTI
)) {
3793 /* Too many to filter perfectly -- accept all multicasts. */
3794 rx_mode
= AcceptBroadcast
| AcceptMulticast
| AcceptMyPhys
;
3795 mc_filter
[1] = mc_filter
[0] = 0xffffffff;
3797 struct dev_mc_list
*mclist
;
3800 rx_mode
= AcceptBroadcast
| AcceptMyPhys
;
3801 mc_filter
[1] = mc_filter
[0] = 0;
3802 for (i
= 0, mclist
= dev
->mc_list
; mclist
&& i
< dev
->mc_count
;
3803 i
++, mclist
= mclist
->next
) {
3804 int bit_nr
= ether_crc(ETH_ALEN
, mclist
->dmi_addr
) >> 26;
3805 mc_filter
[bit_nr
>> 5] |= 1 << (bit_nr
& 31);
3806 rx_mode
|= AcceptMulticast
;
3810 spin_lock_irqsave(&tp
->lock
, flags
);
3812 tmp
= rtl8169_rx_config
| rx_mode
|
3813 (RTL_R32(RxConfig
) & rtl_chip_info
[tp
->chipset
].RxConfigMask
);
3815 if (tp
->mac_version
> RTL_GIGA_MAC_VER_06
) {
3816 u32 data
= mc_filter
[0];
3818 mc_filter
[0] = swab32(mc_filter
[1]);
3819 mc_filter
[1] = swab32(data
);
3822 RTL_W32(MAR0
+ 0, mc_filter
[0]);
3823 RTL_W32(MAR0
+ 4, mc_filter
[1]);
3825 RTL_W32(RxConfig
, tmp
);
3827 spin_unlock_irqrestore(&tp
->lock
, flags
);
3831 * rtl8169_get_stats - Get rtl8169 read/write statistics
3832 * @dev: The Ethernet Device to get statistics for
3834 * Get TX/RX statistics for rtl8169
3836 static struct net_device_stats
*rtl8169_get_stats(struct net_device
*dev
)
3838 struct rtl8169_private
*tp
= netdev_priv(dev
);
3839 void __iomem
*ioaddr
= tp
->mmio_addr
;
3840 unsigned long flags
;
3842 if (netif_running(dev
)) {
3843 spin_lock_irqsave(&tp
->lock
, flags
);
3844 rtl8169_rx_missed(dev
, ioaddr
);
3845 spin_unlock_irqrestore(&tp
->lock
, flags
);
3853 static int rtl8169_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3855 struct net_device
*dev
= pci_get_drvdata(pdev
);
3856 struct rtl8169_private
*tp
= netdev_priv(dev
);
3857 void __iomem
*ioaddr
= tp
->mmio_addr
;
3859 if (!netif_running(dev
))
3860 goto out_pci_suspend
;
3862 netif_device_detach(dev
);
3863 netif_stop_queue(dev
);
3865 spin_lock_irq(&tp
->lock
);
3867 rtl8169_asic_down(ioaddr
);
3869 rtl8169_rx_missed(dev
, ioaddr
);
3871 spin_unlock_irq(&tp
->lock
);
3874 pci_save_state(pdev
);
3875 pci_enable_wake(pdev
, pci_choose_state(pdev
, state
),
3876 (tp
->features
& RTL_FEATURE_WOL
) ? 1 : 0);
3877 pci_set_power_state(pdev
, pci_choose_state(pdev
, state
));
3882 static int rtl8169_resume(struct pci_dev
*pdev
)
3884 struct net_device
*dev
= pci_get_drvdata(pdev
);
3886 pci_set_power_state(pdev
, PCI_D0
);
3887 pci_restore_state(pdev
);
3888 pci_enable_wake(pdev
, PCI_D0
, 0);
3890 if (!netif_running(dev
))
3893 netif_device_attach(dev
);
3895 rtl8169_schedule_work(dev
, rtl8169_reset_task
);
3900 static void rtl_shutdown(struct pci_dev
*pdev
)
3902 rtl8169_suspend(pdev
, PMSG_SUSPEND
);
3905 #endif /* CONFIG_PM */
3907 static struct pci_driver rtl8169_pci_driver
= {
3909 .id_table
= rtl8169_pci_tbl
,
3910 .probe
= rtl8169_init_one
,
3911 .remove
= __devexit_p(rtl8169_remove_one
),
3913 .suspend
= rtl8169_suspend
,
3914 .resume
= rtl8169_resume
,
3915 .shutdown
= rtl_shutdown
,
3919 static int __init
rtl8169_init_module(void)
3921 return pci_register_driver(&rtl8169_pci_driver
);
3924 static void __exit
rtl8169_cleanup_module(void)
3926 pci_unregister_driver(&rtl8169_pci_driver
);
3929 module_init(rtl8169_init_module
);
3930 module_exit(rtl8169_cleanup_module
);