include/asm-blackfin/mach-bf548/bf548.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf548/bf548.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:  System MMR register and memory map for ADSP-BF548
   8  *
   9  * Modified:
  10  *               Copyright 2004-2007 Analog Devices Inc.
  11  *
  12  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2 of the License, or
  17  * (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, see the file COPYING, or write
  26  * to the Free Software Foundation, Inc.,
  27  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  28  */
  29
  30 #ifndef __MACH_BF548_H__
  31 #define __MACH_BF548_H__
  32
  33 #define SUPPORTED_REVID 0
  34
  35 #define OFFSET_(x) ((x) & 0x0000FFFF)
  36
  37 /*some misc defines*/
  38 #define IMASK_IVG15             0x8000
  39 #define IMASK_IVG14             0x4000
  40 #define IMASK_IVG13             0x2000
  41 #define IMASK_IVG12             0x1000
  42
  43 #define IMASK_IVG11             0x0800
  44 #define IMASK_IVG10             0x0400
  45 #define IMASK_IVG9              0x0200
  46 #define IMASK_IVG8              0x0100
  47
  48 #define IMASK_IVG7              0x0080
  49 #define IMASK_IVGTMR    0x0040
  50 #define IMASK_IVGHW             0x0020
  51
  52 /***************************/
  53
  54
  55 #define BLKFIN_DSUBBANKS        4
  56 #define BLKFIN_DWAYS            2
  57 #define BLKFIN_DLINES           64
  58 #define BLKFIN_ISUBBANKS        4
  59 #define BLKFIN_IWAYS            4
  60 #define BLKFIN_ILINES           32
  61
  62 #define WAY0_L                  0x1
  63 #define WAY1_L                  0x2
  64 #define WAY01_L                 0x3
  65 #define WAY2_L                  0x4
  66 #define WAY02_L                 0x5
  67 #define WAY12_L                 0x6
  68 #define WAY012_L                0x7
  69
  70 #define WAY3_L                  0x8
  71 #define WAY03_L                 0x9
  72 #define WAY13_L                 0xA
  73 #define WAY013_L                0xB
  74
  75 #define WAY32_L                 0xC
  76 #define WAY320_L                0xD
  77 #define WAY321_L                0xE
  78 #define WAYALL_L                0xF
  79
  80 #define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
  81
  82 /********************************* EBIU Settings ************************************/
  83 #define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
  84 #define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
  85
  86 #ifdef CONFIG_C_AMBEN_ALL
  87 #define V_AMBEN AMBEN_ALL
  88 #endif
  89 #ifdef CONFIG_C_AMBEN
  90 #define V_AMBEN 0x0
  91 #endif
  92 #ifdef CONFIG_C_AMBEN_B0
  93 #define V_AMBEN AMBEN_B0
  94 #endif
  95 #ifdef CONFIG_C_AMBEN_B0_B1
  96 #define V_AMBEN AMBEN_B0_B1
  97 #endif
  98 #ifdef CONFIG_C_AMBEN_B0_B1_B2
  99 #define V_AMBEN AMBEN_B0_B1_B2
 100 #endif
 101 #ifdef CONFIG_C_AMCKEN
 102 #define V_AMCKEN AMCKEN
 103 #else
 104 #define V_AMCKEN 0x0
 105 #endif
 106
 107 #define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
 108
 109 #define MAX_VC  650000000
 110 #define MIN_VC  50000000
 111
 112 /********************************PLL Settings **************************************/
 113 #ifdef CONFIG_BFIN_KERNEL_CLOCK
 114 #if (CONFIG_VCO_MULT < 0)
 115 #error "VCO Multiplier is less than 0. Please select a different value"
 116 #endif
 117
 118 #if (CONFIG_VCO_MULT == 0)
 119 #error "VCO Multiplier should be greater than 0. Please select a different value"
 120 #endif
 121
 122 #if (CONFIG_VCO_MULT > 64)
 123 #error "VCO Multiplier is more than 64. Please select a different value"
 124 #endif
 125
 126 #ifndef CONFIG_CLKIN_HALF
 127 #define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
 128 #else
 129 #define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
 130 #endif
 131
 132 #ifndef CONFIG_PLL_BYPASS
 133 #define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
 134 #define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
 135 #else
 136 #define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
 137 #define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
 138 #endif
 139
 140 #if (CONFIG_SCLK_DIV < 1)
 141 #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
 142 #endif
 143
 144 #if (CONFIG_SCLK_DIV > 15)
 145 #error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
 146 #endif
 147
 148 #if (CONFIG_CCLK_DIV != 1)
 149 #if (CONFIG_CCLK_DIV != 2)
 150 #if (CONFIG_CCLK_DIV != 4)
 151 #if (CONFIG_CCLK_DIV != 8)
 152 #error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
 153 #endif
 154 #endif
 155 #endif
 156 #endif
 157
 158 #if (CONFIG_VCO_HZ > MAX_VC)
 159 #error "VCO selected is more than maximum value. Please change the VCO multipler"
 160 #endif
 161
 162 #if (CONFIG_SCLK_HZ > 133000000)
 163 #error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
 164 #endif
 165
 166 #if (CONFIG_SCLK_HZ < 27000000)
 167 #error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
 168 #endif
 169
 170 #if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
 171 #if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
 172 #if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
 173 #error "Please select sclk less than cclk"
 174 #endif
 175 #endif
 176 #endif
 177
 178 #if (CONFIG_CCLK_DIV == 1)
 179 #define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
 180 #endif
 181 #if (CONFIG_CCLK_DIV == 2)
 182 #define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
 183 #endif
 184 #if (CONFIG_CCLK_DIV == 4)
 185 #define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
 186 #endif
 187 #if (CONFIG_CCLK_DIV == 8)
 188 #define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
 189 #endif
 190 #ifndef CONFIG_CCLK_ACT_DIV
 191 #define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
 192 #endif
 193
 194 #endif  /* CONFIG_BFIN_KERNEL_CLOCK */
 195
 196 #ifdef CONFIG_BF542
 197 #define CPU "BF542"
 198 #define CPUID 0x027c8000
 199 #endif
 200 #ifdef CONFIG_BF544
 201 #define CPU "BF544"
 202 #define CPUID 0x027c8000
 203 #endif
 204 #ifdef CONFIG_BF548
 205 #define CPU "BF548"
 206 #define CPUID 0x027c6000
 207 #endif
 208 #ifdef CONFIG_BF549
 209 #define CPU "BF549"
 210 #endif
 211 #ifndef CPU
 212 #define CPU "UNKNOWN"
 213 #define CPUID 0x0
 214 #endif
 215
 216 #if (CONFIG_MEM_SIZE % 4)
 217 #error "SDRAM mem size must be multible of 4MB"
 218 #endif
 219
 220 #define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
 221 #define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
 222 #define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
 223 #define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
 224
 225 /*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
 226
 227 #define ANOMALY_05000158_WORKAROUND             0x200
 228 #ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
 229 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
 230                         | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
 231 #else                           /*Write Through */
 232 #define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
 233                         | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
 234 #endif
 235
 236
 237 #define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
 238 #define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
 239 #define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
 240 #define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
 241
 242 #define SIZE_1K 0x00000400      /* 1K */
 243 #define SIZE_4K 0x00001000      /* 4K */
 244 #define SIZE_1M 0x00100000      /* 1M */
 245 #define SIZE_4M 0x00400000      /* 4M */
 246
 247 #define MAX_CPLBS (16 * 2)
 248
 249 /*
 250 * Number of required data CPLB switchtable entries
 251 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
 252 * approx 16 for smaller 1MB page size CPLBs for allignment purposes
 253 * 1 for L1 Data Memory
 254 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
 255 * 1 for ASYNC Memory
 256 */
 257
 258
 259 #define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
 260
 261 /*
 262 * Number of required instruction CPLB switchtable entries
 263 * MEMSIZE / 4 (we mostly install 4M page size CPLBs
 264 * approx 12 for smaller 1MB page size CPLBs for allignment purposes
 265 * 1 for L1 Instruction Memory
 266 * 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
 267 */
 268
 269 #define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
 270
 271 #endif  /* __MACH_BF48_H__  */