2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 /* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
37 /* For use by IPS driver */
38 extern unsigned long i915_read_mch_val(void);
39 extern bool i915_gpu_raise(void);
40 extern bool i915_gpu_lower(void);
41 extern bool i915_gpu_busy(void);
42 extern bool i915_gpu_turbo_disable(void);
45 /* Each region is a minimum of 16k, and there are at most 255 of them.
47 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
48 * of chars for next/prev indices */
49 #define I915_LOG_MIN_TEX_REGION_SIZE 14
51 typedef struct _drm_i915_init
{
54 I915_CLEANUP_DMA
= 0x02,
55 I915_RESUME_DMA
= 0x03
57 unsigned int mmio_offset
;
58 int sarea_priv_offset
;
59 unsigned int ring_start
;
60 unsigned int ring_end
;
61 unsigned int ring_size
;
62 unsigned int front_offset
;
63 unsigned int back_offset
;
64 unsigned int depth_offset
;
68 unsigned int pitch_bits
;
69 unsigned int back_pitch
;
70 unsigned int depth_pitch
;
75 typedef struct _drm_i915_sarea
{
76 struct drm_tex_region texList
[I915_NR_TEX_REGIONS
+ 1];
77 int last_upload
; /* last time texture was uploaded */
78 int last_enqueue
; /* last time a buffer was enqueued */
79 int last_dispatch
; /* age of the most recently dispatched buffer */
80 int ctxOwner
; /* last context to upload state */
82 int pf_enabled
; /* is pageflipping allowed? */
84 int pf_current_page
; /* which buffer is being displayed? */
85 int perf_boxes
; /* performance boxes to be displayed */
86 int width
, height
; /* screen size in pixels */
88 drm_handle_t front_handle
;
92 drm_handle_t back_handle
;
96 drm_handle_t depth_handle
;
100 drm_handle_t tex_handle
;
103 int log_tex_granularity
;
105 int rotation
; /* 0, 90, 180 or 270 */
109 int virtualX
, virtualY
;
111 unsigned int front_tiled
;
112 unsigned int back_tiled
;
113 unsigned int depth_tiled
;
114 unsigned int rotated_tiled
;
115 unsigned int rotated2_tiled
;
126 /* fill out some space for old userspace triple buffer */
127 drm_handle_t unused_handle
;
128 __u32 unused1
, unused2
, unused3
;
130 /* buffer object handles for static buffers. May change
131 * over the lifetime of the client.
133 __u32 front_bo_handle
;
134 __u32 back_bo_handle
;
135 __u32 unused_bo_handle
;
136 __u32 depth_bo_handle
;
140 /* due to userspace building against these headers we need some compat here */
141 #define planeA_x pipeA_x
142 #define planeA_y pipeA_y
143 #define planeA_w pipeA_w
144 #define planeA_h pipeA_h
145 #define planeB_x pipeB_x
146 #define planeB_y pipeB_y
147 #define planeB_w pipeB_w
148 #define planeB_h pipeB_h
150 /* Flags for perf_boxes
152 #define I915_BOX_RING_EMPTY 0x1
153 #define I915_BOX_FLIP 0x2
154 #define I915_BOX_WAIT 0x4
155 #define I915_BOX_TEXTURE_LOAD 0x8
156 #define I915_BOX_LOST_CONTEXT 0x10
158 /* I915 specific ioctls
159 * The device specific ioctl range is 0x40 to 0x79.
161 #define DRM_I915_INIT 0x00
162 #define DRM_I915_FLUSH 0x01
163 #define DRM_I915_FLIP 0x02
164 #define DRM_I915_BATCHBUFFER 0x03
165 #define DRM_I915_IRQ_EMIT 0x04
166 #define DRM_I915_IRQ_WAIT 0x05
167 #define DRM_I915_GETPARAM 0x06
168 #define DRM_I915_SETPARAM 0x07
169 #define DRM_I915_ALLOC 0x08
170 #define DRM_I915_FREE 0x09
171 #define DRM_I915_INIT_HEAP 0x0a
172 #define DRM_I915_CMDBUFFER 0x0b
173 #define DRM_I915_DESTROY_HEAP 0x0c
174 #define DRM_I915_SET_VBLANK_PIPE 0x0d
175 #define DRM_I915_GET_VBLANK_PIPE 0x0e
176 #define DRM_I915_VBLANK_SWAP 0x0f
177 #define DRM_I915_HWS_ADDR 0x11
178 #define DRM_I915_GEM_INIT 0x13
179 #define DRM_I915_GEM_EXECBUFFER 0x14
180 #define DRM_I915_GEM_PIN 0x15
181 #define DRM_I915_GEM_UNPIN 0x16
182 #define DRM_I915_GEM_BUSY 0x17
183 #define DRM_I915_GEM_THROTTLE 0x18
184 #define DRM_I915_GEM_ENTERVT 0x19
185 #define DRM_I915_GEM_LEAVEVT 0x1a
186 #define DRM_I915_GEM_CREATE 0x1b
187 #define DRM_I915_GEM_PREAD 0x1c
188 #define DRM_I915_GEM_PWRITE 0x1d
189 #define DRM_I915_GEM_MMAP 0x1e
190 #define DRM_I915_GEM_SET_DOMAIN 0x1f
191 #define DRM_I915_GEM_SW_FINISH 0x20
192 #define DRM_I915_GEM_SET_TILING 0x21
193 #define DRM_I915_GEM_GET_TILING 0x22
194 #define DRM_I915_GEM_GET_APERTURE 0x23
195 #define DRM_I915_GEM_MMAP_GTT 0x24
196 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
197 #define DRM_I915_GEM_MADVISE 0x26
198 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
199 #define DRM_I915_OVERLAY_ATTRS 0x28
200 #define DRM_I915_GEM_EXECBUFFER2 0x29
201 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
202 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
204 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
205 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
206 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
207 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
208 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
209 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
210 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
211 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
212 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
213 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
214 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
215 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
216 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
217 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
218 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
219 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
220 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
221 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
222 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
223 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
224 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
225 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
226 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
227 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
228 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
229 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
230 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
231 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
232 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
233 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
234 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
235 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
236 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
237 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
238 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
239 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
240 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
241 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
242 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
243 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
244 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
245 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
247 /* Allow drivers to submit batchbuffers directly to hardware, relying
248 * on the security mechanisms provided by hardware.
250 typedef struct drm_i915_batchbuffer
{
251 int start
; /* agp offset */
252 int used
; /* nr bytes in use */
253 int DR1
; /* hw flags for GFX_OP_DRAWRECT_INFO */
254 int DR4
; /* window origin for GFX_OP_DRAWRECT_INFO */
255 int num_cliprects
; /* mulitpass with multiple cliprects? */
256 struct drm_clip_rect __user
*cliprects
; /* pointer to userspace cliprects */
257 } drm_i915_batchbuffer_t
;
259 /* As above, but pass a pointer to userspace buffer which can be
260 * validated by the kernel prior to sending to hardware.
262 typedef struct _drm_i915_cmdbuffer
{
263 char __user
*buf
; /* pointer to userspace command buffer */
264 int sz
; /* nr bytes in buf */
265 int DR1
; /* hw flags for GFX_OP_DRAWRECT_INFO */
266 int DR4
; /* window origin for GFX_OP_DRAWRECT_INFO */
267 int num_cliprects
; /* mulitpass with multiple cliprects? */
268 struct drm_clip_rect __user
*cliprects
; /* pointer to userspace cliprects */
269 } drm_i915_cmdbuffer_t
;
271 /* Userspace can request & wait on irq's:
273 typedef struct drm_i915_irq_emit
{
275 } drm_i915_irq_emit_t
;
277 typedef struct drm_i915_irq_wait
{
279 } drm_i915_irq_wait_t
;
281 /* Ioctl to query kernel params:
283 #define I915_PARAM_IRQ_ACTIVE 1
284 #define I915_PARAM_ALLOW_BATCHBUFFER 2
285 #define I915_PARAM_LAST_DISPATCH 3
286 #define I915_PARAM_CHIPSET_ID 4
287 #define I915_PARAM_HAS_GEM 5
288 #define I915_PARAM_NUM_FENCES_AVAIL 6
289 #define I915_PARAM_HAS_OVERLAY 7
290 #define I915_PARAM_HAS_PAGEFLIPPING 8
291 #define I915_PARAM_HAS_EXECBUF2 9
292 #define I915_PARAM_HAS_BSD 10
293 #define I915_PARAM_HAS_BLT 11
294 #define I915_PARAM_HAS_RELAXED_FENCING 12
295 #define I915_PARAM_HAS_COHERENT_RINGS 13
296 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
297 #define I915_PARAM_HAS_RELAXED_DELTA 15
298 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
299 #define I915_PARAM_HAS_LLC 17
301 typedef struct drm_i915_getparam
{
304 } drm_i915_getparam_t
;
306 /* Ioctl to set kernel params:
308 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
309 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
310 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
311 #define I915_SETPARAM_NUM_USED_FENCES 4
313 typedef struct drm_i915_setparam
{
316 } drm_i915_setparam_t
;
318 /* A memory manager for regions of shared memory:
320 #define I915_MEM_REGION_AGP 1
322 typedef struct drm_i915_mem_alloc
{
326 int __user
*region_offset
; /* offset from start of fb or agp */
327 } drm_i915_mem_alloc_t
;
329 typedef struct drm_i915_mem_free
{
332 } drm_i915_mem_free_t
;
334 typedef struct drm_i915_mem_init_heap
{
338 } drm_i915_mem_init_heap_t
;
340 /* Allow memory manager to be torn down and re-initialized (eg on
343 typedef struct drm_i915_mem_destroy_heap
{
345 } drm_i915_mem_destroy_heap_t
;
347 /* Allow X server to configure which pipes to monitor for vblank signals
349 #define DRM_I915_VBLANK_PIPE_A 1
350 #define DRM_I915_VBLANK_PIPE_B 2
352 typedef struct drm_i915_vblank_pipe
{
354 } drm_i915_vblank_pipe_t
;
356 /* Schedule buffer swap at given vertical blank:
358 typedef struct drm_i915_vblank_swap
{
359 drm_drawable_t drawable
;
360 enum drm_vblank_seq_type seqtype
;
361 unsigned int sequence
;
362 } drm_i915_vblank_swap_t
;
364 typedef struct drm_i915_hws_addr
{
366 } drm_i915_hws_addr_t
;
368 struct drm_i915_gem_init
{
370 * Beginning offset in the GTT to be managed by the DRM memory
375 * Ending offset in the GTT to be managed by the DRM memory
381 struct drm_i915_gem_create
{
383 * Requested size for the object.
385 * The (page-aligned) allocated size for the object will be returned.
389 * Returned handle for the object.
391 * Object handles are nonzero.
397 struct drm_i915_gem_pread
{
398 /** Handle for the object being read. */
401 /** Offset into the object to read from */
403 /** Length of data to read */
406 * Pointer to write the data into.
408 * This is a fixed-size type for 32/64 compatibility.
413 struct drm_i915_gem_pwrite
{
414 /** Handle for the object being written to. */
417 /** Offset into the object to write to */
419 /** Length of data to write */
422 * Pointer to read the data from.
424 * This is a fixed-size type for 32/64 compatibility.
429 struct drm_i915_gem_mmap
{
430 /** Handle for the object being mapped. */
433 /** Offset in the object to map. */
436 * Length of data to map.
438 * The value will be page-aligned.
442 * Returned pointer the data was mapped at.
444 * This is a fixed-size type for 32/64 compatibility.
449 struct drm_i915_gem_mmap_gtt
{
450 /** Handle for the object being mapped. */
454 * Fake offset to use for subsequent mmap call
456 * This is a fixed-size type for 32/64 compatibility.
461 struct drm_i915_gem_set_domain
{
462 /** Handle for the object */
465 /** New read domains */
468 /** New write domain */
472 struct drm_i915_gem_sw_finish
{
473 /** Handle for the object */
477 struct drm_i915_gem_relocation_entry
{
479 * Handle of the buffer being pointed to by this relocation entry.
481 * It's appealing to make this be an index into the mm_validate_entry
482 * list to refer to the buffer, but this allows the driver to create
483 * a relocation list for state buffers and not re-write it per
484 * exec using the buffer.
489 * Value to be added to the offset of the target buffer to make up
490 * the relocation entry.
494 /** Offset in the buffer the relocation entry will be written into */
498 * Offset value of the target buffer that the relocation entry was last
501 * If the buffer has the same offset as last time, we can skip syncing
502 * and writing the relocation. This value is written back out by
503 * the execbuffer ioctl when the relocation is written.
505 __u64 presumed_offset
;
508 * Target memory domains read by this operation.
513 * Target memory domains written by this operation.
515 * Note that only one domain may be written by the whole
516 * execbuffer operation, so that where there are conflicts,
517 * the application will get -EINVAL back.
523 * Intel memory domains
525 * Most of these just align with the various caches in
526 * the system and are used to flush and invalidate as
527 * objects end up cached in different domains.
530 #define I915_GEM_DOMAIN_CPU 0x00000001
531 /** Render cache, used by 2D and 3D drawing */
532 #define I915_GEM_DOMAIN_RENDER 0x00000002
533 /** Sampler cache, used by texture engine */
534 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
535 /** Command queue, used to load batch buffers */
536 #define I915_GEM_DOMAIN_COMMAND 0x00000008
537 /** Instruction cache, used by shader programs */
538 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
539 /** Vertex address cache */
540 #define I915_GEM_DOMAIN_VERTEX 0x00000020
541 /** GTT domain - aperture and scanout */
542 #define I915_GEM_DOMAIN_GTT 0x00000040
545 struct drm_i915_gem_exec_object
{
547 * User's handle for a buffer to be bound into the GTT for this
552 /** Number of relocations to be performed on this buffer */
553 __u32 relocation_count
;
555 * Pointer to array of struct drm_i915_gem_relocation_entry containing
556 * the relocations to be performed in this buffer.
560 /** Required alignment in graphics aperture */
564 * Returned value of the updated offset of the object, for future
565 * presumed_offset writes.
570 struct drm_i915_gem_execbuffer
{
572 * List of buffers to be validated with their relocations to be
573 * performend on them.
575 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
577 * These buffers must be listed in an order such that all relocations
578 * a buffer is performing refer to buffers that have already appeared
579 * in the validate list.
584 /** Offset in the batchbuffer to start execution from. */
585 __u32 batch_start_offset
;
586 /** Bytes used in batchbuffer from batch_start_offset */
591 /** This is a struct drm_clip_rect *cliprects */
595 struct drm_i915_gem_exec_object2
{
597 * User's handle for a buffer to be bound into the GTT for this
602 /** Number of relocations to be performed on this buffer */
603 __u32 relocation_count
;
605 * Pointer to array of struct drm_i915_gem_relocation_entry containing
606 * the relocations to be performed in this buffer.
610 /** Required alignment in graphics aperture */
614 * Returned value of the updated offset of the object, for future
615 * presumed_offset writes.
619 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
625 struct drm_i915_gem_execbuffer2
{
627 * List of gem_exec_object2 structs
632 /** Offset in the batchbuffer to start execution from. */
633 __u32 batch_start_offset
;
634 /** Bytes used in batchbuffer from batch_start_offset */
639 /** This is a struct drm_clip_rect *cliprects */
641 #define I915_EXEC_RING_MASK (7<<0)
642 #define I915_EXEC_DEFAULT (0<<0)
643 #define I915_EXEC_RENDER (1<<0)
644 #define I915_EXEC_BSD (2<<0)
645 #define I915_EXEC_BLT (3<<0)
647 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
648 * Gen6+ only supports relative addressing to dynamic state (default) and
649 * absolute addressing.
651 * These flags are ignored for the BSD and BLT rings.
653 #define I915_EXEC_CONSTANTS_MASK (3<<6)
654 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
655 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
656 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
662 /** Resets the SO write offset registers for transform feedback on gen7. */
663 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
665 struct drm_i915_gem_pin
{
666 /** Handle of the buffer to be pinned. */
670 /** alignment required within the aperture */
673 /** Returned GTT offset of the buffer. */
677 struct drm_i915_gem_unpin
{
678 /** Handle of the buffer to be unpinned. */
683 struct drm_i915_gem_busy
{
684 /** Handle of the buffer to check for busy */
687 /** Return busy status (1 if busy, 0 if idle) */
691 #define I915_TILING_NONE 0
692 #define I915_TILING_X 1
693 #define I915_TILING_Y 2
695 #define I915_BIT_6_SWIZZLE_NONE 0
696 #define I915_BIT_6_SWIZZLE_9 1
697 #define I915_BIT_6_SWIZZLE_9_10 2
698 #define I915_BIT_6_SWIZZLE_9_11 3
699 #define I915_BIT_6_SWIZZLE_9_10_11 4
700 /* Not seen by userland */
701 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
702 /* Seen by userland. */
703 #define I915_BIT_6_SWIZZLE_9_17 6
704 #define I915_BIT_6_SWIZZLE_9_10_17 7
706 struct drm_i915_gem_set_tiling
{
707 /** Handle of the buffer to have its tiling state updated */
711 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
714 * This value is to be set on request, and will be updated by the
715 * kernel on successful return with the actual chosen tiling layout.
717 * The tiling mode may be demoted to I915_TILING_NONE when the system
718 * has bit 6 swizzling that can't be managed correctly by GEM.
720 * Buffer contents become undefined when changing tiling_mode.
725 * Stride in bytes for the object when in I915_TILING_X or
731 * Returned address bit 6 swizzling required for CPU access through
737 struct drm_i915_gem_get_tiling
{
738 /** Handle of the buffer to get tiling state for. */
742 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
748 * Returned address bit 6 swizzling required for CPU access through
754 struct drm_i915_gem_get_aperture
{
755 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
759 * Available space in the aperture used by i915_gem_execbuffer, in
762 __u64 aper_available_size
;
765 struct drm_i915_get_pipe_from_crtc_id
{
766 /** ID of CRTC being requested **/
769 /** pipe of requested CRTC **/
773 #define I915_MADV_WILLNEED 0
774 #define I915_MADV_DONTNEED 1
775 #define __I915_MADV_PURGED 2 /* internal state */
777 struct drm_i915_gem_madvise
{
778 /** Handle of the buffer to change the backing store advice */
781 /* Advice: either the buffer will be needed again in the near future,
782 * or wont be and could be discarded under memory pressure.
786 /** Whether the backing store still exists. */
791 #define I915_OVERLAY_TYPE_MASK 0xff
792 #define I915_OVERLAY_YUV_PLANAR 0x01
793 #define I915_OVERLAY_YUV_PACKED 0x02
794 #define I915_OVERLAY_RGB 0x03
796 #define I915_OVERLAY_DEPTH_MASK 0xff00
797 #define I915_OVERLAY_RGB24 0x1000
798 #define I915_OVERLAY_RGB16 0x2000
799 #define I915_OVERLAY_RGB15 0x3000
800 #define I915_OVERLAY_YUV422 0x0100
801 #define I915_OVERLAY_YUV411 0x0200
802 #define I915_OVERLAY_YUV420 0x0300
803 #define I915_OVERLAY_YUV410 0x0400
805 #define I915_OVERLAY_SWAP_MASK 0xff0000
806 #define I915_OVERLAY_NO_SWAP 0x000000
807 #define I915_OVERLAY_UV_SWAP 0x010000
808 #define I915_OVERLAY_Y_SWAP 0x020000
809 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
811 #define I915_OVERLAY_FLAGS_MASK 0xff000000
812 #define I915_OVERLAY_ENABLE 0x01000000
814 struct drm_intel_overlay_put_image
{
815 /* various flags and src format description */
817 /* source picture description */
819 /* stride values and offsets are in bytes, buffer relative */
820 __u16 stride_Y
; /* stride for packed formats */
822 __u32 offset_Y
; /* offset for packet formats */
828 /* to compensate the scaling factors for partially covered surfaces */
829 __u16 src_scan_width
;
830 __u16 src_scan_height
;
831 /* output crtc description */
840 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
841 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
842 struct drm_intel_overlay_attrs
{
857 * Intel sprite handling
859 * Color keying works with a min/mask/max tuple. Both source and destination
860 * color keying is allowed.
863 * Sprite pixels within the min & max values, masked against the color channels
864 * specified in the mask field, will be transparent. All other pixels will
865 * be displayed on top of the primary plane. For RGB surfaces, only the min
866 * and mask fields will be used; ranged compares are not allowed.
868 * Destination keying:
869 * Primary plane pixels that match the min value, masked against the color
870 * channels specified in the mask field, will be replaced by corresponding
871 * pixels from the sprite plane.
873 * Note that source & destination keying are exclusive; only one can be
874 * active on a given plane.
877 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
878 #define I915_SET_COLORKEY_DESTINATION (1<<1)
879 #define I915_SET_COLORKEY_SOURCE (1<<2)
880 struct drm_intel_sprite_colorkey
{
888 #endif /* _I915_DRM_H_ */