drivers/net/wireless/b43/phy_lcn.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n LCN-PHY support
   5
   6   This program is free software; you can redistribute it and/or modify
   7   it under the terms of the GNU General Public License as published by
   8   the Free Software Foundation; either version 2 of the License, or
   9   (at your option) any later version.
  10
  11   This program is distributed in the hope that it will be useful,
  12   but WITHOUT ANY WARRANTY; without even the implied warranty of
  13   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14   GNU General Public License for more details.
  15
  16   You should have received a copy of the GNU General Public License
  17   along with this program; see the file COPYING.  If not, write to
  18   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  19   Boston, MA 02110-1301, USA.
  20
  21 */
  22
  23 #include <linux/slab.h>
  24
  25 #include "b43.h"
  26 #include "phy_lcn.h"
  27 #include "tables_phy_lcn.h"
  28 #include "main.h"
  29
  30 /**************************************************
  31  * Radio 2064.
  32  **************************************************/
  33
  34 static void b43_radio_2064_channel_setup(struct b43_wldev *dev)
  35 {
  36         u16 save[2];
  37
  38         b43_radio_set(dev, 0x09d, 0x4);
  39         b43_radio_write(dev, 0x09e, 0xf);
  40
  41         b43_radio_write(dev, 0x02a, 0xb);
  42         b43_radio_maskset(dev, 0x030, ~0x3, 0xa);
  43         b43_radio_maskset(dev, 0x091, ~0x3, 0);
  44         b43_radio_maskset(dev, 0x038, ~0xf, 0x7);
  45         b43_radio_maskset(dev, 0x030, ~0xc, 0x8);
  46         b43_radio_maskset(dev, 0x05e, ~0xf, 0x8);
  47         b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80);
  48         b43_radio_write(dev, 0x06c, 0x80);
  49
  50         save[0] = b43_radio_read(dev, 0x044);
  51         save[1] = b43_radio_read(dev, 0x12b);
  52
  53         b43_radio_set(dev, 0x044, 0x7);
  54         b43_radio_set(dev, 0x12b, 0xe);
  55
  56         /* TODO */
  57
  58         b43_radio_write(dev, 0x040, 0xfb);
  59
  60         b43_radio_write(dev, 0x041, 0x9a);
  61         b43_radio_write(dev, 0x042, 0xa3);
  62         b43_radio_write(dev, 0x043, 0x0c);
  63
  64         /* TODO */
  65
  66         b43_radio_set(dev, 0x044, 0x0c);
  67         udelay(1);
  68
  69         b43_radio_write(dev, 0x044, save[0]);
  70         b43_radio_write(dev, 0x12b, save[1]);
  71
  72         b43_radio_write(dev, 0x038, 0x0);
  73         b43_radio_write(dev, 0x091, 0x7);
  74 }
  75
  76 static void b43_radio_2064_init(struct b43_wldev *dev)
  77 {
  78         b43_radio_write(dev, 0x09c, 0x0020);
  79         b43_radio_write(dev, 0x105, 0x0008);
  80         b43_radio_write(dev, 0x032, 0x0062);
  81         b43_radio_write(dev, 0x033, 0x0019);
  82         b43_radio_write(dev, 0x090, 0x0010);
  83         b43_radio_write(dev, 0x010, 0x0000);
  84         b43_radio_write(dev, 0x060, 0x007f);
  85         b43_radio_write(dev, 0x061, 0x0072);
  86         b43_radio_write(dev, 0x062, 0x007f);
  87         b43_radio_write(dev, 0x01d, 0x0002);
  88         b43_radio_write(dev, 0x01e, 0x0006);
  89
  90         b43_phy_write(dev, 0x4ea, 0x4688);
  91         b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
  92         b43_phy_mask(dev, 0x4eb, ~0x01c0);
  93         b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);
  94
  95         b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);
  96
  97         b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
  98         b43_radio_set(dev, 0x004, 0x40);
  99         b43_radio_set(dev, 0x120, 0x10);
 100         b43_radio_set(dev, 0x078, 0x80);
 101         b43_radio_set(dev, 0x129, 0x2);
 102         b43_radio_set(dev, 0x057, 0x1);
 103         b43_radio_set(dev, 0x05b, 0x2);
 104
 105         /* TODO: wait for some bit to be set */
 106         b43_radio_read(dev, 0x05c);
 107
 108         b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
 109         b43_radio_mask(dev, 0x057, (u16) ~0xff01);
 110
 111         b43_phy_write(dev, 0x933, 0x2d6b);
 112         b43_phy_write(dev, 0x934, 0x2d6b);
 113         b43_phy_write(dev, 0x935, 0x2d6b);
 114         b43_phy_write(dev, 0x936, 0x2d6b);
 115         b43_phy_write(dev, 0x937, 0x016b);
 116
 117         b43_radio_mask(dev, 0x057, (u16) ~0xff02);
 118         b43_radio_write(dev, 0x0c2, 0x006f);
 119 }
 120
 121 /**************************************************
 122  * Various PHY ops
 123  **************************************************/
 124
 125 static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
 126 {
 127         u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
 128         u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);
 129
 130         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1);
 131         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1);
 132
 133         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
 134         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);
 135
 136         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
 137         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
 138 }
 139
 140 static void b43_phy_lcn_clear_0x07_table(struct b43_wldev *dev)
 141 {
 142         u8 i;
 143
 144         b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340);
 145         for (i = 0; i < 30; i++) {
 146                 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
 147                 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
 148         }
 149
 150         b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80);
 151         for (i = 0; i < 64; i++) {
 152                 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
 153                 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
 154         }
 155 }
 156
 157 static void b43_phy_lcn_pre_radio_init(struct b43_wldev *dev)
 158 {
 159         b43_radio_write(dev, 0x11c, 0);
 160
 161         b43_phy_write(dev, 0x43b, 0);
 162         b43_phy_write(dev, 0x43c, 0);
 163         b43_phy_write(dev, 0x44c, 0);
 164         b43_phy_write(dev, 0x4e6, 0);
 165         b43_phy_write(dev, 0x4f9, 0);
 166         b43_phy_write(dev, 0x4b0, 0);
 167         b43_phy_write(dev, 0x938, 0);
 168         b43_phy_write(dev, 0x4b0, 0);
 169         b43_phy_write(dev, 0x44e, 0);
 170
 171         b43_phy_set(dev, 0x567, 0x03);
 172
 173         b43_phy_set(dev, 0x44a, 0x44);
 174         b43_phy_write(dev, 0x44a, 0x80);
 175
 176         b43_phy_maskset(dev, 0x634, ~0xff, 0xc);
 177         b43_phy_maskset(dev, 0x634, ~0xff, 0xa);
 178
 179         b43_phy_write(dev, 0x910, 0x1);
 180
 181         b43_phy_maskset(dev, 0x448, ~0x300, 0x100);
 182         b43_phy_maskset(dev, 0x608, ~0xff, 0x17);
 183         b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);
 184
 185         b43_phy_set(dev, 0x805, 0x1);
 186
 187         b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
 188         b43_phy_maskset(dev, 0x030, ~0x7, 0x3);
 189
 190         b43_phy_write(dev, 0x414, 0x1e10);
 191         b43_phy_write(dev, 0x415, 0x0640);
 192
 193         b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);
 194
 195         b43_phy_set(dev, 0x44a, 0x44);
 196         b43_phy_write(dev, 0x44a, 0x80);
 197
 198         b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
 199         b43_phy_maskset(dev, 0x420, ~0xff, 0x10);
 200
 201         b43_radio_set(dev, 0x09b, 0xf0);
 202
 203         b43_phy_write(dev, 0x7d6, 0x0902);
 204
 205         /* TODO: more ops */
 206 }
 207
 208 static void b43_phy_lcn_save_configsth_restore(struct b43_wldev *dev)
 209 {
 210         u8 i;
 211
 212         u16 save_radio_regs[6][2] = {
 213                 { 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 },
 214                 { 0x025, 0 }, { 0x112, 0 },
 215         };
 216         u16 save_phy_regs[14][2] = {
 217                 { 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 },
 218                 { 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 },
 219                 { 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 },
 220                 { 0x40d, 0 }, { 0x4a2, 0 },
 221         };
 222         u16 save_radio_4a4;
 223
 224         for (i = 0; i < 6; i++)
 225                 save_radio_regs[i][1] = b43_radio_read(dev,
 226                                                        save_radio_regs[i][0]);
 227         for (i = 0; i < 14; i++)
 228                 save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);
 229         save_radio_4a4 = b43_radio_read(dev, 0x4a4);
 230
 231         /* TODO: config sth */
 232
 233         for (i = 0; i < 6; i++)
 234                 b43_radio_write(dev, save_radio_regs[i][0],
 235                                 save_radio_regs[i][1]);
 236         for (i = 0; i < 14; i++)
 237                 b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);
 238         b43_radio_write(dev, 0x4a4, save_radio_4a4);
 239 }
 240
 241 /**************************************************
 242  * Channel switching ops.
 243  **************************************************/
 244
 245 static int b43_phy_lcn_set_channel(struct b43_wldev *dev,
 246                                    struct ieee80211_channel *channel,
 247                                    enum nl80211_channel_type channel_type)
 248 {
 249         /* TODO: PLL and PHY ops */
 250
 251         b43_phy_set(dev, 0x44a, 0x44);
 252         b43_phy_write(dev, 0x44a, 0x80);
 253
 254         b43_phy_set(dev, 0x44a, 0x44);
 255         b43_phy_write(dev, 0x44a, 0x80);
 256
 257         b43_radio_2064_channel_setup(dev);
 258         mdelay(1);
 259
 260         b43_phy_lcn_afe_set_unset(dev);
 261
 262         /* TODO */
 263
 264         return 0;
 265 }
 266
 267 /**************************************************
 268  * Basic PHY ops.
 269  **************************************************/
 270
 271 static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
 272 {
 273         struct b43_phy_lcn *phy_lcn;
 274
 275         phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
 276         if (!phy_lcn)
 277                 return -ENOMEM;
 278         dev->phy.lcn = phy_lcn;
 279
 280         return 0;
 281 }
 282
 283 static void b43_phy_lcn_op_free(struct b43_wldev *dev)
 284 {
 285         struct b43_phy *phy = &dev->phy;
 286         struct b43_phy_lcn *phy_lcn = phy->lcn;
 287
 288         kfree(phy_lcn);
 289         phy->lcn = NULL;
 290 }
 291
 292 static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
 293 {
 294         struct b43_phy *phy = &dev->phy;
 295         struct b43_phy_lcn *phy_lcn = phy->lcn;
 296
 297         memset(phy_lcn, 0, sizeof(*phy_lcn));
 298 }
 299
 300 static int b43_phy_lcn_op_init(struct b43_wldev *dev)
 301 {
 302         b43_phy_set(dev, 0x44a, 0x80);
 303         b43_phy_mask(dev, 0x44a, 0x7f);
 304         b43_phy_set(dev, 0x6d1, 0x80);
 305         b43_phy_write(dev, 0x6d0, 0x7);
 306
 307         b43_phy_lcn_afe_set_unset(dev);
 308
 309         b43_phy_write(dev, 0x60a, 0xa0);
 310         b43_phy_write(dev, 0x46a, 0x19);
 311         b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);
 312
 313         b43_phy_lcn_tables_init(dev);
 314
 315         b43_phy_lcn_pre_radio_init(dev);
 316         b43_phy_lcn_clear_0x07_table(dev);
 317
 318         if (dev->phy.radio_ver == 0x2064)
 319                 b43_radio_2064_init(dev);
 320         else
 321                 B43_WARN_ON(1);
 322
 323         b43_phy_lcn_save_configsth_restore(dev);
 324
 325         return 0;
 326 }
 327
 328 static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
 329                                         bool blocked)
 330 {
 331         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 332                 b43err(dev->wl, "MAC not suspended\n");
 333
 334         if (blocked) {
 335                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
 336                 b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);
 337
 338                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
 339                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
 340                 b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);
 341
 342                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
 343                 b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
 344         } else {
 345                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
 346                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
 347                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
 348         }
 349 }
 350
 351 static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
 352 {
 353         if (on) {
 354                 b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
 355         } else {
 356                 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
 357                 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
 358         }
 359 }
 360
 361 static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,
 362                                         unsigned int new_channel)
 363 {
 364         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 365         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 366
 367         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 368                 if ((new_channel < 1) || (new_channel > 14))
 369                         return -EINVAL;
 370         } else {
 371                 return -EINVAL;
 372         }
 373
 374         return b43_phy_lcn_set_channel(dev, channel, channel_type);
 375 }
 376
 377 static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
 378 {
 379         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 380                 return 1;
 381         return 36;
 382 }
 383
 384 static enum b43_txpwr_result
 385 b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
 386 {
 387         return B43_TXPWR_RES_DONE;
 388 }
 389
 390 static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
 391 {
 392 }
 393
 394 /**************************************************
 395  * R/W ops.
 396  **************************************************/
 397
 398 static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
 399 {
 400         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 401         return b43_read16(dev, B43_MMIO_PHY_DATA);
 402 }
 403
 404 static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 405 {
 406         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 407         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 408 }
 409
 410 static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 411                                    u16 set)
 412 {
 413         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 414         b43_write16(dev, B43_MMIO_PHY_DATA,
 415                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 416 }
 417
 418 static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
 419 {
 420         /* LCN-PHY needs 0x200 for read access */
 421         reg |= 0x200;
 422
 423         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 424         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 425 }
 426
 427 static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
 428                                        u16 value)
 429 {
 430         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 431         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 432 }
 433
 434 /**************************************************
 435  * PHY ops struct.
 436  **************************************************/
 437
 438 const struct b43_phy_operations b43_phyops_lcn = {
 439         .allocate               = b43_phy_lcn_op_allocate,
 440         .free                   = b43_phy_lcn_op_free,
 441         .prepare_structs        = b43_phy_lcn_op_prepare_structs,
 442         .init                   = b43_phy_lcn_op_init,
 443         .phy_read               = b43_phy_lcn_op_read,
 444         .phy_write              = b43_phy_lcn_op_write,
 445         .phy_maskset            = b43_phy_lcn_op_maskset,
 446         .radio_read             = b43_phy_lcn_op_radio_read,
 447         .radio_write            = b43_phy_lcn_op_radio_write,
 448         .software_rfkill        = b43_phy_lcn_op_software_rfkill,
 449         .switch_analog          = b43_phy_lcn_op_switch_analog,
 450         .switch_channel         = b43_phy_lcn_op_switch_channel,
 451         .get_default_chan       = b43_phy_lcn_op_get_default_chan,
 452         .recalc_txpower         = b43_phy_lcn_op_recalc_txpower,
 453         .adjust_txpower         = b43_phy_lcn_op_adjust_txpower,
 454 };