2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_enum(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
40 uint32_t supported_device
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 uint32_t igp_lane_info
,
50 uint16_t connector_object_id
,
51 struct radeon_hpd
*hpd
,
52 struct radeon_router
*router
);
54 /* from radeon_legacy_encoder.c */
56 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_enum
,
57 uint32_t supported_device
);
59 union atom_supported_devices
{
60 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
62 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
65 static inline struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
68 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
69 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
70 struct radeon_i2c_bus_rec i2c
;
71 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
72 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
73 uint16_t data_offset
, size
;
76 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
79 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
80 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
82 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
83 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
85 for (i
= 0; i
< num_indices
; i
++) {
86 gpio
= &i2c_info
->asGPIO_Info
[i
];
88 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev
)) {
91 (gpio
->usClkMaskRegisterIndex
== 0x1936) &&
92 (gpio
->sucI2cId
.ucAccess
== 0)) {
93 gpio
->sucI2cId
.ucAccess
= 0x97;
94 gpio
->ucDataMaskShift
= 8;
95 gpio
->ucDataEnShift
= 8;
96 gpio
->ucDataY_Shift
= 8;
97 gpio
->ucDataA_Shift
= 8;
101 if (gpio
->sucI2cId
.ucAccess
== id
) {
102 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
103 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
104 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
105 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
106 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
107 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
108 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
109 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
110 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
111 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
112 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
113 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
114 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
115 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
116 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
117 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
119 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
120 i2c
.hw_capable
= true;
122 i2c
.hw_capable
= false;
124 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
129 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
131 if (i2c
.mask_clk_reg
)
141 void radeon_atombios_i2c_init(struct radeon_device
*rdev
)
143 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
144 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
145 struct radeon_i2c_bus_rec i2c
;
146 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
147 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
148 uint16_t data_offset
, size
;
152 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
154 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
155 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
157 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
158 sizeof(ATOM_GPIO_I2C_ASSIGMENT
);
160 for (i
= 0; i
< num_indices
; i
++) {
161 gpio
= &i2c_info
->asGPIO_Info
[i
];
164 /* some evergreen boards have bad data for this entry */
165 if (ASIC_IS_DCE4(rdev
)) {
167 (gpio
->usClkMaskRegisterIndex
== 0x1936) &&
168 (gpio
->sucI2cId
.ucAccess
== 0)) {
169 gpio
->sucI2cId
.ucAccess
= 0x97;
170 gpio
->ucDataMaskShift
= 8;
171 gpio
->ucDataEnShift
= 8;
172 gpio
->ucDataY_Shift
= 8;
173 gpio
->ucDataA_Shift
= 8;
177 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
178 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
179 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
180 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
181 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
182 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
183 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
184 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
185 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
186 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
187 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
188 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
189 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
190 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
191 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
192 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
194 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
195 i2c
.hw_capable
= true;
197 i2c
.hw_capable
= false;
199 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
204 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
206 if (i2c
.mask_clk_reg
) {
208 sprintf(stmp
, "0x%x", i2c
.i2c_id
);
209 rdev
->i2c_bus
[i
] = radeon_i2c_create(rdev
->ddev
, &i2c
, stmp
);
215 static inline struct radeon_gpio_rec
radeon_lookup_gpio(struct radeon_device
*rdev
,
218 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
219 struct radeon_gpio_rec gpio
;
220 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
221 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
222 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
223 u16 data_offset
, size
;
226 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
229 if (atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
)) {
230 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
232 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
233 sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
235 for (i
= 0; i
< num_indices
; i
++) {
236 pin
= &gpio_info
->asGPIO_Pin
[i
];
237 if (id
== pin
->ucGPIO_ID
) {
238 gpio
.id
= pin
->ucGPIO_ID
;
239 gpio
.reg
= pin
->usGpioPin_AIndex
* 4;
240 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
250 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
251 struct radeon_gpio_rec
*gpio
)
253 struct radeon_hpd hpd
;
256 memset(&hpd
, 0, sizeof(struct radeon_hpd
));
258 if (ASIC_IS_DCE4(rdev
))
259 reg
= EVERGREEN_DC_GPIO_HPD_A
;
261 reg
= AVIVO_DC_GPIO_HPD_A
;
264 if (gpio
->reg
== reg
) {
267 hpd
.hpd
= RADEON_HPD_1
;
270 hpd
.hpd
= RADEON_HPD_2
;
273 hpd
.hpd
= RADEON_HPD_3
;
276 hpd
.hpd
= RADEON_HPD_4
;
279 hpd
.hpd
= RADEON_HPD_5
;
282 hpd
.hpd
= RADEON_HPD_6
;
285 hpd
.hpd
= RADEON_HPD_NONE
;
289 hpd
.hpd
= RADEON_HPD_NONE
;
293 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
294 uint32_t supported_device
,
296 struct radeon_i2c_bus_rec
*i2c_bus
,
298 struct radeon_hpd
*hpd
)
300 struct radeon_device
*rdev
= dev
->dev_private
;
302 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
303 if ((dev
->pdev
->device
== 0x791e) &&
304 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
305 (dev
->pdev
->subsystem_device
== 0x826d)) {
306 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
307 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
308 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
311 /* Asrock RS600 board lists the DVI port as HDMI */
312 if ((dev
->pdev
->device
== 0x7941) &&
313 (dev
->pdev
->subsystem_vendor
== 0x1849) &&
314 (dev
->pdev
->subsystem_device
== 0x7941)) {
315 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
316 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
317 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
320 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
321 if ((dev
->pdev
->device
== 0x796e) &&
322 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
323 (dev
->pdev
->subsystem_device
== 0x7302)) {
324 if ((supported_device
== ATOM_DEVICE_DFP2_SUPPORT
) ||
325 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
329 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
330 if ((dev
->pdev
->device
== 0x7941) &&
331 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
332 (dev
->pdev
->subsystem_device
== 0x2412)) {
333 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
337 /* Falcon NW laptop lists vga ddc line for LVDS */
338 if ((dev
->pdev
->device
== 0x5653) &&
339 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
340 (dev
->pdev
->subsystem_device
== 0x0291)) {
341 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
342 i2c_bus
->valid
= false;
347 /* HIS X1300 is DVI+VGA, not DVI+DVI */
348 if ((dev
->pdev
->device
== 0x7146) &&
349 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
350 (dev
->pdev
->subsystem_device
== 0x2058)) {
351 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
355 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
356 if ((dev
->pdev
->device
== 0x7142) &&
357 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
358 (dev
->pdev
->subsystem_device
== 0x2134)) {
359 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
365 if ((dev
->pdev
->device
== 0x71C5) &&
366 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
367 (dev
->pdev
->subsystem_device
== 0x0080)) {
368 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
369 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
371 if (supported_device
== ATOM_DEVICE_CRT2_SUPPORT
)
375 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
376 if ((dev
->pdev
->device
== 0x9598) &&
377 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
378 (dev
->pdev
->subsystem_device
== 0x01da)) {
379 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
380 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
384 /* ASUS HD 3600 board lists the DVI port as HDMI */
385 if ((dev
->pdev
->device
== 0x9598) &&
386 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
387 (dev
->pdev
->subsystem_device
== 0x01e4)) {
388 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
389 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
393 /* ASUS HD 3450 board lists the DVI port as HDMI */
394 if ((dev
->pdev
->device
== 0x95C5) &&
395 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
396 (dev
->pdev
->subsystem_device
== 0x01e2)) {
397 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
398 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
402 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
403 * HDMI + VGA reporting as HDMI
405 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
406 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
407 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
412 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
413 if ((dev
->pdev
->device
== 0x95c4) &&
414 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
415 (dev
->pdev
->subsystem_device
== 0x013c)) {
416 struct radeon_gpio_rec gpio
;
418 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
419 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
420 gpio
= radeon_lookup_gpio(rdev
, 6);
421 *hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
422 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
423 } else if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
424 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)) {
425 gpio
= radeon_lookup_gpio(rdev
, 7);
426 *hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
430 /* XFX Pine Group device rv730 reports no VGA DDC lines
431 * even though they are wired up to record 0x93
433 if ((dev
->pdev
->device
== 0x9498) &&
434 (dev
->pdev
->subsystem_vendor
== 0x1682) &&
435 (dev
->pdev
->subsystem_device
== 0x2452)) {
436 struct radeon_device
*rdev
= dev
->dev_private
;
437 *i2c_bus
= radeon_lookup_i2c_gpio(rdev
, 0x93);
442 const int supported_devices_connector_convert
[] = {
443 DRM_MODE_CONNECTOR_Unknown
,
444 DRM_MODE_CONNECTOR_VGA
,
445 DRM_MODE_CONNECTOR_DVII
,
446 DRM_MODE_CONNECTOR_DVID
,
447 DRM_MODE_CONNECTOR_DVIA
,
448 DRM_MODE_CONNECTOR_SVIDEO
,
449 DRM_MODE_CONNECTOR_Composite
,
450 DRM_MODE_CONNECTOR_LVDS
,
451 DRM_MODE_CONNECTOR_Unknown
,
452 DRM_MODE_CONNECTOR_Unknown
,
453 DRM_MODE_CONNECTOR_HDMIA
,
454 DRM_MODE_CONNECTOR_HDMIB
,
455 DRM_MODE_CONNECTOR_Unknown
,
456 DRM_MODE_CONNECTOR_Unknown
,
457 DRM_MODE_CONNECTOR_9PinDIN
,
458 DRM_MODE_CONNECTOR_DisplayPort
461 const uint16_t supported_devices_connector_object_id_convert
[] = {
462 CONNECTOR_OBJECT_ID_NONE
,
463 CONNECTOR_OBJECT_ID_VGA
,
464 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
465 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
466 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
467 CONNECTOR_OBJECT_ID_COMPOSITE
,
468 CONNECTOR_OBJECT_ID_SVIDEO
,
469 CONNECTOR_OBJECT_ID_LVDS
,
470 CONNECTOR_OBJECT_ID_9PIN_DIN
,
471 CONNECTOR_OBJECT_ID_9PIN_DIN
,
472 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
473 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
474 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
475 CONNECTOR_OBJECT_ID_SVIDEO
478 const int object_connector_convert
[] = {
479 DRM_MODE_CONNECTOR_Unknown
,
480 DRM_MODE_CONNECTOR_DVII
,
481 DRM_MODE_CONNECTOR_DVII
,
482 DRM_MODE_CONNECTOR_DVID
,
483 DRM_MODE_CONNECTOR_DVID
,
484 DRM_MODE_CONNECTOR_VGA
,
485 DRM_MODE_CONNECTOR_Composite
,
486 DRM_MODE_CONNECTOR_SVIDEO
,
487 DRM_MODE_CONNECTOR_Unknown
,
488 DRM_MODE_CONNECTOR_Unknown
,
489 DRM_MODE_CONNECTOR_9PinDIN
,
490 DRM_MODE_CONNECTOR_Unknown
,
491 DRM_MODE_CONNECTOR_HDMIA
,
492 DRM_MODE_CONNECTOR_HDMIB
,
493 DRM_MODE_CONNECTOR_LVDS
,
494 DRM_MODE_CONNECTOR_9PinDIN
,
495 DRM_MODE_CONNECTOR_Unknown
,
496 DRM_MODE_CONNECTOR_Unknown
,
497 DRM_MODE_CONNECTOR_Unknown
,
498 DRM_MODE_CONNECTOR_DisplayPort
,
499 DRM_MODE_CONNECTOR_eDP
,
500 DRM_MODE_CONNECTOR_Unknown
503 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
505 struct radeon_device
*rdev
= dev
->dev_private
;
506 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
507 struct atom_context
*ctx
= mode_info
->atom_context
;
508 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
509 u16 size
, data_offset
;
511 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
512 ATOM_OBJECT_TABLE
*router_obj
;
513 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
514 ATOM_OBJECT_HEADER
*obj_header
;
515 int i
, j
, k
, path_size
, device_support
;
517 u16 igp_lane_info
, conn_id
, connector_object_id
;
518 struct radeon_i2c_bus_rec ddc_bus
;
519 struct radeon_router router
;
520 struct radeon_gpio_rec gpio
;
521 struct radeon_hpd hpd
;
523 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
))
529 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
530 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
531 (ctx
->bios
+ data_offset
+
532 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
533 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
534 (ctx
->bios
+ data_offset
+
535 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
536 router_obj
= (ATOM_OBJECT_TABLE
*)
537 (ctx
->bios
+ data_offset
+
538 le16_to_cpu(obj_header
->usRouterObjectTableOffset
));
539 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
542 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
543 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
544 ATOM_DISPLAY_OBJECT_PATH
*path
;
546 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
547 path_size
+= le16_to_cpu(path
->usSize
);
549 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
550 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
553 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
556 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
559 (le16_to_cpu(path
->usConnObjectId
) &
560 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
562 /* TODO CV support */
563 if (le16_to_cpu(path
->usDeviceTag
) ==
564 ATOM_DEVICE_CV_SUPPORT
)
568 if ((rdev
->flags
& RADEON_IS_IGP
) &&
570 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
571 uint16_t igp_offset
= 0;
572 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
575 GetIndexIntoMasterTable(DATA
,
576 IntegratedSystemInfo
);
578 if (atom_parse_data_header(ctx
, index
, &size
, &frev
,
579 &crev
, &igp_offset
)) {
583 (ATOM_INTEGRATED_SYSTEM_INFO_V2
584 *) (ctx
->bios
+ igp_offset
);
587 uint32_t slot_config
, ct
;
589 if (con_obj_num
== 1)
598 ct
= (slot_config
>> 16) & 0xff;
600 object_connector_convert
602 connector_object_id
= ct
;
604 slot_config
& 0xffff;
612 object_connector_convert
[con_obj_id
];
613 connector_object_id
= con_obj_id
;
618 object_connector_convert
[con_obj_id
];
619 connector_object_id
= con_obj_id
;
622 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
625 router
.ddc_valid
= false;
626 router
.cd_valid
= false;
627 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2); j
++) {
628 uint8_t grph_obj_id
, grph_obj_num
, grph_obj_type
;
631 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
632 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
634 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
635 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
637 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
638 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
640 if (grph_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
641 u16 encoder_obj
= le16_to_cpu(path
->usGraphicObjIds
[j
]);
643 radeon_add_atom_encoder(dev
,
649 } else if (grph_obj_type
== GRAPH_OBJECT_TYPE_ROUTER
) {
650 for (k
= 0; k
< router_obj
->ucNumberOfObjects
; k
++) {
651 u16 router_obj_id
= le16_to_cpu(router_obj
->asObjects
[k
].usObjectID
);
652 if (le16_to_cpu(path
->usGraphicObjIds
[j
]) == router_obj_id
) {
653 ATOM_COMMON_RECORD_HEADER
*record
= (ATOM_COMMON_RECORD_HEADER
*)
654 (ctx
->bios
+ data_offset
+
655 le16_to_cpu(router_obj
->asObjects
[k
].usRecordOffset
));
656 ATOM_I2C_RECORD
*i2c_record
;
657 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
658 ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*ddc_path
;
659 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*cd_path
;
660 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*router_src_dst_table
=
661 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT
*)
662 (ctx
->bios
+ data_offset
+
663 le16_to_cpu(router_obj
->asObjects
[k
].usSrcDstTableOffset
));
666 router
.router_id
= router_obj_id
;
667 for (enum_id
= 0; enum_id
< router_src_dst_table
->ucNumberOfDst
;
669 if (le16_to_cpu(path
->usConnObjectId
) ==
670 le16_to_cpu(router_src_dst_table
->usDstObjectID
[enum_id
]))
674 while (record
->ucRecordType
> 0 &&
675 record
->ucRecordType
<= ATOM_MAX_OBJECT_RECORD_NUMBER
) {
676 switch (record
->ucRecordType
) {
677 case ATOM_I2C_RECORD_TYPE
:
682 (ATOM_I2C_ID_CONFIG_ACCESS
*)
683 &i2c_record
->sucI2cId
;
685 radeon_lookup_i2c_gpio(rdev
,
688 router
.i2c_addr
= i2c_record
->ucI2CAddr
>> 1;
690 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE
:
691 ddc_path
= (ATOM_ROUTER_DDC_PATH_SELECT_RECORD
*)
693 router
.ddc_valid
= true;
694 router
.ddc_mux_type
= ddc_path
->ucMuxType
;
695 router
.ddc_mux_control_pin
= ddc_path
->ucMuxControlPin
;
696 router
.ddc_mux_state
= ddc_path
->ucMuxState
[enum_id
];
698 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE
:
699 cd_path
= (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD
*)
701 router
.cd_valid
= true;
702 router
.cd_mux_type
= cd_path
->ucMuxType
;
703 router
.cd_mux_control_pin
= cd_path
->ucMuxControlPin
;
704 router
.cd_mux_state
= cd_path
->ucMuxState
[enum_id
];
707 record
= (ATOM_COMMON_RECORD_HEADER
*)
708 ((char *)record
+ record
->ucRecordSize
);
715 /* look up gpio for ddc, hpd */
716 ddc_bus
.valid
= false;
717 hpd
.hpd
= RADEON_HPD_NONE
;
718 if ((le16_to_cpu(path
->usDeviceTag
) &
719 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
720 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
721 if (le16_to_cpu(path
->usConnObjectId
) ==
722 le16_to_cpu(con_obj
->asObjects
[j
].
724 ATOM_COMMON_RECORD_HEADER
726 (ATOM_COMMON_RECORD_HEADER
728 (ctx
->bios
+ data_offset
+
729 le16_to_cpu(con_obj
->
732 ATOM_I2C_RECORD
*i2c_record
;
733 ATOM_HPD_INT_RECORD
*hpd_record
;
734 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
736 while (record
->ucRecordType
> 0
739 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
740 switch (record
->ucRecordType
) {
741 case ATOM_I2C_RECORD_TYPE
:
746 (ATOM_I2C_ID_CONFIG_ACCESS
*)
747 &i2c_record
->sucI2cId
;
748 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
752 case ATOM_HPD_INT_RECORD_TYPE
:
754 (ATOM_HPD_INT_RECORD
*)
756 gpio
= radeon_lookup_gpio(rdev
,
757 hpd_record
->ucHPDIntGPIOID
);
758 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
759 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
763 (ATOM_COMMON_RECORD_HEADER
774 /* needed for aux chan transactions */
775 ddc_bus
.hpd
= hpd
.hpd
;
777 conn_id
= le16_to_cpu(path
->usConnObjectId
);
779 if (!radeon_atom_apply_quirks
780 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
781 &ddc_bus
, &conn_id
, &hpd
))
784 radeon_add_atom_connector(dev
,
788 connector_type
, &ddc_bus
,
797 radeon_link_encoder_connector(dev
);
802 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
806 struct radeon_device
*rdev
= dev
->dev_private
;
808 if (rdev
->flags
& RADEON_IS_IGP
) {
809 return supported_devices_connector_object_id_convert
811 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
812 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
813 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
814 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
815 struct atom_context
*ctx
= mode_info
->atom_context
;
816 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
817 uint16_t size
, data_offset
;
819 ATOM_XTMDS_INFO
*xtmds
;
821 if (atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
)) {
822 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
824 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
825 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
826 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
828 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
830 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
831 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
833 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
836 return supported_devices_connector_object_id_convert
839 return supported_devices_connector_object_id_convert
844 struct bios_connector
{
849 struct radeon_i2c_bus_rec ddc_bus
;
850 struct radeon_hpd hpd
;
853 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
857 struct radeon_device
*rdev
= dev
->dev_private
;
858 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
859 struct atom_context
*ctx
= mode_info
->atom_context
;
860 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
861 uint16_t size
, data_offset
;
863 uint16_t device_support
;
865 union atom_supported_devices
*supported_devices
;
866 int i
, j
, max_device
;
867 struct bios_connector
*bios_connectors
;
868 size_t bc_size
= sizeof(*bios_connectors
) * ATOM_MAX_SUPPORTED_DEVICE
;
869 struct radeon_router router
;
871 router
.ddc_valid
= false;
872 router
.cd_valid
= false;
874 bios_connectors
= kzalloc(bc_size
, GFP_KERNEL
);
875 if (!bios_connectors
)
878 if (!atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
,
880 kfree(bios_connectors
);
885 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
887 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
890 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
892 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
894 for (i
= 0; i
< max_device
; i
++) {
895 ATOM_CONNECTOR_INFO_I2C ci
=
896 supported_devices
->info
.asConnInfo
[i
];
898 bios_connectors
[i
].valid
= false;
900 if (!(device_support
& (1 << i
))) {
904 if (i
== ATOM_DEVICE_CV_INDEX
) {
905 DRM_DEBUG_KMS("Skipping Component Video\n");
909 bios_connectors
[i
].connector_type
=
910 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
914 if (bios_connectors
[i
].connector_type
==
915 DRM_MODE_CONNECTOR_Unknown
)
918 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
920 bios_connectors
[i
].line_mux
=
921 ci
.sucI2cId
.ucAccess
;
923 /* give tv unique connector ids */
924 if (i
== ATOM_DEVICE_TV1_INDEX
) {
925 bios_connectors
[i
].ddc_bus
.valid
= false;
926 bios_connectors
[i
].line_mux
= 50;
927 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
928 bios_connectors
[i
].ddc_bus
.valid
= false;
929 bios_connectors
[i
].line_mux
= 51;
930 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
931 bios_connectors
[i
].ddc_bus
.valid
= false;
932 bios_connectors
[i
].line_mux
= 52;
934 bios_connectors
[i
].ddc_bus
=
935 radeon_lookup_i2c_gpio(rdev
,
936 bios_connectors
[i
].line_mux
);
938 if ((crev
> 1) && (frev
> 1)) {
939 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
942 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
945 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
948 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
952 if (i
== ATOM_DEVICE_DFP1_INDEX
)
953 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
954 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
955 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
957 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
960 /* Always set the connector type to VGA for CRT1/CRT2. if they are
961 * shared with a DVI port, we'll pick up the DVI connector when we
962 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
964 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
965 bios_connectors
[i
].connector_type
=
966 DRM_MODE_CONNECTOR_VGA
;
968 if (!radeon_atom_apply_quirks
969 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
970 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
971 &bios_connectors
[i
].hpd
))
974 bios_connectors
[i
].valid
= true;
975 bios_connectors
[i
].devices
= (1 << i
);
977 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
978 radeon_add_atom_encoder(dev
,
979 radeon_get_encoder_enum(dev
,
984 radeon_add_legacy_encoder(dev
,
985 radeon_get_encoder_enum(dev
,
991 /* combine shared connectors */
992 for (i
= 0; i
< max_device
; i
++) {
993 if (bios_connectors
[i
].valid
) {
994 for (j
= 0; j
< max_device
; j
++) {
995 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
996 if (bios_connectors
[i
].line_mux
==
997 bios_connectors
[j
].line_mux
) {
998 /* make sure not to combine LVDS */
999 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1000 bios_connectors
[i
].line_mux
= 53;
1001 bios_connectors
[i
].ddc_bus
.valid
= false;
1004 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1005 bios_connectors
[j
].line_mux
= 53;
1006 bios_connectors
[j
].ddc_bus
.valid
= false;
1009 /* combine analog and digital for DVI-I */
1010 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1011 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
1012 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
1013 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
1014 bios_connectors
[i
].devices
|=
1015 bios_connectors
[j
].devices
;
1016 bios_connectors
[i
].connector_type
=
1017 DRM_MODE_CONNECTOR_DVII
;
1018 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
1019 bios_connectors
[i
].hpd
=
1020 bios_connectors
[j
].hpd
;
1021 bios_connectors
[j
].valid
= false;
1029 /* add the connectors */
1030 for (i
= 0; i
< max_device
; i
++) {
1031 if (bios_connectors
[i
].valid
) {
1032 uint16_t connector_object_id
=
1033 atombios_get_connector_object_id(dev
,
1034 bios_connectors
[i
].connector_type
,
1035 bios_connectors
[i
].devices
);
1036 radeon_add_atom_connector(dev
,
1037 bios_connectors
[i
].line_mux
,
1038 bios_connectors
[i
].devices
,
1041 &bios_connectors
[i
].ddc_bus
,
1043 connector_object_id
,
1044 &bios_connectors
[i
].hpd
,
1049 radeon_link_encoder_connector(dev
);
1051 kfree(bios_connectors
);
1055 union firmware_info
{
1056 ATOM_FIRMWARE_INFO info
;
1057 ATOM_FIRMWARE_INFO_V1_2 info_12
;
1058 ATOM_FIRMWARE_INFO_V1_3 info_13
;
1059 ATOM_FIRMWARE_INFO_V1_4 info_14
;
1060 ATOM_FIRMWARE_INFO_V2_1 info_21
;
1063 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
1065 struct radeon_device
*rdev
= dev
->dev_private
;
1066 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1067 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
1068 union firmware_info
*firmware_info
;
1070 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
1071 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
1072 struct radeon_pll
*dcpll
= &rdev
->clock
.dcpll
;
1073 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
1074 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
1075 uint16_t data_offset
;
1077 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1078 &frev
, &crev
, &data_offset
)) {
1080 (union firmware_info
*)(mode_info
->atom_context
->bios
+
1083 p1pll
->reference_freq
=
1084 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1085 p1pll
->reference_div
= 0;
1088 p1pll
->pll_out_min
=
1089 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
1091 p1pll
->pll_out_min
=
1092 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
1093 p1pll
->pll_out_max
=
1094 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
1097 p1pll
->lcd_pll_out_min
=
1098 le16_to_cpu(firmware_info
->info_14
.usLcdMinPixelClockPLL_Output
) * 100;
1099 if (p1pll
->lcd_pll_out_min
== 0)
1100 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1101 p1pll
->lcd_pll_out_max
=
1102 le16_to_cpu(firmware_info
->info_14
.usLcdMaxPixelClockPLL_Output
) * 100;
1103 if (p1pll
->lcd_pll_out_max
== 0)
1104 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1106 p1pll
->lcd_pll_out_min
= p1pll
->pll_out_min
;
1107 p1pll
->lcd_pll_out_max
= p1pll
->pll_out_max
;
1110 if (p1pll
->pll_out_min
== 0) {
1111 if (ASIC_IS_AVIVO(rdev
))
1112 p1pll
->pll_out_min
= 64800;
1114 p1pll
->pll_out_min
= 20000;
1115 } else if (p1pll
->pll_out_min
> 64800) {
1116 /* Limiting the pll output range is a good thing generally as
1117 * it limits the number of possible pll combinations for a given
1118 * frequency presumably to the ones that work best on each card.
1119 * However, certain duallink DVI monitors seem to like
1120 * pll combinations that would be limited by this at least on
1121 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
1124 p1pll
->pll_out_min
= 64800;
1128 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
1130 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
1135 spll
->reference_freq
=
1136 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1137 spll
->reference_div
= 0;
1140 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
1142 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
1145 if (spll
->pll_out_min
== 0) {
1146 if (ASIC_IS_AVIVO(rdev
))
1147 spll
->pll_out_min
= 64800;
1149 spll
->pll_out_min
= 20000;
1153 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
1155 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
1158 mpll
->reference_freq
=
1159 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
1160 mpll
->reference_div
= 0;
1163 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
1165 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
1168 if (mpll
->pll_out_min
== 0) {
1169 if (ASIC_IS_AVIVO(rdev
))
1170 mpll
->pll_out_min
= 64800;
1172 mpll
->pll_out_min
= 20000;
1176 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
1178 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
1180 rdev
->clock
.default_sclk
=
1181 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
1182 rdev
->clock
.default_mclk
=
1183 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
1185 if (ASIC_IS_DCE4(rdev
)) {
1186 rdev
->clock
.default_dispclk
=
1187 le32_to_cpu(firmware_info
->info_21
.ulDefaultDispEngineClkFreq
);
1188 if (rdev
->clock
.default_dispclk
== 0)
1189 rdev
->clock
.default_dispclk
= 60000; /* 600 Mhz */
1190 rdev
->clock
.dp_extclk
=
1191 le16_to_cpu(firmware_info
->info_21
.usUniphyDPModeExtClkFreq
);
1202 struct _ATOM_INTEGRATED_SYSTEM_INFO info
;
1203 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2
;
1206 bool radeon_atombios_sideport_present(struct radeon_device
*rdev
)
1208 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1209 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1210 union igp_info
*igp_info
;
1214 /* sideport is AMD only */
1215 if (rdev
->family
== CHIP_RS600
)
1218 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1219 &frev
, &crev
, &data_offset
)) {
1220 igp_info
= (union igp_info
*)(mode_info
->atom_context
->bios
+
1224 if (igp_info
->info
.ulBootUpMemoryClock
)
1228 if (igp_info
->info_2
.ulBootUpSidePortClock
)
1232 DRM_ERROR("Unsupported IGP table: %d %d\n", frev
, crev
);
1239 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
1240 struct radeon_encoder_int_tmds
*tmds
)
1242 struct drm_device
*dev
= encoder
->base
.dev
;
1243 struct radeon_device
*rdev
= dev
->dev_private
;
1244 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1245 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
1246 uint16_t data_offset
;
1247 struct _ATOM_TMDS_INFO
*tmds_info
;
1252 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1253 &frev
, &crev
, &data_offset
)) {
1255 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
1258 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
1259 for (i
= 0; i
< 4; i
++) {
1260 tmds
->tmds_pll
[i
].freq
=
1261 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
1262 tmds
->tmds_pll
[i
].value
=
1263 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
1264 tmds
->tmds_pll
[i
].value
|=
1265 (tmds_info
->asMiscInfo
[i
].
1266 ucPLL_VCO_Gain
& 0x3f) << 6;
1267 tmds
->tmds_pll
[i
].value
|=
1268 (tmds_info
->asMiscInfo
[i
].
1269 ucPLL_DutyCycle
& 0xf) << 12;
1270 tmds
->tmds_pll
[i
].value
|=
1271 (tmds_info
->asMiscInfo
[i
].
1272 ucPLL_VoltageSwing
& 0xf) << 16;
1274 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1275 tmds
->tmds_pll
[i
].freq
,
1276 tmds
->tmds_pll
[i
].value
);
1278 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
1279 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
1288 bool radeon_atombios_get_ppll_ss_info(struct radeon_device
*rdev
,
1289 struct radeon_atom_ss
*ss
,
1292 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1293 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1294 uint16_t data_offset
, size
;
1295 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1299 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1300 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1301 &frev
, &crev
, &data_offset
)) {
1303 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1305 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1306 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT
);
1308 for (i
= 0; i
< num_indices
; i
++) {
1309 if (ss_info
->asSS_Info
[i
].ucSS_Id
== id
) {
1311 le16_to_cpu(ss_info
->asSS_Info
[i
].usSpreadSpectrumPercentage
);
1312 ss
->type
= ss_info
->asSS_Info
[i
].ucSpreadSpectrumType
;
1313 ss
->step
= ss_info
->asSS_Info
[i
].ucSS_Step
;
1314 ss
->delay
= ss_info
->asSS_Info
[i
].ucSS_Delay
;
1315 ss
->range
= ss_info
->asSS_Info
[i
].ucSS_Range
;
1316 ss
->refdiv
= ss_info
->asSS_Info
[i
].ucRecommendedRef_Div
;
1324 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device
*rdev
,
1325 struct radeon_atom_ss
*ss
,
1328 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1329 int index
= GetIndexIntoMasterTable(DATA
, IntegratedSystemInfo
);
1330 u16 data_offset
, size
;
1331 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
*igp_info
;
1333 u16 percentage
= 0, rate
= 0;
1335 /* get any igp specific overrides */
1336 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1337 &frev
, &crev
, &data_offset
)) {
1338 igp_info
= (struct _ATOM_INTEGRATED_SYSTEM_INFO_V6
*)
1339 (mode_info
->atom_context
->bios
+ data_offset
);
1341 case ASIC_INTERNAL_SS_ON_TMDS
:
1342 percentage
= le16_to_cpu(igp_info
->usDVISSPercentage
);
1343 rate
= le16_to_cpu(igp_info
->usDVISSpreadRateIn10Hz
);
1345 case ASIC_INTERNAL_SS_ON_HDMI
:
1346 percentage
= le16_to_cpu(igp_info
->usHDMISSPercentage
);
1347 rate
= le16_to_cpu(igp_info
->usHDMISSpreadRateIn10Hz
);
1349 case ASIC_INTERNAL_SS_ON_LVDS
:
1350 percentage
= le16_to_cpu(igp_info
->usLvdsSSPercentage
);
1351 rate
= le16_to_cpu(igp_info
->usLvdsSSpreadRateIn10Hz
);
1355 ss
->percentage
= percentage
;
1361 union asic_ss_info
{
1362 struct _ATOM_ASIC_INTERNAL_SS_INFO info
;
1363 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2
;
1364 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3
;
1367 bool radeon_atombios_get_asic_ss_info(struct radeon_device
*rdev
,
1368 struct radeon_atom_ss
*ss
,
1371 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1372 int index
= GetIndexIntoMasterTable(DATA
, ASIC_InternalSS_Info
);
1373 uint16_t data_offset
, size
;
1374 union asic_ss_info
*ss_info
;
1378 memset(ss
, 0, sizeof(struct radeon_atom_ss
));
1379 if (atom_parse_data_header(mode_info
->atom_context
, index
, &size
,
1380 &frev
, &crev
, &data_offset
)) {
1383 (union asic_ss_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1387 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1388 sizeof(ATOM_ASIC_SS_ASSIGNMENT
);
1390 for (i
= 0; i
< num_indices
; i
++) {
1391 if ((ss_info
->info
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1392 (clock
<= ss_info
->info
.asSpreadSpectrum
[i
].ulTargetClockRange
)) {
1394 le16_to_cpu(ss_info
->info
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1395 ss
->type
= ss_info
->info
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1396 ss
->rate
= le16_to_cpu(ss_info
->info
.asSpreadSpectrum
[i
].usSpreadRateInKhz
);
1402 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1403 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2
);
1404 for (i
= 0; i
< num_indices
; i
++) {
1405 if ((ss_info
->info_2
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1406 (clock
<= ss_info
->info_2
.asSpreadSpectrum
[i
].ulTargetClockRange
)) {
1408 le16_to_cpu(ss_info
->info_2
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1409 ss
->type
= ss_info
->info_2
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1410 ss
->rate
= le16_to_cpu(ss_info
->info_2
.asSpreadSpectrum
[i
].usSpreadRateIn10Hz
);
1416 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) /
1417 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3
);
1418 for (i
= 0; i
< num_indices
; i
++) {
1419 if ((ss_info
->info_3
.asSpreadSpectrum
[i
].ucClockIndication
== id
) &&
1420 (clock
<= ss_info
->info_3
.asSpreadSpectrum
[i
].ulTargetClockRange
)) {
1422 le16_to_cpu(ss_info
->info_3
.asSpreadSpectrum
[i
].usSpreadSpectrumPercentage
);
1423 ss
->type
= ss_info
->info_3
.asSpreadSpectrum
[i
].ucSpreadSpectrumMode
;
1424 ss
->rate
= le16_to_cpu(ss_info
->info_3
.asSpreadSpectrum
[i
].usSpreadRateIn10Hz
);
1425 if (rdev
->flags
& RADEON_IS_IGP
)
1426 radeon_atombios_get_igp_ss_overrides(rdev
, ss
, id
);
1432 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev
, crev
);
1441 struct _ATOM_LVDS_INFO info
;
1442 struct _ATOM_LVDS_INFO_V12 info_12
;
1445 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1449 struct drm_device
*dev
= encoder
->base
.dev
;
1450 struct radeon_device
*rdev
= dev
->dev_private
;
1451 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1452 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1453 uint16_t data_offset
, misc
;
1454 union lvds_info
*lvds_info
;
1456 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1457 int encoder_enum
= (encoder
->encoder_enum
& ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
1459 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1460 &frev
, &crev
, &data_offset
)) {
1462 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1464 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1469 lvds
->native_mode
.clock
=
1470 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1471 lvds
->native_mode
.hdisplay
=
1472 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1473 lvds
->native_mode
.vdisplay
=
1474 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1475 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1476 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1477 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1478 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1479 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1480 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1481 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1482 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1483 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1484 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncOffset
);
1485 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1486 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1487 lvds
->panel_pwr_delay
=
1488 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1489 lvds
->lcd_misc
= lvds_info
->info
.ucLVDS_Misc
;
1491 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1492 if (misc
& ATOM_VSYNC_POLARITY
)
1493 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1494 if (misc
& ATOM_HSYNC_POLARITY
)
1495 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1496 if (misc
& ATOM_COMPOSITESYNC
)
1497 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1498 if (misc
& ATOM_INTERLACE
)
1499 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1500 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1501 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1503 /* set crtc values */
1504 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1506 lvds
->lcd_ss_id
= lvds_info
->info
.ucSS_Id
;
1508 encoder
->native_mode
= lvds
->native_mode
;
1510 if (encoder_enum
== 2)
1513 lvds
->linkb
= false;
1519 struct radeon_encoder_primary_dac
*
1520 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1522 struct drm_device
*dev
= encoder
->base
.dev
;
1523 struct radeon_device
*rdev
= dev
->dev_private
;
1524 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1525 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1526 uint16_t data_offset
;
1527 struct _COMPASSIONATE_DATA
*dac_info
;
1530 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1532 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1533 &frev
, &crev
, &data_offset
)) {
1534 dac_info
= (struct _COMPASSIONATE_DATA
*)
1535 (mode_info
->atom_context
->bios
+ data_offset
);
1537 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1542 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1543 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1544 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1550 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1551 struct drm_display_mode
*mode
)
1553 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1554 ATOM_ANALOG_TV_INFO
*tv_info
;
1555 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1556 ATOM_DTD_FORMAT
*dtd_timings
;
1557 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1559 u16 data_offset
, misc
;
1561 if (!atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
,
1562 &frev
, &crev
, &data_offset
))
1567 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1568 if (index
>= MAX_SUPPORTED_TV_TIMING
)
1571 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1572 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1573 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1574 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1575 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1577 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1578 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1579 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1580 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1581 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1584 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1585 if (misc
& ATOM_VSYNC_POLARITY
)
1586 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1587 if (misc
& ATOM_HSYNC_POLARITY
)
1588 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1589 if (misc
& ATOM_COMPOSITESYNC
)
1590 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1591 if (misc
& ATOM_INTERLACE
)
1592 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1593 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1594 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1596 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1599 /* PAL timings appear to have wrong values for totals */
1600 mode
->crtc_htotal
-= 1;
1601 mode
->crtc_vtotal
-= 1;
1605 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1606 if (index
>= MAX_SUPPORTED_TV_TIMING_V1_2
)
1609 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1610 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1611 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1612 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1613 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1614 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1615 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1616 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1618 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1619 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1620 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1621 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1622 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1623 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1624 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1627 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1628 if (misc
& ATOM_VSYNC_POLARITY
)
1629 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1630 if (misc
& ATOM_HSYNC_POLARITY
)
1631 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1632 if (misc
& ATOM_COMPOSITESYNC
)
1633 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1634 if (misc
& ATOM_INTERLACE
)
1635 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1636 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1637 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1639 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1646 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1648 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1649 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1650 uint16_t data_offset
;
1652 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1653 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1655 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1656 &frev
, &crev
, &data_offset
)) {
1658 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)
1659 (mode_info
->atom_context
->bios
+ data_offset
);
1661 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1663 tv_std
= TV_STD_NTSC
;
1664 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1667 tv_std
= TV_STD_NTSC_J
;
1668 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1671 tv_std
= TV_STD_PAL
;
1672 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1675 tv_std
= TV_STD_PAL_M
;
1676 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1679 tv_std
= TV_STD_PAL_N
;
1680 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1683 tv_std
= TV_STD_PAL_CN
;
1684 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1687 tv_std
= TV_STD_PAL_60
;
1688 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1691 tv_std
= TV_STD_SECAM
;
1692 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1695 tv_std
= TV_STD_NTSC
;
1696 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1703 struct radeon_encoder_tv_dac
*
1704 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1706 struct drm_device
*dev
= encoder
->base
.dev
;
1707 struct radeon_device
*rdev
= dev
->dev_private
;
1708 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1709 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1710 uint16_t data_offset
;
1711 struct _COMPASSIONATE_DATA
*dac_info
;
1714 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1716 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1717 &frev
, &crev
, &data_offset
)) {
1719 dac_info
= (struct _COMPASSIONATE_DATA
*)
1720 (mode_info
->atom_context
->bios
+ data_offset
);
1722 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1727 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1728 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1729 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1731 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1732 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1733 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1735 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1736 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1737 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1739 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1744 static const char *thermal_controller_names
[] = {
1755 static const char *pp_lib_thermal_controller_names
[] = {
1774 struct _ATOM_POWERPLAY_INFO info
;
1775 struct _ATOM_POWERPLAY_INFO_V2 info_2
;
1776 struct _ATOM_POWERPLAY_INFO_V3 info_3
;
1777 struct _ATOM_PPLIB_POWERPLAYTABLE pplib
;
1778 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2
;
1779 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3
;
1782 union pplib_clock_info
{
1783 struct _ATOM_PPLIB_R600_CLOCK_INFO r600
;
1784 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780
;
1785 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen
;
1786 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo
;
1789 union pplib_power_state
{
1790 struct _ATOM_PPLIB_STATE v1
;
1791 struct _ATOM_PPLIB_STATE_V2 v2
;
1794 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device
*rdev
,
1796 u32 misc
, u32 misc2
)
1798 rdev
->pm
.power_state
[state_index
].misc
= misc
;
1799 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
1800 /* order matters! */
1801 if (misc
& ATOM_PM_MISCINFO_POWER_SAVING_MODE
)
1802 rdev
->pm
.power_state
[state_index
].type
=
1803 POWER_STATE_TYPE_POWERSAVE
;
1804 if (misc
& ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE
)
1805 rdev
->pm
.power_state
[state_index
].type
=
1806 POWER_STATE_TYPE_BATTERY
;
1807 if (misc
& ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE
)
1808 rdev
->pm
.power_state
[state_index
].type
=
1809 POWER_STATE_TYPE_BATTERY
;
1810 if (misc
& ATOM_PM_MISCINFO_LOAD_BALANCE_EN
)
1811 rdev
->pm
.power_state
[state_index
].type
=
1812 POWER_STATE_TYPE_BALANCED
;
1813 if (misc
& ATOM_PM_MISCINFO_3D_ACCELERATION_EN
) {
1814 rdev
->pm
.power_state
[state_index
].type
=
1815 POWER_STATE_TYPE_PERFORMANCE
;
1816 rdev
->pm
.power_state
[state_index
].flags
&=
1817 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1819 if (misc2
& ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE
)
1820 rdev
->pm
.power_state
[state_index
].type
=
1821 POWER_STATE_TYPE_BALANCED
;
1822 if (misc
& ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE
) {
1823 rdev
->pm
.power_state
[state_index
].type
=
1824 POWER_STATE_TYPE_DEFAULT
;
1825 rdev
->pm
.default_power_state_index
= state_index
;
1826 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
1827 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
1828 } else if (state_index
== 0) {
1829 rdev
->pm
.power_state
[state_index
].clock_info
[0].flags
|=
1830 RADEON_PM_MODE_NO_DISPLAY
;
1834 static int radeon_atombios_parse_power_table_1_3(struct radeon_device
*rdev
)
1836 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1837 u32 misc
, misc2
= 0;
1838 int num_modes
= 0, i
;
1839 int state_index
= 0;
1840 struct radeon_i2c_bus_rec i2c_bus
;
1841 union power_info
*power_info
;
1842 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
1846 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
1847 &frev
, &crev
, &data_offset
))
1849 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1851 /* add the i2c bus for thermal/fan chip */
1852 if (power_info
->info
.ucOverdriveThermalController
> 0) {
1853 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1854 thermal_controller_names
[power_info
->info
.ucOverdriveThermalController
],
1855 power_info
->info
.ucOverdriveControllerAddress
>> 1);
1856 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, power_info
->info
.ucOverdriveI2cLine
);
1857 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
1858 if (rdev
->pm
.i2c_bus
) {
1859 struct i2c_board_info info
= { };
1860 const char *name
= thermal_controller_names
[power_info
->info
.
1861 ucOverdriveThermalController
];
1862 info
.addr
= power_info
->info
.ucOverdriveControllerAddress
>> 1;
1863 strlcpy(info
.type
, name
, sizeof(info
.type
));
1864 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
1867 num_modes
= power_info
->info
.ucNumOfPowerModeEntries
;
1868 if (num_modes
> ATOM_MAX_NUMBEROF_POWER_BLOCK
)
1869 num_modes
= ATOM_MAX_NUMBEROF_POWER_BLOCK
;
1870 /* last mode is usually default, array is low to high */
1871 for (i
= 0; i
< num_modes
; i
++) {
1872 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
1875 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1876 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1877 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usMemoryClock
);
1878 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1879 le16_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].usEngineClock
);
1880 /* skip invalid modes */
1881 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1882 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1884 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1885 power_info
->info
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1886 misc
= le32_to_cpu(power_info
->info
.asPowerPlayInfo
[i
].ulMiscInfo
);
1887 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1888 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1889 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1891 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1892 radeon_lookup_gpio(rdev
,
1893 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1894 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1895 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1898 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1900 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1901 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1903 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1904 power_info
->info
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1906 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1907 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, 0);
1911 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1912 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1913 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMemoryClock
);
1914 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1915 le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulEngineClock
);
1916 /* skip invalid modes */
1917 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1918 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1920 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1921 power_info
->info_2
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1922 misc
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo
);
1923 misc2
= le32_to_cpu(power_info
->info_2
.asPowerPlayInfo
[i
].ulMiscInfo2
);
1924 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1925 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1926 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1928 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1929 radeon_lookup_gpio(rdev
,
1930 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1931 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1932 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1935 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1937 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1938 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1940 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1941 power_info
->info_2
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1943 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1944 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
1948 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
1949 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
=
1950 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMemoryClock
);
1951 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
=
1952 le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulEngineClock
);
1953 /* skip invalid modes */
1954 if ((rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
== 0) ||
1955 (rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
== 0))
1957 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
1958 power_info
->info_3
.asPowerPlayInfo
[i
].ucNumPciELanes
;
1959 misc
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo
);
1960 misc2
= le32_to_cpu(power_info
->info_3
.asPowerPlayInfo
[i
].ulMiscInfo2
);
1961 if ((misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT
) ||
1962 (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)) {
1963 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1965 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.gpio
=
1966 radeon_lookup_gpio(rdev
,
1967 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
);
1968 if (misc
& ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH
)
1969 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1972 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.active_high
=
1974 } else if (misc
& ATOM_PM_MISCINFO_PROGRAM_VOLTAGE
) {
1975 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
=
1977 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddc_id
=
1978 power_info
->info_3
.asPowerPlayInfo
[i
].ucVoltageDropIndex
;
1979 if (misc2
& ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN
) {
1980 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_enabled
=
1982 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.vddci_id
=
1983 power_info
->info_3
.asPowerPlayInfo
[i
].ucVDDCI_VoltageDropIndex
;
1986 rdev
->pm
.power_state
[state_index
].flags
= RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
1987 radeon_atombios_parse_misc_flags_1_3(rdev
, state_index
, misc
, misc2
);
1992 /* last mode is usually default */
1993 if (rdev
->pm
.default_power_state_index
== -1) {
1994 rdev
->pm
.power_state
[state_index
- 1].type
=
1995 POWER_STATE_TYPE_DEFAULT
;
1996 rdev
->pm
.default_power_state_index
= state_index
- 1;
1997 rdev
->pm
.power_state
[state_index
- 1].default_clock_mode
=
1998 &rdev
->pm
.power_state
[state_index
- 1].clock_info
[0];
1999 rdev
->pm
.power_state
[state_index
].flags
&=
2000 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2001 rdev
->pm
.power_state
[state_index
].misc
= 0;
2002 rdev
->pm
.power_state
[state_index
].misc2
= 0;
2007 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device
*rdev
,
2008 ATOM_PPLIB_THERMALCONTROLLER
*controller
)
2010 struct radeon_i2c_bus_rec i2c_bus
;
2012 /* add the i2c bus for thermal/fan chip */
2013 if (controller
->ucType
> 0) {
2014 if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV6xx
) {
2015 DRM_INFO("Internal thermal controller %s fan control\n",
2016 (controller
->ucFanParameters
&
2017 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2018 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV6XX
;
2019 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_RV770
) {
2020 DRM_INFO("Internal thermal controller %s fan control\n",
2021 (controller
->ucFanParameters
&
2022 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2023 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_RV770
;
2024 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_EVERGREEN
) {
2025 DRM_INFO("Internal thermal controller %s fan control\n",
2026 (controller
->ucFanParameters
&
2027 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2028 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_EVERGREEN
;
2029 } else if (controller
->ucType
== ATOM_PP_THERMALCONTROLLER_SUMO
) {
2030 DRM_INFO("Internal thermal controller %s fan control\n",
2031 (controller
->ucFanParameters
&
2032 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2033 rdev
->pm
.int_thermal_type
= THERMAL_TYPE_SUMO
;
2034 } else if ((controller
->ucType
==
2035 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO
) ||
2036 (controller
->ucType
==
2037 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL
) ||
2038 (controller
->ucType
==
2039 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL
)) {
2040 DRM_INFO("Special thermal controller config\n");
2042 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2043 pp_lib_thermal_controller_names
[controller
->ucType
],
2044 controller
->ucI2cAddress
>> 1,
2045 (controller
->ucFanParameters
&
2046 ATOM_PP_FANPARAMETERS_NOFAN
) ? "without" : "with");
2047 i2c_bus
= radeon_lookup_i2c_gpio(rdev
, controller
->ucI2cLine
);
2048 rdev
->pm
.i2c_bus
= radeon_i2c_lookup(rdev
, &i2c_bus
);
2049 if (rdev
->pm
.i2c_bus
) {
2050 struct i2c_board_info info
= { };
2051 const char *name
= pp_lib_thermal_controller_names
[controller
->ucType
];
2052 info
.addr
= controller
->ucI2cAddress
>> 1;
2053 strlcpy(info
.type
, name
, sizeof(info
.type
));
2054 i2c_new_device(&rdev
->pm
.i2c_bus
->adapter
, &info
);
2060 static u16
radeon_atombios_get_default_vddc(struct radeon_device
*rdev
)
2062 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2063 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
2066 union firmware_info
*firmware_info
;
2069 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2070 &frev
, &crev
, &data_offset
)) {
2072 (union firmware_info
*)(mode_info
->atom_context
->bios
+
2074 vddc
= firmware_info
->info_14
.usBootUpVDDCVoltage
;
2080 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device
*rdev
,
2081 int state_index
, int mode_index
,
2082 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
)
2085 u32 misc
= le32_to_cpu(non_clock_info
->ulCapsAndSettings
);
2086 u32 misc2
= le16_to_cpu(non_clock_info
->usClassification
);
2087 u16 vddc
= radeon_atombios_get_default_vddc(rdev
);
2089 rdev
->pm
.power_state
[state_index
].misc
= misc
;
2090 rdev
->pm
.power_state
[state_index
].misc2
= misc2
;
2091 rdev
->pm
.power_state
[state_index
].pcie_lanes
=
2092 ((misc
& ATOM_PPLIB_PCIE_LINK_WIDTH_MASK
) >>
2093 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT
) + 1;
2094 switch (misc2
& ATOM_PPLIB_CLASSIFICATION_UI_MASK
) {
2095 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY
:
2096 rdev
->pm
.power_state
[state_index
].type
=
2097 POWER_STATE_TYPE_BATTERY
;
2099 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED
:
2100 rdev
->pm
.power_state
[state_index
].type
=
2101 POWER_STATE_TYPE_BALANCED
;
2103 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE
:
2104 rdev
->pm
.power_state
[state_index
].type
=
2105 POWER_STATE_TYPE_PERFORMANCE
;
2107 case ATOM_PPLIB_CLASSIFICATION_UI_NONE
:
2108 if (misc2
& ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE
)
2109 rdev
->pm
.power_state
[state_index
].type
=
2110 POWER_STATE_TYPE_PERFORMANCE
;
2113 rdev
->pm
.power_state
[state_index
].flags
= 0;
2114 if (misc
& ATOM_PPLIB_SINGLE_DISPLAY_ONLY
)
2115 rdev
->pm
.power_state
[state_index
].flags
|=
2116 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY
;
2117 if (misc2
& ATOM_PPLIB_CLASSIFICATION_BOOT
) {
2118 rdev
->pm
.power_state
[state_index
].type
=
2119 POWER_STATE_TYPE_DEFAULT
;
2120 rdev
->pm
.default_power_state_index
= state_index
;
2121 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2122 &rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
- 1];
2123 /* patch the table values with the default slck/mclk from firmware info */
2124 for (j
= 0; j
< mode_index
; j
++) {
2125 rdev
->pm
.power_state
[state_index
].clock_info
[j
].mclk
=
2126 rdev
->clock
.default_mclk
;
2127 rdev
->pm
.power_state
[state_index
].clock_info
[j
].sclk
=
2128 rdev
->clock
.default_sclk
;
2130 rdev
->pm
.power_state
[state_index
].clock_info
[j
].voltage
.voltage
=
2136 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device
*rdev
,
2137 int state_index
, int mode_index
,
2138 union pplib_clock_info
*clock_info
)
2142 if (rdev
->flags
& RADEON_IS_IGP
) {
2143 if (rdev
->family
>= CHIP_PALM
) {
2144 sclk
= le16_to_cpu(clock_info
->sumo
.usEngineClockLow
);
2145 sclk
|= clock_info
->sumo
.ucEngineClockHigh
<< 16;
2146 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2148 sclk
= le16_to_cpu(clock_info
->rs780
.usLowEngineClockLow
);
2149 sclk
|= clock_info
->rs780
.ucLowEngineClockHigh
<< 16;
2150 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2152 } else if (ASIC_IS_DCE4(rdev
)) {
2153 sclk
= le16_to_cpu(clock_info
->evergreen
.usEngineClockLow
);
2154 sclk
|= clock_info
->evergreen
.ucEngineClockHigh
<< 16;
2155 mclk
= le16_to_cpu(clock_info
->evergreen
.usMemoryClockLow
);
2156 mclk
|= clock_info
->evergreen
.ucMemoryClockHigh
<< 16;
2157 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2158 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2159 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2161 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2162 clock_info
->evergreen
.usVDDC
;
2164 sclk
= le16_to_cpu(clock_info
->r600
.usEngineClockLow
);
2165 sclk
|= clock_info
->r600
.ucEngineClockHigh
<< 16;
2166 mclk
= le16_to_cpu(clock_info
->r600
.usMemoryClockLow
);
2167 mclk
|= clock_info
->r600
.ucMemoryClockHigh
<< 16;
2168 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
= mclk
;
2169 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
= sclk
;
2170 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.type
=
2172 rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].voltage
.voltage
=
2173 clock_info
->r600
.usVDDC
;
2176 if (rdev
->flags
& RADEON_IS_IGP
) {
2177 /* skip invalid modes */
2178 if (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0)
2181 /* skip invalid modes */
2182 if ((rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].mclk
== 0) ||
2183 (rdev
->pm
.power_state
[state_index
].clock_info
[mode_index
].sclk
== 0))
2189 static int radeon_atombios_parse_power_table_4_5(struct radeon_device
*rdev
)
2191 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2192 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2193 union pplib_power_state
*power_state
;
2195 int state_index
= 0, mode_index
= 0;
2196 union pplib_clock_info
*clock_info
;
2198 union power_info
*power_info
;
2199 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2203 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2204 &frev
, &crev
, &data_offset
))
2206 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2208 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2209 /* first mode is usually default, followed by low to high */
2210 for (i
= 0; i
< power_info
->pplib
.ucNumStates
; i
++) {
2212 power_state
= (union pplib_power_state
*)
2213 (mode_info
->atom_context
->bios
+ data_offset
+
2214 le16_to_cpu(power_info
->pplib
.usStateArrayOffset
) +
2215 i
* power_info
->pplib
.ucStateEntrySize
);
2216 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2217 (mode_info
->atom_context
->bios
+ data_offset
+
2218 le16_to_cpu(power_info
->pplib
.usNonClockInfoArrayOffset
) +
2219 (power_state
->v1
.ucNonClockStateIndex
*
2220 power_info
->pplib
.ucNonClockSize
));
2221 for (j
= 0; j
< (power_info
->pplib
.ucStateEntrySize
- 1); j
++) {
2222 clock_info
= (union pplib_clock_info
*)
2223 (mode_info
->atom_context
->bios
+ data_offset
+
2224 le16_to_cpu(power_info
->pplib
.usClockInfoArrayOffset
) +
2225 (power_state
->v1
.ucClockStateIndices
[j
] *
2226 power_info
->pplib
.ucClockInfoSize
));
2227 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2228 state_index
, mode_index
,
2233 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2235 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2240 /* if multiple clock modes, mark the lowest as no display */
2241 for (i
= 0; i
< state_index
; i
++) {
2242 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2243 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2244 RADEON_PM_MODE_NO_DISPLAY
;
2246 /* first mode is usually default */
2247 if (rdev
->pm
.default_power_state_index
== -1) {
2248 rdev
->pm
.power_state
[0].type
=
2249 POWER_STATE_TYPE_DEFAULT
;
2250 rdev
->pm
.default_power_state_index
= 0;
2251 rdev
->pm
.power_state
[0].default_clock_mode
=
2252 &rdev
->pm
.power_state
[0].clock_info
[0];
2257 static int radeon_atombios_parse_power_table_6(struct radeon_device
*rdev
)
2259 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2260 struct _ATOM_PPLIB_NONCLOCK_INFO
*non_clock_info
;
2261 union pplib_power_state
*power_state
;
2262 int i
, j
, non_clock_array_index
, clock_array_index
;
2263 int state_index
= 0, mode_index
= 0;
2264 union pplib_clock_info
*clock_info
;
2265 struct StateArray
*state_array
;
2266 struct ClockInfoArray
*clock_info_array
;
2267 struct NonClockInfoArray
*non_clock_info_array
;
2269 union power_info
*power_info
;
2270 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2274 if (!atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2275 &frev
, &crev
, &data_offset
))
2277 power_info
= (union power_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
2279 radeon_atombios_add_pplib_thermal_controller(rdev
, &power_info
->pplib
.sThermalController
);
2280 state_array
= (struct StateArray
*)
2281 (mode_info
->atom_context
->bios
+ data_offset
+
2282 power_info
->pplib
.usStateArrayOffset
);
2283 clock_info_array
= (struct ClockInfoArray
*)
2284 (mode_info
->atom_context
->bios
+ data_offset
+
2285 power_info
->pplib
.usClockInfoArrayOffset
);
2286 non_clock_info_array
= (struct NonClockInfoArray
*)
2287 (mode_info
->atom_context
->bios
+ data_offset
+
2288 power_info
->pplib
.usNonClockInfoArrayOffset
);
2289 for (i
= 0; i
< state_array
->ucNumEntries
; i
++) {
2291 power_state
= (union pplib_power_state
*)&state_array
->states
[i
];
2292 /* XXX this might be an inagua bug... */
2293 non_clock_array_index
= i
; /* power_state->v2.nonClockInfoIndex */
2294 non_clock_info
= (struct _ATOM_PPLIB_NONCLOCK_INFO
*)
2295 &non_clock_info_array
->nonClockInfo
[non_clock_array_index
];
2296 for (j
= 0; j
< power_state
->v2
.ucNumDPMLevels
; j
++) {
2297 clock_array_index
= power_state
->v2
.clockInfoIndex
[j
];
2298 /* XXX this might be an inagua bug... */
2299 if (clock_array_index
>= clock_info_array
->ucNumEntries
)
2301 clock_info
= (union pplib_clock_info
*)
2302 &clock_info_array
->clockInfo
[clock_array_index
];
2303 valid
= radeon_atombios_parse_pplib_clock_info(rdev
,
2304 state_index
, mode_index
,
2309 rdev
->pm
.power_state
[state_index
].num_clock_modes
= mode_index
;
2311 radeon_atombios_parse_pplib_non_clock_info(rdev
, state_index
, mode_index
,
2316 /* if multiple clock modes, mark the lowest as no display */
2317 for (i
= 0; i
< state_index
; i
++) {
2318 if (rdev
->pm
.power_state
[i
].num_clock_modes
> 1)
2319 rdev
->pm
.power_state
[i
].clock_info
[0].flags
|=
2320 RADEON_PM_MODE_NO_DISPLAY
;
2322 /* first mode is usually default */
2323 if (rdev
->pm
.default_power_state_index
== -1) {
2324 rdev
->pm
.power_state
[0].type
=
2325 POWER_STATE_TYPE_DEFAULT
;
2326 rdev
->pm
.default_power_state_index
= 0;
2327 rdev
->pm
.power_state
[0].default_clock_mode
=
2328 &rdev
->pm
.power_state
[0].clock_info
[0];
2333 void radeon_atombios_get_power_modes(struct radeon_device
*rdev
)
2335 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
2336 int index
= GetIndexIntoMasterTable(DATA
, PowerPlayInfo
);
2339 int state_index
= 0;
2341 rdev
->pm
.default_power_state_index
= -1;
2343 if (atom_parse_data_header(mode_info
->atom_context
, index
, NULL
,
2344 &frev
, &crev
, &data_offset
)) {
2349 state_index
= radeon_atombios_parse_power_table_1_3(rdev
);
2353 state_index
= radeon_atombios_parse_power_table_4_5(rdev
);
2356 state_index
= radeon_atombios_parse_power_table_6(rdev
);
2362 /* add the default mode */
2363 rdev
->pm
.power_state
[state_index
].type
=
2364 POWER_STATE_TYPE_DEFAULT
;
2365 rdev
->pm
.power_state
[state_index
].num_clock_modes
= 1;
2366 rdev
->pm
.power_state
[state_index
].clock_info
[0].mclk
= rdev
->clock
.default_mclk
;
2367 rdev
->pm
.power_state
[state_index
].clock_info
[0].sclk
= rdev
->clock
.default_sclk
;
2368 rdev
->pm
.power_state
[state_index
].default_clock_mode
=
2369 &rdev
->pm
.power_state
[state_index
].clock_info
[0];
2370 rdev
->pm
.power_state
[state_index
].clock_info
[0].voltage
.type
= VOLTAGE_NONE
;
2371 rdev
->pm
.power_state
[state_index
].pcie_lanes
= 16;
2372 rdev
->pm
.default_power_state_index
= state_index
;
2373 rdev
->pm
.power_state
[state_index
].flags
= 0;
2377 rdev
->pm
.num_power_states
= state_index
;
2379 rdev
->pm
.current_power_state_index
= rdev
->pm
.default_power_state_index
;
2380 rdev
->pm
.current_clock_mode_index
= 0;
2381 rdev
->pm
.current_vddc
= rdev
->pm
.power_state
[rdev
->pm
.default_power_state_index
].clock_info
[0].voltage
.voltage
;
2384 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
2386 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
2387 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
2389 args
.ucEnable
= enable
;
2391 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2394 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
2396 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
2397 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
2399 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2400 return args
.ulReturnEngineClock
;
2403 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
2405 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
2406 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
2408 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2409 return args
.ulReturnMemoryClock
;
2412 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
2415 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
2416 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
2418 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
2420 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2423 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
2426 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
2427 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
2429 if (rdev
->flags
& RADEON_IS_IGP
)
2432 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
2434 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2438 struct _SET_VOLTAGE_PS_ALLOCATION alloc
;
2439 struct _SET_VOLTAGE_PARAMETERS v1
;
2440 struct _SET_VOLTAGE_PARAMETERS_V2 v2
;
2443 void radeon_atom_set_voltage(struct radeon_device
*rdev
, u16 level
)
2445 union set_voltage args
;
2446 int index
= GetIndexIntoMasterTable(COMMAND
, SetVoltage
);
2447 u8 frev
, crev
, volt_index
= level
;
2449 if (!atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
))
2454 args
.v1
.ucVoltageType
= SET_VOLTAGE_TYPE_ASIC_VDDC
;
2455 args
.v1
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_ALL_SOURCE
;
2456 args
.v1
.ucVoltageIndex
= volt_index
;
2459 args
.v2
.ucVoltageType
= SET_VOLTAGE_TYPE_ASIC_VDDC
;
2460 args
.v2
.ucVoltageMode
= SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE
;
2461 args
.v2
.usVoltageLevel
= cpu_to_le16(level
);
2464 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
2468 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
2473 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
2475 struct radeon_device
*rdev
= dev
->dev_private
;
2476 uint32_t bios_2_scratch
, bios_6_scratch
;
2478 if (rdev
->family
>= CHIP_R600
) {
2479 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2480 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2482 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2483 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2486 /* let the bios control the backlight */
2487 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
2489 /* tell the bios not to handle mode switching */
2490 bios_6_scratch
|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
| ATOM_S6_ACC_MODE
);
2492 if (rdev
->family
>= CHIP_R600
) {
2493 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2494 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2496 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
2497 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2502 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
2504 uint32_t scratch_reg
;
2507 if (rdev
->family
>= CHIP_R600
)
2508 scratch_reg
= R600_BIOS_0_SCRATCH
;
2510 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2512 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2513 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
2516 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
2518 uint32_t scratch_reg
;
2521 if (rdev
->family
>= CHIP_R600
)
2522 scratch_reg
= R600_BIOS_0_SCRATCH
;
2524 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
2526 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
2527 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
2530 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
2532 struct drm_device
*dev
= encoder
->dev
;
2533 struct radeon_device
*rdev
= dev
->dev_private
;
2534 uint32_t bios_6_scratch
;
2536 if (rdev
->family
>= CHIP_R600
)
2537 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2539 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2542 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
2544 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
2546 if (rdev
->family
>= CHIP_R600
)
2547 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2549 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2552 /* at some point we may want to break this out into individual functions */
2554 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
2555 struct drm_encoder
*encoder
,
2558 struct drm_device
*dev
= connector
->dev
;
2559 struct radeon_device
*rdev
= dev
->dev_private
;
2560 struct radeon_connector
*radeon_connector
=
2561 to_radeon_connector(connector
);
2562 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2563 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
2565 if (rdev
->family
>= CHIP_R600
) {
2566 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
2567 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2568 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
2570 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
2571 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2572 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
2575 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
2576 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
2578 DRM_DEBUG_KMS("TV1 connected\n");
2579 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
2580 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
2582 DRM_DEBUG_KMS("TV1 disconnected\n");
2583 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
2584 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
2585 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
2588 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
2589 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
2591 DRM_DEBUG_KMS("CV connected\n");
2592 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
2593 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
2595 DRM_DEBUG_KMS("CV disconnected\n");
2596 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
2597 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
2598 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
2601 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
2602 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
2604 DRM_DEBUG_KMS("LCD1 connected\n");
2605 bios_0_scratch
|= ATOM_S0_LCD1
;
2606 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
2607 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
2609 DRM_DEBUG_KMS("LCD1 disconnected\n");
2610 bios_0_scratch
&= ~ATOM_S0_LCD1
;
2611 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
2612 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
2615 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
2616 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
2618 DRM_DEBUG_KMS("CRT1 connected\n");
2619 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
2620 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
2621 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
2623 DRM_DEBUG_KMS("CRT1 disconnected\n");
2624 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
2625 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
2626 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
2629 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
2630 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
2632 DRM_DEBUG_KMS("CRT2 connected\n");
2633 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
2634 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
2635 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
2637 DRM_DEBUG_KMS("CRT2 disconnected\n");
2638 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
2639 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
2640 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
2643 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
2644 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
2646 DRM_DEBUG_KMS("DFP1 connected\n");
2647 bios_0_scratch
|= ATOM_S0_DFP1
;
2648 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
2649 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
2651 DRM_DEBUG_KMS("DFP1 disconnected\n");
2652 bios_0_scratch
&= ~ATOM_S0_DFP1
;
2653 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
2654 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
2657 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
2658 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
2660 DRM_DEBUG_KMS("DFP2 connected\n");
2661 bios_0_scratch
|= ATOM_S0_DFP2
;
2662 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
2663 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
2665 DRM_DEBUG_KMS("DFP2 disconnected\n");
2666 bios_0_scratch
&= ~ATOM_S0_DFP2
;
2667 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
2668 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
2671 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
2672 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
2674 DRM_DEBUG_KMS("DFP3 connected\n");
2675 bios_0_scratch
|= ATOM_S0_DFP3
;
2676 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
2677 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
2679 DRM_DEBUG_KMS("DFP3 disconnected\n");
2680 bios_0_scratch
&= ~ATOM_S0_DFP3
;
2681 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
2682 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
2685 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
2686 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
2688 DRM_DEBUG_KMS("DFP4 connected\n");
2689 bios_0_scratch
|= ATOM_S0_DFP4
;
2690 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
2691 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
2693 DRM_DEBUG_KMS("DFP4 disconnected\n");
2694 bios_0_scratch
&= ~ATOM_S0_DFP4
;
2695 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
2696 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
2699 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
2700 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
2702 DRM_DEBUG_KMS("DFP5 connected\n");
2703 bios_0_scratch
|= ATOM_S0_DFP5
;
2704 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
2705 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
2707 DRM_DEBUG_KMS("DFP5 disconnected\n");
2708 bios_0_scratch
&= ~ATOM_S0_DFP5
;
2709 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
2710 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
2714 if (rdev
->family
>= CHIP_R600
) {
2715 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
2716 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2717 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
2719 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
2720 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2721 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
2726 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
2728 struct drm_device
*dev
= encoder
->dev
;
2729 struct radeon_device
*rdev
= dev
->dev_private
;
2730 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2731 uint32_t bios_3_scratch
;
2733 if (rdev
->family
>= CHIP_R600
)
2734 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
2736 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
2738 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2739 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
2740 bios_3_scratch
|= (crtc
<< 18);
2742 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2743 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
2744 bios_3_scratch
|= (crtc
<< 24);
2746 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2747 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
2748 bios_3_scratch
|= (crtc
<< 16);
2750 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2751 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
2752 bios_3_scratch
|= (crtc
<< 20);
2754 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2755 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
2756 bios_3_scratch
|= (crtc
<< 17);
2758 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2759 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
2760 bios_3_scratch
|= (crtc
<< 19);
2762 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2763 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
2764 bios_3_scratch
|= (crtc
<< 23);
2766 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2767 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
2768 bios_3_scratch
|= (crtc
<< 25);
2771 if (rdev
->family
>= CHIP_R600
)
2772 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
2774 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
2778 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
2780 struct drm_device
*dev
= encoder
->dev
;
2781 struct radeon_device
*rdev
= dev
->dev_private
;
2782 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
2783 uint32_t bios_2_scratch
;
2785 if (rdev
->family
>= CHIP_R600
)
2786 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
2788 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
2790 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
2792 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
2794 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
2796 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
2798 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
2800 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
2802 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
2804 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
2806 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
2808 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
2810 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
2812 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
2814 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
2816 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
2818 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
2820 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
2822 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
2824 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
2826 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
2828 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
2830 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
2832 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
2834 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
2836 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
2838 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
2840 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
2842 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
2844 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
2846 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
2848 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
2851 if (rdev
->family
>= CHIP_R600
)
2852 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
2854 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);