4 * Compaq ASIC3 support.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
12 * Copyright 2007-2008 OpenedHand Ltd.
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
19 #include <linux/version.h>
20 #include <linux/kernel.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
24 #include <linux/spinlock.h>
25 #include <linux/platform_device.h>
27 #include <linux/mfd/asic3.h>
30 void __iomem
*mapping
;
31 unsigned int bus_shift
;
33 unsigned int irq_base
;
36 struct gpio_chip gpio
;
40 static int asic3_gpio_get(struct gpio_chip
*chip
, unsigned offset
);
42 static inline void asic3_write_register(struct asic3
*asic
,
43 unsigned int reg
, u32 value
)
45 iowrite16(value
, asic
->mapping
+
46 (reg
>> asic
->bus_shift
));
49 static inline u32
asic3_read_register(struct asic3
*asic
,
52 return ioread16(asic
->mapping
+
53 (reg
>> asic
->bus_shift
));
57 #define MAX_ASIC_ISR_LOOPS 20
58 #define ASIC3_GPIO_BASE_INCR \
59 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
61 static void asic3_irq_flip_edge(struct asic3
*asic
,
67 spin_lock_irqsave(&asic
->lock
, flags
);
68 edge
= asic3_read_register(asic
,
69 base
+ ASIC3_GPIO_EDGE_TRIGGER
);
71 asic3_write_register(asic
,
72 base
+ ASIC3_GPIO_EDGE_TRIGGER
, edge
);
73 spin_unlock_irqrestore(&asic
->lock
, flags
);
76 static void asic3_irq_demux(unsigned int irq
, struct irq_desc
*desc
)
84 asic
= desc
->handler_data
;
86 for (iter
= 0 ; iter
< MAX_ASIC_ISR_LOOPS
; iter
++) {
90 spin_lock_irqsave(&asic
->lock
, flags
);
91 status
= asic3_read_register(asic
,
92 ASIC3_OFFSET(INTR
, P_INT_STAT
));
93 spin_unlock_irqrestore(&asic
->lock
, flags
);
95 /* Check all ten register bits */
96 if ((status
& 0x3ff) == 0)
99 /* Handle GPIO IRQs */
100 for (bank
= 0; bank
< ASIC3_NUM_GPIO_BANKS
; bank
++) {
101 if (status
& (1 << bank
)) {
102 unsigned long base
, istat
;
104 base
= ASIC3_GPIO_A_BASE
105 + bank
* ASIC3_GPIO_BASE_INCR
;
107 spin_lock_irqsave(&asic
->lock
, flags
);
108 istat
= asic3_read_register(asic
,
110 ASIC3_GPIO_INT_STATUS
);
111 /* Clearing IntStatus */
112 asic3_write_register(asic
,
114 ASIC3_GPIO_INT_STATUS
, 0);
115 spin_unlock_irqrestore(&asic
->lock
, flags
);
117 for (i
= 0; i
< ASIC3_GPIOS_PER_BANK
; i
++) {
124 irqnr
= asic
->irq_base
+
125 (ASIC3_GPIOS_PER_BANK
* bank
)
127 desc
= irq_desc
+ irqnr
;
128 desc
->handle_irq(irqnr
, desc
);
129 if (asic
->irq_bothedge
[bank
] & bit
)
130 asic3_irq_flip_edge(asic
, base
,
136 /* Handle remaining IRQs in the status register */
137 for (i
= ASIC3_NUM_GPIOS
; i
< ASIC3_NR_IRQS
; i
++) {
138 /* They start at bit 4 and go up */
139 if (status
& (1 << (i
- ASIC3_NUM_GPIOS
+ 4))) {
140 desc
= irq_desc
+ asic
->irq_base
+ i
;
141 desc
->handle_irq(asic
->irq_base
+ i
,
147 if (iter
>= MAX_ASIC_ISR_LOOPS
)
148 dev_err(asic
->dev
, "interrupt processing overrun\n");
151 static inline int asic3_irq_to_bank(struct asic3
*asic
, int irq
)
155 n
= (irq
- asic
->irq_base
) >> 4;
157 return (n
* (ASIC3_GPIO_B_BASE
- ASIC3_GPIO_A_BASE
));
160 static inline int asic3_irq_to_index(struct asic3
*asic
, int irq
)
162 return (irq
- asic
->irq_base
) & 0xf;
165 static void asic3_mask_gpio_irq(unsigned int irq
)
167 struct asic3
*asic
= get_irq_chip_data(irq
);
168 u32 val
, bank
, index
;
171 bank
= asic3_irq_to_bank(asic
, irq
);
172 index
= asic3_irq_to_index(asic
, irq
);
174 spin_lock_irqsave(&asic
->lock
, flags
);
175 val
= asic3_read_register(asic
, bank
+ ASIC3_GPIO_MASK
);
177 asic3_write_register(asic
, bank
+ ASIC3_GPIO_MASK
, val
);
178 spin_unlock_irqrestore(&asic
->lock
, flags
);
181 static void asic3_mask_irq(unsigned int irq
)
183 struct asic3
*asic
= get_irq_chip_data(irq
);
187 spin_lock_irqsave(&asic
->lock
, flags
);
188 regval
= asic3_read_register(asic
,
190 ASIC3_INTR_INT_MASK
);
192 regval
&= ~(ASIC3_INTMASK_MASK0
<<
193 (irq
- (asic
->irq_base
+ ASIC3_NUM_GPIOS
)));
195 asic3_write_register(asic
,
199 spin_unlock_irqrestore(&asic
->lock
, flags
);
202 static void asic3_unmask_gpio_irq(unsigned int irq
)
204 struct asic3
*asic
= get_irq_chip_data(irq
);
205 u32 val
, bank
, index
;
208 bank
= asic3_irq_to_bank(asic
, irq
);
209 index
= asic3_irq_to_index(asic
, irq
);
211 spin_lock_irqsave(&asic
->lock
, flags
);
212 val
= asic3_read_register(asic
, bank
+ ASIC3_GPIO_MASK
);
213 val
&= ~(1 << index
);
214 asic3_write_register(asic
, bank
+ ASIC3_GPIO_MASK
, val
);
215 spin_unlock_irqrestore(&asic
->lock
, flags
);
218 static void asic3_unmask_irq(unsigned int irq
)
220 struct asic3
*asic
= get_irq_chip_data(irq
);
224 spin_lock_irqsave(&asic
->lock
, flags
);
225 regval
= asic3_read_register(asic
,
227 ASIC3_INTR_INT_MASK
);
229 regval
|= (ASIC3_INTMASK_MASK0
<<
230 (irq
- (asic
->irq_base
+ ASIC3_NUM_GPIOS
)));
232 asic3_write_register(asic
,
236 spin_unlock_irqrestore(&asic
->lock
, flags
);
239 static int asic3_gpio_irq_type(unsigned int irq
, unsigned int type
)
241 struct asic3
*asic
= get_irq_chip_data(irq
);
243 u16 trigger
, level
, edge
, bit
;
246 bank
= asic3_irq_to_bank(asic
, irq
);
247 index
= asic3_irq_to_index(asic
, irq
);
250 spin_lock_irqsave(&asic
->lock
, flags
);
251 level
= asic3_read_register(asic
,
252 bank
+ ASIC3_GPIO_LEVEL_TRIGGER
);
253 edge
= asic3_read_register(asic
,
254 bank
+ ASIC3_GPIO_EDGE_TRIGGER
);
255 trigger
= asic3_read_register(asic
,
256 bank
+ ASIC3_GPIO_TRIGGER_TYPE
);
257 asic
->irq_bothedge
[(irq
- asic
->irq_base
) >> 4] &= ~bit
;
259 if (type
== IRQ_TYPE_EDGE_RISING
) {
262 } else if (type
== IRQ_TYPE_EDGE_FALLING
) {
265 } else if (type
== IRQ_TYPE_EDGE_BOTH
) {
267 if (asic3_gpio_get(&asic
->gpio
, irq
- asic
->irq_base
))
271 asic
->irq_bothedge
[(irq
- asic
->irq_base
) >> 4] |= bit
;
272 } else if (type
== IRQ_TYPE_LEVEL_LOW
) {
275 } else if (type
== IRQ_TYPE_LEVEL_HIGH
) {
280 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
281 * be careful to not unmask them if mask was also called.
282 * Probably need internal state for mask.
284 dev_notice(asic
->dev
, "irq type not changed\n");
286 asic3_write_register(asic
, bank
+ ASIC3_GPIO_LEVEL_TRIGGER
,
288 asic3_write_register(asic
, bank
+ ASIC3_GPIO_EDGE_TRIGGER
,
290 asic3_write_register(asic
, bank
+ ASIC3_GPIO_TRIGGER_TYPE
,
292 spin_unlock_irqrestore(&asic
->lock
, flags
);
296 static struct irq_chip asic3_gpio_irq_chip
= {
297 .name
= "ASIC3-GPIO",
298 .ack
= asic3_mask_gpio_irq
,
299 .mask
= asic3_mask_gpio_irq
,
300 .unmask
= asic3_unmask_gpio_irq
,
301 .set_type
= asic3_gpio_irq_type
,
304 static struct irq_chip asic3_irq_chip
= {
306 .ack
= asic3_mask_irq
,
307 .mask
= asic3_mask_irq
,
308 .unmask
= asic3_unmask_irq
,
311 static int __init
asic3_irq_probe(struct platform_device
*pdev
)
313 struct asic3
*asic
= platform_get_drvdata(pdev
);
314 unsigned long clksel
= 0;
315 unsigned int irq
, irq_base
;
319 ret
= platform_get_irq(pdev
, 0);
324 /* turn on clock to IRQ controller */
325 clksel
|= CLOCK_SEL_CX
;
326 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, SEL
),
329 irq_base
= asic
->irq_base
;
331 for (irq
= irq_base
; irq
< irq_base
+ ASIC3_NR_IRQS
; irq
++) {
332 if (irq
< asic
->irq_base
+ ASIC3_NUM_GPIOS
)
333 set_irq_chip(irq
, &asic3_gpio_irq_chip
);
335 set_irq_chip(irq
, &asic3_irq_chip
);
337 set_irq_chip_data(irq
, asic
);
338 set_irq_handler(irq
, handle_level_irq
);
339 set_irq_flags(irq
, IRQF_VALID
| IRQF_PROBE
);
342 asic3_write_register(asic
, ASIC3_OFFSET(INTR
, INT_MASK
),
343 ASIC3_INTMASK_GINTMASK
);
345 set_irq_chained_handler(asic
->irq_nr
, asic3_irq_demux
);
346 set_irq_type(asic
->irq_nr
, IRQ_TYPE_EDGE_RISING
);
347 set_irq_data(asic
->irq_nr
, asic
);
352 static void asic3_irq_remove(struct platform_device
*pdev
)
354 struct asic3
*asic
= platform_get_drvdata(pdev
);
355 unsigned int irq
, irq_base
;
357 irq_base
= asic
->irq_base
;
359 for (irq
= irq_base
; irq
< irq_base
+ ASIC3_NR_IRQS
; irq
++) {
360 set_irq_flags(irq
, 0);
361 set_irq_handler(irq
, NULL
);
362 set_irq_chip(irq
, NULL
);
363 set_irq_chip_data(irq
, NULL
);
365 set_irq_chained_handler(asic
->irq_nr
, NULL
);
369 static int asic3_gpio_direction(struct gpio_chip
*chip
,
370 unsigned offset
, int out
)
372 u32 mask
= ASIC3_GPIO_TO_MASK(offset
), out_reg
;
373 unsigned int gpio_base
;
377 asic
= container_of(chip
, struct asic3
, gpio
);
378 gpio_base
= ASIC3_GPIO_TO_BASE(offset
);
380 if (gpio_base
> ASIC3_GPIO_D_BASE
) {
381 dev_err(asic
->dev
, "Invalid base (0x%x) for gpio %d\n",
386 spin_lock_irqsave(&asic
->lock
, flags
);
388 out_reg
= asic3_read_register(asic
, gpio_base
+ ASIC3_GPIO_DIRECTION
);
390 /* Input is 0, Output is 1 */
396 asic3_write_register(asic
, gpio_base
+ ASIC3_GPIO_DIRECTION
, out_reg
);
398 spin_unlock_irqrestore(&asic
->lock
, flags
);
404 static int asic3_gpio_direction_input(struct gpio_chip
*chip
,
407 return asic3_gpio_direction(chip
, offset
, 0);
410 static int asic3_gpio_direction_output(struct gpio_chip
*chip
,
411 unsigned offset
, int value
)
413 return asic3_gpio_direction(chip
, offset
, 1);
416 static int asic3_gpio_get(struct gpio_chip
*chip
,
419 unsigned int gpio_base
;
420 u32 mask
= ASIC3_GPIO_TO_MASK(offset
);
423 asic
= container_of(chip
, struct asic3
, gpio
);
424 gpio_base
= ASIC3_GPIO_TO_BASE(offset
);
426 if (gpio_base
> ASIC3_GPIO_D_BASE
) {
427 dev_err(asic
->dev
, "Invalid base (0x%x) for gpio %d\n",
432 return asic3_read_register(asic
, gpio_base
+ ASIC3_GPIO_STATUS
) & mask
;
435 static void asic3_gpio_set(struct gpio_chip
*chip
,
436 unsigned offset
, int value
)
439 unsigned int gpio_base
;
443 asic
= container_of(chip
, struct asic3
, gpio
);
444 gpio_base
= ASIC3_GPIO_TO_BASE(offset
);
446 if (gpio_base
> ASIC3_GPIO_D_BASE
) {
447 dev_err(asic
->dev
, "Invalid base (0x%x) for gpio %d\n",
452 mask
= ASIC3_GPIO_TO_MASK(offset
);
454 spin_lock_irqsave(&asic
->lock
, flags
);
456 out_reg
= asic3_read_register(asic
, gpio_base
+ ASIC3_GPIO_OUT
);
463 asic3_write_register(asic
, gpio_base
+ ASIC3_GPIO_OUT
, out_reg
);
465 spin_unlock_irqrestore(&asic
->lock
, flags
);
470 static __init
int asic3_gpio_probe(struct platform_device
*pdev
,
471 u16
*gpio_config
, int num
)
473 struct asic3
*asic
= platform_get_drvdata(pdev
);
474 u16 alt_reg
[ASIC3_NUM_GPIO_BANKS
];
475 u16 out_reg
[ASIC3_NUM_GPIO_BANKS
];
476 u16 dir_reg
[ASIC3_NUM_GPIO_BANKS
];
479 memzero(alt_reg
, ASIC3_NUM_GPIO_BANKS
* sizeof(u16
));
480 memzero(out_reg
, ASIC3_NUM_GPIO_BANKS
* sizeof(u16
));
481 memzero(dir_reg
, ASIC3_NUM_GPIO_BANKS
* sizeof(u16
));
483 /* Enable all GPIOs */
484 asic3_write_register(asic
, ASIC3_GPIO_OFFSET(A
, MASK
), 0xffff);
485 asic3_write_register(asic
, ASIC3_GPIO_OFFSET(B
, MASK
), 0xffff);
486 asic3_write_register(asic
, ASIC3_GPIO_OFFSET(C
, MASK
), 0xffff);
487 asic3_write_register(asic
, ASIC3_GPIO_OFFSET(D
, MASK
), 0xffff);
489 for (i
= 0; i
< num
; i
++) {
490 u8 alt
, pin
, dir
, init
, bank_num
, bit_num
;
491 u16 config
= gpio_config
[i
];
493 pin
= ASIC3_CONFIG_GPIO_PIN(config
);
494 alt
= ASIC3_CONFIG_GPIO_ALT(config
);
495 dir
= ASIC3_CONFIG_GPIO_DIR(config
);
496 init
= ASIC3_CONFIG_GPIO_INIT(config
);
498 bank_num
= ASIC3_GPIO_TO_BANK(pin
);
499 bit_num
= ASIC3_GPIO_TO_BIT(pin
);
501 alt_reg
[bank_num
] |= (alt
<< bit_num
);
502 out_reg
[bank_num
] |= (init
<< bit_num
);
503 dir_reg
[bank_num
] |= (dir
<< bit_num
);
506 for (i
= 0; i
< ASIC3_NUM_GPIO_BANKS
; i
++) {
507 asic3_write_register(asic
,
508 ASIC3_BANK_TO_BASE(i
) +
509 ASIC3_GPIO_DIRECTION
,
511 asic3_write_register(asic
,
512 ASIC3_BANK_TO_BASE(i
) + ASIC3_GPIO_OUT
,
514 asic3_write_register(asic
,
515 ASIC3_BANK_TO_BASE(i
) +
516 ASIC3_GPIO_ALT_FUNCTION
,
520 return gpiochip_add(&asic
->gpio
);
523 static int asic3_gpio_remove(struct platform_device
*pdev
)
525 struct asic3
*asic
= platform_get_drvdata(pdev
);
527 return gpiochip_remove(&asic
->gpio
);
532 static int __init
asic3_probe(struct platform_device
*pdev
)
534 struct asic3_platform_data
*pdata
= pdev
->dev
.platform_data
;
536 struct resource
*mem
;
537 unsigned long clksel
;
540 asic
= kzalloc(sizeof(struct asic3
), GFP_KERNEL
);
542 printk(KERN_ERR
"kzalloc failed\n");
546 spin_lock_init(&asic
->lock
);
547 platform_set_drvdata(pdev
, asic
);
548 asic
->dev
= &pdev
->dev
;
550 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
553 dev_err(asic
->dev
, "no MEM resource\n");
557 map_size
= mem
->end
- mem
->start
+ 1;
558 asic
->mapping
= ioremap(mem
->start
, map_size
);
559 if (!asic
->mapping
) {
561 dev_err(asic
->dev
, "Couldn't ioremap\n");
565 asic
->irq_base
= pdata
->irq_base
;
567 /* calculate bus shift from mem resource */
568 asic
->bus_shift
= 2 - (map_size
>> 12);
571 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, SEL
), clksel
);
573 ret
= asic3_irq_probe(pdev
);
575 dev_err(asic
->dev
, "Couldn't probe IRQs\n");
579 asic
->gpio
.base
= pdata
->gpio_base
;
580 asic
->gpio
.ngpio
= ASIC3_NUM_GPIOS
;
581 asic
->gpio
.get
= asic3_gpio_get
;
582 asic
->gpio
.set
= asic3_gpio_set
;
583 asic
->gpio
.direction_input
= asic3_gpio_direction_input
;
584 asic
->gpio
.direction_output
= asic3_gpio_direction_output
;
586 ret
= asic3_gpio_probe(pdev
,
588 pdata
->gpio_config_num
);
590 dev_err(asic
->dev
, "GPIO probe failed\n");
594 dev_info(asic
->dev
, "ASIC3 Core driver\n");
599 asic3_irq_remove(pdev
);
602 iounmap(asic
->mapping
);
610 static int asic3_remove(struct platform_device
*pdev
)
613 struct asic3
*asic
= platform_get_drvdata(pdev
);
615 ret
= asic3_gpio_remove(pdev
);
618 asic3_irq_remove(pdev
);
620 asic3_write_register(asic
, ASIC3_OFFSET(CLOCK
, SEL
), 0);
622 iounmap(asic
->mapping
);
629 static void asic3_shutdown(struct platform_device
*pdev
)
633 static struct platform_driver asic3_device_driver
= {
637 .remove
= __devexit_p(asic3_remove
),
638 .shutdown
= asic3_shutdown
,
641 static int __init
asic3_init(void)
644 retval
= platform_driver_probe(&asic3_device_driver
, asic3_probe
);
648 subsys_initcall(asic3_init
);