drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include <linux/io-mapping.h>
  36
  37 /* General customization:
  38  */
  39
  40 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  41
  42 #define DRIVER_NAME             "i915"
  43 #define DRIVER_DESC             "Intel Graphics"
  44 #define DRIVER_DATE             "20080730"
  45
  46 enum pipe {
  47         PIPE_A = 0,
  48         PIPE_B,
  49 };
  50
  51 #define I915_NUM_PIPE   2
  52
  53 /* Interface history:
  54  *
  55  * 1.1: Original.
  56  * 1.2: Add Power Management
  57  * 1.3: Add vblank support
  58  * 1.4: Fix cmdbuffer path, add heap destroy
  59  * 1.5: Add vblank pipe configuration
  60  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  61  *      - Support vertical blank on secondary display pipe
  62  */
  63 #define DRIVER_MAJOR            1
  64 #define DRIVER_MINOR            6
  65 #define DRIVER_PATCHLEVEL       0
  66
  67 #define WATCH_COHERENCY 0
  68 #define WATCH_BUF       0
  69 #define WATCH_EXEC      0
  70 #define WATCH_LRU       0
  71 #define WATCH_RELOC     0
  72 #define WATCH_INACTIVE  0
  73 #define WATCH_PWRITE    0
  74
  75 #define I915_GEM_PHYS_CURSOR_0 1
  76 #define I915_GEM_PHYS_CURSOR_1 2
  77 #define I915_GEM_PHYS_OVERLAY_REGS 3
  78 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  79
  80 struct drm_i915_gem_phys_object {
  81         int id;
  82         struct page **page_list;
  83         drm_dma_handle_t *handle;
  84         struct drm_gem_object *cur_obj;
  85 };
  86
  87 typedef struct _drm_i915_ring_buffer {
  88         int tail_mask;
  89         unsigned long Size;
  90         u8 *virtual_start;
  91         int head;
  92         int tail;
  93         int space;
  94         drm_local_map_t map;
  95         struct drm_gem_object *ring_obj;
  96 } drm_i915_ring_buffer_t;
  97
  98 struct mem_block {
  99         struct mem_block *next;
 100         struct mem_block *prev;
 101         int start;
 102         int size;
 103         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 104 };
 105
 106 struct opregion_header;
 107 struct opregion_acpi;
 108 struct opregion_swsci;
 109 struct opregion_asle;
 110
 111 struct intel_opregion {
 112         struct opregion_header *header;
 113         struct opregion_acpi *acpi;
 114         struct opregion_swsci *swsci;
 115         struct opregion_asle *asle;
 116         int enabled;
 117 };
 118
 119 struct drm_i915_master_private {
 120         drm_local_map_t *sarea;
 121         struct _drm_i915_sarea *sarea_priv;
 122 };
 123 #define I915_FENCE_REG_NONE -1
 124
 125 struct drm_i915_fence_reg {
 126         struct drm_gem_object *obj;
 127 };
 128
 129 typedef struct drm_i915_private {
 130         struct drm_device *dev;
 131
 132         int has_gem;
 133
 134         void __iomem *regs;
 135
 136         drm_i915_ring_buffer_t ring;
 137
 138         drm_dma_handle_t *status_page_dmah;
 139         void *hw_status_page;
 140         dma_addr_t dma_status_page;
 141         uint32_t counter;
 142         unsigned int status_gfx_addr;
 143         drm_local_map_t hws_map;
 144         struct drm_gem_object *hws_obj;
 145
 146         unsigned int cpp;
 147         int back_offset;
 148         int front_offset;
 149         int current_page;
 150         int page_flipping;
 151
 152         wait_queue_head_t irq_queue;
 153         atomic_t irq_received;
 154         /** Protects user_irq_refcount and irq_mask_reg */
 155         spinlock_t user_irq_lock;
 156         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 157         int user_irq_refcount;
 158         /** Cached value of IMR to avoid reads in updating the bitfield */
 159         u32 irq_mask_reg;
 160         u32 pipestat[2];
 161
 162         int tex_lru_log_granularity;
 163         int allow_batchbuffer;
 164         struct mem_block *agp_heap;
 165         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 166         int vblank_pipe;
 167
 168         bool cursor_needs_physical;
 169
 170         struct drm_mm vram;
 171
 172         int irq_enabled;
 173
 174         struct intel_opregion opregion;
 175
 176         /* LVDS info */
 177         int backlight_duty_cycle;  /* restore backlight to this value */
 178         bool panel_wants_dither;
 179         struct drm_display_mode *panel_fixed_mode;
 180         struct drm_display_mode *vbt_mode; /* if any */
 181
 182         /* Feature bits from the VBIOS */
 183         unsigned int int_tv_support:1;
 184         unsigned int lvds_dither:1;
 185         unsigned int lvds_vbt:1;
 186         unsigned int int_crt_support:1;
 187
 188         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 189         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 190         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 191
 192         /* Register state */
 193         u8 saveLBB;
 194         u32 saveDSPACNTR;
 195         u32 saveDSPBCNTR;
 196         u32 saveDSPARB;
 197         u32 saveRENDERSTANDBY;
 198         u32 saveHWS;
 199         u32 savePIPEACONF;
 200         u32 savePIPEBCONF;
 201         u32 savePIPEASRC;
 202         u32 savePIPEBSRC;
 203         u32 saveFPA0;
 204         u32 saveFPA1;
 205         u32 saveDPLL_A;
 206         u32 saveDPLL_A_MD;
 207         u32 saveHTOTAL_A;
 208         u32 saveHBLANK_A;
 209         u32 saveHSYNC_A;
 210         u32 saveVTOTAL_A;
 211         u32 saveVBLANK_A;
 212         u32 saveVSYNC_A;
 213         u32 saveBCLRPAT_A;
 214         u32 savePIPEASTAT;
 215         u32 saveDSPASTRIDE;
 216         u32 saveDSPASIZE;
 217         u32 saveDSPAPOS;
 218         u32 saveDSPAADDR;
 219         u32 saveDSPASURF;
 220         u32 saveDSPATILEOFF;
 221         u32 savePFIT_PGM_RATIOS;
 222         u32 saveBLC_PWM_CTL;
 223         u32 saveBLC_PWM_CTL2;
 224         u32 saveFPB0;
 225         u32 saveFPB1;
 226         u32 saveDPLL_B;
 227         u32 saveDPLL_B_MD;
 228         u32 saveHTOTAL_B;
 229         u32 saveHBLANK_B;
 230         u32 saveHSYNC_B;
 231         u32 saveVTOTAL_B;
 232         u32 saveVBLANK_B;
 233         u32 saveVSYNC_B;
 234         u32 saveBCLRPAT_B;
 235         u32 savePIPEBSTAT;
 236         u32 saveDSPBSTRIDE;
 237         u32 saveDSPBSIZE;
 238         u32 saveDSPBPOS;
 239         u32 saveDSPBADDR;
 240         u32 saveDSPBSURF;
 241         u32 saveDSPBTILEOFF;
 242         u32 saveVGA0;
 243         u32 saveVGA1;
 244         u32 saveVGA_PD;
 245         u32 saveVGACNTRL;
 246         u32 saveADPA;
 247         u32 saveLVDS;
 248         u32 savePP_ON_DELAYS;
 249         u32 savePP_OFF_DELAYS;
 250         u32 saveDVOA;
 251         u32 saveDVOB;
 252         u32 saveDVOC;
 253         u32 savePP_ON;
 254         u32 savePP_OFF;
 255         u32 savePP_CONTROL;
 256         u32 savePP_DIVISOR;
 257         u32 savePFIT_CONTROL;
 258         u32 save_palette_a[256];
 259         u32 save_palette_b[256];
 260         u32 saveFBC_CFB_BASE;
 261         u32 saveFBC_LL_BASE;
 262         u32 saveFBC_CONTROL;
 263         u32 saveFBC_CONTROL2;
 264         u32 saveIER;
 265         u32 saveIIR;
 266         u32 saveIMR;
 267         u32 saveCACHE_MODE_0;
 268         u32 saveD_STATE;
 269         u32 saveCG_2D_DIS;
 270         u32 saveMI_ARB_STATE;
 271         u32 saveSWF0[16];
 272         u32 saveSWF1[16];
 273         u32 saveSWF2[3];
 274         u8 saveMSR;
 275         u8 saveSR[8];
 276         u8 saveGR[25];
 277         u8 saveAR_INDEX;
 278         u8 saveAR[21];
 279         u8 saveDACMASK;
 280         u8 saveDACDATA[256*3]; /* 256 3-byte colors */
 281         u8 saveCR[37];
 282
 283         struct {
 284                 struct drm_mm gtt_space;
 285
 286                 struct io_mapping *gtt_mapping;
 287                 int gtt_mtrr;
 288
 289                 /**
 290                  * List of objects currently involved in rendering from the
 291                  * ringbuffer.
 292                  *
 293                  * Includes buffers having the contents of their GPU caches
 294                  * flushed, not necessarily primitives.  last_rendering_seqno
 295                  * represents when the rendering involved will be completed.
 296                  *
 297                  * A reference is held on the buffer while on this list.
 298                  */
 299                 struct list_head active_list;
 300
 301                 /**
 302                  * List of objects which are not in the ringbuffer but which
 303                  * still have a write_domain which needs to be flushed before
 304                  * unbinding.
 305                  *
 306                  * last_rendering_seqno is 0 while an object is in this list.
 307                  *
 308                  * A reference is held on the buffer while on this list.
 309                  */
 310                 struct list_head flushing_list;
 311
 312                 /**
 313                  * LRU list of objects which are not in the ringbuffer and
 314                  * are ready to unbind, but are still in the GTT.
 315                  *
 316                  * last_rendering_seqno is 0 while an object is in this list.
 317                  *
 318                  * A reference is not held on the buffer while on this list,
 319                  * as merely being GTT-bound shouldn't prevent its being
 320                  * freed, and we'll pull it off the list in the free path.
 321                  */
 322                 struct list_head inactive_list;
 323
 324                 /**
 325                  * List of breadcrumbs associated with GPU requests currently
 326                  * outstanding.
 327                  */
 328                 struct list_head request_list;
 329
 330                 /**
 331                  * We leave the user IRQ off as much as possible,
 332                  * but this means that requests will finish and never
 333                  * be retired once the system goes idle. Set a timer to
 334                  * fire periodically while the ring is running. When it
 335                  * fires, go retire requests.
 336                  */
 337                 struct delayed_work retire_work;
 338
 339                 uint32_t next_gem_seqno;
 340
 341                 /**
 342                  * Waiting sequence number, if any
 343                  */
 344                 uint32_t waiting_gem_seqno;
 345
 346                 /**
 347                  * Last seq seen at irq time
 348                  */
 349                 uint32_t irq_gem_seqno;
 350
 351                 /**
 352                  * Flag if the X Server, and thus DRM, is not currently in
 353                  * control of the device.
 354                  *
 355                  * This is set between LeaveVT and EnterVT.  It needs to be
 356                  * replaced with a semaphore.  It also needs to be
 357                  * transitioned away from for kernel modesetting.
 358                  */
 359                 int suspended;
 360
 361                 /**
 362                  * Flag if the hardware appears to be wedged.
 363                  *
 364                  * This is set when attempts to idle the device timeout.
 365                  * It prevents command submission from occuring and makes
 366                  * every pending request fail
 367                  */
 368                 int wedged;
 369
 370                 /** Bit 6 swizzling required for X tiling */
 371                 uint32_t bit_6_swizzle_x;
 372                 /** Bit 6 swizzling required for Y tiling */
 373                 uint32_t bit_6_swizzle_y;
 374
 375                 /* storage for physical objects */
 376                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 377         } mm;
 378 } drm_i915_private_t;
 379
 380 /** driver private structure attached to each drm_gem_object */
 381 struct drm_i915_gem_object {
 382         struct drm_gem_object *obj;
 383
 384         /** Current space allocated to this object in the GTT, if any. */
 385         struct drm_mm_node *gtt_space;
 386
 387         /** This object's place on the active/flushing/inactive lists */
 388         struct list_head list;
 389
 390         /**
 391          * This is set if the object is on the active or flushing lists
 392          * (has pending rendering), and is not set if it's on inactive (ready
 393          * to be unbound).
 394          */
 395         int active;
 396
 397         /**
 398          * This is set if the object has been written to since last bound
 399          * to the GTT
 400          */
 401         int dirty;
 402
 403         /** AGP memory structure for our GTT binding. */
 404         DRM_AGP_MEM *agp_mem;
 405
 406         struct page **page_list;
 407
 408         /**
 409          * Current offset of the object in GTT space.
 410          *
 411          * This is the same as gtt_space->start
 412          */
 413         uint32_t gtt_offset;
 414         /**
 415          * Required alignment for the object
 416          */
 417         uint32_t gtt_alignment;
 418         /**
 419          * Fake offset for use by mmap(2)
 420          */
 421         uint64_t mmap_offset;
 422
 423         /**
 424          * Fence register bits (if any) for this object.  Will be set
 425          * as needed when mapped into the GTT.
 426          * Protected by dev->struct_mutex.
 427          */
 428         int fence_reg;
 429
 430         /** Boolean whether this object has a valid gtt offset. */
 431         int gtt_bound;
 432
 433         /** How many users have pinned this object in GTT space */
 434         int pin_count;
 435
 436         /** Breadcrumb of last rendering to the buffer. */
 437         uint32_t last_rendering_seqno;
 438
 439         /** Current tiling mode for the object. */
 440         uint32_t tiling_mode;
 441         uint32_t stride;
 442
 443         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 444         uint32_t agp_type;
 445
 446         /**
 447          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 448          * flags which individual pages are valid.
 449          */
 450         uint8_t *page_cpu_valid;
 451
 452         /** User space pin count and filp owning the pin */
 453         uint32_t user_pin_count;
 454         struct drm_file *pin_filp;
 455
 456         /** for phy allocated objects */
 457         struct drm_i915_gem_phys_object *phys_obj;
 458 };
 459
 460 /**
 461  * Request queue structure.
 462  *
 463  * The request queue allows us to note sequence numbers that have been emitted
 464  * and may be associated with active buffers to be retired.
 465  *
 466  * By keeping this list, we can avoid having to do questionable
 467  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 468  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 469  */
 470 struct drm_i915_gem_request {
 471         /** GEM sequence number associated with this request. */
 472         uint32_t seqno;
 473
 474         /** Time at which this request was emitted, in jiffies. */
 475         unsigned long emitted_jiffies;
 476
 477         struct list_head list;
 478 };
 479
 480 struct drm_i915_file_private {
 481         struct {
 482                 uint32_t last_gem_seqno;
 483                 uint32_t last_gem_throttle_seqno;
 484         } mm;
 485 };
 486
 487 enum intel_chip_family {
 488         CHIP_I8XX = 0x01,
 489         CHIP_I9XX = 0x02,
 490         CHIP_I915 = 0x04,
 491         CHIP_I965 = 0x08,
 492 };
 493
 494 extern struct drm_ioctl_desc i915_ioctls[];
 495 extern int i915_max_ioctl;
 496 extern unsigned int i915_fbpercrtc;
 497
 498 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 499 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 500
 501                                 /* i915_dma.c */
 502 extern void i915_kernel_lost_context(struct drm_device * dev);
 503 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 504 extern int i915_driver_unload(struct drm_device *);
 505 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 506 extern void i915_driver_lastclose(struct drm_device * dev);
 507 extern void i915_driver_preclose(struct drm_device *dev,
 508                                  struct drm_file *file_priv);
 509 extern void i915_driver_postclose(struct drm_device *dev,
 510                                   struct drm_file *file_priv);
 511 extern int i915_driver_device_is_agp(struct drm_device * dev);
 512 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 513                               unsigned long arg);
 514 extern int i915_emit_box(struct drm_device *dev,
 515                          struct drm_clip_rect __user *boxes,
 516                          int i, int DR1, int DR4);
 517
 518 /* i915_irq.c */
 519 extern int i915_irq_emit(struct drm_device *dev, void *data,
 520                          struct drm_file *file_priv);
 521 extern int i915_irq_wait(struct drm_device *dev, void *data,
 522                          struct drm_file *file_priv);
 523 void i915_user_irq_get(struct drm_device *dev);
 524 void i915_user_irq_put(struct drm_device *dev);
 525 extern void i915_enable_interrupt (struct drm_device *dev);
 526
 527 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 528 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 529 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 530 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 531 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 532                                 struct drm_file *file_priv);
 533 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 534                                 struct drm_file *file_priv);
 535 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 536 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 537 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 538 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 539                             struct drm_file *file_priv);
 540 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 541
 542 void
 543 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 544
 545 void
 546 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 547
 548
 549 /* i915_mem.c */
 550 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 551                           struct drm_file *file_priv);
 552 extern int i915_mem_free(struct drm_device *dev, void *data,
 553                          struct drm_file *file_priv);
 554 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 555                               struct drm_file *file_priv);
 556 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 557                                  struct drm_file *file_priv);
 558 extern void i915_mem_takedown(struct mem_block **heap);
 559 extern void i915_mem_release(struct drm_device * dev,
 560                              struct drm_file *file_priv, struct mem_block *heap);
 561 /* i915_gem.c */
 562 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 563                         struct drm_file *file_priv);
 564 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 565                           struct drm_file *file_priv);
 566 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 567                          struct drm_file *file_priv);
 568 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 569                           struct drm_file *file_priv);
 570 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 571                         struct drm_file *file_priv);
 572 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 573                         struct drm_file *file_priv);
 574 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 575                               struct drm_file *file_priv);
 576 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 577                              struct drm_file *file_priv);
 578 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 579                         struct drm_file *file_priv);
 580 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 581                        struct drm_file *file_priv);
 582 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 583                          struct drm_file *file_priv);
 584 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 585                         struct drm_file *file_priv);
 586 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 587                             struct drm_file *file_priv);
 588 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 589                            struct drm_file *file_priv);
 590 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 591                            struct drm_file *file_priv);
 592 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 593                         struct drm_file *file_priv);
 594 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 595                         struct drm_file *file_priv);
 596 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 597                                 struct drm_file *file_priv);
 598 void i915_gem_load(struct drm_device *dev);
 599 int i915_gem_proc_init(struct drm_minor *minor);
 600 void i915_gem_proc_cleanup(struct drm_minor *minor);
 601 int i915_gem_init_object(struct drm_gem_object *obj);
 602 void i915_gem_free_object(struct drm_gem_object *obj);
 603 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 604 void i915_gem_object_unpin(struct drm_gem_object *obj);
 605 void i915_gem_lastclose(struct drm_device *dev);
 606 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 607 void i915_gem_retire_requests(struct drm_device *dev);
 608 void i915_gem_retire_work_handler(struct work_struct *work);
 609 void i915_gem_clflush_object(struct drm_gem_object *obj);
 610 int i915_gem_object_set_domain(struct drm_gem_object *obj,
 611                                uint32_t read_domains,
 612                                uint32_t write_domain);
 613 int i915_gem_init_ringbuffer(struct drm_device *dev);
 614 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 615 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
 616                      unsigned long end);
 617 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 618 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
 619                                       int write);
 620 int i915_gem_attach_phys_object(struct drm_device *dev,
 621                                 struct drm_gem_object *obj, int id);
 622 void i915_gem_detach_phys_object(struct drm_device *dev,
 623                                  struct drm_gem_object *obj);
 624 void i915_gem_free_all_phys_object(struct drm_device *dev);
 625
 626 /* i915_gem_tiling.c */
 627 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 628
 629 /* i915_gem_debug.c */
 630 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 631                           const char *where, uint32_t mark);
 632 #if WATCH_INACTIVE
 633 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 634 #else
 635 #define i915_verify_inactive(dev, file, line)
 636 #endif
 637 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 638 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 639                           const char *where, uint32_t mark);
 640 void i915_dump_lru(struct drm_device *dev, const char *where);
 641
 642 /* i915_suspend.c */
 643 extern int i915_save_state(struct drm_device *dev);
 644 extern int i915_restore_state(struct drm_device *dev);
 645
 646 /* i915_suspend.c */
 647 extern int i915_save_state(struct drm_device *dev);
 648 extern int i915_restore_state(struct drm_device *dev);
 649
 650 #ifdef CONFIG_ACPI
 651 /* i915_opregion.c */
 652 extern int intel_opregion_init(struct drm_device *dev);
 653 extern void intel_opregion_free(struct drm_device *dev);
 654 extern void opregion_asle_intr(struct drm_device *dev);
 655 extern void opregion_enable_asle(struct drm_device *dev);
 656 #else
 657 static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
 658 static inline void intel_opregion_free(struct drm_device *dev) { return; }
 659 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 660 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 661 #endif
 662
 663 /* modesetting */
 664 extern void intel_modeset_init(struct drm_device *dev);
 665 extern void intel_modeset_cleanup(struct drm_device *dev);
 666
 667 /**
 668  * Lock test for when it's just for synchronization of ring access.
 669  *
 670  * In that case, we don't need to do it when GEM is initialized as nobody else
 671  * has access to the ring.
 672  */
 673 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 674         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 675                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 676 } while (0)
 677
 678 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 679 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 680 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 681 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 682 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 683 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 684 #ifdef writeq
 685 #define I915_WRITE64(reg, val)  writeq(val, dev_priv->regs + (reg))
 686 #else
 687 #define I915_WRITE64(reg, val)  (writel(val, dev_priv->regs + (reg)), \
 688                                  writel(upper_32_bits(val), dev_priv->regs + \
 689                                         (reg) + 4))
 690 #endif
 691 #define POSTING_READ(reg)       (void)I915_READ(reg)
 692
 693 #define I915_VERBOSE 0
 694
 695 #define RING_LOCALS     unsigned int outring, ringmask, outcount; \
 696                         volatile char *virt;
 697
 698 #define BEGIN_LP_RING(n) do {                           \
 699         if (I915_VERBOSE)                               \
 700                 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));  \
 701         if (dev_priv->ring.space < (n)*4)               \
 702                 i915_wait_ring(dev, (n)*4, __func__);           \
 703         outcount = 0;                                   \
 704         outring = dev_priv->ring.tail;                  \
 705         ringmask = dev_priv->ring.tail_mask;            \
 706         virt = dev_priv->ring.virtual_start;            \
 707 } while (0)
 708
 709 #define OUT_RING(n) do {                                        \
 710         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 711         *(volatile unsigned int *)(virt + outring) = (n);       \
 712         outcount++;                                             \
 713         outring += 4;                                           \
 714         outring &= ringmask;                                    \
 715 } while (0)
 716
 717 #define ADVANCE_LP_RING() do {                                          \
 718         if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring);   \
 719         dev_priv->ring.tail = outring;                                  \
 720         dev_priv->ring.space -= outcount * 4;                           \
 721         I915_WRITE(PRB0_TAIL, outring);                 \
 722 } while(0)
 723
 724 /**
 725  * Reads a dword out of the status page, which is written to from the command
 726  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 727  * MI_STORE_DATA_IMM.
 728  *
 729  * The following dwords have a reserved meaning:
 730  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 731  * 0x04: ring 0 head pointer
 732  * 0x05: ring 1 head pointer (915-class)
 733  * 0x06: ring 2 head pointer (915-class)
 734  * 0x10-0x1b: Context status DWords (GM45)
 735  * 0x1f: Last written status offset. (GM45)
 736  *
 737  * The area from dword 0x20 to 0x3ff is available for driver usage.
 738  */
 739 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 740 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
 741 #define I915_GEM_HWS_INDEX              0x20
 742 #define I915_BREADCRUMB_INDEX           0x21
 743
 744 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 745
 746 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
 747 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
 748 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
 749 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
 750 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
 751
 752 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
 753 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
 754 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
 755 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
 756                         (dev)->pci_device == 0x27AE)
 757 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
 758                        (dev)->pci_device == 0x2982 || \
 759                        (dev)->pci_device == 0x2992 || \
 760                        (dev)->pci_device == 0x29A2 || \
 761                        (dev)->pci_device == 0x2A02 || \
 762                        (dev)->pci_device == 0x2A12 || \
 763                        (dev)->pci_device == 0x2A42 || \
 764                        (dev)->pci_device == 0x2E02 || \
 765                        (dev)->pci_device == 0x2E12 || \
 766                        (dev)->pci_device == 0x2E22)
 767
 768 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
 769
 770 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
 771
 772 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
 773                      (dev)->pci_device == 0x2E12 || \
 774                      (dev)->pci_device == 0x2E22 || \
 775                      IS_GM45(dev))
 776
 777 #define IS_G33(dev)    ((dev)->pci_device == 0x29C2 ||  \
 778                         (dev)->pci_device == 0x29B2 ||  \
 779                         (dev)->pci_device == 0x29D2)
 780
 781 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
 782                       IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
 783
 784 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
 785                         IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
 786
 787 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
 788 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev))
 789
 790 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
 791
 792 #endif