drivers/staging/brcm80211/include/spid.h

   1 /*
   2  * Copyright (c) 2010 Broadcom Corporation
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef _SPI_H
  18 #define _SPI_H
  19
  20 /*
  21  * Brcm SPI Device Register Map.
  22  *
  23  */
  24
  25 typedef volatile struct {
  26         uint8 config;           /* 0x00, len, endian, clock, speed, polarity, wakeup */
  27         uint8 response_delay;   /* 0x01, read response delay in bytes (corerev < 3) */
  28         uint8 status_enable;    /* 0x02, status-enable, intr with status, response_delay
  29                                  * function selection, command/data error check
  30                                  */
  31         uint8 reset_bp;         /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
  32         uint16 intr_reg;        /* 0x04, Intr status register */
  33         uint16 intr_en_reg;     /* 0x06, Intr mask register */
  34         uint32 status_reg;      /* 0x08, RO, Status bits of last spi transfer */
  35         uint16 f1_info_reg;     /* 0x0c, RO, enabled, ready for data transfer, blocksize */
  36         uint16 f2_info_reg;     /* 0x0e, RO, enabled, ready for data transfer, blocksize */
  37         uint16 f3_info_reg;     /* 0x10, RO, enabled, ready for data transfer, blocksize */
  38         uint32 test_read;       /* 0x14, RO 0xfeedbead signature */
  39         uint32 test_rw;         /* 0x18, RW */
  40         uint8 resp_delay_f0;    /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */
  41         uint8 resp_delay_f1;    /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */
  42         uint8 resp_delay_f2;    /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */
  43         uint8 resp_delay_f3;    /* 0x1f, read resp delay bytes for F3 (corerev >= 3) */
  44 } spi_regs_t;
  45
  46 /* SPI device register offsets */
  47 #define SPID_CONFIG                     0x00
  48 #define SPID_RESPONSE_DELAY             0x01
  49 #define SPID_STATUS_ENABLE              0x02
  50 #define SPID_RESET_BP                   0x03    /* (corerev >= 1) */
  51 #define SPID_INTR_REG                   0x04    /* 16 bits - Interrupt status */
  52 #define SPID_INTR_EN_REG                0x06    /* 16 bits - Interrupt mask */
  53 #define SPID_STATUS_REG                 0x08    /* 32 bits */
  54 #define SPID_F1_INFO_REG                0x0C    /* 16 bits */
  55 #define SPID_F2_INFO_REG                0x0E    /* 16 bits */
  56 #define SPID_F3_INFO_REG                0x10    /* 16 bits */
  57 #define SPID_TEST_READ                  0x14    /* 32 bits */
  58 #define SPID_TEST_RW                    0x18    /* 32 bits */
  59 #define SPID_RESP_DELAY_F0              0x1c    /* 8 bits (corerev >= 3) */
  60 #define SPID_RESP_DELAY_F1              0x1d    /* 8 bits (corerev >= 3) */
  61 #define SPID_RESP_DELAY_F2              0x1e    /* 8 bits (corerev >= 3) */
  62 #define SPID_RESP_DELAY_F3              0x1f    /* 8 bits (corerev >= 3) */
  63
  64 /* Bit masks for SPID_CONFIG device register */
  65 #define WORD_LENGTH_32  0x1     /* 0/1 16/32 bit word length */
  66 #define ENDIAN_BIG      0x2     /* 0/1 Little/Big Endian */
  67 #define CLOCK_PHASE     0x4     /* 0/1 clock phase delay */
  68 #define CLOCK_POLARITY  0x8     /* 0/1 Idle state clock polarity is low/high */
  69 #define HIGH_SPEED_MODE 0x10    /* 1/0 High Speed mode / Normal mode */
  70 #define INTR_POLARITY   0x20    /* 1/0 Interrupt active polarity is high/low */
  71 #define WAKE_UP         0x80    /* 0/1 Wake-up command from Host to WLAN */
  72
  73 /* Bit mask for SPID_RESPONSE_DELAY device register */
  74 #define RESPONSE_DELAY_MASK     0xFF    /* Configurable rd response delay in multiples of 8 bits */
  75
  76 /* Bit mask for SPID_STATUS_ENABLE device register */
  77 #define STATUS_ENABLE           0x1     /* 1/0 Status sent/not sent to host after read/write */
  78 #define INTR_WITH_STATUS        0x2     /* 0/1 Do-not / do-interrupt if status is sent */
  79 #define RESP_DELAY_ALL          0x4     /* Applicability of resp delay to F1 or all func's read */
  80 #define DWORD_PKT_LEN_EN        0x8     /* Packet len denoted in dwords instead of bytes */
  81 #define CMD_ERR_CHK_EN          0x20    /* Command error check enable */
  82 #define DATA_ERR_CHK_EN         0x40    /* Data error check enable */
  83
  84 /* Bit mask for SPID_RESET_BP device register */
  85 #define RESET_ON_WLAN_BP_RESET  0x4     /* enable reset for WLAN backplane */
  86 #define RESET_ON_BT_BP_RESET    0x8     /* enable reset for BT backplane */
  87 #define RESET_SPI               0x80    /* reset the above enabled logic */
  88
  89 /* Bit mask for SPID_INTR_REG device register */
  90 #define DATA_UNAVAILABLE        0x0001  /* Requested data not available; Clear by writing a "1" */
  91 #define F2_F3_FIFO_RD_UNDERFLOW 0x0002
  92 #define F2_F3_FIFO_WR_OVERFLOW  0x0004
  93 #define COMMAND_ERROR           0x0008  /* Cleared by writing 1 */
  94 #define DATA_ERROR              0x0010  /* Cleared by writing 1 */
  95 #define F2_PACKET_AVAILABLE     0x0020
  96 #define F3_PACKET_AVAILABLE     0x0040
  97 #define F1_OVERFLOW             0x0080  /* Due to last write. Bkplane has pending write requests */
  98 #define MISC_INTR0              0x0100
  99 #define MISC_INTR1              0x0200
 100 #define MISC_INTR2              0x0400
 101 #define MISC_INTR3              0x0800
 102 #define MISC_INTR4              0x1000
 103 #define F1_INTR                 0x2000
 104 #define F2_INTR                 0x4000
 105 #define F3_INTR                 0x8000
 106
 107 /* Bit mask for 32bit SPID_STATUS_REG device register */
 108 #define STATUS_DATA_NOT_AVAILABLE       0x00000001
 109 #define STATUS_UNDERFLOW                0x00000002
 110 #define STATUS_OVERFLOW                 0x00000004
 111 #define STATUS_F2_INTR                  0x00000008
 112 #define STATUS_F3_INTR                  0x00000010
 113 #define STATUS_F2_RX_READY              0x00000020
 114 #define STATUS_F3_RX_READY              0x00000040
 115 #define STATUS_HOST_CMD_DATA_ERR        0x00000080
 116 #define STATUS_F2_PKT_AVAILABLE         0x00000100
 117 #define STATUS_F2_PKT_LEN_MASK          0x000FFE00
 118 #define STATUS_F2_PKT_LEN_SHIFT         9
 119 #define STATUS_F3_PKT_AVAILABLE         0x00100000
 120 #define STATUS_F3_PKT_LEN_MASK          0xFFE00000
 121 #define STATUS_F3_PKT_LEN_SHIFT         21
 122
 123 /* Bit mask for 16 bits SPID_F1_INFO_REG device register */
 124 #define F1_ENABLED                      0x0001
 125 #define F1_RDY_FOR_DATA_TRANSFER        0x0002
 126 #define F1_MAX_PKT_SIZE                 0x01FC
 127
 128 /* Bit mask for 16 bits SPID_F2_INFO_REG device register */
 129 #define F2_ENABLED                      0x0001
 130 #define F2_RDY_FOR_DATA_TRANSFER        0x0002
 131 #define F2_MAX_PKT_SIZE                 0x3FFC
 132
 133 /* Bit mask for 16 bits SPID_F3_INFO_REG device register */
 134 #define F3_ENABLED                      0x0001
 135 #define F3_RDY_FOR_DATA_TRANSFER        0x0002
 136 #define F3_MAX_PKT_SIZE                 0x3FFC
 137
 138 /* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */
 139 #define TEST_RO_DATA_32BIT_LE           0xFEEDBEAD
 140
 141 /* Maximum number of I/O funcs */
 142 #define SPI_MAX_IOFUNCS         4
 143
 144 #define SPI_MAX_PKT_LEN         (2048*4)
 145
 146 /* Misc defines */
 147 #define SPI_FUNC_0              0
 148 #define SPI_FUNC_1              1
 149 #define SPI_FUNC_2              2
 150 #define SPI_FUNC_3              3
 151
 152 #define WAIT_F2RXFIFORDY        100
 153 #define WAIT_F2RXFIFORDY_DELAY  20
 154
 155 #endif                          /* _SPI_H */