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drm/radeon/kms: DCE5 atom transmitter control updates
[linux-2.6/libata-dev.git] / drivers / gpu / drm / radeon / radeon_encoders.c
blob76835b0397ab6574d04aebb36e45a007a6e90310
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40 struct drm_device *dev = encoder->dev;
41 struct radeon_device *rdev = dev->dev_private;
42 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43 struct drm_encoder *clone_encoder;
44 uint32_t index_mask = 0;
45 int count;
46
47 /* DIG routing gets problematic */
48 if (rdev->family >= CHIP_R600)
49 return index_mask;
50 /* LVDS/TV are too wacky */
51 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52 return index_mask;
53 /* DVO requires 2x ppll clocks depending on tmds chip */
54 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55 return index_mask;
56
57 count = -1;
58 list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60 count++;
61
62 if (clone_encoder == encoder)
63 continue;
64 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65 continue;
66 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67 continue;
68 else
69 index_mask |= (1 << count);
70 }
71 return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76 struct drm_encoder *encoder;
77
78 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79 encoder->possible_clones = radeon_encoder_clones(encoder);
80 }
81 }
82
83 uint32_t
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86 struct radeon_device *rdev = dev->dev_private;
87 uint32_t ret = 0;
88
89 switch (supported_device) {
90 case ATOM_DEVICE_CRT1_SUPPORT:
91 case ATOM_DEVICE_TV1_SUPPORT:
92 case ATOM_DEVICE_TV2_SUPPORT:
93 case ATOM_DEVICE_CRT2_SUPPORT:
94 case ATOM_DEVICE_CV_SUPPORT:
95 switch (dac) {
96 case 1: /* dac a */
97 if ((rdev->family == CHIP_RS300) ||
98 (rdev->family == CHIP_RS400) ||
99 (rdev->family == CHIP_RS480))
100 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101 else if (ASIC_IS_AVIVO(rdev))
102 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103 else
104 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105 break;
106 case 2: /* dac b */
107 if (ASIC_IS_AVIVO(rdev))
108 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109 else {
110 /*if (rdev->family == CHIP_R200)
111 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112 else*/
113 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114 }
115 break;
116 case 3: /* external dac */
117 if (ASIC_IS_AVIVO(rdev))
118 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119 else
120 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121 break;
122 }
123 break;
124 case ATOM_DEVICE_LCD1_SUPPORT:
125 if (ASIC_IS_AVIVO(rdev))
126 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127 else
128 ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129 break;
130 case ATOM_DEVICE_DFP1_SUPPORT:
131 if ((rdev->family == CHIP_RS300) ||
132 (rdev->family == CHIP_RS400) ||
133 (rdev->family == CHIP_RS480))
134 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135 else if (ASIC_IS_AVIVO(rdev))
136 ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137 else
138 ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139 break;
140 case ATOM_DEVICE_LCD2_SUPPORT:
141 case ATOM_DEVICE_DFP2_SUPPORT:
142 if ((rdev->family == CHIP_RS600) ||
143 (rdev->family == CHIP_RS690) ||
144 (rdev->family == CHIP_RS740))
145 ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146 else if (ASIC_IS_AVIVO(rdev))
147 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148 else
149 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150 break;
151 case ATOM_DEVICE_DFP3_SUPPORT:
152 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153 break;
154 }
155
156 return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162 switch (radeon_encoder->encoder_id) {
163 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169 case ENCODER_OBJECT_ID_INTERNAL_DDI:
170 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174 return true;
175 default:
176 return false;
177 }
178 }
179
180 void
181 radeon_link_encoder_connector(struct drm_device *dev)
182 {
183 struct drm_connector *connector;
184 struct radeon_connector *radeon_connector;
185 struct drm_encoder *encoder;
186 struct radeon_encoder *radeon_encoder;
187
188 /* walk the list and link encoders to connectors */
189 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190 radeon_connector = to_radeon_connector(connector);
191 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192 radeon_encoder = to_radeon_encoder(encoder);
193 if (radeon_encoder->devices & radeon_connector->devices)
194 drm_mode_connector_attach_encoder(connector, encoder);
195 }
196 }
197 }
198
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 {
201 struct drm_device *dev = encoder->dev;
202 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203 struct drm_connector *connector;
204
205 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206 if (connector->encoder == encoder) {
207 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208 radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209 DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210 radeon_encoder->active_device, radeon_encoder->devices,
211 radeon_connector->devices, encoder->encoder_type);
212 }
213 }
214 }
215
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 {
219 struct drm_device *dev = encoder->dev;
220 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221 struct drm_connector *connector;
222 struct radeon_connector *radeon_connector;
223
224 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225 radeon_connector = to_radeon_connector(connector);
226 if (radeon_encoder->active_device & radeon_connector->devices)
227 return connector;
228 }
229 return NULL;
230 }
231
232 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
233 {
234 struct drm_device *dev = encoder->dev;
235 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
236 struct drm_encoder *other_encoder;
237 struct radeon_encoder *other_radeon_encoder;
238
239 if (radeon_encoder->is_ext_encoder)
240 return NULL;
241
242 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
243 if (other_encoder == encoder)
244 continue;
245 other_radeon_encoder = to_radeon_encoder(other_encoder);
246 if (other_radeon_encoder->is_ext_encoder &&
247 (radeon_encoder->devices & other_radeon_encoder->devices))
248 return other_encoder;
249 }
250 return NULL;
251 }
252
253 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
254 struct drm_display_mode *adjusted_mode)
255 {
256 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
257 struct drm_device *dev = encoder->dev;
258 struct radeon_device *rdev = dev->dev_private;
259 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
260 unsigned hblank = native_mode->htotal - native_mode->hdisplay;
261 unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
262 unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
263 unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
264 unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
265 unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
266
267 adjusted_mode->clock = native_mode->clock;
268 adjusted_mode->flags = native_mode->flags;
269
270 if (ASIC_IS_AVIVO(rdev)) {
271 adjusted_mode->hdisplay = native_mode->hdisplay;
272 adjusted_mode->vdisplay = native_mode->vdisplay;
273 }
274
275 adjusted_mode->htotal = native_mode->hdisplay + hblank;
276 adjusted_mode->hsync_start = native_mode->hdisplay + hover;
277 adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
278
279 adjusted_mode->vtotal = native_mode->vdisplay + vblank;
280 adjusted_mode->vsync_start = native_mode->vdisplay + vover;
281 adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
282
283 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
284
285 if (ASIC_IS_AVIVO(rdev)) {
286 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
287 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
288 }
289
290 adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
291 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
292 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
293
294 adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
295 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
296 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
297
298 }
299
300 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
301 struct drm_display_mode *mode,
302 struct drm_display_mode *adjusted_mode)
303 {
304 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
305 struct drm_device *dev = encoder->dev;
306 struct radeon_device *rdev = dev->dev_private;
307
308 /* set the active encoder to connector routing */
309 radeon_encoder_set_active_device(encoder);
310 drm_mode_set_crtcinfo(adjusted_mode, 0);
311
312 /* hw bug */
313 if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
314 && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
315 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
316
317 /* get the native mode for LVDS */
318 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
319 radeon_panel_mode_fixup(encoder, adjusted_mode);
320
321 /* get the native mode for TV */
322 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
323 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
324 if (tv_dac) {
325 if (tv_dac->tv_std == TV_STD_NTSC ||
326 tv_dac->tv_std == TV_STD_NTSC_J ||
327 tv_dac->tv_std == TV_STD_PAL_M)
328 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
329 else
330 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
331 }
332 }
333
334 if (ASIC_IS_DCE3(rdev) &&
335 (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
336 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
337 radeon_dp_set_link_config(connector, mode);
338 }
339
340 return true;
341 }
342
343 static void
344 atombios_dac_setup(struct drm_encoder *encoder, int action)
345 {
346 struct drm_device *dev = encoder->dev;
347 struct radeon_device *rdev = dev->dev_private;
348 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
349 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
350 int index = 0;
351 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
352
353 memset(&args, 0, sizeof(args));
354
355 switch (radeon_encoder->encoder_id) {
356 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
357 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
358 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
359 break;
360 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
361 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
362 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
363 break;
364 }
365
366 args.ucAction = action;
367
368 if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
369 args.ucDacStandard = ATOM_DAC1_PS2;
370 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
371 args.ucDacStandard = ATOM_DAC1_CV;
372 else {
373 switch (dac_info->tv_std) {
374 case TV_STD_PAL:
375 case TV_STD_PAL_M:
376 case TV_STD_SCART_PAL:
377 case TV_STD_SECAM:
378 case TV_STD_PAL_CN:
379 args.ucDacStandard = ATOM_DAC1_PAL;
380 break;
381 case TV_STD_NTSC:
382 case TV_STD_NTSC_J:
383 case TV_STD_PAL_60:
384 default:
385 args.ucDacStandard = ATOM_DAC1_NTSC;
386 break;
387 }
388 }
389 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
390
391 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
392
393 }
394
395 static void
396 atombios_tv_setup(struct drm_encoder *encoder, int action)
397 {
398 struct drm_device *dev = encoder->dev;
399 struct radeon_device *rdev = dev->dev_private;
400 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
401 TV_ENCODER_CONTROL_PS_ALLOCATION args;
402 int index = 0;
403 struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
404
405 memset(&args, 0, sizeof(args));
406
407 index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
408
409 args.sTVEncoder.ucAction = action;
410
411 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
412 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
413 else {
414 switch (dac_info->tv_std) {
415 case TV_STD_NTSC:
416 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
417 break;
418 case TV_STD_PAL:
419 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
420 break;
421 case TV_STD_PAL_M:
422 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
423 break;
424 case TV_STD_PAL_60:
425 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
426 break;
427 case TV_STD_NTSC_J:
428 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
429 break;
430 case TV_STD_SCART_PAL:
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
432 break;
433 case TV_STD_SECAM:
434 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
435 break;
436 case TV_STD_PAL_CN:
437 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
438 break;
439 default:
440 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
441 break;
442 }
443 }
444
445 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
446
447 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
448
449 }
450
451 union dvo_encoder_control {
452 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
453 DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
454 DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
455 };
456
457 void
458 atombios_dvo_setup(struct drm_encoder *encoder, int action)
459 {
460 struct drm_device *dev = encoder->dev;
461 struct radeon_device *rdev = dev->dev_private;
462 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
463 union dvo_encoder_control args;
464 int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
465
466 memset(&args, 0, sizeof(args));
467
468 if (ASIC_IS_DCE3(rdev)) {
469 /* DCE3+ */
470 args.dvo_v3.ucAction = action;
471 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
472 args.dvo_v3.ucDVOConfig = 0; /* XXX */
473 } else if (ASIC_IS_DCE2(rdev)) {
474 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
475 args.dvo.sDVOEncoder.ucAction = action;
476 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
477 /* DFP1, CRT1, TV1 depending on the type of port */
478 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
479
480 if (radeon_encoder->pixel_clock > 165000)
481 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
482 } else {
483 /* R4xx, R5xx */
484 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
485
486 if (radeon_encoder->pixel_clock > 165000)
487 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
488
489 /*if (pScrn->rgbBits == 8)*/
490 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
491 }
492
493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
494 }
495
496 union lvds_encoder_control {
497 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1;
498 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
499 };
500
501 void
502 atombios_digital_setup(struct drm_encoder *encoder, int action)
503 {
504 struct drm_device *dev = encoder->dev;
505 struct radeon_device *rdev = dev->dev_private;
506 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
507 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
508 union lvds_encoder_control args;
509 int index = 0;
510 int hdmi_detected = 0;
511 uint8_t frev, crev;
512
513 if (!dig)
514 return;
515
516 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
517 hdmi_detected = 1;
518
519 memset(&args, 0, sizeof(args));
520
521 switch (radeon_encoder->encoder_id) {
522 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
523 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
524 break;
525 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
526 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
527 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
528 break;
529 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
530 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
531 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
532 else
533 index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
534 break;
535 }
536
537 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
538 return;
539
540 switch (frev) {
541 case 1:
542 case 2:
543 switch (crev) {
544 case 1:
545 args.v1.ucMisc = 0;
546 args.v1.ucAction = action;
547 if (hdmi_detected)
548 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
549 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
550 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
551 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
552 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
553 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
554 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
555 } else {
556 if (dig->linkb)
557 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
558 if (radeon_encoder->pixel_clock > 165000)
559 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
560 /*if (pScrn->rgbBits == 8) */
561 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
562 }
563 break;
564 case 2:
565 case 3:
566 args.v2.ucMisc = 0;
567 args.v2.ucAction = action;
568 if (crev == 3) {
569 if (dig->coherent_mode)
570 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
571 }
572 if (hdmi_detected)
573 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
574 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
575 args.v2.ucTruncate = 0;
576 args.v2.ucSpatial = 0;
577 args.v2.ucTemporal = 0;
578 args.v2.ucFRC = 0;
579 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
580 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
581 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
582 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
583 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
584 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
585 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
586 }
587 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
588 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
589 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
590 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
591 if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
592 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
593 }
594 } else {
595 if (dig->linkb)
596 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
597 if (radeon_encoder->pixel_clock > 165000)
598 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
599 }
600 break;
601 default:
602 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
603 break;
604 }
605 break;
606 default:
607 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
608 break;
609 }
610
611 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
612 }
613
614 int
615 atombios_get_encoder_mode(struct drm_encoder *encoder)
616 {
617 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
618 struct drm_device *dev = encoder->dev;
619 struct radeon_device *rdev = dev->dev_private;
620 struct drm_connector *connector;
621 struct radeon_connector *radeon_connector;
622 struct radeon_connector_atom_dig *dig_connector;
623
624 connector = radeon_get_connector_for_encoder(encoder);
625 if (!connector) {
626 switch (radeon_encoder->encoder_id) {
627 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
628 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
629 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
630 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
631 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
632 return ATOM_ENCODER_MODE_DVI;
633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
634 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
635 default:
636 return ATOM_ENCODER_MODE_CRT;
637 }
638 }
639 radeon_connector = to_radeon_connector(connector);
640
641 switch (connector->connector_type) {
642 case DRM_MODE_CONNECTOR_DVII:
643 case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
644 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
645 /* fix me */
646 if (ASIC_IS_DCE4(rdev))
647 return ATOM_ENCODER_MODE_DVI;
648 else
649 return ATOM_ENCODER_MODE_HDMI;
650 } else if (radeon_connector->use_digital)
651 return ATOM_ENCODER_MODE_DVI;
652 else
653 return ATOM_ENCODER_MODE_CRT;
654 break;
655 case DRM_MODE_CONNECTOR_DVID:
656 case DRM_MODE_CONNECTOR_HDMIA:
657 default:
658 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
659 /* fix me */
660 if (ASIC_IS_DCE4(rdev))
661 return ATOM_ENCODER_MODE_DVI;
662 else
663 return ATOM_ENCODER_MODE_HDMI;
664 } else
665 return ATOM_ENCODER_MODE_DVI;
666 break;
667 case DRM_MODE_CONNECTOR_LVDS:
668 return ATOM_ENCODER_MODE_LVDS;
669 break;
670 case DRM_MODE_CONNECTOR_DisplayPort:
671 case DRM_MODE_CONNECTOR_eDP:
672 dig_connector = radeon_connector->con_priv;
673 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
674 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
675 return ATOM_ENCODER_MODE_DP;
676 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
677 /* fix me */
678 if (ASIC_IS_DCE4(rdev))
679 return ATOM_ENCODER_MODE_DVI;
680 else
681 return ATOM_ENCODER_MODE_HDMI;
682 } else
683 return ATOM_ENCODER_MODE_DVI;
684 break;
685 case DRM_MODE_CONNECTOR_DVIA:
686 case DRM_MODE_CONNECTOR_VGA:
687 return ATOM_ENCODER_MODE_CRT;
688 break;
689 case DRM_MODE_CONNECTOR_Composite:
690 case DRM_MODE_CONNECTOR_SVIDEO:
691 case DRM_MODE_CONNECTOR_9PinDIN:
692 /* fix me */
693 return ATOM_ENCODER_MODE_TV;
694 /*return ATOM_ENCODER_MODE_CV;*/
695 break;
696 }
697 }
698
699 /*
700 * DIG Encoder/Transmitter Setup
701 *
702 * DCE 3.0/3.1
703 * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
704 * Supports up to 3 digital outputs
705 * - 2 DIG encoder blocks.
706 * DIG1 can drive UNIPHY link A or link B
707 * DIG2 can drive UNIPHY link B or LVTMA
708 *
709 * DCE 3.2
710 * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
711 * Supports up to 5 digital outputs
712 * - 2 DIG encoder blocks.
713 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
714 *
715 * DCE 4.0/5.0
716 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
717 * Supports up to 6 digital outputs
718 * - 6 DIG encoder blocks.
719 * - DIG to PHY mapping is hardcoded
720 * DIG1 drives UNIPHY0 link A, A+B
721 * DIG2 drives UNIPHY0 link B
722 * DIG3 drives UNIPHY1 link A, A+B
723 * DIG4 drives UNIPHY1 link B
724 * DIG5 drives UNIPHY2 link A, A+B
725 * DIG6 drives UNIPHY2 link B
726 *
727 * DCE 4.1
728 * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
729 * Supports up to 6 digital outputs
730 * - 2 DIG encoder blocks.
731 * DIG1/2 can drive UNIPHY0/1/2 link A or link B
732 *
733 * Routing
734 * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
735 * Examples:
736 * crtc0 -> dig2 -> LVTMA links A+B -> TMDS/HDMI
737 * crtc1 -> dig1 -> UNIPHY0 link B -> DP
738 * crtc0 -> dig1 -> UNIPHY2 link A -> LVDS
739 * crtc1 -> dig2 -> UNIPHY1 link B+A -> TMDS/HDMI
740 */
741
742 union dig_encoder_control {
743 DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
744 DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
745 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
746 };
747
748 void
749 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
750 {
751 struct drm_device *dev = encoder->dev;
752 struct radeon_device *rdev = dev->dev_private;
753 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
754 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
755 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
756 union dig_encoder_control args;
757 int index = 0;
758 uint8_t frev, crev;
759 int dp_clock = 0;
760 int dp_lane_count = 0;
761
762 if (connector) {
763 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
764 struct radeon_connector_atom_dig *dig_connector =
765 radeon_connector->con_priv;
766
767 dp_clock = dig_connector->dp_clock;
768 dp_lane_count = dig_connector->dp_lane_count;
769 }
770
771 /* no dig encoder assigned */
772 if (dig->dig_encoder == -1)
773 return;
774
775 memset(&args, 0, sizeof(args));
776
777 if (ASIC_IS_DCE4(rdev))
778 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
779 else {
780 if (dig->dig_encoder)
781 index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
782 else
783 index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
784 }
785
786 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
787 return;
788
789 args.v1.ucAction = action;
790 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
791 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
792
793 if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
794 if (dp_clock == 270000)
795 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
796 args.v1.ucLaneNum = dp_lane_count;
797 } else if (radeon_encoder->pixel_clock > 165000)
798 args.v1.ucLaneNum = 8;
799 else
800 args.v1.ucLaneNum = 4;
801
802 if (ASIC_IS_DCE4(rdev)) {
803 args.v3.acConfig.ucDigSel = dig->dig_encoder;
804 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
805 } else {
806 switch (radeon_encoder->encoder_id) {
807 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
808 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
809 break;
810 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
811 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
812 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
813 break;
814 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
815 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
816 break;
817 }
818 if (dig->linkb)
819 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
820 else
821 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
822 }
823
824 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
825
826 }
827
828 union dig_transmitter_control {
829 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
830 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
831 DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
832 DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
833 };
834
835 void
836 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
837 {
838 struct drm_device *dev = encoder->dev;
839 struct radeon_device *rdev = dev->dev_private;
840 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
841 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
842 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
843 union dig_transmitter_control args;
844 int index = 0;
845 uint8_t frev, crev;
846 bool is_dp = false;
847 int pll_id = 0;
848 int dp_clock = 0;
849 int dp_lane_count = 0;
850 int connector_object_id = 0;
851 int igp_lane_info = 0;
852
853 if (connector) {
854 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
855 struct radeon_connector_atom_dig *dig_connector =
856 radeon_connector->con_priv;
857
858 dp_clock = dig_connector->dp_clock;
859 dp_lane_count = dig_connector->dp_lane_count;
860 connector_object_id =
861 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
862 igp_lane_info = dig_connector->igp_lane_info;
863 }
864
865 /* no dig encoder assigned */
866 if (dig->dig_encoder == -1)
867 return;
868
869 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
870 is_dp = true;
871
872 memset(&args, 0, sizeof(args));
873
874 switch (radeon_encoder->encoder_id) {
875 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
876 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
877 break;
878 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
879 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
880 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
881 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
882 break;
883 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
884 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
885 break;
886 }
887
888 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
889 return;
890
891 args.v1.ucAction = action;
892 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
893 args.v1.usInitInfo = connector_object_id;
894 } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
895 args.v1.asMode.ucLaneSel = lane_num;
896 args.v1.asMode.ucLaneSet = lane_set;
897 } else {
898 if (is_dp)
899 args.v1.usPixelClock =
900 cpu_to_le16(dp_clock / 10);
901 else if (radeon_encoder->pixel_clock > 165000)
902 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
903 else
904 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
905 }
906 if (ASIC_IS_DCE4(rdev)) {
907 if (is_dp)
908 args.v3.ucLaneNum = dp_lane_count;
909 else if (radeon_encoder->pixel_clock > 165000)
910 args.v3.ucLaneNum = 8;
911 else
912 args.v3.ucLaneNum = 4;
913
914 if (dig->linkb) {
915 args.v3.acConfig.ucLinkSel = 1;
916 args.v3.acConfig.ucEncoderSel = 1;
917 }
918
919 /* Select the PLL for the PHY
920 * DP PHY should be clocked from external src if there is
921 * one.
922 */
923 if (encoder->crtc) {
924 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
925 pll_id = radeon_crtc->pll_id;
926 }
927
928 if (ASIC_IS_DCE5(rdev)) {
929 if (is_dp && rdev->clock.dp_extclk)
930 args.v4.acConfig.ucRefClkSource = 3; /* external src */
931 else
932 args.v4.acConfig.ucRefClkSource = pll_id;
933 } else {
934 if (is_dp && rdev->clock.dp_extclk)
935 args.v3.acConfig.ucRefClkSource = 2; /* external src */
936 else
937 args.v3.acConfig.ucRefClkSource = pll_id;
938 }
939
940 switch (radeon_encoder->encoder_id) {
941 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
942 args.v3.acConfig.ucTransmitterSel = 0;
943 break;
944 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
945 args.v3.acConfig.ucTransmitterSel = 1;
946 break;
947 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
948 args.v3.acConfig.ucTransmitterSel = 2;
949 break;
950 }
951
952 if (is_dp)
953 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
954 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
955 if (dig->coherent_mode)
956 args.v3.acConfig.fCoherentMode = 1;
957 if (radeon_encoder->pixel_clock > 165000)
958 args.v3.acConfig.fDualLinkConnector = 1;
959 }
960 } else if (ASIC_IS_DCE32(rdev)) {
961 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
962 if (dig->linkb)
963 args.v2.acConfig.ucLinkSel = 1;
964
965 switch (radeon_encoder->encoder_id) {
966 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
967 args.v2.acConfig.ucTransmitterSel = 0;
968 break;
969 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
970 args.v2.acConfig.ucTransmitterSel = 1;
971 break;
972 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
973 args.v2.acConfig.ucTransmitterSel = 2;
974 break;
975 }
976
977 if (is_dp)
978 args.v2.acConfig.fCoherentMode = 1;
979 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
980 if (dig->coherent_mode)
981 args.v2.acConfig.fCoherentMode = 1;
982 if (radeon_encoder->pixel_clock > 165000)
983 args.v2.acConfig.fDualLinkConnector = 1;
984 }
985 } else {
986 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
987
988 if (dig->dig_encoder)
989 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
990 else
991 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
992
993 if ((rdev->flags & RADEON_IS_IGP) &&
994 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
995 if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
996 if (igp_lane_info & 0x1)
997 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
998 else if (igp_lane_info & 0x2)
999 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1000 else if (igp_lane_info & 0x4)
1001 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1002 else if (igp_lane_info & 0x8)
1003 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1004 } else {
1005 if (igp_lane_info & 0x3)
1006 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1007 else if (igp_lane_info & 0xc)
1008 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1009 }
1010 }
1011
1012 if (dig->linkb)
1013 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1014 else
1015 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1016
1017 if (is_dp)
1018 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1019 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1020 if (dig->coherent_mode)
1021 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1022 if (radeon_encoder->pixel_clock > 165000)
1023 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1024 }
1025 }
1026
1027 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1028 }
1029
1030 void
1031 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1032 {
1033 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1034 struct drm_device *dev = radeon_connector->base.dev;
1035 struct radeon_device *rdev = dev->dev_private;
1036 union dig_transmitter_control args;
1037 int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1038 uint8_t frev, crev;
1039
1040 if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1041 return;
1042
1043 if (!ASIC_IS_DCE4(rdev))
1044 return;
1045
1046 if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) ||
1047 (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1048 return;
1049
1050 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1051 return;
1052
1053 memset(&args, 0, sizeof(args));
1054
1055 args.v1.ucAction = action;
1056
1057 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1058 }
1059
1060 union external_encoder_control {
1061 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1062 EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1063 };
1064
1065 static void
1066 atombios_external_encoder_setup(struct drm_encoder *encoder,
1067 struct drm_encoder *ext_encoder,
1068 int action)
1069 {
1070 struct drm_device *dev = encoder->dev;
1071 struct radeon_device *rdev = dev->dev_private;
1072 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1073 struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1074 union external_encoder_control args;
1075 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1076 int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1077 u8 frev, crev;
1078 int dp_clock = 0;
1079 int dp_lane_count = 0;
1080 int connector_object_id = 0;
1081 u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1082
1083 if (connector) {
1084 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1085 struct radeon_connector_atom_dig *dig_connector =
1086 radeon_connector->con_priv;
1087
1088 dp_clock = dig_connector->dp_clock;
1089 dp_lane_count = dig_connector->dp_lane_count;
1090 connector_object_id =
1091 (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1092 }
1093
1094 memset(&args, 0, sizeof(args));
1095
1096 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1097 return;
1098
1099 switch (frev) {
1100 case 1:
1101 /* no params on frev 1 */
1102 break;
1103 case 2:
1104 switch (crev) {
1105 case 1:
1106 case 2:
1107 args.v1.sDigEncoder.ucAction = action;
1108 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1109 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1110
1111 if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1112 if (dp_clock == 270000)
1113 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1114 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1115 } else if (radeon_encoder->pixel_clock > 165000)
1116 args.v1.sDigEncoder.ucLaneNum = 8;
1117 else
1118 args.v1.sDigEncoder.ucLaneNum = 4;
1119 break;
1120 case 3:
1121 args.v3.sExtEncoder.ucAction = action;
1122 if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1123 args.v3.sExtEncoder.usConnectorId = connector_object_id;
1124 else
1125 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1126 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1127
1128 if (args.v3.sExtEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1129 if (dp_clock == 270000)
1130 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1131 else if (dp_clock == 540000)
1132 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1133 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1134 } else if (radeon_encoder->pixel_clock > 165000)
1135 args.v3.sExtEncoder.ucLaneNum = 8;
1136 else
1137 args.v3.sExtEncoder.ucLaneNum = 4;
1138 switch (ext_enum) {
1139 case GRAPH_OBJECT_ENUM_ID1:
1140 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1141 break;
1142 case GRAPH_OBJECT_ENUM_ID2:
1143 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1144 break;
1145 case GRAPH_OBJECT_ENUM_ID3:
1146 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1147 break;
1148 }
1149 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1150 break;
1151 default:
1152 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1153 return;
1154 }
1155 break;
1156 default:
1157 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1158 return;
1159 }
1160 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1161 }
1162
1163 static void
1164 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1165 {
1166 struct drm_device *dev = encoder->dev;
1167 struct radeon_device *rdev = dev->dev_private;
1168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1169 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1170 ENABLE_YUV_PS_ALLOCATION args;
1171 int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1172 uint32_t temp, reg;
1173
1174 memset(&args, 0, sizeof(args));
1175
1176 if (rdev->family >= CHIP_R600)
1177 reg = R600_BIOS_3_SCRATCH;
1178 else
1179 reg = RADEON_BIOS_3_SCRATCH;
1180
1181 /* XXX: fix up scratch reg handling */
1182 temp = RREG32(reg);
1183 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1184 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1185 (radeon_crtc->crtc_id << 18)));
1186 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1187 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1188 else
1189 WREG32(reg, 0);
1190
1191 if (enable)
1192 args.ucEnable = ATOM_ENABLE;
1193 args.ucCRTC = radeon_crtc->crtc_id;
1194
1195 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1196
1197 WREG32(reg, temp);
1198 }
1199
1200 static void
1201 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1202 {
1203 struct drm_device *dev = encoder->dev;
1204 struct radeon_device *rdev = dev->dev_private;
1205 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1206 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1207 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1208 int index = 0;
1209 bool is_dig = false;
1210
1211 memset(&args, 0, sizeof(args));
1212
1213 DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1214 radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1215 radeon_encoder->active_device);
1216 switch (radeon_encoder->encoder_id) {
1217 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1218 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1219 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1220 break;
1221 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1222 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1223 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1224 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1225 is_dig = true;
1226 break;
1227 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1228 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1229 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1230 break;
1231 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1232 if (ASIC_IS_DCE3(rdev))
1233 is_dig = true;
1234 else
1235 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1236 break;
1237 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1238 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1239 break;
1240 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1241 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1242 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1243 else
1244 index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1245 break;
1246 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1247 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1248 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1249 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1250 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1251 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1252 else
1253 index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1254 break;
1255 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1256 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1257 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1258 index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1259 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1260 index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1261 else
1262 index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1263 break;
1264 }
1265
1266 if (is_dig) {
1267 switch (mode) {
1268 case DRM_MODE_DPMS_ON:
1269 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1270 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1271 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1272
1273 if (connector &&
1274 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1275 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1276 struct radeon_connector_atom_dig *radeon_dig_connector =
1277 radeon_connector->con_priv;
1278 atombios_set_edp_panel_power(connector,
1279 ATOM_TRANSMITTER_ACTION_POWER_ON);
1280 radeon_dig_connector->edp_on = true;
1281 }
1282 dp_link_train(encoder, connector);
1283 if (ASIC_IS_DCE4(rdev))
1284 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1285 }
1286 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1287 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1288 break;
1289 case DRM_MODE_DPMS_STANDBY:
1290 case DRM_MODE_DPMS_SUSPEND:
1291 case DRM_MODE_DPMS_OFF:
1292 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1293 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1294 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1295
1296 if (ASIC_IS_DCE4(rdev))
1297 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1298 if (connector &&
1299 (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1300 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1301 struct radeon_connector_atom_dig *radeon_dig_connector =
1302 radeon_connector->con_priv;
1303 atombios_set_edp_panel_power(connector,
1304 ATOM_TRANSMITTER_ACTION_POWER_OFF);
1305 radeon_dig_connector->edp_on = false;
1306 }
1307 }
1308 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1309 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1310 break;
1311 }
1312 } else {
1313 switch (mode) {
1314 case DRM_MODE_DPMS_ON:
1315 args.ucAction = ATOM_ENABLE;
1316 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1317 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1318 args.ucAction = ATOM_LCD_BLON;
1319 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1320 }
1321 break;
1322 case DRM_MODE_DPMS_STANDBY:
1323 case DRM_MODE_DPMS_SUSPEND:
1324 case DRM_MODE_DPMS_OFF:
1325 args.ucAction = ATOM_DISABLE;
1326 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1327 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1328 args.ucAction = ATOM_LCD_BLOFF;
1329 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1330 }
1331 break;
1332 }
1333 }
1334
1335 if (ext_encoder) {
1336 int action;
1337
1338 switch (mode) {
1339 case DRM_MODE_DPMS_ON:
1340 default:
1341 if (ASIC_IS_DCE41(rdev))
1342 action = EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT;
1343 else
1344 action = ATOM_ENABLE;
1345 break;
1346 case DRM_MODE_DPMS_STANDBY:
1347 case DRM_MODE_DPMS_SUSPEND:
1348 case DRM_MODE_DPMS_OFF:
1349 if (ASIC_IS_DCE41(rdev))
1350 action = EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT;
1351 else
1352 action = ATOM_DISABLE;
1353 break;
1354 }
1355 atombios_external_encoder_setup(encoder, ext_encoder, action);
1356 }
1357
1358 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1359
1360 }
1361
1362 union crtc_source_param {
1363 SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1364 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1365 };
1366
1367 static void
1368 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1369 {
1370 struct drm_device *dev = encoder->dev;
1371 struct radeon_device *rdev = dev->dev_private;
1372 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1373 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1374 union crtc_source_param args;
1375 int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1376 uint8_t frev, crev;
1377 struct radeon_encoder_atom_dig *dig;
1378
1379 memset(&args, 0, sizeof(args));
1380
1381 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1382 return;
1383
1384 switch (frev) {
1385 case 1:
1386 switch (crev) {
1387 case 1:
1388 default:
1389 if (ASIC_IS_AVIVO(rdev))
1390 args.v1.ucCRTC = radeon_crtc->crtc_id;
1391 else {
1392 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1393 args.v1.ucCRTC = radeon_crtc->crtc_id;
1394 } else {
1395 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1396 }
1397 }
1398 switch (radeon_encoder->encoder_id) {
1399 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1400 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1401 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1402 break;
1403 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1404 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1405 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1406 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1407 else
1408 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1409 break;
1410 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1411 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1412 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1413 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1414 break;
1415 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1416 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1417 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1418 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1419 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1420 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1421 else
1422 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1423 break;
1424 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1425 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1426 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1427 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1428 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1429 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1430 else
1431 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1432 break;
1433 }
1434 break;
1435 case 2:
1436 args.v2.ucCRTC = radeon_crtc->crtc_id;
1437 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1438 switch (radeon_encoder->encoder_id) {
1439 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1440 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1441 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1442 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1443 dig = radeon_encoder->enc_priv;
1444 switch (dig->dig_encoder) {
1445 case 0:
1446 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1447 break;
1448 case 1:
1449 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1450 break;
1451 case 2:
1452 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1453 break;
1454 case 3:
1455 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1456 break;
1457 case 4:
1458 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1459 break;
1460 case 5:
1461 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1462 break;
1463 }
1464 break;
1465 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1466 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1467 break;
1468 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1469 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1470 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1471 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1472 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1473 else
1474 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1475 break;
1476 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1477 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1478 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1479 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1480 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1481 else
1482 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1483 break;
1484 }
1485 break;
1486 }
1487 break;
1488 default:
1489 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1490 return;
1491 }
1492
1493 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1494
1495 /* update scratch regs with new routing */
1496 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1497 }
1498
1499 static void
1500 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1501 struct drm_display_mode *mode)
1502 {
1503 struct drm_device *dev = encoder->dev;
1504 struct radeon_device *rdev = dev->dev_private;
1505 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1506 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1507
1508 /* Funky macbooks */
1509 if ((dev->pdev->device == 0x71C5) &&
1510 (dev->pdev->subsystem_vendor == 0x106b) &&
1511 (dev->pdev->subsystem_device == 0x0080)) {
1512 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1513 uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1514
1515 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1516 lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1517
1518 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1519 }
1520 }
1521
1522 /* set scaler clears this on some chips */
1523 /* XXX check DCE4 */
1524 if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1525 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1526 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1527 AVIVO_D1MODE_INTERLEAVE_EN);
1528 }
1529 }
1530
1531 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1532 {
1533 struct drm_device *dev = encoder->dev;
1534 struct radeon_device *rdev = dev->dev_private;
1535 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1536 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1537 struct drm_encoder *test_encoder;
1538 struct radeon_encoder_atom_dig *dig;
1539 uint32_t dig_enc_in_use = 0;
1540
1541 if (ASIC_IS_DCE4(rdev)) {
1542 dig = radeon_encoder->enc_priv;
1543 if (ASIC_IS_DCE41(rdev)) {
1544 if (dig->linkb)
1545 return 1;
1546 else
1547 return 0;
1548 } else {
1549 switch (radeon_encoder->encoder_id) {
1550 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1551 if (dig->linkb)
1552 return 1;
1553 else
1554 return 0;
1555 break;
1556 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1557 if (dig->linkb)
1558 return 3;
1559 else
1560 return 2;
1561 break;
1562 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1563 if (dig->linkb)
1564 return 5;
1565 else
1566 return 4;
1567 break;
1568 }
1569 }
1570 }
1571
1572 /* on DCE32 and encoder can driver any block so just crtc id */
1573 if (ASIC_IS_DCE32(rdev)) {
1574 return radeon_crtc->crtc_id;
1575 }
1576
1577 /* on DCE3 - LVTMA can only be driven by DIGB */
1578 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1579 struct radeon_encoder *radeon_test_encoder;
1580
1581 if (encoder == test_encoder)
1582 continue;
1583
1584 if (!radeon_encoder_is_digital(test_encoder))
1585 continue;
1586
1587 radeon_test_encoder = to_radeon_encoder(test_encoder);
1588 dig = radeon_test_encoder->enc_priv;
1589
1590 if (dig->dig_encoder >= 0)
1591 dig_enc_in_use |= (1 << dig->dig_encoder);
1592 }
1593
1594 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1595 if (dig_enc_in_use & 0x2)
1596 DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1597 return 1;
1598 }
1599 if (!(dig_enc_in_use & 1))
1600 return 0;
1601 return 1;
1602 }
1603
1604 static void
1605 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1606 struct drm_display_mode *mode,
1607 struct drm_display_mode *adjusted_mode)
1608 {
1609 struct drm_device *dev = encoder->dev;
1610 struct radeon_device *rdev = dev->dev_private;
1611 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1612 struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1613
1614 radeon_encoder->pixel_clock = adjusted_mode->clock;
1615
1616 if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1617 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1618 atombios_yuv_setup(encoder, true);
1619 else
1620 atombios_yuv_setup(encoder, false);
1621 }
1622
1623 switch (radeon_encoder->encoder_id) {
1624 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1625 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1626 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1627 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1628 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1629 break;
1630 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1631 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1633 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1634 if (ASIC_IS_DCE4(rdev)) {
1635 /* disable the transmitter */
1636 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1637 /* setup and enable the encoder */
1638 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1639
1640 /* init and enable the transmitter */
1641 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1642 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1643 } else {
1644 /* disable the encoder and transmitter */
1645 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1646 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1647
1648 /* setup and enable the encoder and transmitter */
1649 atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1650 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1651 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1652 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1653 }
1654 break;
1655 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1656 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1657 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1658 atombios_dvo_setup(encoder, ATOM_ENABLE);
1659 break;
1660 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1661 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1662 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1663 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1664 atombios_dac_setup(encoder, ATOM_ENABLE);
1665 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1666 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1667 atombios_tv_setup(encoder, ATOM_ENABLE);
1668 else
1669 atombios_tv_setup(encoder, ATOM_DISABLE);
1670 }
1671 break;
1672 }
1673
1674 if (ext_encoder) {
1675 if (ASIC_IS_DCE41(rdev)) {
1676 atombios_external_encoder_setup(encoder, ext_encoder,
1677 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1678 atombios_external_encoder_setup(encoder, ext_encoder,
1679 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1680 } else
1681 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1682 }
1683
1684 atombios_apply_encoder_quirks(encoder, adjusted_mode);
1685
1686 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1687 r600_hdmi_enable(encoder);
1688 r600_hdmi_setmode(encoder, adjusted_mode);
1689 }
1690 }
1691
1692 static bool
1693 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1694 {
1695 struct drm_device *dev = encoder->dev;
1696 struct radeon_device *rdev = dev->dev_private;
1697 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1698 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1699
1700 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1701 ATOM_DEVICE_CV_SUPPORT |
1702 ATOM_DEVICE_CRT_SUPPORT)) {
1703 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1704 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1705 uint8_t frev, crev;
1706
1707 memset(&args, 0, sizeof(args));
1708
1709 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1710 return false;
1711
1712 args.sDacload.ucMisc = 0;
1713
1714 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1715 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1716 args.sDacload.ucDacType = ATOM_DAC_A;
1717 else
1718 args.sDacload.ucDacType = ATOM_DAC_B;
1719
1720 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1721 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1722 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1723 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1724 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1725 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1726 if (crev >= 3)
1727 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1728 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1729 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1730 if (crev >= 3)
1731 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1732 }
1733
1734 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1735
1736 return true;
1737 } else
1738 return false;
1739 }
1740
1741 static enum drm_connector_status
1742 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1743 {
1744 struct drm_device *dev = encoder->dev;
1745 struct radeon_device *rdev = dev->dev_private;
1746 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1747 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1748 uint32_t bios_0_scratch;
1749
1750 if (!atombios_dac_load_detect(encoder, connector)) {
1751 DRM_DEBUG_KMS("detect returned false \n");
1752 return connector_status_unknown;
1753 }
1754
1755 if (rdev->family >= CHIP_R600)
1756 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1757 else
1758 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1759
1760 DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1761 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1762 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1763 return connector_status_connected;
1764 }
1765 if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1766 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1767 return connector_status_connected;
1768 }
1769 if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1770 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1771 return connector_status_connected;
1772 }
1773 if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1774 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1775 return connector_status_connected; /* CTV */
1776 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1777 return connector_status_connected; /* STV */
1778 }
1779 return connector_status_disconnected;
1780 }
1781
1782 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1783 {
1784 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1785 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1786
1787 if (radeon_encoder->active_device &
1788 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1789 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1790 if (dig)
1791 dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1792 }
1793
1794 radeon_atom_output_lock(encoder, true);
1795 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1796
1797 /* select the clock/data port if it uses a router */
1798 if (connector) {
1799 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1800 if (radeon_connector->router.cd_valid)
1801 radeon_router_select_cd_port(radeon_connector);
1802 }
1803
1804 /* this is needed for the pll/ss setup to work correctly in some cases */
1805 atombios_set_encoder_crtc_source(encoder);
1806 }
1807
1808 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1809 {
1810 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1811 radeon_atom_output_lock(encoder, false);
1812 }
1813
1814 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1815 {
1816 struct drm_device *dev = encoder->dev;
1817 struct radeon_device *rdev = dev->dev_private;
1818 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1819 struct radeon_encoder_atom_dig *dig;
1820
1821 /* check for pre-DCE3 cards with shared encoders;
1822 * can't really use the links individually, so don't disable
1823 * the encoder if it's in use by another connector
1824 */
1825 if (!ASIC_IS_DCE3(rdev)) {
1826 struct drm_encoder *other_encoder;
1827 struct radeon_encoder *other_radeon_encoder;
1828
1829 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1830 other_radeon_encoder = to_radeon_encoder(other_encoder);
1831 if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1832 drm_helper_encoder_in_use(other_encoder))
1833 goto disable_done;
1834 }
1835 }
1836
1837 radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1838
1839 switch (radeon_encoder->encoder_id) {
1840 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1841 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1842 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1843 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1844 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1845 break;
1846 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1847 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1848 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1849 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1850 if (ASIC_IS_DCE4(rdev))
1851 /* disable the transmitter */
1852 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1853 else {
1854 /* disable the encoder and transmitter */
1855 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1856 atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1857 }
1858 break;
1859 case ENCODER_OBJECT_ID_INTERNAL_DDI:
1860 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1861 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1862 atombios_dvo_setup(encoder, ATOM_DISABLE);
1863 break;
1864 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1865 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1866 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1867 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1868 atombios_dac_setup(encoder, ATOM_DISABLE);
1869 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1870 atombios_tv_setup(encoder, ATOM_DISABLE);
1871 break;
1872 }
1873
1874 disable_done:
1875 if (radeon_encoder_is_digital(encoder)) {
1876 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1877 r600_hdmi_disable(encoder);
1878 dig = radeon_encoder->enc_priv;
1879 dig->dig_encoder = -1;
1880 }
1881 radeon_encoder->active_device = 0;
1882 }
1883
1884 /* these are handled by the primary encoders */
1885 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
1886 {
1887
1888 }
1889
1890 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
1891 {
1892
1893 }
1894
1895 static void
1896 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
1897 struct drm_display_mode *mode,
1898 struct drm_display_mode *adjusted_mode)
1899 {
1900
1901 }
1902
1903 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
1904 {
1905
1906 }
1907
1908 static void
1909 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
1910 {
1911
1912 }
1913
1914 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
1915 struct drm_display_mode *mode,
1916 struct drm_display_mode *adjusted_mode)
1917 {
1918 return true;
1919 }
1920
1921 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
1922 .dpms = radeon_atom_ext_dpms,
1923 .mode_fixup = radeon_atom_ext_mode_fixup,
1924 .prepare = radeon_atom_ext_prepare,
1925 .mode_set = radeon_atom_ext_mode_set,
1926 .commit = radeon_atom_ext_commit,
1927 .disable = radeon_atom_ext_disable,
1928 /* no detect for TMDS/LVDS yet */
1929 };
1930
1931 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1932 .dpms = radeon_atom_encoder_dpms,
1933 .mode_fixup = radeon_atom_mode_fixup,
1934 .prepare = radeon_atom_encoder_prepare,
1935 .mode_set = radeon_atom_encoder_mode_set,
1936 .commit = radeon_atom_encoder_commit,
1937 .disable = radeon_atom_encoder_disable,
1938 /* no detect for TMDS/LVDS yet */
1939 };
1940
1941 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1942 .dpms = radeon_atom_encoder_dpms,
1943 .mode_fixup = radeon_atom_mode_fixup,
1944 .prepare = radeon_atom_encoder_prepare,
1945 .mode_set = radeon_atom_encoder_mode_set,
1946 .commit = radeon_atom_encoder_commit,
1947 .detect = radeon_atom_dac_detect,
1948 };
1949
1950 void radeon_enc_destroy(struct drm_encoder *encoder)
1951 {
1952 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1953 kfree(radeon_encoder->enc_priv);
1954 drm_encoder_cleanup(encoder);
1955 kfree(radeon_encoder);
1956 }
1957
1958 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1959 .destroy = radeon_enc_destroy,
1960 };
1961
1962 struct radeon_encoder_atom_dac *
1963 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1964 {
1965 struct drm_device *dev = radeon_encoder->base.dev;
1966 struct radeon_device *rdev = dev->dev_private;
1967 struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1968
1969 if (!dac)
1970 return NULL;
1971
1972 dac->tv_std = radeon_atombios_get_tv_info(rdev);
1973 return dac;
1974 }
1975
1976 struct radeon_encoder_atom_dig *
1977 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1978 {
1979 int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1980 struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1981
1982 if (!dig)
1983 return NULL;
1984
1985 /* coherent mode by default */
1986 dig->coherent_mode = true;
1987 dig->dig_encoder = -1;
1988
1989 if (encoder_enum == 2)
1990 dig->linkb = true;
1991 else
1992 dig->linkb = false;
1993
1994 return dig;
1995 }
1996
1997 void
1998 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1999 {
2000 struct radeon_device *rdev = dev->dev_private;
2001 struct drm_encoder *encoder;
2002 struct radeon_encoder *radeon_encoder;
2003
2004 /* see if we already added it */
2005 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2006 radeon_encoder = to_radeon_encoder(encoder);
2007 if (radeon_encoder->encoder_enum == encoder_enum) {
2008 radeon_encoder->devices |= supported_device;
2009 return;
2010 }
2011
2012 }
2013
2014 /* add a new one */
2015 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2016 if (!radeon_encoder)
2017 return;
2018
2019 encoder = &radeon_encoder->base;
2020 switch (rdev->num_crtc) {
2021 case 1:
2022 encoder->possible_crtcs = 0x1;
2023 break;
2024 case 2:
2025 default:
2026 encoder->possible_crtcs = 0x3;
2027 break;
2028 case 6:
2029 encoder->possible_crtcs = 0x3f;
2030 break;
2031 }
2032
2033 radeon_encoder->enc_priv = NULL;
2034
2035 radeon_encoder->encoder_enum = encoder_enum;
2036 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2037 radeon_encoder->devices = supported_device;
2038 radeon_encoder->rmx_type = RMX_OFF;
2039 radeon_encoder->underscan_type = UNDERSCAN_OFF;
2040 radeon_encoder->is_ext_encoder = false;
2041
2042 switch (radeon_encoder->encoder_id) {
2043 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2044 case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2045 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2046 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2047 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2048 radeon_encoder->rmx_type = RMX_FULL;
2049 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2050 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2051 } else {
2052 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2053 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2054 if (ASIC_IS_AVIVO(rdev))
2055 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
2056 }
2057 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2058 break;
2059 case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2060 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2061 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2062 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2063 break;
2064 case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2065 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2066 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2067 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2068 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2069 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2070 break;
2071 case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2072 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2073 case ENCODER_OBJECT_ID_INTERNAL_DDI:
2074 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2075 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2076 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2077 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2078 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2079 radeon_encoder->rmx_type = RMX_FULL;
2080 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2081 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2082 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2083 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2084 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2085 } else {
2086 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2087 radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2088 if (ASIC_IS_AVIVO(rdev))
2089 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
2090 }
2091 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2092 break;
2093 case ENCODER_OBJECT_ID_SI170B:
2094 case ENCODER_OBJECT_ID_CH7303:
2095 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2096 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2097 case ENCODER_OBJECT_ID_TITFP513:
2098 case ENCODER_OBJECT_ID_VT1623:
2099 case ENCODER_OBJECT_ID_HDMI_SI1930:
2100 case ENCODER_OBJECT_ID_TRAVIS:
2101 case ENCODER_OBJECT_ID_NUTMEG:
2102 /* these are handled by the primary encoders */
2103 radeon_encoder->is_ext_encoder = true;
2104 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2105 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2106 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2107 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2108 else
2109 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2110 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2111 break;
2112 }
2113 }
Linux 2.6 libata-dev (mirror)