2 * max77693-private.h - Voltage regulator driver for the Maxim 77693
4 * Copyright (C) 2012 Samsung Electrnoics
5 * SangYoung Son <hello.son@samsung.com>
7 * This program is not provided / owned by Maxim Integrated Products.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #ifndef __LINUX_MFD_MAX77693_PRIV_H
25 #define __LINUX_MFD_MAX77693_PRIV_H
27 #include <linux/i2c.h>
29 #define MAX77693_NUM_IRQ_MUIC_REGS 3
30 #define MAX77693_REG_INVALID (0xff)
32 /* Slave addr = 0xCC: PMIC, Charger, Flash LED */
33 enum max77693_pmic_reg
{
34 MAX77693_LED_REG_IFLASH1
= 0x00,
35 MAX77693_LED_REG_IFLASH2
= 0x01,
36 MAX77693_LED_REG_ITORCH
= 0x02,
37 MAX77693_LED_REG_ITORCHTIMER
= 0x03,
38 MAX77693_LED_REG_FLASH_TIMER
= 0x04,
39 MAX77693_LED_REG_FLASH_EN
= 0x05,
40 MAX77693_LED_REG_MAX_FLASH1
= 0x06,
41 MAX77693_LED_REG_MAX_FLASH2
= 0x07,
42 MAX77693_LED_REG_MAX_FLASH3
= 0x08,
43 MAX77693_LED_REG_MAX_FLASH4
= 0x09,
44 MAX77693_LED_REG_VOUT_CNTL
= 0x0A,
45 MAX77693_LED_REG_VOUT_FLASH1
= 0x0B,
46 MAX77693_LED_REG_VOUT_FLASH2
= 0x0C,
47 MAX77693_LED_REG_FLASH_INT
= 0x0E,
48 MAX77693_LED_REG_FLASH_INT_MASK
= 0x0F,
49 MAX77693_LED_REG_FLASH_INT_STATUS
= 0x10,
51 MAX77693_PMIC_REG_PMIC_ID1
= 0x20,
52 MAX77693_PMIC_REG_PMIC_ID2
= 0x21,
53 MAX77693_PMIC_REG_INTSRC
= 0x22,
54 MAX77693_PMIC_REG_INTSRC_MASK
= 0x23,
55 MAX77693_PMIC_REG_TOPSYS_INT
= 0x24,
56 MAX77693_PMIC_REG_TOPSYS_INT_MASK
= 0x26,
57 MAX77693_PMIC_REG_TOPSYS_STAT
= 0x28,
58 MAX77693_PMIC_REG_MAINCTRL1
= 0x2A,
59 MAX77693_PMIC_REG_LSCNFG
= 0x2B,
61 MAX77693_CHG_REG_CHG_INT
= 0xB0,
62 MAX77693_CHG_REG_CHG_INT_MASK
= 0xB1,
63 MAX77693_CHG_REG_CHG_INT_OK
= 0xB2,
64 MAX77693_CHG_REG_CHG_DETAILS_00
= 0xB3,
65 MAX77693_CHG_REG_CHG_DETAILS_01
= 0xB4,
66 MAX77693_CHG_REG_CHG_DETAILS_02
= 0xB5,
67 MAX77693_CHG_REG_CHG_DETAILS_03
= 0xB6,
68 MAX77693_CHG_REG_CHG_CNFG_00
= 0xB7,
69 MAX77693_CHG_REG_CHG_CNFG_01
= 0xB8,
70 MAX77693_CHG_REG_CHG_CNFG_02
= 0xB9,
71 MAX77693_CHG_REG_CHG_CNFG_03
= 0xBA,
72 MAX77693_CHG_REG_CHG_CNFG_04
= 0xBB,
73 MAX77693_CHG_REG_CHG_CNFG_05
= 0xBC,
74 MAX77693_CHG_REG_CHG_CNFG_06
= 0xBD,
75 MAX77693_CHG_REG_CHG_CNFG_07
= 0xBE,
76 MAX77693_CHG_REG_CHG_CNFG_08
= 0xBF,
77 MAX77693_CHG_REG_CHG_CNFG_09
= 0xC0,
78 MAX77693_CHG_REG_CHG_CNFG_10
= 0xC1,
79 MAX77693_CHG_REG_CHG_CNFG_11
= 0xC2,
80 MAX77693_CHG_REG_CHG_CNFG_12
= 0xC3,
81 MAX77693_CHG_REG_CHG_CNFG_13
= 0xC4,
82 MAX77693_CHG_REG_CHG_CNFG_14
= 0xC5,
83 MAX77693_CHG_REG_SAFEOUT_CTRL
= 0xC6,
85 MAX77693_PMIC_REG_END
,
88 /* Slave addr = 0x4A: MUIC */
89 enum max77693_muic_reg
{
90 MAX77693_MUIC_REG_ID
= 0x00,
91 MAX77693_MUIC_REG_INT1
= 0x01,
92 MAX77693_MUIC_REG_INT2
= 0x02,
93 MAX77693_MUIC_REG_INT3
= 0x03,
94 MAX77693_MUIC_REG_STATUS1
= 0x04,
95 MAX77693_MUIC_REG_STATUS2
= 0x05,
96 MAX77693_MUIC_REG_STATUS3
= 0x06,
97 MAX77693_MUIC_REG_INTMASK1
= 0x07,
98 MAX77693_MUIC_REG_INTMASK2
= 0x08,
99 MAX77693_MUIC_REG_INTMASK3
= 0x09,
100 MAX77693_MUIC_REG_CDETCTRL1
= 0x0A,
101 MAX77693_MUIC_REG_CDETCTRL2
= 0x0B,
102 MAX77693_MUIC_REG_CTRL1
= 0x0C,
103 MAX77693_MUIC_REG_CTRL2
= 0x0D,
104 MAX77693_MUIC_REG_CTRL3
= 0x0E,
106 MAX77693_MUIC_REG_END
,
109 /* MAX77693 INTMASK1~2 Register */
110 #define INTMASK1_ADC1K_SHIFT 3
111 #define INTMASK1_ADCERR_SHIFT 2
112 #define INTMASK1_ADCLOW_SHIFT 1
113 #define INTMASK1_ADC_SHIFT 0
114 #define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
115 #define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
116 #define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
117 #define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
119 #define INTMASK2_VIDRM_SHIFT 5
120 #define INTMASK2_VBVOLT_SHIFT 4
121 #define INTMASK2_DXOVP_SHIFT 3
122 #define INTMASK2_DCDTMR_SHIFT 2
123 #define INTMASK2_CHGDETRUN_SHIFT 1
124 #define INTMASK2_CHGTYP_SHIFT 0
125 #define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
126 #define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
127 #define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
128 #define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
129 #define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
130 #define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
132 /* MAX77693 MUIC - STATUS1~3 Register */
133 #define STATUS1_ADC_SHIFT (0)
134 #define STATUS1_ADCLOW_SHIFT (5)
135 #define STATUS1_ADCERR_SHIFT (6)
136 #define STATUS1_ADC1K_SHIFT (7)
137 #define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
138 #define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
139 #define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
140 #define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
142 #define STATUS2_CHGTYP_SHIFT (0)
143 #define STATUS2_CHGDETRUN_SHIFT (3)
144 #define STATUS2_DCDTMR_SHIFT (4)
145 #define STATUS2_DXOVP_SHIFT (5)
146 #define STATUS2_VBVOLT_SHIFT (6)
147 #define STATUS2_VIDRM_SHIFT (7)
148 #define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
149 #define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
150 #define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
151 #define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
152 #define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
153 #define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT)
155 #define STATUS3_OVP_SHIFT (2)
156 #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
158 /* MAX77693 CDETCTRL1~2 register */
159 #define CDETCTRL1_CHGDETEN_SHIFT (0)
160 #define CDETCTRL1_CHGTYPMAN_SHIFT (1)
161 #define CDETCTRL1_DCDEN_SHIFT (2)
162 #define CDETCTRL1_DCD2SCT_SHIFT (3)
163 #define CDETCTRL1_CDDELAY_SHIFT (4)
164 #define CDETCTRL1_DCDCPL_SHIFT (5)
165 #define CDETCTRL1_CDPDET_SHIFT (7)
166 #define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
167 #define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
168 #define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
169 #define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
170 #define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
171 #define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
172 #define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
174 #define CDETCTRL2_VIDRMEN_SHIFT (1)
175 #define CDETCTRL2_DXOVPEN_SHIFT (3)
176 #define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
177 #define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
179 /* MAX77693 MUIC - CONTROL1~3 register */
180 #define COMN1SW_SHIFT (0)
181 #define COMP2SW_SHIFT (3)
182 #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
183 #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
184 #define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
185 #define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
186 | (1 << COMN1SW_SHIFT))
187 #define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
188 | (2 << COMN1SW_SHIFT))
189 #define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
190 | (3 << COMN1SW_SHIFT))
191 #define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
192 | (0 << COMN1SW_SHIFT))
194 #define CONTROL2_LOWPWR_SHIFT (0)
195 #define CONTROL2_ADCEN_SHIFT (1)
196 #define CONTROL2_CPEN_SHIFT (2)
197 #define CONTROL2_SFOUTASRT_SHIFT (3)
198 #define CONTROL2_SFOUTORD_SHIFT (4)
199 #define CONTROL2_ACCDET_SHIFT (5)
200 #define CONTROL2_USBCPINT_SHIFT (6)
201 #define CONTROL2_RCPS_SHIFT (7)
202 #define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
203 #define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
204 #define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
205 #define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
206 #define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
207 #define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
208 #define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
209 #define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
211 #define CONTROL3_JIGSET_SHIFT (0)
212 #define CONTROL3_BTLDSET_SHIFT (2)
213 #define CONTROL3_ADCDBSET_SHIFT (4)
214 #define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
215 #define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
216 #define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
218 /* Slave addr = 0x90: Haptic */
219 enum max77693_haptic_reg
{
220 MAX77693_HAPTIC_REG_STATUS
= 0x00,
221 MAX77693_HAPTIC_REG_CONFIG1
= 0x01,
222 MAX77693_HAPTIC_REG_CONFIG2
= 0x02,
223 MAX77693_HAPTIC_REG_CONFIG_CHNL
= 0x03,
224 MAX77693_HAPTIC_REG_CONFG_CYC1
= 0x04,
225 MAX77693_HAPTIC_REG_CONFG_CYC2
= 0x05,
226 MAX77693_HAPTIC_REG_CONFIG_PER1
= 0x06,
227 MAX77693_HAPTIC_REG_CONFIG_PER2
= 0x07,
228 MAX77693_HAPTIC_REG_CONFIG_PER3
= 0x08,
229 MAX77693_HAPTIC_REG_CONFIG_PER4
= 0x09,
230 MAX77693_HAPTIC_REG_CONFIG_DUTY1
= 0x0A,
231 MAX77693_HAPTIC_REG_CONFIG_DUTY2
= 0x0B,
232 MAX77693_HAPTIC_REG_CONFIG_PWM1
= 0x0C,
233 MAX77693_HAPTIC_REG_CONFIG_PWM2
= 0x0D,
234 MAX77693_HAPTIC_REG_CONFIG_PWM3
= 0x0E,
235 MAX77693_HAPTIC_REG_CONFIG_PWM4
= 0x0F,
236 MAX77693_HAPTIC_REG_REV
= 0x10,
238 MAX77693_HAPTIC_REG_END
,
241 enum max77693_irq_source
{
249 MAX77693_IRQ_GROUP_NR
,
254 MAX77693_LED_IRQ_FLED2_OPEN
,
255 MAX77693_LED_IRQ_FLED2_SHORT
,
256 MAX77693_LED_IRQ_FLED1_OPEN
,
257 MAX77693_LED_IRQ_FLED1_SHORT
,
258 MAX77693_LED_IRQ_MAX_FLASH
,
261 MAX77693_TOPSYS_IRQ_T120C_INT
,
262 MAX77693_TOPSYS_IRQ_T140C_INT
,
263 MAX77693_TOPSYS_IRQ_LOWSYS_INT
,
266 MAX77693_CHG_IRQ_BYP_I
,
267 MAX77693_CHG_IRQ_THM_I
,
268 MAX77693_CHG_IRQ_BAT_I
,
269 MAX77693_CHG_IRQ_CHG_I
,
270 MAX77693_CHG_IRQ_CHGIN_I
,
273 MAX77693_MUIC_IRQ_INT1_ADC
,
274 MAX77693_MUIC_IRQ_INT1_ADC_LOW
,
275 MAX77693_MUIC_IRQ_INT1_ADC_ERR
,
276 MAX77693_MUIC_IRQ_INT1_ADC1K
,
279 MAX77693_MUIC_IRQ_INT2_CHGTYP
,
280 MAX77693_MUIC_IRQ_INT2_CHGDETREUN
,
281 MAX77693_MUIC_IRQ_INT2_DCDTMR
,
282 MAX77693_MUIC_IRQ_INT2_DXOVP
,
283 MAX77693_MUIC_IRQ_INT2_VBVOLT
,
284 MAX77693_MUIC_IRQ_INT2_VIDRM
,
287 MAX77693_MUIC_IRQ_INT3_EOC
,
288 MAX77693_MUIC_IRQ_INT3_CGMBC
,
289 MAX77693_MUIC_IRQ_INT3_OVP
,
290 MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR
,
291 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED
,
292 MAX77693_MUIC_IRQ_INT3_BAT_DET
,
297 struct max77693_dev
{
299 struct i2c_client
*i2c
; /* 0xCC , PMIC, Charger, Flash LED */
300 struct i2c_client
*muic
; /* 0x4A , MUIC */
301 struct i2c_client
*haptic
; /* 0x90 , Haptic */
305 struct regmap
*regmap
;
306 struct regmap
*regmap_muic
;
307 struct regmap
*regmap_haptic
;
309 struct irq_domain
*irq_domain
;
314 struct mutex irqlock
;
315 int irq_masks_cur
[MAX77693_IRQ_GROUP_NR
];
316 int irq_masks_cache
[MAX77693_IRQ_GROUP_NR
];
319 enum max77693_types
{
323 extern int max77693_read_reg(struct regmap
*map
, u8 reg
, u8
*dest
);
324 extern int max77693_bulk_read(struct regmap
*map
, u8 reg
, int count
,
326 extern int max77693_write_reg(struct regmap
*map
, u8 reg
, u8 value
);
327 extern int max77693_bulk_write(struct regmap
*map
, u8 reg
, int count
,
329 extern int max77693_update_reg(struct regmap
*map
, u8 reg
, u8 val
, u8 mask
);
331 extern int max77693_irq_init(struct max77693_dev
*max77686
);
332 extern void max77693_irq_exit(struct max77693_dev
*max77686
);
333 extern int max77693_irq_resume(struct max77693_dev
*max77686
);
335 #endif /* __LINUX_MFD_MAX77693_PRIV_H */