drivers/gpu/drm/radeon/radeon_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <glisse@freedesktop.org>
  26  */
  27 #include <drm/drmP.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon_reg.h"
  30 #include "radeon.h"
  31
  32 static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
  33 {
  34         struct drm_device *ddev = p->rdev->ddev;
  35         struct radeon_cs_chunk *chunk;
  36         unsigned i, j;
  37         bool duplicate;
  38
  39         if (p->chunk_relocs_idx == -1) {
  40                 return 0;
  41         }
  42         chunk = &p->chunks[p->chunk_relocs_idx];
  43         p->dma_reloc_idx = 0;
  44         /* FIXME: we assume that each relocs use 4 dwords */
  45         p->nrelocs = chunk->length_dw / 4;
  46         p->relocs_ptr = kcalloc(p->nrelocs, sizeof(void *), GFP_KERNEL);
  47         if (p->relocs_ptr == NULL) {
  48                 return -ENOMEM;
  49         }
  50         p->relocs = kcalloc(p->nrelocs, sizeof(struct radeon_cs_reloc), GFP_KERNEL);
  51         if (p->relocs == NULL) {
  52                 return -ENOMEM;
  53         }
  54         for (i = 0; i < p->nrelocs; i++) {
  55                 struct drm_radeon_cs_reloc *r;
  56
  57                 duplicate = false;
  58                 r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4];
  59                 for (j = 0; j < i; j++) {
  60                         if (r->handle == p->relocs[j].handle) {
  61                                 p->relocs_ptr[i] = &p->relocs[j];
  62                                 duplicate = true;
  63                                 break;
  64                         }
  65                 }
  66                 if (!duplicate) {
  67                         p->relocs[i].gobj = drm_gem_object_lookup(ddev,
  68                                                                   p->filp,
  69                                                                   r->handle);
  70                         if (p->relocs[i].gobj == NULL) {
  71                                 DRM_ERROR("gem object lookup failed 0x%x\n",
  72                                           r->handle);
  73                                 return -ENOENT;
  74                         }
  75                         p->relocs_ptr[i] = &p->relocs[i];
  76                         p->relocs[i].robj = gem_to_radeon_bo(p->relocs[i].gobj);
  77                         p->relocs[i].lobj.bo = p->relocs[i].robj;
  78                         p->relocs[i].lobj.wdomain = r->write_domain;
  79                         p->relocs[i].lobj.rdomain = r->read_domains;
  80                         p->relocs[i].lobj.tv.bo = &p->relocs[i].robj->tbo;
  81                         p->relocs[i].handle = r->handle;
  82                         p->relocs[i].flags = r->flags;
  83                         radeon_bo_list_add_object(&p->relocs[i].lobj,
  84                                                   &p->validated);
  85
  86                 } else
  87                         p->relocs[i].handle = 0;
  88         }
  89         return radeon_bo_list_validate(&p->validated);
  90 }
  91
  92 static int radeon_cs_get_ring(struct radeon_cs_parser *p, u32 ring, s32 priority)
  93 {
  94         p->priority = priority;
  95
  96         switch (ring) {
  97         default:
  98                 DRM_ERROR("unknown ring id: %d\n", ring);
  99                 return -EINVAL;
 100         case RADEON_CS_RING_GFX:
 101                 p->ring = RADEON_RING_TYPE_GFX_INDEX;
 102                 break;
 103         case RADEON_CS_RING_COMPUTE:
 104                 if (p->rdev->family >= CHIP_TAHITI) {
 105                         if (p->priority > 0)
 106                                 p->ring = CAYMAN_RING_TYPE_CP1_INDEX;
 107                         else
 108                                 p->ring = CAYMAN_RING_TYPE_CP2_INDEX;
 109                 } else
 110                         p->ring = RADEON_RING_TYPE_GFX_INDEX;
 111                 break;
 112         case RADEON_CS_RING_DMA:
 113                 if (p->rdev->family >= CHIP_CAYMAN) {
 114                         if (p->priority > 0)
 115                                 p->ring = R600_RING_TYPE_DMA_INDEX;
 116                         else
 117                                 p->ring = CAYMAN_RING_TYPE_DMA1_INDEX;
 118                 } else if (p->rdev->family >= CHIP_R600) {
 119                         p->ring = R600_RING_TYPE_DMA_INDEX;
 120                 } else {
 121                         return -EINVAL;
 122                 }
 123                 break;
 124         }
 125         return 0;
 126 }
 127
 128 static void radeon_cs_sync_rings(struct radeon_cs_parser *p)
 129 {
 130         int i;
 131
 132         for (i = 0; i < p->nrelocs; i++) {
 133                 if (!p->relocs[i].robj)
 134                         continue;
 135
 136                 radeon_ib_sync_to(&p->ib, p->relocs[i].robj->tbo.sync_obj);
 137         }
 138 }
 139
 140 /* XXX: note that this is called from the legacy UMS CS ioctl as well */
 141 int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data)
 142 {
 143         struct drm_radeon_cs *cs = data;
 144         uint64_t *chunk_array_ptr;
 145         unsigned size, i;
 146         u32 ring = RADEON_CS_RING_GFX;
 147         s32 priority = 0;
 148
 149         if (!cs->num_chunks) {
 150                 return 0;
 151         }
 152         /* get chunks */
 153         INIT_LIST_HEAD(&p->validated);
 154         p->idx = 0;
 155         p->ib.sa_bo = NULL;
 156         p->ib.semaphore = NULL;
 157         p->const_ib.sa_bo = NULL;
 158         p->const_ib.semaphore = NULL;
 159         p->chunk_ib_idx = -1;
 160         p->chunk_relocs_idx = -1;
 161         p->chunk_flags_idx = -1;
 162         p->chunk_const_ib_idx = -1;
 163         p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL);
 164         if (p->chunks_array == NULL) {
 165                 return -ENOMEM;
 166         }
 167         chunk_array_ptr = (uint64_t *)(unsigned long)(cs->chunks);
 168         if (DRM_COPY_FROM_USER(p->chunks_array, chunk_array_ptr,
 169                                sizeof(uint64_t)*cs->num_chunks)) {
 170                 return -EFAULT;
 171         }
 172         p->cs_flags = 0;
 173         p->nchunks = cs->num_chunks;
 174         p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL);
 175         if (p->chunks == NULL) {
 176                 return -ENOMEM;
 177         }
 178         for (i = 0; i < p->nchunks; i++) {
 179                 struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
 180                 struct drm_radeon_cs_chunk user_chunk;
 181                 uint32_t __user *cdata;
 182
 183                 chunk_ptr = (void __user*)(unsigned long)p->chunks_array[i];
 184                 if (DRM_COPY_FROM_USER(&user_chunk, chunk_ptr,
 185                                        sizeof(struct drm_radeon_cs_chunk))) {
 186                         return -EFAULT;
 187                 }
 188                 p->chunks[i].length_dw = user_chunk.length_dw;
 189                 p->chunks[i].kdata = NULL;
 190                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 191                 p->chunks[i].user_ptr = (void __user *)(unsigned long)user_chunk.chunk_data;
 192                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) {
 193                         p->chunk_relocs_idx = i;
 194                 }
 195                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_IB) {
 196                         p->chunk_ib_idx = i;
 197                         /* zero length IB isn't useful */
 198                         if (p->chunks[i].length_dw == 0)
 199                                 return -EINVAL;
 200                 }
 201                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_CONST_IB) {
 202                         p->chunk_const_ib_idx = i;
 203                         /* zero length CONST IB isn't useful */
 204                         if (p->chunks[i].length_dw == 0)
 205                                 return -EINVAL;
 206                 }
 207                 if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
 208                         p->chunk_flags_idx = i;
 209                         /* zero length flags aren't useful */
 210                         if (p->chunks[i].length_dw == 0)
 211                                 return -EINVAL;
 212                 }
 213
 214                 cdata = (uint32_t *)(unsigned long)user_chunk.chunk_data;
 215                 if ((p->chunks[i].chunk_id == RADEON_CHUNK_ID_RELOCS) ||
 216                     (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS)) {
 217                         size = p->chunks[i].length_dw * sizeof(uint32_t);
 218                         p->chunks[i].kdata = kmalloc(size, GFP_KERNEL);
 219                         if (p->chunks[i].kdata == NULL) {
 220                                 return -ENOMEM;
 221                         }
 222                         if (DRM_COPY_FROM_USER(p->chunks[i].kdata,
 223                                                p->chunks[i].user_ptr, size)) {
 224                                 return -EFAULT;
 225                         }
 226                         if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) {
 227                                 p->cs_flags = p->chunks[i].kdata[0];
 228                                 if (p->chunks[i].length_dw > 1)
 229                                         ring = p->chunks[i].kdata[1];
 230                                 if (p->chunks[i].length_dw > 2)
 231                                         priority = (s32)p->chunks[i].kdata[2];
 232                         }
 233                 }
 234         }
 235
 236         /* these are KMS only */
 237         if (p->rdev) {
 238                 if ((p->cs_flags & RADEON_CS_USE_VM) &&
 239                     !p->rdev->vm_manager.enabled) {
 240                         DRM_ERROR("VM not active on asic!\n");
 241                         return -EINVAL;
 242                 }
 243
 244                 /* we only support VM on SI+ */
 245                 if ((p->rdev->family >= CHIP_TAHITI) &&
 246                     ((p->cs_flags & RADEON_CS_USE_VM) == 0)) {
 247                         DRM_ERROR("VM required on SI+!\n");
 248                         return -EINVAL;
 249                 }
 250
 251                 if (radeon_cs_get_ring(p, ring, priority))
 252                         return -EINVAL;
 253         }
 254
 255         /* deal with non-vm */
 256         if ((p->chunk_ib_idx != -1) &&
 257             ((p->cs_flags & RADEON_CS_USE_VM) == 0) &&
 258             (p->chunks[p->chunk_ib_idx].chunk_id == RADEON_CHUNK_ID_IB)) {
 259                 if (p->chunks[p->chunk_ib_idx].length_dw > (16 * 1024)) {
 260                         DRM_ERROR("cs IB too big: %d\n",
 261                                   p->chunks[p->chunk_ib_idx].length_dw);
 262                         return -EINVAL;
 263                 }
 264                 if (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) {
 265                         p->chunks[p->chunk_ib_idx].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL);
 266                         p->chunks[p->chunk_ib_idx].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL);
 267                         if (p->chunks[p->chunk_ib_idx].kpage[0] == NULL ||
 268                             p->chunks[p->chunk_ib_idx].kpage[1] == NULL) {
 269                                 kfree(p->chunks[p->chunk_ib_idx].kpage[0]);
 270                                 kfree(p->chunks[p->chunk_ib_idx].kpage[1]);
 271                                 p->chunks[p->chunk_ib_idx].kpage[0] = NULL;
 272                                 p->chunks[p->chunk_ib_idx].kpage[1] = NULL;
 273                                 return -ENOMEM;
 274                         }
 275                 }
 276                 p->chunks[p->chunk_ib_idx].kpage_idx[0] = -1;
 277                 p->chunks[p->chunk_ib_idx].kpage_idx[1] = -1;
 278                 p->chunks[p->chunk_ib_idx].last_copied_page = -1;
 279                 p->chunks[p->chunk_ib_idx].last_page_index =
 280                         ((p->chunks[p->chunk_ib_idx].length_dw * 4) - 1) / PAGE_SIZE;
 281         }
 282
 283         return 0;
 284 }
 285
 286 /**
 287  * cs_parser_fini() - clean parser states
 288  * @parser:     parser structure holding parsing context.
 289  * @error:      error number
 290  *
 291  * If error is set than unvalidate buffer, otherwise just free memory
 292  * used by parsing context.
 293  **/
 294 static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error)
 295 {
 296         unsigned i;
 297
 298         if (!error) {
 299                 ttm_eu_fence_buffer_objects(&parser->validated,
 300                                             parser->ib.fence);
 301         } else {
 302                 ttm_eu_backoff_reservation(&parser->validated);
 303         }
 304
 305         if (parser->relocs != NULL) {
 306                 for (i = 0; i < parser->nrelocs; i++) {
 307                         if (parser->relocs[i].gobj)
 308                                 drm_gem_object_unreference_unlocked(parser->relocs[i].gobj);
 309                 }
 310         }
 311         kfree(parser->track);
 312         kfree(parser->relocs);
 313         kfree(parser->relocs_ptr);
 314         for (i = 0; i < parser->nchunks; i++) {
 315                 kfree(parser->chunks[i].kdata);
 316                 if ((parser->rdev->flags & RADEON_IS_AGP)) {
 317                         kfree(parser->chunks[i].kpage[0]);
 318                         kfree(parser->chunks[i].kpage[1]);
 319                 }
 320         }
 321         kfree(parser->chunks);
 322         kfree(parser->chunks_array);
 323         radeon_ib_free(parser->rdev, &parser->ib);
 324         radeon_ib_free(parser->rdev, &parser->const_ib);
 325 }
 326
 327 static int radeon_cs_ib_chunk(struct radeon_device *rdev,
 328                               struct radeon_cs_parser *parser)
 329 {
 330         struct radeon_cs_chunk *ib_chunk;
 331         int r;
 332
 333         if (parser->chunk_ib_idx == -1)
 334                 return 0;
 335
 336         if (parser->cs_flags & RADEON_CS_USE_VM)
 337                 return 0;
 338
 339         ib_chunk = &parser->chunks[parser->chunk_ib_idx];
 340         /* Copy the packet into the IB, the parser will read from the
 341          * input memory (cached) and write to the IB (which can be
 342          * uncached).
 343          */
 344         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
 345                            NULL, ib_chunk->length_dw * 4);
 346         if (r) {
 347                 DRM_ERROR("Failed to get ib !\n");
 348                 return r;
 349         }
 350         parser->ib.length_dw = ib_chunk->length_dw;
 351         r = radeon_cs_parse(rdev, parser->ring, parser);
 352         if (r || parser->parser_error) {
 353                 DRM_ERROR("Invalid command stream !\n");
 354                 return r;
 355         }
 356         r = radeon_cs_finish_pages(parser);
 357         if (r) {
 358                 DRM_ERROR("Invalid command stream !\n");
 359                 return r;
 360         }
 361         radeon_cs_sync_rings(parser);
 362         r = radeon_ib_schedule(rdev, &parser->ib, NULL);
 363         if (r) {
 364                 DRM_ERROR("Failed to schedule IB !\n");
 365         }
 366         return r;
 367 }
 368
 369 static int radeon_bo_vm_update_pte(struct radeon_cs_parser *parser,
 370                                    struct radeon_vm *vm)
 371 {
 372         struct radeon_device *rdev = parser->rdev;
 373         struct radeon_bo_list *lobj;
 374         struct radeon_bo *bo;
 375         int r;
 376
 377         r = radeon_vm_bo_update_pte(rdev, vm, rdev->ring_tmp_bo.bo, &rdev->ring_tmp_bo.bo->tbo.mem);
 378         if (r) {
 379                 return r;
 380         }
 381         list_for_each_entry(lobj, &parser->validated, tv.head) {
 382                 bo = lobj->bo;
 383                 r = radeon_vm_bo_update_pte(parser->rdev, vm, bo, &bo->tbo.mem);
 384                 if (r) {
 385                         return r;
 386                 }
 387         }
 388         return 0;
 389 }
 390
 391 static int radeon_cs_ib_vm_chunk(struct radeon_device *rdev,
 392                                  struct radeon_cs_parser *parser)
 393 {
 394         struct radeon_cs_chunk *ib_chunk;
 395         struct radeon_fpriv *fpriv = parser->filp->driver_priv;
 396         struct radeon_vm *vm = &fpriv->vm;
 397         int r;
 398
 399         if (parser->chunk_ib_idx == -1)
 400                 return 0;
 401         if ((parser->cs_flags & RADEON_CS_USE_VM) == 0)
 402                 return 0;
 403
 404         if ((rdev->family >= CHIP_TAHITI) &&
 405             (parser->chunk_const_ib_idx != -1)) {
 406                 ib_chunk = &parser->chunks[parser->chunk_const_ib_idx];
 407                 if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 408                         DRM_ERROR("cs IB CONST too big: %d\n", ib_chunk->length_dw);
 409                         return -EINVAL;
 410                 }
 411                 r =  radeon_ib_get(rdev, parser->ring, &parser->const_ib,
 412                                    vm, ib_chunk->length_dw * 4);
 413                 if (r) {
 414                         DRM_ERROR("Failed to get const ib !\n");
 415                         return r;
 416                 }
 417                 parser->const_ib.is_const_ib = true;
 418                 parser->const_ib.length_dw = ib_chunk->length_dw;
 419                 /* Copy the packet into the IB */
 420                 if (DRM_COPY_FROM_USER(parser->const_ib.ptr, ib_chunk->user_ptr,
 421                                        ib_chunk->length_dw * 4)) {
 422                         return -EFAULT;
 423                 }
 424                 r = radeon_ring_ib_parse(rdev, parser->ring, &parser->const_ib);
 425                 if (r) {
 426                         return r;
 427                 }
 428         }
 429
 430         ib_chunk = &parser->chunks[parser->chunk_ib_idx];
 431         if (ib_chunk->length_dw > RADEON_IB_VM_MAX_SIZE) {
 432                 DRM_ERROR("cs IB too big: %d\n", ib_chunk->length_dw);
 433                 return -EINVAL;
 434         }
 435         r =  radeon_ib_get(rdev, parser->ring, &parser->ib,
 436                            vm, ib_chunk->length_dw * 4);
 437         if (r) {
 438                 DRM_ERROR("Failed to get ib !\n");
 439                 return r;
 440         }
 441         parser->ib.length_dw = ib_chunk->length_dw;
 442         /* Copy the packet into the IB */
 443         if (DRM_COPY_FROM_USER(parser->ib.ptr, ib_chunk->user_ptr,
 444                                ib_chunk->length_dw * 4)) {
 445                 return -EFAULT;
 446         }
 447         r = radeon_ring_ib_parse(rdev, parser->ring, &parser->ib);
 448         if (r) {
 449                 return r;
 450         }
 451
 452         mutex_lock(&rdev->vm_manager.lock);
 453         mutex_lock(&vm->mutex);
 454         r = radeon_vm_alloc_pt(rdev, vm);
 455         if (r) {
 456                 goto out;
 457         }
 458         r = radeon_bo_vm_update_pte(parser, vm);
 459         if (r) {
 460                 goto out;
 461         }
 462         radeon_cs_sync_rings(parser);
 463         radeon_ib_sync_to(&parser->ib, vm->fence);
 464         radeon_ib_sync_to(&parser->ib, radeon_vm_grab_id(
 465                 rdev, vm, parser->ring));
 466
 467         if ((rdev->family >= CHIP_TAHITI) &&
 468             (parser->chunk_const_ib_idx != -1)) {
 469                 r = radeon_ib_schedule(rdev, &parser->ib, &parser->const_ib);
 470         } else {
 471                 r = radeon_ib_schedule(rdev, &parser->ib, NULL);
 472         }
 473
 474         if (!r) {
 475                 radeon_vm_fence(rdev, vm, parser->ib.fence);
 476         }
 477
 478 out:
 479         radeon_vm_add_to_lru(rdev, vm);
 480         mutex_unlock(&vm->mutex);
 481         mutex_unlock(&rdev->vm_manager.lock);
 482         return r;
 483 }
 484
 485 static int radeon_cs_handle_lockup(struct radeon_device *rdev, int r)
 486 {
 487         if (r == -EDEADLK) {
 488                 r = radeon_gpu_reset(rdev);
 489                 if (!r)
 490                         r = -EAGAIN;
 491         }
 492         return r;
 493 }
 494
 495 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 496 {
 497         struct radeon_device *rdev = dev->dev_private;
 498         struct radeon_cs_parser parser;
 499         int r;
 500
 501         down_read(&rdev->exclusive_lock);
 502         if (!rdev->accel_working) {
 503                 up_read(&rdev->exclusive_lock);
 504                 return -EBUSY;
 505         }
 506         /* initialize parser */
 507         memset(&parser, 0, sizeof(struct radeon_cs_parser));
 508         parser.filp = filp;
 509         parser.rdev = rdev;
 510         parser.dev = rdev->dev;
 511         parser.family = rdev->family;
 512         r = radeon_cs_parser_init(&parser, data);
 513         if (r) {
 514                 DRM_ERROR("Failed to initialize parser !\n");
 515                 radeon_cs_parser_fini(&parser, r);
 516                 up_read(&rdev->exclusive_lock);
 517                 r = radeon_cs_handle_lockup(rdev, r);
 518                 return r;
 519         }
 520         r = radeon_cs_parser_relocs(&parser);
 521         if (r) {
 522                 if (r != -ERESTARTSYS)
 523                         DRM_ERROR("Failed to parse relocation %d!\n", r);
 524                 radeon_cs_parser_fini(&parser, r);
 525                 up_read(&rdev->exclusive_lock);
 526                 r = radeon_cs_handle_lockup(rdev, r);
 527                 return r;
 528         }
 529         r = radeon_cs_ib_chunk(rdev, &parser);
 530         if (r) {
 531                 goto out;
 532         }
 533         r = radeon_cs_ib_vm_chunk(rdev, &parser);
 534         if (r) {
 535                 goto out;
 536         }
 537 out:
 538         radeon_cs_parser_fini(&parser, r);
 539         up_read(&rdev->exclusive_lock);
 540         r = radeon_cs_handle_lockup(rdev, r);
 541         return r;
 542 }
 543
 544 int radeon_cs_finish_pages(struct radeon_cs_parser *p)
 545 {
 546         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 547         int i;
 548         int size = PAGE_SIZE;
 549
 550         for (i = ibc->last_copied_page + 1; i <= ibc->last_page_index; i++) {
 551                 if (i == ibc->last_page_index) {
 552                         size = (ibc->length_dw * 4) % PAGE_SIZE;
 553                         if (size == 0)
 554                                 size = PAGE_SIZE;
 555                 }
 556
 557                 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
 558                                        ibc->user_ptr + (i * PAGE_SIZE),
 559                                        size))
 560                         return -EFAULT;
 561         }
 562         return 0;
 563 }
 564
 565 static int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx)
 566 {
 567         int new_page;
 568         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 569         int i;
 570         int size = PAGE_SIZE;
 571         bool copy1 = (p->rdev && (p->rdev->flags & RADEON_IS_AGP)) ?
 572                 false : true;
 573
 574         for (i = ibc->last_copied_page + 1; i < pg_idx; i++) {
 575                 if (DRM_COPY_FROM_USER(p->ib.ptr + (i * (PAGE_SIZE/4)),
 576                                        ibc->user_ptr + (i * PAGE_SIZE),
 577                                        PAGE_SIZE)) {
 578                         p->parser_error = -EFAULT;
 579                         return 0;
 580                 }
 581         }
 582
 583         if (pg_idx == ibc->last_page_index) {
 584                 size = (ibc->length_dw * 4) % PAGE_SIZE;
 585                 if (size == 0)
 586                         size = PAGE_SIZE;
 587         }
 588
 589         new_page = ibc->kpage_idx[0] < ibc->kpage_idx[1] ? 0 : 1;
 590         if (copy1)
 591                 ibc->kpage[new_page] = p->ib.ptr + (pg_idx * (PAGE_SIZE / 4));
 592
 593         if (DRM_COPY_FROM_USER(ibc->kpage[new_page],
 594                                ibc->user_ptr + (pg_idx * PAGE_SIZE),
 595                                size)) {
 596                 p->parser_error = -EFAULT;
 597                 return 0;
 598         }
 599
 600         /* copy to IB for non single case */
 601         if (!copy1)
 602                 memcpy((void *)(p->ib.ptr+(pg_idx*(PAGE_SIZE/4))), ibc->kpage[new_page], size);
 603
 604         ibc->last_copied_page = pg_idx;
 605         ibc->kpage_idx[new_page] = pg_idx;
 606
 607         return new_page;
 608 }
 609
 610 u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 611 {
 612         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 613         u32 pg_idx, pg_offset;
 614         u32 idx_value = 0;
 615         int new_page;
 616
 617         pg_idx = (idx * 4) / PAGE_SIZE;
 618         pg_offset = (idx * 4) % PAGE_SIZE;
 619
 620         if (ibc->kpage_idx[0] == pg_idx)
 621                 return ibc->kpage[0][pg_offset/4];
 622         if (ibc->kpage_idx[1] == pg_idx)
 623                 return ibc->kpage[1][pg_offset/4];
 624
 625         new_page = radeon_cs_update_pages(p, pg_idx);
 626         if (new_page < 0) {
 627                 p->parser_error = new_page;
 628                 return 0;
 629         }
 630
 631         idx_value = ibc->kpage[new_page][pg_offset/4];
 632         return idx_value;
 633 }
 634
 635 /**
 636  * radeon_cs_packet_parse() - parse cp packet and point ib index to next packet
 637  * @parser:     parser structure holding parsing context.
 638  * @pkt:        where to store packet information
 639  *
 640  * Assume that chunk_ib_index is properly set. Will return -EINVAL
 641  * if packet is bigger than remaining ib size. or if packets is unknown.
 642  **/
 643 int radeon_cs_packet_parse(struct radeon_cs_parser *p,
 644                            struct radeon_cs_packet *pkt,
 645                            unsigned idx)
 646 {
 647         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
 648         struct radeon_device *rdev = p->rdev;
 649         uint32_t header;
 650
 651         if (idx >= ib_chunk->length_dw) {
 652                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
 653                           idx, ib_chunk->length_dw);
 654                 return -EINVAL;
 655         }
 656         header = radeon_get_ib_value(p, idx);
 657         pkt->idx = idx;
 658         pkt->type = RADEON_CP_PACKET_GET_TYPE(header);
 659         pkt->count = RADEON_CP_PACKET_GET_COUNT(header);
 660         pkt->one_reg_wr = 0;
 661         switch (pkt->type) {
 662         case RADEON_PACKET_TYPE0:
 663                 if (rdev->family < CHIP_R600) {
 664                         pkt->reg = R100_CP_PACKET0_GET_REG(header);
 665                         pkt->one_reg_wr =
 666                                 RADEON_CP_PACKET0_GET_ONE_REG_WR(header);
 667                 } else
 668                         pkt->reg = R600_CP_PACKET0_GET_REG(header);
 669                 break;
 670         case RADEON_PACKET_TYPE3:
 671                 pkt->opcode = RADEON_CP_PACKET3_GET_OPCODE(header);
 672                 break;
 673         case RADEON_PACKET_TYPE2:
 674                 pkt->count = -1;
 675                 break;
 676         default:
 677                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
 678                 return -EINVAL;
 679         }
 680         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
 681                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
 682                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
 683                 return -EINVAL;
 684         }
 685         return 0;
 686 }
 687
 688 /**
 689  * radeon_cs_packet_next_is_pkt3_nop() - test if the next packet is P3 NOP
 690  * @p:          structure holding the parser context.
 691  *
 692  * Check if the next packet is NOP relocation packet3.
 693  **/
 694 bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p)
 695 {
 696         struct radeon_cs_packet p3reloc;
 697         int r;
 698
 699         r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
 700         if (r)
 701                 return false;
 702         if (p3reloc.type != RADEON_PACKET_TYPE3)
 703                 return false;
 704         if (p3reloc.opcode != RADEON_PACKET3_NOP)
 705                 return false;
 706         return true;
 707 }
 708
 709 /**
 710  * radeon_cs_dump_packet() - dump raw packet context
 711  * @p:          structure holding the parser context.
 712  * @pkt:        structure holding the packet.
 713  *
 714  * Used mostly for debugging and error reporting.
 715  **/
 716 void radeon_cs_dump_packet(struct radeon_cs_parser *p,
 717                            struct radeon_cs_packet *pkt)
 718 {
 719         volatile uint32_t *ib;
 720         unsigned i;
 721         unsigned idx;
 722
 723         ib = p->ib.ptr;
 724         idx = pkt->idx;
 725         for (i = 0; i <= (pkt->count + 1); i++, idx++)
 726                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
 727 }
 728
 729 /**
 730  * radeon_cs_packet_next_reloc() - parse next (should be reloc) packet
 731  * @parser:             parser structure holding parsing context.
 732  * @data:               pointer to relocation data
 733  * @offset_start:       starting offset
 734  * @offset_mask:        offset mask (to align start offset on)
 735  * @reloc:              reloc informations
 736  *
 737  * Check if next packet is relocation packet3, do bo validation and compute
 738  * GPU offset using the provided start.
 739  **/
 740 int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
 741                                 struct radeon_cs_reloc **cs_reloc,
 742                                 int nomm)
 743 {
 744         struct radeon_cs_chunk *relocs_chunk;
 745         struct radeon_cs_packet p3reloc;
 746         unsigned idx;
 747         int r;
 748
 749         if (p->chunk_relocs_idx == -1) {
 750                 DRM_ERROR("No relocation chunk !\n");
 751                 return -EINVAL;
 752         }
 753         *cs_reloc = NULL;
 754         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
 755         r = radeon_cs_packet_parse(p, &p3reloc, p->idx);
 756         if (r)
 757                 return r;
 758         p->idx += p3reloc.count + 2;
 759         if (p3reloc.type != RADEON_PACKET_TYPE3 ||
 760             p3reloc.opcode != RADEON_PACKET3_NOP) {
 761                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
 762                           p3reloc.idx);
 763                 radeon_cs_dump_packet(p, &p3reloc);
 764                 return -EINVAL;
 765         }
 766         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
 767         if (idx >= relocs_chunk->length_dw) {
 768                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
 769                           idx, relocs_chunk->length_dw);
 770                 radeon_cs_dump_packet(p, &p3reloc);
 771                 return -EINVAL;
 772         }
 773         /* FIXME: we assume reloc size is 4 dwords */
 774         if (nomm) {
 775                 *cs_reloc = p->relocs;
 776                 (*cs_reloc)->lobj.gpu_offset =
 777                         (u64)relocs_chunk->kdata[idx + 3] << 32;
 778                 (*cs_reloc)->lobj.gpu_offset |= relocs_chunk->kdata[idx + 0];
 779         } else
 780                 *cs_reloc = p->relocs_ptr[(idx / 4)];
 781         return 0;
 782 }