2 * Calxeda Highbank AHCI SATA platform driver
3 * Copyright 2012 Calxeda, Inc.
5 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #include <linux/kernel.h>
20 #include <linux/gfp.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/types.h>
24 #include <linux/err.h>
26 #include <linux/spinlock.h>
27 #include <linux/device.h>
28 #include <linux/of_device.h>
29 #include <linux/of_address.h>
30 #include <linux/platform_device.h>
31 #include <linux/libata.h>
32 #include <linux/ahci_platform.h>
33 #include <linux/interrupt.h>
34 #include <linux/delay.h>
35 #include <linux/export.h>
38 #define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
39 #define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
40 #define SERDES_CR_CTL 0x80a0
41 #define SERDES_CR_ADDR 0x80a1
42 #define SERDES_CR_DATA 0x80a2
43 #define CR_BUSY 0x0001
44 #define CR_START 0x0001
45 #define CR_WR_RDN 0x0002
46 #define CPHY_RX_INPUT_STS 0x2002
47 #define CPHY_SATA_OVERRIDE 0x4000
48 #define CPHY_OVERRIDE 0x2005
49 #define SPHY_LANE 0x100
50 #define SPHY_HALF_RATE 0x0001
51 #define CPHY_SATA_DPLL_MODE 0x0700
52 #define CPHY_SATA_DPLL_SHIFT 8
53 #define CPHY_SATA_DPLL_RESET (1 << 11)
54 #define CPHY_PHY_COUNT 6
55 #define CPHY_LANE_COUNT 4
56 #define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
58 static DEFINE_SPINLOCK(cphy_lock
);
59 /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
60 * sata ports to their phys and then to their lanes within the phys
62 struct phy_lane_info
{
63 void __iomem
*phy_base
;
67 static struct phy_lane_info port_data
[CPHY_PORT_COUNT
];
69 static u32
__combo_phy_reg_read(u8 sata_port
, u32 addr
)
72 u8 dev
= port_data
[sata_port
].phy_devs
;
73 spin_lock(&cphy_lock
);
74 writel(CPHY_MAP(dev
, addr
), port_data
[sata_port
].phy_base
+ 0x800);
75 data
= readl(port_data
[sata_port
].phy_base
+ CPHY_ADDR(addr
));
76 spin_unlock(&cphy_lock
);
80 static void __combo_phy_reg_write(u8 sata_port
, u32 addr
, u32 data
)
82 u8 dev
= port_data
[sata_port
].phy_devs
;
83 spin_lock(&cphy_lock
);
84 writel(CPHY_MAP(dev
, addr
), port_data
[sata_port
].phy_base
+ 0x800);
85 writel(data
, port_data
[sata_port
].phy_base
+ CPHY_ADDR(addr
));
86 spin_unlock(&cphy_lock
);
89 static void combo_phy_wait_for_ready(u8 sata_port
)
91 while (__combo_phy_reg_read(sata_port
, SERDES_CR_CTL
) & CR_BUSY
)
95 static u32
combo_phy_read(u8 sata_port
, u32 addr
)
97 combo_phy_wait_for_ready(sata_port
);
98 __combo_phy_reg_write(sata_port
, SERDES_CR_ADDR
, addr
);
99 __combo_phy_reg_write(sata_port
, SERDES_CR_CTL
, CR_START
);
100 combo_phy_wait_for_ready(sata_port
);
101 return __combo_phy_reg_read(sata_port
, SERDES_CR_DATA
);
104 static void combo_phy_write(u8 sata_port
, u32 addr
, u32 data
)
106 combo_phy_wait_for_ready(sata_port
);
107 __combo_phy_reg_write(sata_port
, SERDES_CR_ADDR
, addr
);
108 __combo_phy_reg_write(sata_port
, SERDES_CR_DATA
, data
);
109 __combo_phy_reg_write(sata_port
, SERDES_CR_CTL
, CR_WR_RDN
| CR_START
);
112 static void highbank_cphy_disable_overrides(u8 sata_port
)
114 u8 lane
= port_data
[sata_port
].lane_mapping
;
116 if (unlikely(port_data
[sata_port
].phy_base
== NULL
))
118 tmp
= combo_phy_read(sata_port
, CPHY_RX_INPUT_STS
+ lane
* SPHY_LANE
);
119 tmp
&= ~CPHY_SATA_OVERRIDE
;
120 combo_phy_write(sata_port
, CPHY_OVERRIDE
+ lane
* SPHY_LANE
, tmp
);
123 static void cphy_override_rx_mode(u8 sata_port
, u32 val
)
125 u8 lane
= port_data
[sata_port
].lane_mapping
;
127 tmp
= combo_phy_read(sata_port
, CPHY_RX_INPUT_STS
+ lane
* SPHY_LANE
);
128 tmp
&= ~CPHY_SATA_OVERRIDE
;
129 combo_phy_write(sata_port
, CPHY_OVERRIDE
+ lane
* SPHY_LANE
, tmp
);
131 tmp
|= CPHY_SATA_OVERRIDE
;
132 combo_phy_write(sata_port
, CPHY_OVERRIDE
+ lane
* SPHY_LANE
, tmp
);
134 tmp
&= ~CPHY_SATA_DPLL_MODE
;
135 tmp
|= val
<< CPHY_SATA_DPLL_SHIFT
;
136 combo_phy_write(sata_port
, CPHY_OVERRIDE
+ lane
* SPHY_LANE
, tmp
);
138 tmp
|= CPHY_SATA_DPLL_RESET
;
139 combo_phy_write(sata_port
, CPHY_OVERRIDE
+ lane
* SPHY_LANE
, tmp
);
141 tmp
&= ~CPHY_SATA_DPLL_RESET
;
142 combo_phy_write(sata_port
, CPHY_OVERRIDE
+ lane
* SPHY_LANE
, tmp
);
147 static void highbank_cphy_override_lane(u8 sata_port
)
149 u8 lane
= port_data
[sata_port
].lane_mapping
;
152 if (unlikely(port_data
[sata_port
].phy_base
== NULL
))
155 tmp
= combo_phy_read(sata_port
, CPHY_RX_INPUT_STS
+
157 } while ((tmp
& SPHY_HALF_RATE
) && (k
++ < 1000));
158 cphy_override_rx_mode(sata_port
, 3);
161 static int highbank_initialize_phys(struct device
*dev
, void __iomem
*addr
)
163 struct device_node
*sata_node
= dev
->of_node
;
164 int phy_count
= 0, phy
, port
= 0;
165 void __iomem
*cphy_base
[CPHY_PHY_COUNT
];
166 struct device_node
*phy_nodes
[CPHY_PHY_COUNT
];
167 memset(port_data
, 0, sizeof(struct phy_lane_info
) * CPHY_PORT_COUNT
);
168 memset(phy_nodes
, 0, sizeof(struct device_node
*) * CPHY_PHY_COUNT
);
172 struct of_phandle_args phy_data
;
173 if (of_parse_phandle_with_args(sata_node
,
174 "calxeda,port-phys", "#phy-cells",
177 for (phy
= 0; phy
< phy_count
; phy
++) {
178 if (phy_nodes
[phy
] == phy_data
.np
)
181 if (phy_nodes
[phy
] == NULL
) {
182 phy_nodes
[phy
] = phy_data
.np
;
183 cphy_base
[phy
] = of_iomap(phy_nodes
[phy
], 0);
184 if (cphy_base
[phy
] == NULL
) {
189 port_data
[port
].lane_mapping
= phy_data
.args
[0];
190 of_property_read_u32(phy_nodes
[phy
], "phydev", &tmp
);
191 port_data
[port
].phy_devs
= tmp
;
192 port_data
[port
].phy_base
= cphy_base
[phy
];
193 of_node_put(phy_data
.np
);
195 } while (port
< CPHY_PORT_COUNT
);
199 static int ahci_highbank_hardreset(struct ata_link
*link
, unsigned int *class,
200 unsigned long deadline
)
202 const unsigned long *timing
= sata_ehc_deb_timing(&link
->eh_context
);
203 struct ata_port
*ap
= link
->ap
;
204 struct ahci_port_priv
*pp
= ap
->private_data
;
205 u8
*d2h_fis
= pp
->rx_fis
+ RX_FIS_D2H_REG
;
206 struct ata_taskfile tf
;
212 ahci_stop_engine(ap
);
214 /* clear D2H reception area to properly wait for D2H FIS */
215 ata_tf_init(link
->device
, &tf
);
216 tf
.command
= ATA_BUSY
;
217 ata_tf_to_fis(&tf
, 0, 0, d2h_fis
);
220 highbank_cphy_disable_overrides(link
->ap
->port_no
);
221 rc
= sata_link_hardreset(link
, timing
, deadline
, &online
, NULL
);
222 highbank_cphy_override_lane(link
->ap
->port_no
);
224 /* If the status is 1, we are connected, but the link did not
225 * come up. So retry resetting the link again.
227 if (sata_scr_read(link
, SCR_STATUS
, &sstatus
))
229 if (!(sstatus
& 0x3))
231 } while (!online
&& retry
--);
233 ahci_start_engine(ap
);
236 *class = ahci_dev_classify(ap
);
241 static struct ata_port_operations ahci_highbank_ops
= {
242 .inherits
= &ahci_ops
,
243 .hardreset
= ahci_highbank_hardreset
,
246 static const struct ata_port_info ahci_highbank_port_info
= {
247 .flags
= AHCI_FLAG_COMMON
,
248 .pio_mask
= ATA_PIO4
,
249 .udma_mask
= ATA_UDMA6
,
250 .port_ops
= &ahci_highbank_ops
,
253 static struct scsi_host_template ahci_highbank_platform_sht
= {
254 AHCI_SHT("highbank-ahci"),
257 static const struct of_device_id ahci_of_match
[] = {
258 { .compatible
= "calxeda,hb-ahci" },
261 MODULE_DEVICE_TABLE(of
, ahci_of_match
);
263 static int ahci_highbank_probe(struct platform_device
*pdev
)
265 struct device
*dev
= &pdev
->dev
;
266 struct ahci_host_priv
*hpriv
;
267 struct ata_host
*host
;
268 struct resource
*mem
;
273 struct ata_port_info pi
= ahci_highbank_port_info
;
274 const struct ata_port_info
*ppi
[] = { &pi
, NULL
};
276 mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
278 dev_err(dev
, "no mmio space\n");
282 irq
= platform_get_irq(pdev
, 0);
284 dev_err(dev
, "no irq\n");
288 hpriv
= devm_kzalloc(dev
, sizeof(*hpriv
), GFP_KERNEL
);
290 dev_err(dev
, "can't alloc ahci_host_priv\n");
294 hpriv
->flags
|= (unsigned long)pi
.private_data
;
296 hpriv
->mmio
= devm_ioremap(dev
, mem
->start
, resource_size(mem
));
298 dev_err(dev
, "can't map %pR\n", mem
);
302 rc
= highbank_initialize_phys(dev
, hpriv
->mmio
);
307 ahci_save_initial_config(dev
, hpriv
, 0, 0);
310 if (hpriv
->cap
& HOST_CAP_NCQ
)
311 pi
.flags
|= ATA_FLAG_NCQ
;
313 if (hpriv
->cap
& HOST_CAP_PMP
)
314 pi
.flags
|= ATA_FLAG_PMP
;
316 ahci_set_em_messages(hpriv
, &pi
);
318 /* CAP.NP sometimes indicate the index of the last enabled
319 * port, at other times, that of the last possible port, so
320 * determining the maximum port number requires looking at
321 * both CAP.NP and port_map.
323 n_ports
= max(ahci_nr_ports(hpriv
->cap
), fls(hpriv
->port_map
));
325 host
= ata_host_alloc_pinfo(dev
, ppi
, n_ports
);
331 host
->private_data
= hpriv
;
333 if (!(hpriv
->cap
& HOST_CAP_SSS
) || ahci_ignore_sss
)
334 host
->flags
|= ATA_HOST_PARALLEL_SCAN
;
336 if (pi
.flags
& ATA_FLAG_EM
)
339 for (i
= 0; i
< host
->n_ports
; i
++) {
340 struct ata_port
*ap
= host
->ports
[i
];
342 ata_port_desc(ap
, "mmio %pR", mem
);
343 ata_port_desc(ap
, "port 0x%x", 0x100 + ap
->port_no
* 0x80);
345 /* set enclosure management message type */
346 if (ap
->flags
& ATA_FLAG_EM
)
347 ap
->em_message_type
= hpriv
->em_msg_type
;
349 /* disabled/not-implemented port */
350 if (!(hpriv
->port_map
& (1 << i
)))
351 ap
->ops
= &ata_dummy_port_ops
;
354 rc
= ahci_reset_controller(host
);
358 ahci_init_controller(host
);
359 ahci_print_info(host
, "platform");
361 rc
= ata_host_activate(host
, irq
, ahci_interrupt
, 0,
362 &ahci_highbank_platform_sht
);
371 #ifdef CONFIG_PM_SLEEP
372 static int ahci_highbank_suspend(struct device
*dev
)
374 struct ata_host
*host
= dev_get_drvdata(dev
);
375 struct ahci_host_priv
*hpriv
= host
->private_data
;
376 void __iomem
*mmio
= hpriv
->mmio
;
380 if (hpriv
->flags
& AHCI_HFLAG_NO_SUSPEND
) {
381 dev_err(dev
, "firmware update required for suspend/resume\n");
386 * AHCI spec rev1.1 section 8.3.3:
387 * Software must disable interrupts prior to requesting a
388 * transition of the HBA to D3 state.
390 ctl
= readl(mmio
+ HOST_CTL
);
392 writel(ctl
, mmio
+ HOST_CTL
);
393 readl(mmio
+ HOST_CTL
); /* flush */
395 rc
= ata_host_suspend(host
, PMSG_SUSPEND
);
402 static int ahci_highbank_resume(struct device
*dev
)
404 struct ata_host
*host
= dev_get_drvdata(dev
);
407 if (dev
->power
.power_state
.event
== PM_EVENT_SUSPEND
) {
408 rc
= ahci_reset_controller(host
);
412 ahci_init_controller(host
);
415 ata_host_resume(host
);
421 SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops
,
422 ahci_highbank_suspend
, ahci_highbank_resume
);
424 static struct platform_driver ahci_highbank_driver
= {
425 .remove
= ata_platform_remove_one
,
427 .name
= "highbank-ahci",
428 .owner
= THIS_MODULE
,
429 .of_match_table
= ahci_of_match
,
430 .pm
= &ahci_highbank_pm_ops
,
432 .probe
= ahci_highbank_probe
,
435 module_platform_driver(ahci_highbank_driver
);
437 MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
438 MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
439 MODULE_LICENSE("GPL");
440 MODULE_ALIAS("sata:highbank");