2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/export.h>
24 #include <asm/mipsregs.h>
25 #include <asm/watch.h>
27 #include <asm/spram.h>
28 #include <asm/uaccess.h>
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
37 void (*cpu_wait
)(void);
38 EXPORT_SYMBOL(cpu_wait
);
40 static void r3081_wait(void)
42 unsigned long cfg
= read_c0_conf();
43 write_c0_conf(cfg
| R30XX_CONF_HALT
);
46 static void r39xx_wait(void)
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT
);
54 extern void r4k_wait(void);
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
63 void r4k_wait_irqoff(void)
67 __asm__(" .set push \n"
72 __asm__(" .globl __pastwait \n"
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
80 static void rm7k_wait_irqoff(void)
90 " mtc0 $1, $12 # stalls until W stage \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
102 static void au1k_wait(void)
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
115 : : "r" (au1k_wait
));
118 static int __initdata nowait
;
120 static int __init
wait_disable(char *s
)
127 __setup("nowait", wait_disable
);
129 static int __cpuinitdata mips_fpu_disabled
;
131 static int __init
fpu_disable(char *s
)
133 cpu_data
[0].options
&= ~MIPS_CPU_FPU
;
134 mips_fpu_disabled
= 1;
139 __setup("nofpu", fpu_disable
);
141 int __cpuinitdata mips_dsp_disabled
;
143 static int __init
dsp_disable(char *s
)
145 cpu_data
[0].ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
146 mips_dsp_disabled
= 1;
151 __setup("nodsp", dsp_disable
);
153 void __init
check_wait(void)
155 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
158 printk("Wait instruction disabled.\n");
162 switch (c
->cputype
) {
165 cpu_wait
= r3081_wait
;
168 cpu_wait
= r39xx_wait
;
171 /* case CPU_R4300: */
189 case CPU_CAVIUM_OCTEON
:
190 case CPU_CAVIUM_OCTEON_PLUS
:
191 case CPU_CAVIUM_OCTEON2
:
200 cpu_wait
= rm7k_wait_irqoff
;
209 if (read_c0_config7() & MIPS_CONF7_WII
)
210 cpu_wait
= r4k_wait_irqoff
;
215 if ((c
->processor_id
& 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
216 cpu_wait
= r4k_wait_irqoff
;
220 cpu_wait
= r4k_wait_irqoff
;
223 cpu_wait
= au1k_wait
;
227 * WAIT on Rev1.0 has E1, E2, E3 and E16.
228 * WAIT on Rev2.0 and Rev3.0 has E16.
229 * Rev3.1 WAIT is nop, why bother
231 if ((c
->processor_id
& 0xff) <= 0x64)
235 * Another rev is incremeting c0_count at a reduced clock
236 * rate while in WAIT mode. So we basically have the choice
237 * between using the cp0 timer as clocksource or avoiding
238 * the WAIT instruction. Until more details are known,
239 * disable the use of WAIT for 20Kc entirely.
244 if ((c
->processor_id
& 0x00ff) >= 0x40)
252 static inline void check_errata(void)
254 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
256 switch (c
->cputype
) {
259 * Erratum "RPS May Cause Incorrect Instruction Execution"
260 * This code only handles VPE0, any SMP/SMTC/RTOS code
261 * making use of VPE1 will be responsable for that VPE.
263 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
264 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
271 void __init
check_bugs32(void)
277 * Probe whether cpu has config register by trying to play with
278 * alternate cache bit and see whether it matters.
279 * It's used by cpu_probe to distinguish between R3000A and R3081.
281 static inline int cpu_has_confreg(void)
283 #ifdef CONFIG_CPU_R3000
284 extern unsigned long r3k_cache_size(unsigned long);
285 unsigned long size1
, size2
;
286 unsigned long cfg
= read_c0_conf();
288 size1
= r3k_cache_size(ST0_ISC
);
289 write_c0_conf(cfg
^ R30XX_CONF_AC
);
290 size2
= r3k_cache_size(ST0_ISC
);
292 return size1
!= size2
;
298 static inline void set_elf_platform(int cpu
, const char *plat
)
301 __elf_platform
= plat
;
305 * Get the FPU Implementation/Revision.
307 static inline unsigned long cpu_get_fpu_id(void)
309 unsigned long tmp
, fpu_id
;
311 tmp
= read_c0_status();
313 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
314 write_c0_status(tmp
);
319 * Check the CPU has an FPU the official way.
321 static inline int __cpu_has_fpu(void)
323 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
326 static inline void cpu_probe_vmbits(struct cpuinfo_mips
*c
)
328 #ifdef __NEED_VMBITS_PROBE
329 write_c0_entryhi(0x3fffffffffffe000ULL
);
330 back_to_back_c0_hazard();
331 c
->vmbits
= fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL
);
335 static void __cpuinit
set_isa(struct cpuinfo_mips
*c
, unsigned int isa
)
338 case MIPS_CPU_ISA_M64R2
:
339 c
->isa_level
|= MIPS_CPU_ISA_M32R2
| MIPS_CPU_ISA_M64R2
;
340 case MIPS_CPU_ISA_M64R1
:
341 c
->isa_level
|= MIPS_CPU_ISA_M32R1
| MIPS_CPU_ISA_M64R1
;
343 c
->isa_level
|= MIPS_CPU_ISA_V
;
344 case MIPS_CPU_ISA_IV
:
345 c
->isa_level
|= MIPS_CPU_ISA_IV
;
346 case MIPS_CPU_ISA_III
:
347 c
->isa_level
|= MIPS_CPU_ISA_I
| MIPS_CPU_ISA_II
|
351 case MIPS_CPU_ISA_M32R2
:
352 c
->isa_level
|= MIPS_CPU_ISA_M32R2
;
353 case MIPS_CPU_ISA_M32R1
:
354 c
->isa_level
|= MIPS_CPU_ISA_M32R1
;
355 case MIPS_CPU_ISA_II
:
356 c
->isa_level
|= MIPS_CPU_ISA_II
;
358 c
->isa_level
|= MIPS_CPU_ISA_I
;
363 static char unknown_isa
[] __cpuinitdata
= KERN_ERR \
364 "Unsupported ISA type, c0.config0: %d.";
366 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
368 unsigned int config0
;
371 config0
= read_c0_config();
373 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
374 c
->options
|= MIPS_CPU_TLB
;
375 isa
= (config0
& MIPS_CONF_AT
) >> 13;
378 switch ((config0
& MIPS_CONF_AR
) >> 10) {
380 set_isa(c
, MIPS_CPU_ISA_M32R1
);
383 set_isa(c
, MIPS_CPU_ISA_M32R2
);
390 switch ((config0
& MIPS_CONF_AR
) >> 10) {
392 set_isa(c
, MIPS_CPU_ISA_M64R1
);
395 set_isa(c
, MIPS_CPU_ISA_M64R2
);
405 return config0
& MIPS_CONF_M
;
408 panic(unknown_isa
, config0
);
411 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
413 unsigned int config1
;
415 config1
= read_c0_config1();
417 if (config1
& MIPS_CONF1_MD
)
418 c
->ases
|= MIPS_ASE_MDMX
;
419 if (config1
& MIPS_CONF1_WR
)
420 c
->options
|= MIPS_CPU_WATCH
;
421 if (config1
& MIPS_CONF1_CA
)
422 c
->ases
|= MIPS_ASE_MIPS16
;
423 if (config1
& MIPS_CONF1_EP
)
424 c
->options
|= MIPS_CPU_EJTAG
;
425 if (config1
& MIPS_CONF1_FP
) {
426 c
->options
|= MIPS_CPU_FPU
;
427 c
->options
|= MIPS_CPU_32FPR
;
430 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
432 return config1
& MIPS_CONF_M
;
435 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
437 unsigned int config2
;
439 config2
= read_c0_config2();
441 if (config2
& MIPS_CONF2_SL
)
442 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
444 return config2
& MIPS_CONF_M
;
447 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
449 unsigned int config3
;
451 config3
= read_c0_config3();
453 if (config3
& MIPS_CONF3_SM
) {
454 c
->ases
|= MIPS_ASE_SMARTMIPS
;
455 c
->options
|= MIPS_CPU_RIXI
;
457 if (config3
& MIPS_CONF3_RXI
)
458 c
->options
|= MIPS_CPU_RIXI
;
459 if (config3
& MIPS_CONF3_DSP
)
460 c
->ases
|= MIPS_ASE_DSP
;
461 if (config3
& MIPS_CONF3_DSP2P
)
462 c
->ases
|= MIPS_ASE_DSP2P
;
463 if (config3
& MIPS_CONF3_VINT
)
464 c
->options
|= MIPS_CPU_VINT
;
465 if (config3
& MIPS_CONF3_VEIC
)
466 c
->options
|= MIPS_CPU_VEIC
;
467 if (config3
& MIPS_CONF3_MT
)
468 c
->ases
|= MIPS_ASE_MIPSMT
;
469 if (config3
& MIPS_CONF3_ULRI
)
470 c
->options
|= MIPS_CPU_ULRI
;
471 if (config3
& MIPS_CONF3_ISA
)
472 c
->options
|= MIPS_CPU_MICROMIPS
;
473 if (config3
& MIPS_CONF3_VZ
)
474 c
->ases
|= MIPS_ASE_VZ
;
476 return config3
& MIPS_CONF_M
;
479 static inline unsigned int decode_config4(struct cpuinfo_mips
*c
)
481 unsigned int config4
;
483 config4
= read_c0_config4();
485 if ((config4
& MIPS_CONF4_MMUEXTDEF
) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
487 c
->tlbsize
+= (config4
& MIPS_CONF4_MMUSIZEEXT
) * 0x40;
489 c
->kscratch_mask
= (config4
>> 16) & 0xff;
491 return config4
& MIPS_CONF_M
;
494 static void __cpuinit
decode_configs(struct cpuinfo_mips
*c
)
498 /* MIPS32 or MIPS64 compliant CPU. */
499 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
500 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
502 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
504 ok
= decode_config0(c
); /* Read Config registers. */
505 BUG_ON(!ok
); /* Arch spec violation! */
507 ok
= decode_config1(c
);
509 ok
= decode_config2(c
);
511 ok
= decode_config3(c
);
513 ok
= decode_config4(c
);
515 mips_probe_watch_registers(c
);
518 c
->core
= read_c0_ebase() & 0x3ff;
521 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
524 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
526 switch (c
->processor_id
& 0xff00) {
528 c
->cputype
= CPU_R2000
;
529 __cpu_name
[cpu
] = "R2000";
530 set_isa(c
, MIPS_CPU_ISA_I
);
531 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
534 c
->options
|= MIPS_CPU_FPU
;
538 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
) {
539 if (cpu_has_confreg()) {
540 c
->cputype
= CPU_R3081E
;
541 __cpu_name
[cpu
] = "R3081";
543 c
->cputype
= CPU_R3000A
;
544 __cpu_name
[cpu
] = "R3000A";
547 c
->cputype
= CPU_R3000
;
548 __cpu_name
[cpu
] = "R3000";
550 set_isa(c
, MIPS_CPU_ISA_I
);
551 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
554 c
->options
|= MIPS_CPU_FPU
;
558 if (read_c0_config() & CONF_SC
) {
559 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
560 c
->cputype
= CPU_R4400PC
;
561 __cpu_name
[cpu
] = "R4400PC";
563 c
->cputype
= CPU_R4000PC
;
564 __cpu_name
[cpu
] = "R4000PC";
567 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
568 c
->cputype
= CPU_R4400SC
;
569 __cpu_name
[cpu
] = "R4400SC";
571 c
->cputype
= CPU_R4000SC
;
572 __cpu_name
[cpu
] = "R4000SC";
576 set_isa(c
, MIPS_CPU_ISA_III
);
577 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
578 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
582 case PRID_IMP_VR41XX
:
583 set_isa(c
, MIPS_CPU_ISA_III
);
584 c
->options
= R4K_OPTS
;
586 switch (c
->processor_id
& 0xf0) {
587 case PRID_REV_VR4111
:
588 c
->cputype
= CPU_VR4111
;
589 __cpu_name
[cpu
] = "NEC VR4111";
591 case PRID_REV_VR4121
:
592 c
->cputype
= CPU_VR4121
;
593 __cpu_name
[cpu
] = "NEC VR4121";
595 case PRID_REV_VR4122
:
596 if ((c
->processor_id
& 0xf) < 0x3) {
597 c
->cputype
= CPU_VR4122
;
598 __cpu_name
[cpu
] = "NEC VR4122";
600 c
->cputype
= CPU_VR4181A
;
601 __cpu_name
[cpu
] = "NEC VR4181A";
604 case PRID_REV_VR4130
:
605 if ((c
->processor_id
& 0xf) < 0x4) {
606 c
->cputype
= CPU_VR4131
;
607 __cpu_name
[cpu
] = "NEC VR4131";
609 c
->cputype
= CPU_VR4133
;
610 c
->options
|= MIPS_CPU_LLSC
;
611 __cpu_name
[cpu
] = "NEC VR4133";
615 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
616 c
->cputype
= CPU_VR41XX
;
617 __cpu_name
[cpu
] = "NEC Vr41xx";
622 c
->cputype
= CPU_R4300
;
623 __cpu_name
[cpu
] = "R4300";
624 set_isa(c
, MIPS_CPU_ISA_III
);
625 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
630 c
->cputype
= CPU_R4600
;
631 __cpu_name
[cpu
] = "R4600";
632 set_isa(c
, MIPS_CPU_ISA_III
);
633 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
640 * This processor doesn't have an MMU, so it's not
641 * "real easy" to run Linux on it. It is left purely
642 * for documentation. Commented out because it shares
643 * it's c0_prid id number with the TX3900.
645 c
->cputype
= CPU_R4650
;
646 __cpu_name
[cpu
] = "R4650";
647 set_isa(c
, MIPS_CPU_ISA_III
);
648 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
653 set_isa(c
, MIPS_CPU_ISA_I
);
654 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
656 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
657 c
->cputype
= CPU_TX3927
;
658 __cpu_name
[cpu
] = "TX3927";
661 switch (c
->processor_id
& 0xff) {
662 case PRID_REV_TX3912
:
663 c
->cputype
= CPU_TX3912
;
664 __cpu_name
[cpu
] = "TX3912";
667 case PRID_REV_TX3922
:
668 c
->cputype
= CPU_TX3922
;
669 __cpu_name
[cpu
] = "TX3922";
676 c
->cputype
= CPU_R4700
;
677 __cpu_name
[cpu
] = "R4700";
678 set_isa(c
, MIPS_CPU_ISA_III
);
679 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
684 c
->cputype
= CPU_TX49XX
;
685 __cpu_name
[cpu
] = "R49XX";
686 set_isa(c
, MIPS_CPU_ISA_III
);
687 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
688 if (!(c
->processor_id
& 0x08))
689 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
693 c
->cputype
= CPU_R5000
;
694 __cpu_name
[cpu
] = "R5000";
695 set_isa(c
, MIPS_CPU_ISA_IV
);
696 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
701 c
->cputype
= CPU_R5432
;
702 __cpu_name
[cpu
] = "R5432";
703 set_isa(c
, MIPS_CPU_ISA_IV
);
704 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
705 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
709 c
->cputype
= CPU_R5500
;
710 __cpu_name
[cpu
] = "R5500";
711 set_isa(c
, MIPS_CPU_ISA_IV
);
712 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
713 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
716 case PRID_IMP_NEVADA
:
717 c
->cputype
= CPU_NEVADA
;
718 __cpu_name
[cpu
] = "Nevada";
719 set_isa(c
, MIPS_CPU_ISA_IV
);
720 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
721 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
725 c
->cputype
= CPU_R6000
;
726 __cpu_name
[cpu
] = "R6000";
727 set_isa(c
, MIPS_CPU_ISA_II
);
728 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
732 case PRID_IMP_R6000A
:
733 c
->cputype
= CPU_R6000A
;
734 __cpu_name
[cpu
] = "R6000A";
735 set_isa(c
, MIPS_CPU_ISA_II
);
736 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
740 case PRID_IMP_RM7000
:
741 c
->cputype
= CPU_RM7000
;
742 __cpu_name
[cpu
] = "RM7000";
743 set_isa(c
, MIPS_CPU_ISA_IV
);
744 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
747 * Undocumented RM7000: Bit 29 in the info register of
748 * the RM7000 v2.0 indicates if the TLB has 48 or 64
751 * 29 1 => 64 entry JTLB
754 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
756 case PRID_IMP_RM9000
:
757 c
->cputype
= CPU_RM9000
;
758 __cpu_name
[cpu
] = "RM9000";
759 set_isa(c
, MIPS_CPU_ISA_IV
);
760 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
763 * Bit 29 in the info register of the RM9000
764 * indicates if the TLB has 48 or 64 entries.
766 * 29 1 => 64 entry JTLB
769 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
772 c
->cputype
= CPU_R8000
;
773 __cpu_name
[cpu
] = "RM8000";
774 set_isa(c
, MIPS_CPU_ISA_IV
);
775 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
776 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
778 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
780 case PRID_IMP_R10000
:
781 c
->cputype
= CPU_R10000
;
782 __cpu_name
[cpu
] = "R10000";
783 set_isa(c
, MIPS_CPU_ISA_IV
);
784 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
785 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
786 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
790 case PRID_IMP_R12000
:
791 c
->cputype
= CPU_R12000
;
792 __cpu_name
[cpu
] = "R12000";
793 set_isa(c
, MIPS_CPU_ISA_IV
);
794 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
795 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
796 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
800 case PRID_IMP_R14000
:
801 c
->cputype
= CPU_R14000
;
802 __cpu_name
[cpu
] = "R14000";
803 set_isa(c
, MIPS_CPU_ISA_IV
);
804 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
805 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
806 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
810 case PRID_IMP_LOONGSON2
:
811 c
->cputype
= CPU_LOONGSON2
;
812 __cpu_name
[cpu
] = "ICT Loongson-2";
814 switch (c
->processor_id
& PRID_REV_MASK
) {
815 case PRID_REV_LOONGSON2E
:
816 set_elf_platform(cpu
, "loongson2e");
818 case PRID_REV_LOONGSON2F
:
819 set_elf_platform(cpu
, "loongson2f");
823 set_isa(c
, MIPS_CPU_ISA_III
);
824 c
->options
= R4K_OPTS
|
825 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
829 case PRID_IMP_LOONGSON1
:
832 c
->cputype
= CPU_LOONGSON1
;
834 switch (c
->processor_id
& PRID_REV_MASK
) {
835 case PRID_REV_LOONGSON1B
:
836 __cpu_name
[cpu
] = "Loongson 1B";
844 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
847 switch (c
->processor_id
& 0xff00) {
849 c
->cputype
= CPU_4KC
;
850 __cpu_name
[cpu
] = "MIPS 4Kc";
853 case PRID_IMP_4KECR2
:
854 c
->cputype
= CPU_4KEC
;
855 __cpu_name
[cpu
] = "MIPS 4KEc";
859 c
->cputype
= CPU_4KSC
;
860 __cpu_name
[cpu
] = "MIPS 4KSc";
863 c
->cputype
= CPU_5KC
;
864 __cpu_name
[cpu
] = "MIPS 5Kc";
867 c
->cputype
= CPU_5KE
;
868 __cpu_name
[cpu
] = "MIPS 5KE";
871 c
->cputype
= CPU_20KC
;
872 __cpu_name
[cpu
] = "MIPS 20Kc";
875 c
->cputype
= CPU_24K
;
876 __cpu_name
[cpu
] = "MIPS 24Kc";
879 c
->cputype
= CPU_24K
;
880 __cpu_name
[cpu
] = "MIPS 24KEc";
883 c
->cputype
= CPU_25KF
;
884 __cpu_name
[cpu
] = "MIPS 25Kc";
887 c
->cputype
= CPU_34K
;
888 __cpu_name
[cpu
] = "MIPS 34Kc";
891 c
->cputype
= CPU_74K
;
892 __cpu_name
[cpu
] = "MIPS 74Kc";
895 c
->cputype
= CPU_M14KC
;
896 __cpu_name
[cpu
] = "MIPS M14Kc";
898 case PRID_IMP_M14KEC
:
899 c
->cputype
= CPU_M14KEC
;
900 __cpu_name
[cpu
] = "MIPS M14KEc";
903 c
->cputype
= CPU_1004K
;
904 __cpu_name
[cpu
] = "MIPS 1004Kc";
907 c
->cputype
= CPU_74K
;
908 __cpu_name
[cpu
] = "MIPS 1074Kc";
915 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
918 switch (c
->processor_id
& 0xff00) {
919 case PRID_IMP_AU1_REV1
:
920 case PRID_IMP_AU1_REV2
:
921 c
->cputype
= CPU_ALCHEMY
;
922 switch ((c
->processor_id
>> 24) & 0xff) {
924 __cpu_name
[cpu
] = "Au1000";
927 __cpu_name
[cpu
] = "Au1500";
930 __cpu_name
[cpu
] = "Au1100";
933 __cpu_name
[cpu
] = "Au1550";
936 __cpu_name
[cpu
] = "Au1200";
937 if ((c
->processor_id
& 0xff) == 2)
938 __cpu_name
[cpu
] = "Au1250";
941 __cpu_name
[cpu
] = "Au1210";
944 __cpu_name
[cpu
] = "Au1xxx";
951 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
955 switch (c
->processor_id
& 0xff00) {
957 c
->cputype
= CPU_SB1
;
958 __cpu_name
[cpu
] = "SiByte SB1";
959 /* FPU in pass1 is known to have issues. */
960 if ((c
->processor_id
& 0xff) < 0x02)
961 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
964 c
->cputype
= CPU_SB1A
;
965 __cpu_name
[cpu
] = "SiByte SB1A";
970 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
973 switch (c
->processor_id
& 0xff00) {
974 case PRID_IMP_SR71000
:
975 c
->cputype
= CPU_SR71000
;
976 __cpu_name
[cpu
] = "Sandcraft SR71000";
983 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
986 switch (c
->processor_id
& 0xff00) {
987 case PRID_IMP_PR4450
:
988 c
->cputype
= CPU_PR4450
;
989 __cpu_name
[cpu
] = "Philips PR4450";
990 set_isa(c
, MIPS_CPU_ISA_M32R1
);
995 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
998 switch (c
->processor_id
& 0xff00) {
999 case PRID_IMP_BMIPS32_REV4
:
1000 case PRID_IMP_BMIPS32_REV8
:
1001 c
->cputype
= CPU_BMIPS32
;
1002 __cpu_name
[cpu
] = "Broadcom BMIPS32";
1003 set_elf_platform(cpu
, "bmips32");
1005 case PRID_IMP_BMIPS3300
:
1006 case PRID_IMP_BMIPS3300_ALT
:
1007 case PRID_IMP_BMIPS3300_BUG
:
1008 c
->cputype
= CPU_BMIPS3300
;
1009 __cpu_name
[cpu
] = "Broadcom BMIPS3300";
1010 set_elf_platform(cpu
, "bmips3300");
1012 case PRID_IMP_BMIPS43XX
: {
1013 int rev
= c
->processor_id
& 0xff;
1015 if (rev
>= PRID_REV_BMIPS4380_LO
&&
1016 rev
<= PRID_REV_BMIPS4380_HI
) {
1017 c
->cputype
= CPU_BMIPS4380
;
1018 __cpu_name
[cpu
] = "Broadcom BMIPS4380";
1019 set_elf_platform(cpu
, "bmips4380");
1021 c
->cputype
= CPU_BMIPS4350
;
1022 __cpu_name
[cpu
] = "Broadcom BMIPS4350";
1023 set_elf_platform(cpu
, "bmips4350");
1027 case PRID_IMP_BMIPS5000
:
1028 c
->cputype
= CPU_BMIPS5000
;
1029 __cpu_name
[cpu
] = "Broadcom BMIPS5000";
1030 set_elf_platform(cpu
, "bmips5000");
1031 c
->options
|= MIPS_CPU_ULRI
;
1036 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
1039 switch (c
->processor_id
& 0xff00) {
1040 case PRID_IMP_CAVIUM_CN38XX
:
1041 case PRID_IMP_CAVIUM_CN31XX
:
1042 case PRID_IMP_CAVIUM_CN30XX
:
1043 c
->cputype
= CPU_CAVIUM_OCTEON
;
1044 __cpu_name
[cpu
] = "Cavium Octeon";
1046 case PRID_IMP_CAVIUM_CN58XX
:
1047 case PRID_IMP_CAVIUM_CN56XX
:
1048 case PRID_IMP_CAVIUM_CN50XX
:
1049 case PRID_IMP_CAVIUM_CN52XX
:
1050 c
->cputype
= CPU_CAVIUM_OCTEON_PLUS
;
1051 __cpu_name
[cpu
] = "Cavium Octeon+";
1053 set_elf_platform(cpu
, "octeon");
1055 case PRID_IMP_CAVIUM_CN61XX
:
1056 case PRID_IMP_CAVIUM_CN63XX
:
1057 case PRID_IMP_CAVIUM_CN66XX
:
1058 case PRID_IMP_CAVIUM_CN68XX
:
1059 c
->cputype
= CPU_CAVIUM_OCTEON2
;
1060 __cpu_name
[cpu
] = "Cavium Octeon II";
1061 set_elf_platform(cpu
, "octeon2");
1064 printk(KERN_INFO
"Unknown Octeon chip!\n");
1065 c
->cputype
= CPU_UNKNOWN
;
1070 static inline void cpu_probe_ingenic(struct cpuinfo_mips
*c
, unsigned int cpu
)
1073 /* JZRISC does not implement the CP0 counter. */
1074 c
->options
&= ~MIPS_CPU_COUNTER
;
1075 switch (c
->processor_id
& 0xff00) {
1076 case PRID_IMP_JZRISC
:
1077 c
->cputype
= CPU_JZRISC
;
1078 __cpu_name
[cpu
] = "Ingenic JZRISC";
1081 panic("Unknown Ingenic Processor ID!");
1086 static inline void cpu_probe_netlogic(struct cpuinfo_mips
*c
, int cpu
)
1090 if ((c
->processor_id
& 0xff00) == PRID_IMP_NETLOGIC_AU13XX
) {
1091 c
->cputype
= CPU_ALCHEMY
;
1092 __cpu_name
[cpu
] = "Au1300";
1093 /* following stuff is not for Alchemy */
1097 c
->options
= (MIPS_CPU_TLB
|
1105 switch (c
->processor_id
& 0xff00) {
1106 case PRID_IMP_NETLOGIC_XLP8XX
:
1107 case PRID_IMP_NETLOGIC_XLP3XX
:
1108 c
->cputype
= CPU_XLP
;
1109 __cpu_name
[cpu
] = "Netlogic XLP";
1112 case PRID_IMP_NETLOGIC_XLR732
:
1113 case PRID_IMP_NETLOGIC_XLR716
:
1114 case PRID_IMP_NETLOGIC_XLR532
:
1115 case PRID_IMP_NETLOGIC_XLR308
:
1116 case PRID_IMP_NETLOGIC_XLR532C
:
1117 case PRID_IMP_NETLOGIC_XLR516C
:
1118 case PRID_IMP_NETLOGIC_XLR508C
:
1119 case PRID_IMP_NETLOGIC_XLR308C
:
1120 c
->cputype
= CPU_XLR
;
1121 __cpu_name
[cpu
] = "Netlogic XLR";
1124 case PRID_IMP_NETLOGIC_XLS608
:
1125 case PRID_IMP_NETLOGIC_XLS408
:
1126 case PRID_IMP_NETLOGIC_XLS404
:
1127 case PRID_IMP_NETLOGIC_XLS208
:
1128 case PRID_IMP_NETLOGIC_XLS204
:
1129 case PRID_IMP_NETLOGIC_XLS108
:
1130 case PRID_IMP_NETLOGIC_XLS104
:
1131 case PRID_IMP_NETLOGIC_XLS616B
:
1132 case PRID_IMP_NETLOGIC_XLS608B
:
1133 case PRID_IMP_NETLOGIC_XLS416B
:
1134 case PRID_IMP_NETLOGIC_XLS412B
:
1135 case PRID_IMP_NETLOGIC_XLS408B
:
1136 case PRID_IMP_NETLOGIC_XLS404B
:
1137 c
->cputype
= CPU_XLR
;
1138 __cpu_name
[cpu
] = "Netlogic XLS";
1142 pr_info("Unknown Netlogic chip id [%02x]!\n",
1144 c
->cputype
= CPU_XLR
;
1148 if (c
->cputype
== CPU_XLP
) {
1149 set_isa(c
, MIPS_CPU_ISA_M64R2
);
1150 c
->options
|= (MIPS_CPU_FPU
| MIPS_CPU_ULRI
| MIPS_CPU_MCHECK
);
1151 /* This will be updated again after all threads are woken up */
1152 c
->tlbsize
= ((read_c0_config6() >> 16) & 0xffff) + 1;
1154 set_isa(c
, MIPS_CPU_ISA_M64R1
);
1155 c
->tlbsize
= ((read_c0_config1() >> 25) & 0x3f) + 1;
1160 /* For use by uaccess.h */
1162 EXPORT_SYMBOL(__ua_limit
);
1165 const char *__cpu_name
[NR_CPUS
];
1166 const char *__elf_platform
;
1168 __cpuinit
void cpu_probe(void)
1170 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1171 unsigned int cpu
= smp_processor_id();
1173 c
->processor_id
= PRID_IMP_UNKNOWN
;
1174 c
->fpu_id
= FPIR_IMP_NONE
;
1175 c
->cputype
= CPU_UNKNOWN
;
1177 c
->processor_id
= read_c0_prid();
1178 switch (c
->processor_id
& 0xff0000) {
1179 case PRID_COMP_LEGACY
:
1180 cpu_probe_legacy(c
, cpu
);
1182 case PRID_COMP_MIPS
:
1183 cpu_probe_mips(c
, cpu
);
1185 case PRID_COMP_ALCHEMY
:
1186 cpu_probe_alchemy(c
, cpu
);
1188 case PRID_COMP_SIBYTE
:
1189 cpu_probe_sibyte(c
, cpu
);
1191 case PRID_COMP_BROADCOM
:
1192 cpu_probe_broadcom(c
, cpu
);
1194 case PRID_COMP_SANDCRAFT
:
1195 cpu_probe_sandcraft(c
, cpu
);
1198 cpu_probe_nxp(c
, cpu
);
1200 case PRID_COMP_CAVIUM
:
1201 cpu_probe_cavium(c
, cpu
);
1203 case PRID_COMP_INGENIC
:
1204 cpu_probe_ingenic(c
, cpu
);
1206 case PRID_COMP_NETLOGIC
:
1207 cpu_probe_netlogic(c
, cpu
);
1211 BUG_ON(!__cpu_name
[cpu
]);
1212 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
1215 * Platform code can force the cpu type to optimize code
1216 * generation. In that case be sure the cpu type is correctly
1217 * manually setup otherwise it could trigger some nasty bugs.
1219 BUG_ON(current_cpu_type() != c
->cputype
);
1221 if (mips_fpu_disabled
)
1222 c
->options
&= ~MIPS_CPU_FPU
;
1224 if (mips_dsp_disabled
)
1225 c
->ases
&= ~(MIPS_ASE_DSP
| MIPS_ASE_DSP2P
);
1227 if (c
->options
& MIPS_CPU_FPU
) {
1228 c
->fpu_id
= cpu_get_fpu_id();
1230 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
1231 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
1232 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
1233 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
1234 if (c
->fpu_id
& MIPS_FPIR_3D
)
1235 c
->ases
|= MIPS_ASE_MIPS3D
;
1239 if (cpu_has_mips_r2
) {
1240 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1241 /* R2 has Performance Counter Interrupt indicator */
1242 c
->options
|= MIPS_CPU_PCI
;
1247 cpu_probe_vmbits(c
);
1251 __ua_limit
= ~((1ull << cpu_vmbits
) - 1);
1255 __cpuinit
void cpu_report(void)
1257 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1259 printk(KERN_INFO
"CPU revision is: %08x (%s)\n",
1260 c
->processor_id
, cpu_name_string());
1261 if (c
->options
& MIPS_CPU_FPU
)
1262 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);