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igb: Enable auto-crossover during forced operation on 82580 and above.
[linux-2.6/libata-dev.git] / drivers / net / ethernet / intel / igb / e1000_phy.c
blobfe76004aca4e7a8464811629d9cfec18dac2f8b2
1 /*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/if_ether.h>
29 #include <linux/delay.h>
30
31 #include "e1000_mac.h"
32 #include "e1000_phy.h"
33
34 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
35 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
36 u16 *phy_ctrl);
37 static s32 igb_wait_autoneg(struct e1000_hw *hw);
38 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
39
40 /* Cable length tables */
41 static const u16 e1000_m88_cable_length_table[] =
42 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
43 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
44 (sizeof(e1000_m88_cable_length_table) / \
45 sizeof(e1000_m88_cable_length_table[0]))
46
47 static const u16 e1000_igp_2_cable_length_table[] =
48 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
49 0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
50 6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
51 21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
52 40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
53 60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
54 83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
55 104, 109, 114, 118, 121, 124};
56 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
57 (sizeof(e1000_igp_2_cable_length_table) / \
58 sizeof(e1000_igp_2_cable_length_table[0]))
59
60 /**
61 * igb_check_reset_block - Check if PHY reset is blocked
62 * @hw: pointer to the HW structure
63 *
64 * Read the PHY management control register and check whether a PHY reset
65 * is blocked. If a reset is not blocked return 0, otherwise
66 * return E1000_BLK_PHY_RESET (12).
67 **/
68 s32 igb_check_reset_block(struct e1000_hw *hw)
69 {
70 u32 manc;
71
72 manc = rd32(E1000_MANC);
73
74 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
75 E1000_BLK_PHY_RESET : 0;
76 }
77
78 /**
79 * igb_get_phy_id - Retrieve the PHY ID and revision
80 * @hw: pointer to the HW structure
81 *
82 * Reads the PHY registers and stores the PHY ID and possibly the PHY
83 * revision in the hardware structure.
84 **/
85 s32 igb_get_phy_id(struct e1000_hw *hw)
86 {
87 struct e1000_phy_info *phy = &hw->phy;
88 s32 ret_val = 0;
89 u16 phy_id;
90
91 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
92 if (ret_val)
93 goto out;
94
95 phy->id = (u32)(phy_id << 16);
96 udelay(20);
97 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
98 if (ret_val)
99 goto out;
100
101 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
102 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
103
104 out:
105 return ret_val;
106 }
107
108 /**
109 * igb_phy_reset_dsp - Reset PHY DSP
110 * @hw: pointer to the HW structure
111 *
112 * Reset the digital signal processor.
113 **/
114 static s32 igb_phy_reset_dsp(struct e1000_hw *hw)
115 {
116 s32 ret_val = 0;
117
118 if (!(hw->phy.ops.write_reg))
119 goto out;
120
121 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
122 if (ret_val)
123 goto out;
124
125 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
126
127 out:
128 return ret_val;
129 }
130
131 /**
132 * igb_read_phy_reg_mdic - Read MDI control register
133 * @hw: pointer to the HW structure
134 * @offset: register offset to be read
135 * @data: pointer to the read data
136 *
137 * Reads the MDI control regsiter in the PHY at offset and stores the
138 * information read to data.
139 **/
140 s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
141 {
142 struct e1000_phy_info *phy = &hw->phy;
143 u32 i, mdic = 0;
144 s32 ret_val = 0;
145
146 if (offset > MAX_PHY_REG_ADDRESS) {
147 hw_dbg("PHY Address %d is out of range\n", offset);
148 ret_val = -E1000_ERR_PARAM;
149 goto out;
150 }
151
152 /*
153 * Set up Op-code, Phy Address, and register offset in the MDI
154 * Control register. The MAC will take care of interfacing with the
155 * PHY to retrieve the desired data.
156 */
157 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
158 (phy->addr << E1000_MDIC_PHY_SHIFT) |
159 (E1000_MDIC_OP_READ));
160
161 wr32(E1000_MDIC, mdic);
162
163 /*
164 * Poll the ready bit to see if the MDI read completed
165 * Increasing the time out as testing showed failures with
166 * the lower time out
167 */
168 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
169 udelay(50);
170 mdic = rd32(E1000_MDIC);
171 if (mdic & E1000_MDIC_READY)
172 break;
173 }
174 if (!(mdic & E1000_MDIC_READY)) {
175 hw_dbg("MDI Read did not complete\n");
176 ret_val = -E1000_ERR_PHY;
177 goto out;
178 }
179 if (mdic & E1000_MDIC_ERROR) {
180 hw_dbg("MDI Error\n");
181 ret_val = -E1000_ERR_PHY;
182 goto out;
183 }
184 *data = (u16) mdic;
185
186 out:
187 return ret_val;
188 }
189
190 /**
191 * igb_write_phy_reg_mdic - Write MDI control register
192 * @hw: pointer to the HW structure
193 * @offset: register offset to write to
194 * @data: data to write to register at offset
195 *
196 * Writes data to MDI control register in the PHY at offset.
197 **/
198 s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
199 {
200 struct e1000_phy_info *phy = &hw->phy;
201 u32 i, mdic = 0;
202 s32 ret_val = 0;
203
204 if (offset > MAX_PHY_REG_ADDRESS) {
205 hw_dbg("PHY Address %d is out of range\n", offset);
206 ret_val = -E1000_ERR_PARAM;
207 goto out;
208 }
209
210 /*
211 * Set up Op-code, Phy Address, and register offset in the MDI
212 * Control register. The MAC will take care of interfacing with the
213 * PHY to retrieve the desired data.
214 */
215 mdic = (((u32)data) |
216 (offset << E1000_MDIC_REG_SHIFT) |
217 (phy->addr << E1000_MDIC_PHY_SHIFT) |
218 (E1000_MDIC_OP_WRITE));
219
220 wr32(E1000_MDIC, mdic);
221
222 /*
223 * Poll the ready bit to see if the MDI read completed
224 * Increasing the time out as testing showed failures with
225 * the lower time out
226 */
227 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
228 udelay(50);
229 mdic = rd32(E1000_MDIC);
230 if (mdic & E1000_MDIC_READY)
231 break;
232 }
233 if (!(mdic & E1000_MDIC_READY)) {
234 hw_dbg("MDI Write did not complete\n");
235 ret_val = -E1000_ERR_PHY;
236 goto out;
237 }
238 if (mdic & E1000_MDIC_ERROR) {
239 hw_dbg("MDI Error\n");
240 ret_val = -E1000_ERR_PHY;
241 goto out;
242 }
243
244 out:
245 return ret_val;
246 }
247
248 /**
249 * igb_read_phy_reg_i2c - Read PHY register using i2c
250 * @hw: pointer to the HW structure
251 * @offset: register offset to be read
252 * @data: pointer to the read data
253 *
254 * Reads the PHY register at offset using the i2c interface and stores the
255 * retrieved information in data.
256 **/
257 s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
258 {
259 struct e1000_phy_info *phy = &hw->phy;
260 u32 i, i2ccmd = 0;
261
262
263 /*
264 * Set up Op-code, Phy Address, and register address in the I2CCMD
265 * register. The MAC will take care of interfacing with the
266 * PHY to retrieve the desired data.
267 */
268 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
269 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
270 (E1000_I2CCMD_OPCODE_READ));
271
272 wr32(E1000_I2CCMD, i2ccmd);
273
274 /* Poll the ready bit to see if the I2C read completed */
275 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
276 udelay(50);
277 i2ccmd = rd32(E1000_I2CCMD);
278 if (i2ccmd & E1000_I2CCMD_READY)
279 break;
280 }
281 if (!(i2ccmd & E1000_I2CCMD_READY)) {
282 hw_dbg("I2CCMD Read did not complete\n");
283 return -E1000_ERR_PHY;
284 }
285 if (i2ccmd & E1000_I2CCMD_ERROR) {
286 hw_dbg("I2CCMD Error bit set\n");
287 return -E1000_ERR_PHY;
288 }
289
290 /* Need to byte-swap the 16-bit value. */
291 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
292
293 return 0;
294 }
295
296 /**
297 * igb_write_phy_reg_i2c - Write PHY register using i2c
298 * @hw: pointer to the HW structure
299 * @offset: register offset to write to
300 * @data: data to write at register offset
301 *
302 * Writes the data to PHY register at the offset using the i2c interface.
303 **/
304 s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
305 {
306 struct e1000_phy_info *phy = &hw->phy;
307 u32 i, i2ccmd = 0;
308 u16 phy_data_swapped;
309
310 /* Prevent overwritting SFP I2C EEPROM which is at A0 address.*/
311 if ((hw->phy.addr == 0) || (hw->phy.addr > 7)) {
312 hw_dbg("PHY I2C Address %d is out of range.\n",
313 hw->phy.addr);
314 return -E1000_ERR_CONFIG;
315 }
316
317 /* Swap the data bytes for the I2C interface */
318 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
319
320 /*
321 * Set up Op-code, Phy Address, and register address in the I2CCMD
322 * register. The MAC will take care of interfacing with the
323 * PHY to retrieve the desired data.
324 */
325 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
326 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
327 E1000_I2CCMD_OPCODE_WRITE |
328 phy_data_swapped);
329
330 wr32(E1000_I2CCMD, i2ccmd);
331
332 /* Poll the ready bit to see if the I2C read completed */
333 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
334 udelay(50);
335 i2ccmd = rd32(E1000_I2CCMD);
336 if (i2ccmd & E1000_I2CCMD_READY)
337 break;
338 }
339 if (!(i2ccmd & E1000_I2CCMD_READY)) {
340 hw_dbg("I2CCMD Write did not complete\n");
341 return -E1000_ERR_PHY;
342 }
343 if (i2ccmd & E1000_I2CCMD_ERROR) {
344 hw_dbg("I2CCMD Error bit set\n");
345 return -E1000_ERR_PHY;
346 }
347
348 return 0;
349 }
350
351 /**
352 * igb_read_phy_reg_igp - Read igp PHY register
353 * @hw: pointer to the HW structure
354 * @offset: register offset to be read
355 * @data: pointer to the read data
356 *
357 * Acquires semaphore, if necessary, then reads the PHY register at offset
358 * and storing the retrieved information in data. Release any acquired
359 * semaphores before exiting.
360 **/
361 s32 igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
362 {
363 s32 ret_val = 0;
364
365 if (!(hw->phy.ops.acquire))
366 goto out;
367
368 ret_val = hw->phy.ops.acquire(hw);
369 if (ret_val)
370 goto out;
371
372 if (offset > MAX_PHY_MULTI_PAGE_REG) {
373 ret_val = igb_write_phy_reg_mdic(hw,
374 IGP01E1000_PHY_PAGE_SELECT,
375 (u16)offset);
376 if (ret_val) {
377 hw->phy.ops.release(hw);
378 goto out;
379 }
380 }
381
382 ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
383 data);
384
385 hw->phy.ops.release(hw);
386
387 out:
388 return ret_val;
389 }
390
391 /**
392 * igb_write_phy_reg_igp - Write igp PHY register
393 * @hw: pointer to the HW structure
394 * @offset: register offset to write to
395 * @data: data to write at register offset
396 *
397 * Acquires semaphore, if necessary, then writes the data to PHY register
398 * at the offset. Release any acquired semaphores before exiting.
399 **/
400 s32 igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
401 {
402 s32 ret_val = 0;
403
404 if (!(hw->phy.ops.acquire))
405 goto out;
406
407 ret_val = hw->phy.ops.acquire(hw);
408 if (ret_val)
409 goto out;
410
411 if (offset > MAX_PHY_MULTI_PAGE_REG) {
412 ret_val = igb_write_phy_reg_mdic(hw,
413 IGP01E1000_PHY_PAGE_SELECT,
414 (u16)offset);
415 if (ret_val) {
416 hw->phy.ops.release(hw);
417 goto out;
418 }
419 }
420
421 ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
422 data);
423
424 hw->phy.ops.release(hw);
425
426 out:
427 return ret_val;
428 }
429
430 /**
431 * igb_copper_link_setup_82580 - Setup 82580 PHY for copper link
432 * @hw: pointer to the HW structure
433 *
434 * Sets up Carrier-sense on Transmit and downshift values.
435 **/
436 s32 igb_copper_link_setup_82580(struct e1000_hw *hw)
437 {
438 struct e1000_phy_info *phy = &hw->phy;
439 s32 ret_val;
440 u16 phy_data;
441
442
443 if (phy->reset_disable) {
444 ret_val = 0;
445 goto out;
446 }
447
448 if (phy->type == e1000_phy_82580) {
449 ret_val = hw->phy.ops.reset(hw);
450 if (ret_val) {
451 hw_dbg("Error resetting the PHY.\n");
452 goto out;
453 }
454 }
455
456 /* Enable CRS on TX. This must be set for half-duplex operation. */
457 ret_val = phy->ops.read_reg(hw, I82580_CFG_REG, &phy_data);
458 if (ret_val)
459 goto out;
460
461 phy_data |= I82580_CFG_ASSERT_CRS_ON_TX;
462
463 /* Enable downshift */
464 phy_data |= I82580_CFG_ENABLE_DOWNSHIFT;
465
466 ret_val = phy->ops.write_reg(hw, I82580_CFG_REG, phy_data);
467 if (ret_val)
468 goto out;
469
470 /* Set MDI/MDIX mode */
471 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
472 if (ret_val)
473 goto out;
474 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
475 /*
476 * Options:
477 * 0 - Auto (default)
478 * 1 - MDI mode
479 * 2 - MDI-X mode
480 */
481 switch (hw->phy.mdix) {
482 case 1:
483 break;
484 case 2:
485 phy_data |= I82580_PHY_CTRL2_MANUAL_MDIX;
486 break;
487 case 0:
488 default:
489 phy_data |= I82580_PHY_CTRL2_AUTO_MDI_MDIX;
490 break;
491 }
492 ret_val = hw->phy.ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
493
494 out:
495 return ret_val;
496 }
497
498 /**
499 * igb_copper_link_setup_m88 - Setup m88 PHY's for copper link
500 * @hw: pointer to the HW structure
501 *
502 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
503 * and downshift values are set also.
504 **/
505 s32 igb_copper_link_setup_m88(struct e1000_hw *hw)
506 {
507 struct e1000_phy_info *phy = &hw->phy;
508 s32 ret_val;
509 u16 phy_data;
510
511 if (phy->reset_disable) {
512 ret_val = 0;
513 goto out;
514 }
515
516 /* Enable CRS on TX. This must be set for half-duplex operation. */
517 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
518 if (ret_val)
519 goto out;
520
521 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
522
523 /*
524 * Options:
525 * MDI/MDI-X = 0 (default)
526 * 0 - Auto for all speeds
527 * 1 - MDI mode
528 * 2 - MDI-X mode
529 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
530 */
531 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
532
533 switch (phy->mdix) {
534 case 1:
535 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
536 break;
537 case 2:
538 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
539 break;
540 case 3:
541 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
542 break;
543 case 0:
544 default:
545 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
546 break;
547 }
548
549 /*
550 * Options:
551 * disable_polarity_correction = 0 (default)
552 * Automatic Correction for Reversed Cable Polarity
553 * 0 - Disabled
554 * 1 - Enabled
555 */
556 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
557 if (phy->disable_polarity_correction == 1)
558 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
559
560 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
561 if (ret_val)
562 goto out;
563
564 if (phy->revision < E1000_REVISION_4) {
565 /*
566 * Force TX_CLK in the Extended PHY Specific Control Register
567 * to 25MHz clock.
568 */
569 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
570 &phy_data);
571 if (ret_val)
572 goto out;
573
574 phy_data |= M88E1000_EPSCR_TX_CLK_25;
575
576 if ((phy->revision == E1000_REVISION_2) &&
577 (phy->id == M88E1111_I_PHY_ID)) {
578 /* 82573L PHY - set the downshift counter to 5x. */
579 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
580 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
581 } else {
582 /* Configure Master and Slave downshift values */
583 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
584 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
585 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
586 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
587 }
588 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
589 phy_data);
590 if (ret_val)
591 goto out;
592 }
593
594 /* Commit the changes. */
595 ret_val = igb_phy_sw_reset(hw);
596 if (ret_val) {
597 hw_dbg("Error committing the PHY changes\n");
598 goto out;
599 }
600 if (phy->type == e1000_phy_i210) {
601 ret_val = igb_set_master_slave_mode(hw);
602 if (ret_val)
603 return ret_val;
604 }
605
606 out:
607 return ret_val;
608 }
609
610 /**
611 * igb_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
612 * @hw: pointer to the HW structure
613 *
614 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
615 * Also enables and sets the downshift parameters.
616 **/
617 s32 igb_copper_link_setup_m88_gen2(struct e1000_hw *hw)
618 {
619 struct e1000_phy_info *phy = &hw->phy;
620 s32 ret_val;
621 u16 phy_data;
622
623 if (phy->reset_disable) {
624 ret_val = 0;
625 goto out;
626 }
627
628 /* Enable CRS on Tx. This must be set for half-duplex operation. */
629 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
630 if (ret_val)
631 goto out;
632
633 /*
634 * Options:
635 * MDI/MDI-X = 0 (default)
636 * 0 - Auto for all speeds
637 * 1 - MDI mode
638 * 2 - MDI-X mode
639 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
640 */
641 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
642
643 switch (phy->mdix) {
644 case 1:
645 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
646 break;
647 case 2:
648 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
649 break;
650 case 3:
651 /* M88E1112 does not support this mode) */
652 if (phy->id != M88E1112_E_PHY_ID) {
653 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
654 break;
655 }
656 case 0:
657 default:
658 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
659 break;
660 }
661
662 /*
663 * Options:
664 * disable_polarity_correction = 0 (default)
665 * Automatic Correction for Reversed Cable Polarity
666 * 0 - Disabled
667 * 1 - Enabled
668 */
669 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
670 if (phy->disable_polarity_correction == 1)
671 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
672
673 /* Enable downshift and setting it to X6 */
674 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
675 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
676 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
677
678 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
679 if (ret_val)
680 goto out;
681
682 /* Commit the changes. */
683 ret_val = igb_phy_sw_reset(hw);
684 if (ret_val) {
685 hw_dbg("Error committing the PHY changes\n");
686 goto out;
687 }
688
689 out:
690 return ret_val;
691 }
692
693 /**
694 * igb_copper_link_setup_igp - Setup igp PHY's for copper link
695 * @hw: pointer to the HW structure
696 *
697 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
698 * igp PHY's.
699 **/
700 s32 igb_copper_link_setup_igp(struct e1000_hw *hw)
701 {
702 struct e1000_phy_info *phy = &hw->phy;
703 s32 ret_val;
704 u16 data;
705
706 if (phy->reset_disable) {
707 ret_val = 0;
708 goto out;
709 }
710
711 ret_val = phy->ops.reset(hw);
712 if (ret_val) {
713 hw_dbg("Error resetting the PHY.\n");
714 goto out;
715 }
716
717 /*
718 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
719 * timeout issues when LFS is enabled.
720 */
721 msleep(100);
722
723 /*
724 * The NVM settings will configure LPLU in D3 for
725 * non-IGP1 PHYs.
726 */
727 if (phy->type == e1000_phy_igp) {
728 /* disable lplu d3 during driver init */
729 if (phy->ops.set_d3_lplu_state)
730 ret_val = phy->ops.set_d3_lplu_state(hw, false);
731 if (ret_val) {
732 hw_dbg("Error Disabling LPLU D3\n");
733 goto out;
734 }
735 }
736
737 /* disable lplu d0 during driver init */
738 ret_val = phy->ops.set_d0_lplu_state(hw, false);
739 if (ret_val) {
740 hw_dbg("Error Disabling LPLU D0\n");
741 goto out;
742 }
743 /* Configure mdi-mdix settings */
744 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
745 if (ret_val)
746 goto out;
747
748 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
749
750 switch (phy->mdix) {
751 case 1:
752 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
753 break;
754 case 2:
755 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
756 break;
757 case 0:
758 default:
759 data |= IGP01E1000_PSCR_AUTO_MDIX;
760 break;
761 }
762 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
763 if (ret_val)
764 goto out;
765
766 /* set auto-master slave resolution settings */
767 if (hw->mac.autoneg) {
768 /*
769 * when autonegotiation advertisement is only 1000Mbps then we
770 * should disable SmartSpeed and enable Auto MasterSlave
771 * resolution as hardware default.
772 */
773 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
774 /* Disable SmartSpeed */
775 ret_val = phy->ops.read_reg(hw,
776 IGP01E1000_PHY_PORT_CONFIG,
777 &data);
778 if (ret_val)
779 goto out;
780
781 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
782 ret_val = phy->ops.write_reg(hw,
783 IGP01E1000_PHY_PORT_CONFIG,
784 data);
785 if (ret_val)
786 goto out;
787
788 /* Set auto Master/Slave resolution process */
789 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
790 if (ret_val)
791 goto out;
792
793 data &= ~CR_1000T_MS_ENABLE;
794 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
795 if (ret_val)
796 goto out;
797 }
798
799 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
800 if (ret_val)
801 goto out;
802
803 /* load defaults for future use */
804 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
805 ((data & CR_1000T_MS_VALUE) ?
806 e1000_ms_force_master :
807 e1000_ms_force_slave) :
808 e1000_ms_auto;
809
810 switch (phy->ms_type) {
811 case e1000_ms_force_master:
812 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
813 break;
814 case e1000_ms_force_slave:
815 data |= CR_1000T_MS_ENABLE;
816 data &= ~(CR_1000T_MS_VALUE);
817 break;
818 case e1000_ms_auto:
819 data &= ~CR_1000T_MS_ENABLE;
820 default:
821 break;
822 }
823 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
824 if (ret_val)
825 goto out;
826 }
827
828 out:
829 return ret_val;
830 }
831
832 /**
833 * igb_copper_link_autoneg - Setup/Enable autoneg for copper link
834 * @hw: pointer to the HW structure
835 *
836 * Performs initial bounds checking on autoneg advertisement parameter, then
837 * configure to advertise the full capability. Setup the PHY to autoneg
838 * and restart the negotiation process between the link partner. If
839 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
840 **/
841 static s32 igb_copper_link_autoneg(struct e1000_hw *hw)
842 {
843 struct e1000_phy_info *phy = &hw->phy;
844 s32 ret_val;
845 u16 phy_ctrl;
846
847 /*
848 * Perform some bounds checking on the autoneg advertisement
849 * parameter.
850 */
851 phy->autoneg_advertised &= phy->autoneg_mask;
852
853 /*
854 * If autoneg_advertised is zero, we assume it was not defaulted
855 * by the calling code so we set to advertise full capability.
856 */
857 if (phy->autoneg_advertised == 0)
858 phy->autoneg_advertised = phy->autoneg_mask;
859
860 hw_dbg("Reconfiguring auto-neg advertisement params\n");
861 ret_val = igb_phy_setup_autoneg(hw);
862 if (ret_val) {
863 hw_dbg("Error Setting up Auto-Negotiation\n");
864 goto out;
865 }
866 hw_dbg("Restarting Auto-Neg\n");
867
868 /*
869 * Restart auto-negotiation by setting the Auto Neg Enable bit and
870 * the Auto Neg Restart bit in the PHY control register.
871 */
872 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
873 if (ret_val)
874 goto out;
875
876 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
877 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
878 if (ret_val)
879 goto out;
880
881 /*
882 * Does the user want to wait for Auto-Neg to complete here, or
883 * check at a later time (for example, callback routine).
884 */
885 if (phy->autoneg_wait_to_complete) {
886 ret_val = igb_wait_autoneg(hw);
887 if (ret_val) {
888 hw_dbg("Error while waiting for "
889 "autoneg to complete\n");
890 goto out;
891 }
892 }
893
894 hw->mac.get_link_status = true;
895
896 out:
897 return ret_val;
898 }
899
900 /**
901 * igb_phy_setup_autoneg - Configure PHY for auto-negotiation
902 * @hw: pointer to the HW structure
903 *
904 * Reads the MII auto-neg advertisement register and/or the 1000T control
905 * register and if the PHY is already setup for auto-negotiation, then
906 * return successful. Otherwise, setup advertisement and flow control to
907 * the appropriate values for the wanted auto-negotiation.
908 **/
909 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw)
910 {
911 struct e1000_phy_info *phy = &hw->phy;
912 s32 ret_val;
913 u16 mii_autoneg_adv_reg;
914 u16 mii_1000t_ctrl_reg = 0;
915
916 phy->autoneg_advertised &= phy->autoneg_mask;
917
918 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
919 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
920 if (ret_val)
921 goto out;
922
923 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
924 /* Read the MII 1000Base-T Control Register (Address 9). */
925 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
926 &mii_1000t_ctrl_reg);
927 if (ret_val)
928 goto out;
929 }
930
931 /*
932 * Need to parse both autoneg_advertised and fc and set up
933 * the appropriate PHY registers. First we will parse for
934 * autoneg_advertised software override. Since we can advertise
935 * a plethora of combinations, we need to check each bit
936 * individually.
937 */
938
939 /*
940 * First we clear all the 10/100 mb speed bits in the Auto-Neg
941 * Advertisement Register (Address 4) and the 1000 mb speed bits in
942 * the 1000Base-T Control Register (Address 9).
943 */
944 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
945 NWAY_AR_100TX_HD_CAPS |
946 NWAY_AR_10T_FD_CAPS |
947 NWAY_AR_10T_HD_CAPS);
948 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
949
950 hw_dbg("autoneg_advertised %x\n", phy->autoneg_advertised);
951
952 /* Do we want to advertise 10 Mb Half Duplex? */
953 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
954 hw_dbg("Advertise 10mb Half duplex\n");
955 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
956 }
957
958 /* Do we want to advertise 10 Mb Full Duplex? */
959 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
960 hw_dbg("Advertise 10mb Full duplex\n");
961 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
962 }
963
964 /* Do we want to advertise 100 Mb Half Duplex? */
965 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
966 hw_dbg("Advertise 100mb Half duplex\n");
967 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
968 }
969
970 /* Do we want to advertise 100 Mb Full Duplex? */
971 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
972 hw_dbg("Advertise 100mb Full duplex\n");
973 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
974 }
975
976 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
977 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
978 hw_dbg("Advertise 1000mb Half duplex request denied!\n");
979
980 /* Do we want to advertise 1000 Mb Full Duplex? */
981 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
982 hw_dbg("Advertise 1000mb Full duplex\n");
983 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
984 }
985
986 /*
987 * Check for a software override of the flow control settings, and
988 * setup the PHY advertisement registers accordingly. If
989 * auto-negotiation is enabled, then software will have to set the
990 * "PAUSE" bits to the correct value in the Auto-Negotiation
991 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
992 * negotiation.
993 *
994 * The possible values of the "fc" parameter are:
995 * 0: Flow control is completely disabled
996 * 1: Rx flow control is enabled (we can receive pause frames
997 * but not send pause frames).
998 * 2: Tx flow control is enabled (we can send pause frames
999 * but we do not support receiving pause frames).
1000 * 3: Both Rx and TX flow control (symmetric) are enabled.
1001 * other: No software override. The flow control configuration
1002 * in the EEPROM is used.
1003 */
1004 switch (hw->fc.current_mode) {
1005 case e1000_fc_none:
1006 /*
1007 * Flow control (RX & TX) is completely disabled by a
1008 * software over-ride.
1009 */
1010 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1011 break;
1012 case e1000_fc_rx_pause:
1013 /*
1014 * RX Flow control is enabled, and TX Flow control is
1015 * disabled, by a software over-ride.
1016 *
1017 * Since there really isn't a way to advertise that we are
1018 * capable of RX Pause ONLY, we will advertise that we
1019 * support both symmetric and asymmetric RX PAUSE. Later
1020 * (in e1000_config_fc_after_link_up) we will disable the
1021 * hw's ability to send PAUSE frames.
1022 */
1023 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1024 break;
1025 case e1000_fc_tx_pause:
1026 /*
1027 * TX Flow control is enabled, and RX Flow control is
1028 * disabled, by a software over-ride.
1029 */
1030 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1031 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1032 break;
1033 case e1000_fc_full:
1034 /*
1035 * Flow control (both RX and TX) is enabled by a software
1036 * over-ride.
1037 */
1038 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1039 break;
1040 default:
1041 hw_dbg("Flow control param set incorrectly\n");
1042 ret_val = -E1000_ERR_CONFIG;
1043 goto out;
1044 }
1045
1046 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1047 if (ret_val)
1048 goto out;
1049
1050 hw_dbg("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1051
1052 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1053 ret_val = phy->ops.write_reg(hw,
1054 PHY_1000T_CTRL,
1055 mii_1000t_ctrl_reg);
1056 if (ret_val)
1057 goto out;
1058 }
1059
1060 out:
1061 return ret_val;
1062 }
1063
1064 /**
1065 * igb_setup_copper_link - Configure copper link settings
1066 * @hw: pointer to the HW structure
1067 *
1068 * Calls the appropriate function to configure the link for auto-neg or forced
1069 * speed and duplex. Then we check for link, once link is established calls
1070 * to configure collision distance and flow control are called. If link is
1071 * not established, we return -E1000_ERR_PHY (-2).
1072 **/
1073 s32 igb_setup_copper_link(struct e1000_hw *hw)
1074 {
1075 s32 ret_val;
1076 bool link;
1077
1078
1079 if (hw->mac.autoneg) {
1080 /*
1081 * Setup autoneg and flow control advertisement and perform
1082 * autonegotiation.
1083 */
1084 ret_val = igb_copper_link_autoneg(hw);
1085 if (ret_val)
1086 goto out;
1087 } else {
1088 /*
1089 * PHY will be set to 10H, 10F, 100H or 100F
1090 * depending on user settings.
1091 */
1092 hw_dbg("Forcing Speed and Duplex\n");
1093 ret_val = hw->phy.ops.force_speed_duplex(hw);
1094 if (ret_val) {
1095 hw_dbg("Error Forcing Speed and Duplex\n");
1096 goto out;
1097 }
1098 }
1099
1100 /*
1101 * Check link status. Wait up to 100 microseconds for link to become
1102 * valid.
1103 */
1104 ret_val = igb_phy_has_link(hw,
1105 COPPER_LINK_UP_LIMIT,
1106 10,
1107 &link);
1108 if (ret_val)
1109 goto out;
1110
1111 if (link) {
1112 hw_dbg("Valid link established!!!\n");
1113 igb_config_collision_dist(hw);
1114 ret_val = igb_config_fc_after_link_up(hw);
1115 } else {
1116 hw_dbg("Unable to establish link!!!\n");
1117 }
1118
1119 out:
1120 return ret_val;
1121 }
1122
1123 /**
1124 * igb_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1125 * @hw: pointer to the HW structure
1126 *
1127 * Calls the PHY setup function to force speed and duplex. Clears the
1128 * auto-crossover to force MDI manually. Waits for link and returns
1129 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1130 **/
1131 s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1132 {
1133 struct e1000_phy_info *phy = &hw->phy;
1134 s32 ret_val;
1135 u16 phy_data;
1136 bool link;
1137
1138 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1139 if (ret_val)
1140 goto out;
1141
1142 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1143
1144 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1145 if (ret_val)
1146 goto out;
1147
1148 /*
1149 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1150 * forced whenever speed and duplex are forced.
1151 */
1152 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1153 if (ret_val)
1154 goto out;
1155
1156 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1157 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1158
1159 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1160 if (ret_val)
1161 goto out;
1162
1163 hw_dbg("IGP PSCR: %X\n", phy_data);
1164
1165 udelay(1);
1166
1167 if (phy->autoneg_wait_to_complete) {
1168 hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
1169
1170 ret_val = igb_phy_has_link(hw,
1171 PHY_FORCE_LIMIT,
1172 100000,
1173 &link);
1174 if (ret_val)
1175 goto out;
1176
1177 if (!link)
1178 hw_dbg("Link taking longer than expected.\n");
1179
1180 /* Try once more */
1181 ret_val = igb_phy_has_link(hw,
1182 PHY_FORCE_LIMIT,
1183 100000,
1184 &link);
1185 if (ret_val)
1186 goto out;
1187 }
1188
1189 out:
1190 return ret_val;
1191 }
1192
1193 /**
1194 * igb_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1195 * @hw: pointer to the HW structure
1196 *
1197 * Calls the PHY setup function to force speed and duplex. Clears the
1198 * auto-crossover to force MDI manually. Resets the PHY to commit the
1199 * changes. If time expires while waiting for link up, we reset the DSP.
1200 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
1201 * successful completion, else return corresponding error code.
1202 **/
1203 s32 igb_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1204 {
1205 struct e1000_phy_info *phy = &hw->phy;
1206 s32 ret_val;
1207 u16 phy_data;
1208 bool link;
1209
1210 /* I210 and I211 devices support Auto-Crossover in forced operation. */
1211 if (phy->type != e1000_phy_i210) {
1212 /*
1213 * Clear Auto-Crossover to force MDI manually. M88E1000
1214 * requires MDI forced whenever speed and duplex are forced.
1215 */
1216 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL,
1217 &phy_data);
1218 if (ret_val)
1219 goto out;
1220
1221 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1222 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL,
1223 phy_data);
1224 if (ret_val)
1225 goto out;
1226
1227 hw_dbg("M88E1000 PSCR: %X\n", phy_data);
1228 }
1229
1230 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1231 if (ret_val)
1232 goto out;
1233
1234 igb_phy_force_speed_duplex_setup(hw, &phy_data);
1235
1236 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1237 if (ret_val)
1238 goto out;
1239
1240 /* Reset the phy to commit changes. */
1241 ret_val = igb_phy_sw_reset(hw);
1242 if (ret_val)
1243 goto out;
1244
1245 if (phy->autoneg_wait_to_complete) {
1246 hw_dbg("Waiting for forced speed/duplex link on M88 phy.\n");
1247
1248 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
1249 if (ret_val)
1250 goto out;
1251
1252 if (!link) {
1253 bool reset_dsp = true;
1254
1255 switch (hw->phy.id) {
1256 case I347AT4_E_PHY_ID:
1257 case M88E1112_E_PHY_ID:
1258 case I210_I_PHY_ID:
1259 reset_dsp = false;
1260 break;
1261 default:
1262 if (hw->phy.type != e1000_phy_m88)
1263 reset_dsp = false;
1264 break;
1265 }
1266 if (!reset_dsp)
1267 hw_dbg("Link taking longer than expected.\n");
1268 else {
1269 /*
1270 * We didn't get link.
1271 * Reset the DSP and cross our fingers.
1272 */
1273 ret_val = phy->ops.write_reg(hw,
1274 M88E1000_PHY_PAGE_SELECT,
1275 0x001d);
1276 if (ret_val)
1277 goto out;
1278 ret_val = igb_phy_reset_dsp(hw);
1279 if (ret_val)
1280 goto out;
1281 }
1282 }
1283
1284 /* Try once more */
1285 ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT,
1286 100000, &link);
1287 if (ret_val)
1288 goto out;
1289 }
1290
1291 if (hw->phy.type != e1000_phy_m88 ||
1292 hw->phy.id == I347AT4_E_PHY_ID ||
1293 hw->phy.id == M88E1112_E_PHY_ID ||
1294 hw->phy.id == I210_I_PHY_ID)
1295 goto out;
1296
1297 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1298 if (ret_val)
1299 goto out;
1300
1301 /*
1302 * Resetting the phy means we need to re-force TX_CLK in the
1303 * Extended PHY Specific Control Register to 25MHz clock from
1304 * the reset value of 2.5MHz.
1305 */
1306 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1307 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1308 if (ret_val)
1309 goto out;
1310
1311 /*
1312 * In addition, we must re-enable CRS on Tx for both half and full
1313 * duplex.
1314 */
1315 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1316 if (ret_val)
1317 goto out;
1318
1319 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1320 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1321
1322 out:
1323 return ret_val;
1324 }
1325
1326 /**
1327 * igb_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1328 * @hw: pointer to the HW structure
1329 * @phy_ctrl: pointer to current value of PHY_CONTROL
1330 *
1331 * Forces speed and duplex on the PHY by doing the following: disable flow
1332 * control, force speed/duplex on the MAC, disable auto speed detection,
1333 * disable auto-negotiation, configure duplex, configure speed, configure
1334 * the collision distance, write configuration to CTRL register. The
1335 * caller must write to the PHY_CONTROL register for these settings to
1336 * take affect.
1337 **/
1338 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
1339 u16 *phy_ctrl)
1340 {
1341 struct e1000_mac_info *mac = &hw->mac;
1342 u32 ctrl;
1343
1344 /* Turn off flow control when forcing speed/duplex */
1345 hw->fc.current_mode = e1000_fc_none;
1346
1347 /* Force speed/duplex on the mac */
1348 ctrl = rd32(E1000_CTRL);
1349 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1350 ctrl &= ~E1000_CTRL_SPD_SEL;
1351
1352 /* Disable Auto Speed Detection */
1353 ctrl &= ~E1000_CTRL_ASDE;
1354
1355 /* Disable autoneg on the phy */
1356 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1357
1358 /* Forcing Full or Half Duplex? */
1359 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1360 ctrl &= ~E1000_CTRL_FD;
1361 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1362 hw_dbg("Half Duplex\n");
1363 } else {
1364 ctrl |= E1000_CTRL_FD;
1365 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1366 hw_dbg("Full Duplex\n");
1367 }
1368
1369 /* Forcing 10mb or 100mb? */
1370 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1371 ctrl |= E1000_CTRL_SPD_100;
1372 *phy_ctrl |= MII_CR_SPEED_100;
1373 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1374 hw_dbg("Forcing 100mb\n");
1375 } else {
1376 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1377 *phy_ctrl |= MII_CR_SPEED_10;
1378 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1379 hw_dbg("Forcing 10mb\n");
1380 }
1381
1382 igb_config_collision_dist(hw);
1383
1384 wr32(E1000_CTRL, ctrl);
1385 }
1386
1387 /**
1388 * igb_set_d3_lplu_state - Sets low power link up state for D3
1389 * @hw: pointer to the HW structure
1390 * @active: boolean used to enable/disable lplu
1391 *
1392 * Success returns 0, Failure returns 1
1393 *
1394 * The low power link up (lplu) state is set to the power management level D3
1395 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1396 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1397 * is used during Dx states where the power conservation is most important.
1398 * During driver activity, SmartSpeed should be enabled so performance is
1399 * maintained.
1400 **/
1401 s32 igb_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1402 {
1403 struct e1000_phy_info *phy = &hw->phy;
1404 s32 ret_val = 0;
1405 u16 data;
1406
1407 if (!(hw->phy.ops.read_reg))
1408 goto out;
1409
1410 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1411 if (ret_val)
1412 goto out;
1413
1414 if (!active) {
1415 data &= ~IGP02E1000_PM_D3_LPLU;
1416 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1417 data);
1418 if (ret_val)
1419 goto out;
1420 /*
1421 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1422 * during Dx states where the power conservation is most
1423 * important. During driver activity we should enable
1424 * SmartSpeed, so performance is maintained.
1425 */
1426 if (phy->smart_speed == e1000_smart_speed_on) {
1427 ret_val = phy->ops.read_reg(hw,
1428 IGP01E1000_PHY_PORT_CONFIG,
1429 &data);
1430 if (ret_val)
1431 goto out;
1432
1433 data |= IGP01E1000_PSCFR_SMART_SPEED;
1434 ret_val = phy->ops.write_reg(hw,
1435 IGP01E1000_PHY_PORT_CONFIG,
1436 data);
1437 if (ret_val)
1438 goto out;
1439 } else if (phy->smart_speed == e1000_smart_speed_off) {
1440 ret_val = phy->ops.read_reg(hw,
1441 IGP01E1000_PHY_PORT_CONFIG,
1442 &data);
1443 if (ret_val)
1444 goto out;
1445
1446 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1447 ret_val = phy->ops.write_reg(hw,
1448 IGP01E1000_PHY_PORT_CONFIG,
1449 data);
1450 if (ret_val)
1451 goto out;
1452 }
1453 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1454 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1455 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1456 data |= IGP02E1000_PM_D3_LPLU;
1457 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1458 data);
1459 if (ret_val)
1460 goto out;
1461
1462 /* When LPLU is enabled, we should disable SmartSpeed */
1463 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1464 &data);
1465 if (ret_val)
1466 goto out;
1467
1468 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1469 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1470 data);
1471 }
1472
1473 out:
1474 return ret_val;
1475 }
1476
1477 /**
1478 * igb_check_downshift - Checks whether a downshift in speed occurred
1479 * @hw: pointer to the HW structure
1480 *
1481 * Success returns 0, Failure returns 1
1482 *
1483 * A downshift is detected by querying the PHY link health.
1484 **/
1485 s32 igb_check_downshift(struct e1000_hw *hw)
1486 {
1487 struct e1000_phy_info *phy = &hw->phy;
1488 s32 ret_val;
1489 u16 phy_data, offset, mask;
1490
1491 switch (phy->type) {
1492 case e1000_phy_i210:
1493 case e1000_phy_m88:
1494 case e1000_phy_gg82563:
1495 offset = M88E1000_PHY_SPEC_STATUS;
1496 mask = M88E1000_PSSR_DOWNSHIFT;
1497 break;
1498 case e1000_phy_igp_2:
1499 case e1000_phy_igp:
1500 case e1000_phy_igp_3:
1501 offset = IGP01E1000_PHY_LINK_HEALTH;
1502 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1503 break;
1504 default:
1505 /* speed downshift not supported */
1506 phy->speed_downgraded = false;
1507 ret_val = 0;
1508 goto out;
1509 }
1510
1511 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1512
1513 if (!ret_val)
1514 phy->speed_downgraded = (phy_data & mask) ? true : false;
1515
1516 out:
1517 return ret_val;
1518 }
1519
1520 /**
1521 * igb_check_polarity_m88 - Checks the polarity.
1522 * @hw: pointer to the HW structure
1523 *
1524 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1525 *
1526 * Polarity is determined based on the PHY specific status register.
1527 **/
1528 s32 igb_check_polarity_m88(struct e1000_hw *hw)
1529 {
1530 struct e1000_phy_info *phy = &hw->phy;
1531 s32 ret_val;
1532 u16 data;
1533
1534 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1535
1536 if (!ret_val)
1537 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1538 ? e1000_rev_polarity_reversed
1539 : e1000_rev_polarity_normal;
1540
1541 return ret_val;
1542 }
1543
1544 /**
1545 * igb_check_polarity_igp - Checks the polarity.
1546 * @hw: pointer to the HW structure
1547 *
1548 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1549 *
1550 * Polarity is determined based on the PHY port status register, and the
1551 * current speed (since there is no polarity at 100Mbps).
1552 **/
1553 static s32 igb_check_polarity_igp(struct e1000_hw *hw)
1554 {
1555 struct e1000_phy_info *phy = &hw->phy;
1556 s32 ret_val;
1557 u16 data, offset, mask;
1558
1559 /*
1560 * Polarity is determined based on the speed of
1561 * our connection.
1562 */
1563 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1564 if (ret_val)
1565 goto out;
1566
1567 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1568 IGP01E1000_PSSR_SPEED_1000MBPS) {
1569 offset = IGP01E1000_PHY_PCS_INIT_REG;
1570 mask = IGP01E1000_PHY_POLARITY_MASK;
1571 } else {
1572 /*
1573 * This really only applies to 10Mbps since
1574 * there is no polarity for 100Mbps (always 0).
1575 */
1576 offset = IGP01E1000_PHY_PORT_STATUS;
1577 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1578 }
1579
1580 ret_val = phy->ops.read_reg(hw, offset, &data);
1581
1582 if (!ret_val)
1583 phy->cable_polarity = (data & mask)
1584 ? e1000_rev_polarity_reversed
1585 : e1000_rev_polarity_normal;
1586
1587 out:
1588 return ret_val;
1589 }
1590
1591 /**
1592 * igb_wait_autoneg - Wait for auto-neg compeletion
1593 * @hw: pointer to the HW structure
1594 *
1595 * Waits for auto-negotiation to complete or for the auto-negotiation time
1596 * limit to expire, which ever happens first.
1597 **/
1598 static s32 igb_wait_autoneg(struct e1000_hw *hw)
1599 {
1600 s32 ret_val = 0;
1601 u16 i, phy_status;
1602
1603 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1604 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1605 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1606 if (ret_val)
1607 break;
1608 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1609 if (ret_val)
1610 break;
1611 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1612 break;
1613 msleep(100);
1614 }
1615
1616 /*
1617 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1618 * has completed.
1619 */
1620 return ret_val;
1621 }
1622
1623 /**
1624 * igb_phy_has_link - Polls PHY for link
1625 * @hw: pointer to the HW structure
1626 * @iterations: number of times to poll for link
1627 * @usec_interval: delay between polling attempts
1628 * @success: pointer to whether polling was successful or not
1629 *
1630 * Polls the PHY status register for link, 'iterations' number of times.
1631 **/
1632 s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
1633 u32 usec_interval, bool *success)
1634 {
1635 s32 ret_val = 0;
1636 u16 i, phy_status;
1637
1638 for (i = 0; i < iterations; i++) {
1639 /*
1640 * Some PHYs require the PHY_STATUS register to be read
1641 * twice due to the link bit being sticky. No harm doing
1642 * it across the board.
1643 */
1644 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1645 if (ret_val) {
1646 /*
1647 * If the first read fails, another entity may have
1648 * ownership of the resources, wait and try again to
1649 * see if they have relinquished the resources yet.
1650 */
1651 udelay(usec_interval);
1652 }
1653 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
1654 if (ret_val)
1655 break;
1656 if (phy_status & MII_SR_LINK_STATUS)
1657 break;
1658 if (usec_interval >= 1000)
1659 mdelay(usec_interval/1000);
1660 else
1661 udelay(usec_interval);
1662 }
1663
1664 *success = (i < iterations) ? true : false;
1665
1666 return ret_val;
1667 }
1668
1669 /**
1670 * igb_get_cable_length_m88 - Determine cable length for m88 PHY
1671 * @hw: pointer to the HW structure
1672 *
1673 * Reads the PHY specific status register to retrieve the cable length
1674 * information. The cable length is determined by averaging the minimum and
1675 * maximum values to get the "average" cable length. The m88 PHY has four
1676 * possible cable length values, which are:
1677 * Register Value Cable Length
1678 * 0 < 50 meters
1679 * 1 50 - 80 meters
1680 * 2 80 - 110 meters
1681 * 3 110 - 140 meters
1682 * 4 > 140 meters
1683 **/
1684 s32 igb_get_cable_length_m88(struct e1000_hw *hw)
1685 {
1686 struct e1000_phy_info *phy = &hw->phy;
1687 s32 ret_val;
1688 u16 phy_data, index;
1689
1690 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1691 if (ret_val)
1692 goto out;
1693
1694 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1695 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1696 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1697 ret_val = -E1000_ERR_PHY;
1698 goto out;
1699 }
1700
1701 phy->min_cable_length = e1000_m88_cable_length_table[index];
1702 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1703
1704 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1705
1706 out:
1707 return ret_val;
1708 }
1709
1710 s32 igb_get_cable_length_m88_gen2(struct e1000_hw *hw)
1711 {
1712 struct e1000_phy_info *phy = &hw->phy;
1713 s32 ret_val;
1714 u16 phy_data, phy_data2, index, default_page, is_cm;
1715
1716 switch (hw->phy.id) {
1717 case I210_I_PHY_ID:
1718 /* Get cable length from PHY Cable Diagnostics Control Reg */
1719 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1720 (I347AT4_PCDL + phy->addr),
1721 &phy_data);
1722 if (ret_val)
1723 return ret_val;
1724
1725 /* Check if the unit of cable length is meters or cm */
1726 ret_val = phy->ops.read_reg(hw, (0x7 << GS40G_PAGE_SHIFT) +
1727 I347AT4_PCDC, &phy_data2);
1728 if (ret_val)
1729 return ret_val;
1730
1731 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1732
1733 /* Populate the phy structure with cable length in meters */
1734 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1735 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1736 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1737 break;
1738 case I347AT4_E_PHY_ID:
1739 /* Remember the original page select and set it to 7 */
1740 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1741 &default_page);
1742 if (ret_val)
1743 goto out;
1744
1745 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
1746 if (ret_val)
1747 goto out;
1748
1749 /* Get cable length from PHY Cable Diagnostics Control Reg */
1750 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
1751 &phy_data);
1752 if (ret_val)
1753 goto out;
1754
1755 /* Check if the unit of cable length is meters or cm */
1756 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
1757 if (ret_val)
1758 goto out;
1759
1760 is_cm = !(phy_data2 & I347AT4_PCDC_CABLE_LENGTH_UNIT);
1761
1762 /* Populate the phy structure with cable length in meters */
1763 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
1764 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
1765 phy->cable_length = phy_data / (is_cm ? 100 : 1);
1766
1767 /* Reset the page selec to its original value */
1768 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1769 default_page);
1770 if (ret_val)
1771 goto out;
1772 break;
1773 case M88E1112_E_PHY_ID:
1774 /* Remember the original page select and set it to 5 */
1775 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
1776 &default_page);
1777 if (ret_val)
1778 goto out;
1779
1780 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
1781 if (ret_val)
1782 goto out;
1783
1784 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
1785 &phy_data);
1786 if (ret_val)
1787 goto out;
1788
1789 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1790 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1791 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
1792 ret_val = -E1000_ERR_PHY;
1793 goto out;
1794 }
1795
1796 phy->min_cable_length = e1000_m88_cable_length_table[index];
1797 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
1798
1799 phy->cable_length = (phy->min_cable_length +
1800 phy->max_cable_length) / 2;
1801
1802 /* Reset the page select to its original value */
1803 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
1804 default_page);
1805 if (ret_val)
1806 goto out;
1807
1808 break;
1809 default:
1810 ret_val = -E1000_ERR_PHY;
1811 goto out;
1812 }
1813
1814 out:
1815 return ret_val;
1816 }
1817
1818 /**
1819 * igb_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1820 * @hw: pointer to the HW structure
1821 *
1822 * The automatic gain control (agc) normalizes the amplitude of the
1823 * received signal, adjusting for the attenuation produced by the
1824 * cable. By reading the AGC registers, which represent the
1825 * combination of coarse and fine gain value, the value can be put
1826 * into a lookup table to obtain the approximate cable length
1827 * for each channel.
1828 **/
1829 s32 igb_get_cable_length_igp_2(struct e1000_hw *hw)
1830 {
1831 struct e1000_phy_info *phy = &hw->phy;
1832 s32 ret_val = 0;
1833 u16 phy_data, i, agc_value = 0;
1834 u16 cur_agc_index, max_agc_index = 0;
1835 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1836 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
1837 IGP02E1000_PHY_AGC_A,
1838 IGP02E1000_PHY_AGC_B,
1839 IGP02E1000_PHY_AGC_C,
1840 IGP02E1000_PHY_AGC_D
1841 };
1842
1843 /* Read the AGC registers for all channels */
1844 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1845 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
1846 if (ret_val)
1847 goto out;
1848
1849 /*
1850 * Getting bits 15:9, which represent the combination of
1851 * coarse and fine gain values. The result is a number
1852 * that can be put into the lookup table to obtain the
1853 * approximate cable length.
1854 */
1855 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1856 IGP02E1000_AGC_LENGTH_MASK;
1857
1858 /* Array index bound check. */
1859 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1860 (cur_agc_index == 0)) {
1861 ret_val = -E1000_ERR_PHY;
1862 goto out;
1863 }
1864
1865 /* Remove min & max AGC values from calculation. */
1866 if (e1000_igp_2_cable_length_table[min_agc_index] >
1867 e1000_igp_2_cable_length_table[cur_agc_index])
1868 min_agc_index = cur_agc_index;
1869 if (e1000_igp_2_cable_length_table[max_agc_index] <
1870 e1000_igp_2_cable_length_table[cur_agc_index])
1871 max_agc_index = cur_agc_index;
1872
1873 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1874 }
1875
1876 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1877 e1000_igp_2_cable_length_table[max_agc_index]);
1878 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1879
1880 /* Calculate cable length with the error range of +/- 10 meters. */
1881 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1882 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1883 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1884
1885 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1886
1887 out:
1888 return ret_val;
1889 }
1890
1891 /**
1892 * igb_get_phy_info_m88 - Retrieve PHY information
1893 * @hw: pointer to the HW structure
1894 *
1895 * Valid for only copper links. Read the PHY status register (sticky read)
1896 * to verify that link is up. Read the PHY special control register to
1897 * determine the polarity and 10base-T extended distance. Read the PHY
1898 * special status register to determine MDI/MDIx and current speed. If
1899 * speed is 1000, then determine cable length, local and remote receiver.
1900 **/
1901 s32 igb_get_phy_info_m88(struct e1000_hw *hw)
1902 {
1903 struct e1000_phy_info *phy = &hw->phy;
1904 s32 ret_val;
1905 u16 phy_data;
1906 bool link;
1907
1908 if (phy->media_type != e1000_media_type_copper) {
1909 hw_dbg("Phy info is only valid for copper media\n");
1910 ret_val = -E1000_ERR_CONFIG;
1911 goto out;
1912 }
1913
1914 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1915 if (ret_val)
1916 goto out;
1917
1918 if (!link) {
1919 hw_dbg("Phy info is only valid if link is up\n");
1920 ret_val = -E1000_ERR_CONFIG;
1921 goto out;
1922 }
1923
1924 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1925 if (ret_val)
1926 goto out;
1927
1928 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
1929 ? true : false;
1930
1931 ret_val = igb_check_polarity_m88(hw);
1932 if (ret_val)
1933 goto out;
1934
1935 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1936 if (ret_val)
1937 goto out;
1938
1939 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? true : false;
1940
1941 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1942 ret_val = phy->ops.get_cable_length(hw);
1943 if (ret_val)
1944 goto out;
1945
1946 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
1947 if (ret_val)
1948 goto out;
1949
1950 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1951 ? e1000_1000t_rx_status_ok
1952 : e1000_1000t_rx_status_not_ok;
1953
1954 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1955 ? e1000_1000t_rx_status_ok
1956 : e1000_1000t_rx_status_not_ok;
1957 } else {
1958 /* Set values to "undefined" */
1959 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1960 phy->local_rx = e1000_1000t_rx_status_undefined;
1961 phy->remote_rx = e1000_1000t_rx_status_undefined;
1962 }
1963
1964 out:
1965 return ret_val;
1966 }
1967
1968 /**
1969 * igb_get_phy_info_igp - Retrieve igp PHY information
1970 * @hw: pointer to the HW structure
1971 *
1972 * Read PHY status to determine if link is up. If link is up, then
1973 * set/determine 10base-T extended distance and polarity correction. Read
1974 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1975 * determine on the cable length, local and remote receiver.
1976 **/
1977 s32 igb_get_phy_info_igp(struct e1000_hw *hw)
1978 {
1979 struct e1000_phy_info *phy = &hw->phy;
1980 s32 ret_val;
1981 u16 data;
1982 bool link;
1983
1984 ret_val = igb_phy_has_link(hw, 1, 0, &link);
1985 if (ret_val)
1986 goto out;
1987
1988 if (!link) {
1989 hw_dbg("Phy info is only valid if link is up\n");
1990 ret_val = -E1000_ERR_CONFIG;
1991 goto out;
1992 }
1993
1994 phy->polarity_correction = true;
1995
1996 ret_val = igb_check_polarity_igp(hw);
1997 if (ret_val)
1998 goto out;
1999
2000 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2001 if (ret_val)
2002 goto out;
2003
2004 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? true : false;
2005
2006 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2007 IGP01E1000_PSSR_SPEED_1000MBPS) {
2008 ret_val = phy->ops.get_cable_length(hw);
2009 if (ret_val)
2010 goto out;
2011
2012 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2013 if (ret_val)
2014 goto out;
2015
2016 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2017 ? e1000_1000t_rx_status_ok
2018 : e1000_1000t_rx_status_not_ok;
2019
2020 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2021 ? e1000_1000t_rx_status_ok
2022 : e1000_1000t_rx_status_not_ok;
2023 } else {
2024 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2025 phy->local_rx = e1000_1000t_rx_status_undefined;
2026 phy->remote_rx = e1000_1000t_rx_status_undefined;
2027 }
2028
2029 out:
2030 return ret_val;
2031 }
2032
2033 /**
2034 * igb_phy_sw_reset - PHY software reset
2035 * @hw: pointer to the HW structure
2036 *
2037 * Does a software reset of the PHY by reading the PHY control register and
2038 * setting/write the control register reset bit to the PHY.
2039 **/
2040 s32 igb_phy_sw_reset(struct e1000_hw *hw)
2041 {
2042 s32 ret_val = 0;
2043 u16 phy_ctrl;
2044
2045 if (!(hw->phy.ops.read_reg))
2046 goto out;
2047
2048 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2049 if (ret_val)
2050 goto out;
2051
2052 phy_ctrl |= MII_CR_RESET;
2053 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2054 if (ret_val)
2055 goto out;
2056
2057 udelay(1);
2058
2059 out:
2060 return ret_val;
2061 }
2062
2063 /**
2064 * igb_phy_hw_reset - PHY hardware reset
2065 * @hw: pointer to the HW structure
2066 *
2067 * Verify the reset block is not blocking us from resetting. Acquire
2068 * semaphore (if necessary) and read/set/write the device control reset
2069 * bit in the PHY. Wait the appropriate delay time for the device to
2070 * reset and relase the semaphore (if necessary).
2071 **/
2072 s32 igb_phy_hw_reset(struct e1000_hw *hw)
2073 {
2074 struct e1000_phy_info *phy = &hw->phy;
2075 s32 ret_val;
2076 u32 ctrl;
2077
2078 ret_val = igb_check_reset_block(hw);
2079 if (ret_val) {
2080 ret_val = 0;
2081 goto out;
2082 }
2083
2084 ret_val = phy->ops.acquire(hw);
2085 if (ret_val)
2086 goto out;
2087
2088 ctrl = rd32(E1000_CTRL);
2089 wr32(E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2090 wrfl();
2091
2092 udelay(phy->reset_delay_us);
2093
2094 wr32(E1000_CTRL, ctrl);
2095 wrfl();
2096
2097 udelay(150);
2098
2099 phy->ops.release(hw);
2100
2101 ret_val = phy->ops.get_cfg_done(hw);
2102
2103 out:
2104 return ret_val;
2105 }
2106
2107 /**
2108 * igb_phy_init_script_igp3 - Inits the IGP3 PHY
2109 * @hw: pointer to the HW structure
2110 *
2111 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2112 **/
2113 s32 igb_phy_init_script_igp3(struct e1000_hw *hw)
2114 {
2115 hw_dbg("Running IGP 3 PHY init script\n");
2116
2117 /* PHY init IGP 3 */
2118 /* Enable rise/fall, 10-mode work in class-A */
2119 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2120 /* Remove all caps from Replica path filter */
2121 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2122 /* Bias trimming for ADC, AFE and Driver (Default) */
2123 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2124 /* Increase Hybrid poly bias */
2125 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2126 /* Add 4% to TX amplitude in Giga mode */
2127 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2128 /* Disable trimming (TTT) */
2129 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2130 /* Poly DC correction to 94.6% + 2% for all channels */
2131 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2132 /* ABS DC correction to 95.9% */
2133 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2134 /* BG temp curve trim */
2135 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2136 /* Increasing ADC OPAMP stage 1 currents to max */
2137 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2138 /* Force 1000 ( required for enabling PHY regs configuration) */
2139 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2140 /* Set upd_freq to 6 */
2141 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2142 /* Disable NPDFE */
2143 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2144 /* Disable adaptive fixed FFE (Default) */
2145 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2146 /* Enable FFE hysteresis */
2147 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2148 /* Fixed FFE for short cable lengths */
2149 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2150 /* Fixed FFE for medium cable lengths */
2151 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2152 /* Fixed FFE for long cable lengths */
2153 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2154 /* Enable Adaptive Clip Threshold */
2155 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2156 /* AHT reset limit to 1 */
2157 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2158 /* Set AHT master delay to 127 msec */
2159 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2160 /* Set scan bits for AHT */
2161 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2162 /* Set AHT Preset bits */
2163 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2164 /* Change integ_factor of channel A to 3 */
2165 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2166 /* Change prop_factor of channels BCD to 8 */
2167 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2168 /* Change cg_icount + enable integbp for channels BCD */
2169 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2170 /*
2171 * Change cg_icount + enable integbp + change prop_factor_master
2172 * to 8 for channel A
2173 */
2174 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2175 /* Disable AHT in Slave mode on channel A */
2176 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2177 /*
2178 * Enable LPLU and disable AN to 1000 in non-D0a states,
2179 * Enable SPD+B2B
2180 */
2181 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2182 /* Enable restart AN on an1000_dis change */
2183 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2184 /* Enable wh_fifo read clock in 10/100 modes */
2185 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2186 /* Restart AN, Speed selection is 1000 */
2187 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2188
2189 return 0;
2190 }
2191
2192 /**
2193 * igb_power_up_phy_copper - Restore copper link in case of PHY power down
2194 * @hw: pointer to the HW structure
2195 *
2196 * In the case of a PHY power down to save power, or to turn off link during a
2197 * driver unload, restore the link to previous settings.
2198 **/
2199 void igb_power_up_phy_copper(struct e1000_hw *hw)
2200 {
2201 u16 mii_reg = 0;
2202 u16 power_reg = 0;
2203
2204 /* The PHY will retain its settings across a power down/up cycle */
2205 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2206 mii_reg &= ~MII_CR_POWER_DOWN;
2207 if (hw->phy.type == e1000_phy_i210) {
2208 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2209 power_reg &= ~GS40G_CS_POWER_DOWN;
2210 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2211 }
2212 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2213 }
2214
2215 /**
2216 * igb_power_down_phy_copper - Power down copper PHY
2217 * @hw: pointer to the HW structure
2218 *
2219 * Power down PHY to save power when interface is down and wake on lan
2220 * is not enabled.
2221 **/
2222 void igb_power_down_phy_copper(struct e1000_hw *hw)
2223 {
2224 u16 mii_reg = 0;
2225 u16 power_reg = 0;
2226
2227 /* The PHY will retain its settings across a power down/up cycle */
2228 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2229 mii_reg |= MII_CR_POWER_DOWN;
2230
2231 /* i210 Phy requires an additional bit for power up/down */
2232 if (hw->phy.type == e1000_phy_i210) {
2233 hw->phy.ops.read_reg(hw, GS40G_COPPER_SPEC, &power_reg);
2234 power_reg |= GS40G_CS_POWER_DOWN;
2235 hw->phy.ops.write_reg(hw, GS40G_COPPER_SPEC, power_reg);
2236 }
2237 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2238 msleep(1);
2239 }
2240
2241 /**
2242 * igb_check_polarity_82580 - Checks the polarity.
2243 * @hw: pointer to the HW structure
2244 *
2245 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2246 *
2247 * Polarity is determined based on the PHY specific status register.
2248 **/
2249 static s32 igb_check_polarity_82580(struct e1000_hw *hw)
2250 {
2251 struct e1000_phy_info *phy = &hw->phy;
2252 s32 ret_val;
2253 u16 data;
2254
2255
2256 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2257
2258 if (!ret_val)
2259 phy->cable_polarity = (data & I82580_PHY_STATUS2_REV_POLARITY)
2260 ? e1000_rev_polarity_reversed
2261 : e1000_rev_polarity_normal;
2262
2263 return ret_val;
2264 }
2265
2266 /**
2267 * igb_phy_force_speed_duplex_82580 - Force speed/duplex for I82580 PHY
2268 * @hw: pointer to the HW structure
2269 *
2270 * Calls the PHY setup function to force speed and duplex. Clears the
2271 * auto-crossover to force MDI manually. Waits for link and returns
2272 * successful if link up is successful, else -E1000_ERR_PHY (-2).
2273 **/
2274 s32 igb_phy_force_speed_duplex_82580(struct e1000_hw *hw)
2275 {
2276 struct e1000_phy_info *phy = &hw->phy;
2277 s32 ret_val;
2278 u16 phy_data;
2279 bool link;
2280
2281
2282 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2283 if (ret_val)
2284 goto out;
2285
2286 igb_phy_force_speed_duplex_setup(hw, &phy_data);
2287
2288 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2289 if (ret_val)
2290 goto out;
2291
2292 /*
2293 * Clear Auto-Crossover to force MDI manually. 82580 requires MDI
2294 * forced whenever speed and duplex are forced.
2295 */
2296 ret_val = phy->ops.read_reg(hw, I82580_PHY_CTRL_2, &phy_data);
2297 if (ret_val)
2298 goto out;
2299
2300 phy_data &= ~I82580_PHY_CTRL2_MDIX_CFG_MASK;
2301
2302 ret_val = phy->ops.write_reg(hw, I82580_PHY_CTRL_2, phy_data);
2303 if (ret_val)
2304 goto out;
2305
2306 hw_dbg("I82580_PHY_CTRL_2: %X\n", phy_data);
2307
2308 udelay(1);
2309
2310 if (phy->autoneg_wait_to_complete) {
2311 hw_dbg("Waiting for forced speed/duplex link on 82580 phy\n");
2312
2313 ret_val = igb_phy_has_link(hw,
2314 PHY_FORCE_LIMIT,
2315 100000,
2316 &link);
2317 if (ret_val)
2318 goto out;
2319
2320 if (!link)
2321 hw_dbg("Link taking longer than expected.\n");
2322
2323 /* Try once more */
2324 ret_val = igb_phy_has_link(hw,
2325 PHY_FORCE_LIMIT,
2326 100000,
2327 &link);
2328 if (ret_val)
2329 goto out;
2330 }
2331
2332 out:
2333 return ret_val;
2334 }
2335
2336 /**
2337 * igb_get_phy_info_82580 - Retrieve I82580 PHY information
2338 * @hw: pointer to the HW structure
2339 *
2340 * Read PHY status to determine if link is up. If link is up, then
2341 * set/determine 10base-T extended distance and polarity correction. Read
2342 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2343 * determine on the cable length, local and remote receiver.
2344 **/
2345 s32 igb_get_phy_info_82580(struct e1000_hw *hw)
2346 {
2347 struct e1000_phy_info *phy = &hw->phy;
2348 s32 ret_val;
2349 u16 data;
2350 bool link;
2351
2352
2353 ret_val = igb_phy_has_link(hw, 1, 0, &link);
2354 if (ret_val)
2355 goto out;
2356
2357 if (!link) {
2358 hw_dbg("Phy info is only valid if link is up\n");
2359 ret_val = -E1000_ERR_CONFIG;
2360 goto out;
2361 }
2362
2363 phy->polarity_correction = true;
2364
2365 ret_val = igb_check_polarity_82580(hw);
2366 if (ret_val)
2367 goto out;
2368
2369 ret_val = phy->ops.read_reg(hw, I82580_PHY_STATUS_2, &data);
2370 if (ret_val)
2371 goto out;
2372
2373 phy->is_mdix = (data & I82580_PHY_STATUS2_MDIX) ? true : false;
2374
2375 if ((data & I82580_PHY_STATUS2_SPEED_MASK) ==
2376 I82580_PHY_STATUS2_SPEED_1000MBPS) {
2377 ret_val = hw->phy.ops.get_cable_length(hw);
2378 if (ret_val)
2379 goto out;
2380
2381 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2382 if (ret_val)
2383 goto out;
2384
2385 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2386 ? e1000_1000t_rx_status_ok
2387 : e1000_1000t_rx_status_not_ok;
2388
2389 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2390 ? e1000_1000t_rx_status_ok
2391 : e1000_1000t_rx_status_not_ok;
2392 } else {
2393 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2394 phy->local_rx = e1000_1000t_rx_status_undefined;
2395 phy->remote_rx = e1000_1000t_rx_status_undefined;
2396 }
2397
2398 out:
2399 return ret_val;
2400 }
2401
2402 /**
2403 * igb_get_cable_length_82580 - Determine cable length for 82580 PHY
2404 * @hw: pointer to the HW structure
2405 *
2406 * Reads the diagnostic status register and verifies result is valid before
2407 * placing it in the phy_cable_length field.
2408 **/
2409 s32 igb_get_cable_length_82580(struct e1000_hw *hw)
2410 {
2411 struct e1000_phy_info *phy = &hw->phy;
2412 s32 ret_val;
2413 u16 phy_data, length;
2414
2415
2416 ret_val = phy->ops.read_reg(hw, I82580_PHY_DIAG_STATUS, &phy_data);
2417 if (ret_val)
2418 goto out;
2419
2420 length = (phy_data & I82580_DSTATUS_CABLE_LENGTH) >>
2421 I82580_DSTATUS_CABLE_LENGTH_SHIFT;
2422
2423 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2424 ret_val = -E1000_ERR_PHY;
2425
2426 phy->cable_length = length;
2427
2428 out:
2429 return ret_val;
2430 }
2431
2432 /**
2433 * igb_write_phy_reg_gs40g - Write GS40G PHY register
2434 * @hw: pointer to the HW structure
2435 * @offset: lower half is register offset to write to
2436 * upper half is page to use.
2437 * @data: data to write at register offset
2438 *
2439 * Acquires semaphore, if necessary, then writes the data to PHY register
2440 * at the offset. Release any acquired semaphores before exiting.
2441 **/
2442 s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data)
2443 {
2444 s32 ret_val;
2445 u16 page = offset >> GS40G_PAGE_SHIFT;
2446
2447 offset = offset & GS40G_OFFSET_MASK;
2448 ret_val = hw->phy.ops.acquire(hw);
2449 if (ret_val)
2450 return ret_val;
2451
2452 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2453 if (ret_val)
2454 goto release;
2455 ret_val = igb_write_phy_reg_mdic(hw, offset, data);
2456
2457 release:
2458 hw->phy.ops.release(hw);
2459 return ret_val;
2460 }
2461
2462 /**
2463 * igb_read_phy_reg_gs40g - Read GS40G PHY register
2464 * @hw: pointer to the HW structure
2465 * @offset: lower half is register offset to read to
2466 * upper half is page to use.
2467 * @data: data to read at register offset
2468 *
2469 * Acquires semaphore, if necessary, then reads the data in the PHY register
2470 * at the offset. Release any acquired semaphores before exiting.
2471 **/
2472 s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data)
2473 {
2474 s32 ret_val;
2475 u16 page = offset >> GS40G_PAGE_SHIFT;
2476
2477 offset = offset & GS40G_OFFSET_MASK;
2478 ret_val = hw->phy.ops.acquire(hw);
2479 if (ret_val)
2480 return ret_val;
2481
2482 ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page);
2483 if (ret_val)
2484 goto release;
2485 ret_val = igb_read_phy_reg_mdic(hw, offset, data);
2486
2487 release:
2488 hw->phy.ops.release(hw);
2489 return ret_val;
2490 }
2491
2492 /**
2493 * igb_set_master_slave_mode - Setup PHY for Master/slave mode
2494 * @hw: pointer to the HW structure
2495 *
2496 * Sets up Master/slave mode
2497 **/
2498 static s32 igb_set_master_slave_mode(struct e1000_hw *hw)
2499 {
2500 s32 ret_val;
2501 u16 phy_data;
2502
2503 /* Resolve Master/Slave mode */
2504 ret_val = hw->phy.ops.read_reg(hw, PHY_1000T_CTRL, &phy_data);
2505 if (ret_val)
2506 return ret_val;
2507
2508 /* load defaults for future use */
2509 hw->phy.original_ms_type = (phy_data & CR_1000T_MS_ENABLE) ?
2510 ((phy_data & CR_1000T_MS_VALUE) ?
2511 e1000_ms_force_master :
2512 e1000_ms_force_slave) : e1000_ms_auto;
2513
2514 switch (hw->phy.ms_type) {
2515 case e1000_ms_force_master:
2516 phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
2517 break;
2518 case e1000_ms_force_slave:
2519 phy_data |= CR_1000T_MS_ENABLE;
2520 phy_data &= ~(CR_1000T_MS_VALUE);
2521 break;
2522 case e1000_ms_auto:
2523 phy_data &= ~CR_1000T_MS_ENABLE;
2524 /* fall-through */
2525 default:
2526 break;
2527 }
2528
2529 return hw->phy.ops.write_reg(hw, PHY_1000T_CTRL, phy_data);
2530 }
Linux 2.6 libata-dev (mirror)