arch/sh/kernel/cpu/sh4a/clock-sh7724.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7724.c
   3  *
   4  * SH7724 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <asm/clkdev.h>
  26 #include <asm/clock.h>
  27 #include <asm/hwblk.h>
  28 #include <cpu/sh7724.h>
  29
  30 /* SH7724 registers */
  31 #define FRQCRA          0xa4150000
  32 #define FRQCRB          0xa4150004
  33 #define VCLKCR          0xa4150048
  34 #define FCLKACR         0xa4150008
  35 #define FCLKBCR         0xa415000c
  36 #define IRDACLKCR       0xa4150018
  37 #define PLLCR           0xa4150024
  38 #define SPUCLKCR        0xa415003c
  39 #define FLLFRQ          0xa4150050
  40 #define LSTATS          0xa4150060
  41
  42 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  43 static struct clk r_clk = {
  44         .name           = "rclk",
  45         .id             = -1,
  46         .rate           = 32768,
  47 };
  48
  49 /*
  50  * Default rate for the root input clock, reset this with clk_set_rate()
  51  * from the platform code.
  52  */
  53 struct clk extal_clk = {
  54         .name           = "extal",
  55         .id             = -1,
  56         .rate           = 33333333,
  57 };
  58
  59 /* The fll multiplies the 32khz r_clk, may be used instead of extal */
  60 static unsigned long fll_recalc(struct clk *clk)
  61 {
  62         unsigned long mult = 0;
  63         unsigned long div = 1;
  64
  65         if (__raw_readl(PLLCR) & 0x1000)
  66                 mult = __raw_readl(FLLFRQ) & 0x3ff;
  67
  68         if (__raw_readl(FLLFRQ) & 0x4000)
  69                 div = 2;
  70
  71         return (clk->parent->rate * mult) / div;
  72 }
  73
  74 static struct clk_ops fll_clk_ops = {
  75         .recalc         = fll_recalc,
  76 };
  77
  78 static struct clk fll_clk = {
  79         .name           = "fll_clk",
  80         .id             = -1,
  81         .ops            = &fll_clk_ops,
  82         .parent         = &r_clk,
  83         .flags          = CLK_ENABLE_ON_INIT,
  84 };
  85
  86 static unsigned long pll_recalc(struct clk *clk)
  87 {
  88         unsigned long mult = 1;
  89
  90         if (__raw_readl(PLLCR) & 0x4000)
  91                 mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2;
  92
  93         return clk->parent->rate * mult;
  94 }
  95
  96 static struct clk_ops pll_clk_ops = {
  97         .recalc         = pll_recalc,
  98 };
  99
 100 static struct clk pll_clk = {
 101         .name           = "pll_clk",
 102         .id             = -1,
 103         .ops            = &pll_clk_ops,
 104         .flags          = CLK_ENABLE_ON_INIT,
 105 };
 106
 107 /* A fixed divide-by-3 block use by the div6 clocks */
 108 static unsigned long div3_recalc(struct clk *clk)
 109 {
 110         return clk->parent->rate / 3;
 111 }
 112
 113 static struct clk_ops div3_clk_ops = {
 114         .recalc         = div3_recalc,
 115 };
 116
 117 static struct clk div3_clk = {
 118         .name           = "div3_clk",
 119         .id             = -1,
 120         .ops            = &div3_clk_ops,
 121         .parent         = &pll_clk,
 122 };
 123
 124 struct clk *main_clks[] = {
 125         &r_clk,
 126         &extal_clk,
 127         &fll_clk,
 128         &pll_clk,
 129         &div3_clk,
 130 };
 131
 132 static void div4_kick(struct clk *clk)
 133 {
 134         unsigned long value;
 135
 136         /* set KICK bit in FRQCRA to update hardware setting */
 137         value = __raw_readl(FRQCRA);
 138         value |= (1 << 31);
 139         __raw_writel(value, FRQCRA);
 140 }
 141
 142 static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 };
 143
 144 static struct clk_div_mult_table div4_div_mult_table = {
 145         .divisors = divisors,
 146         .nr_divisors = ARRAY_SIZE(divisors),
 147 };
 148
 149 static struct clk_div4_table div4_table = {
 150         .div_mult_table = &div4_div_mult_table,
 151         .kick = div4_kick,
 152 };
 153
 154 enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR };
 155
 156 #define DIV4(_str, _reg, _bit, _mask, _flags) \
 157   SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
 158
 159 struct clk div4_clks[DIV4_NR] = {
 160         [DIV4_I] = DIV4("cpu_clk", FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
 161         [DIV4_SH] = DIV4("shyway_clk", FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
 162         [DIV4_B] = DIV4("bus_clk", FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
 163         [DIV4_P] = DIV4("peripheral_clk", FRQCRA, 0, 0x2f7c, 0),
 164         [DIV4_M1] = DIV4("vpu_clk", FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
 165 };
 166
 167 enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
 168
 169 struct clk div6_clks[DIV6_NR] = {
 170         [DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
 171         [DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
 172         [DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
 173         [DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
 174         [DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
 175 };
 176
 177 static struct clk mstp_clks[HWBLK_NR] = {
 178         SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 179         SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 180         SH_HWBLK_CLK(HWBLK_OC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 181         SH_HWBLK_CLK(HWBLK_RSMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
 182         SH_HWBLK_CLK(HWBLK_ILMEM, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 183         SH_HWBLK_CLK(HWBLK_L2C, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
 184         SH_HWBLK_CLK(HWBLK_FPU, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
 185         SH_HWBLK_CLK(HWBLK_INTC, &div4_clks[DIV4_P], CLK_ENABLE_ON_INIT),
 186         SH_HWBLK_CLK(HWBLK_DMAC0, &div4_clks[DIV4_B], 0),
 187         SH_HWBLK_CLK(HWBLK_SHYWAY, &div4_clks[DIV4_SH], CLK_ENABLE_ON_INIT),
 188         SH_HWBLK_CLK(HWBLK_HUDI, &div4_clks[DIV4_P], 0),
 189         SH_HWBLK_CLK(HWBLK_UBC, &div4_clks[DIV4_I], 0),
 190         SH_HWBLK_CLK(HWBLK_TMU0, &div4_clks[DIV4_P], 0),
 191         SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
 192         SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
 193         SH_HWBLK_CLK(HWBLK_DMAC1, &div4_clks[DIV4_B], 0),
 194         SH_HWBLK_CLK(HWBLK_TMU1, &div4_clks[DIV4_P], 0),
 195         SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
 196         SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
 197         SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
 198         SH_HWBLK_CLK(HWBLK_SCIF3, &div4_clks[DIV4_B], 0),
 199         SH_HWBLK_CLK(HWBLK_SCIF4, &div4_clks[DIV4_B], 0),
 200         SH_HWBLK_CLK(HWBLK_SCIF5, &div4_clks[DIV4_B], 0),
 201         SH_HWBLK_CLK(HWBLK_MSIOF0, &div4_clks[DIV4_B], 0),
 202         SH_HWBLK_CLK(HWBLK_MSIOF1, &div4_clks[DIV4_B], 0),
 203
 204         SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
 205         SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
 206         SH_HWBLK_CLK(HWBLK_IIC0, &div4_clks[DIV4_P], 0),
 207         SH_HWBLK_CLK(HWBLK_IIC1, &div4_clks[DIV4_P], 0),
 208
 209         SH_HWBLK_CLK(HWBLK_MMC, &div4_clks[DIV4_B], 0),
 210         SH_HWBLK_CLK(HWBLK_ETHER, &div4_clks[DIV4_B], 0),
 211         SH_HWBLK_CLK(HWBLK_ATAPI, &div4_clks[DIV4_B], 0),
 212         SH_HWBLK_CLK(HWBLK_TPU, &div4_clks[DIV4_B], 0),
 213         SH_HWBLK_CLK(HWBLK_IRDA, &div4_clks[DIV4_P], 0),
 214         SH_HWBLK_CLK(HWBLK_TSIF, &div4_clks[DIV4_B], 0),
 215         SH_HWBLK_CLK(HWBLK_USB1, &div4_clks[DIV4_B], 0),
 216         SH_HWBLK_CLK(HWBLK_USB0, &div4_clks[DIV4_B], 0),
 217         SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
 218         SH_HWBLK_CLK(HWBLK_SDHI0, &div4_clks[DIV4_B], 0),
 219         SH_HWBLK_CLK(HWBLK_SDHI1, &div4_clks[DIV4_B], 0),
 220         SH_HWBLK_CLK(HWBLK_VEU1, &div4_clks[DIV4_B], 0),
 221         SH_HWBLK_CLK(HWBLK_CEU1, &div4_clks[DIV4_B], 0),
 222         SH_HWBLK_CLK(HWBLK_BEU1, &div4_clks[DIV4_B], 0),
 223         SH_HWBLK_CLK(HWBLK_2DDMAC, &div4_clks[DIV4_SH], 0),
 224         SH_HWBLK_CLK(HWBLK_SPU, &div4_clks[DIV4_B], 0),
 225         SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
 226         SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
 227         SH_HWBLK_CLK(HWBLK_BEU0, &div4_clks[DIV4_B], 0),
 228         SH_HWBLK_CLK(HWBLK_CEU0, &div4_clks[DIV4_B], 0),
 229         SH_HWBLK_CLK(HWBLK_VEU0, &div4_clks[DIV4_B], 0),
 230         SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
 231         SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_B], 0),
 232 };
 233
 234 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 235
 236 static struct clk_lookup lookups[] = {
 237         /* DIV6 clocks */
 238         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
 239         CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
 240         CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
 241         CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
 242         CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
 243
 244         /* MSTP clocks */
 245         CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]),
 246         CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]),
 247         CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]),
 248         CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]),
 249         CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]),
 250         CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]),
 251         CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]),
 252         CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]),
 253         CLKDEV_CON_ID("dmac0", &mstp_clks[HWBLK_DMAC0]),
 254         CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]),
 255         CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]),
 256         CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]),
 257         {
 258                 /* TMU0 */
 259                 .dev_id         = "sh_tmu.0",
 260                 .con_id         = "tmu_fck",
 261                 .clk            = &mstp_clks[HWBLK_TMU0],
 262         }, {
 263                 /* TMU1 */
 264                 .dev_id         = "sh_tmu.1",
 265                 .con_id         = "tmu_fck",
 266                 .clk            = &mstp_clks[HWBLK_TMU0],
 267         }, {
 268                 /* TMU2 */
 269                 .dev_id         = "sh_tmu.2",
 270                 .con_id         = "tmu_fck",
 271                 .clk            = &mstp_clks[HWBLK_TMU0],
 272         }, {
 273                 /* TMU3 */
 274                 .dev_id         = "sh_tmu.3",
 275                 .con_id         = "tmu_fck",
 276                 .clk            = &mstp_clks[HWBLK_TMU1],
 277         },
 278         CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
 279         CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
 280         CLKDEV_CON_ID("dmac1", &mstp_clks[HWBLK_DMAC1]),
 281         {
 282                 /* TMU4 */
 283                 .dev_id         = "sh_tmu.4",
 284                 .con_id         = "tmu_fck",
 285                 .clk            = &mstp_clks[HWBLK_TMU1],
 286         }, {
 287                 /* TMU5 */
 288                 .dev_id         = "sh_tmu.5",
 289                 .con_id         = "tmu_fck",
 290                 .clk            = &mstp_clks[HWBLK_TMU1],
 291         }, {
 292                 /* SCIF0 */
 293                 .dev_id         = "sh-sci.0",
 294                 .con_id         = "sci_fck",
 295                 .clk            = &mstp_clks[HWBLK_SCIF0],
 296         }, {
 297                 /* SCIF1 */
 298                 .dev_id         = "sh-sci.1",
 299                 .con_id         = "sci_fck",
 300                 .clk            = &mstp_clks[HWBLK_SCIF1],
 301         }, {
 302                 /* SCIF2 */
 303                 .dev_id         = "sh-sci.2",
 304                 .con_id         = "sci_fck",
 305                 .clk            = &mstp_clks[HWBLK_SCIF2],
 306         }, {
 307                 /* SCIF3 */
 308                 .dev_id         = "sh-sci.3",
 309                 .con_id         = "sci_fck",
 310                 .clk            = &mstp_clks[HWBLK_SCIF3],
 311         }, {
 312                 /* SCIF4 */
 313                 .dev_id         = "sh-sci.4",
 314                 .con_id         = "sci_fck",
 315                 .clk            = &mstp_clks[HWBLK_SCIF4],
 316         }, {
 317                 /* SCIF5 */
 318                 .dev_id         = "sh-sci.5",
 319                 .con_id         = "sci_fck",
 320                 .clk            = &mstp_clks[HWBLK_SCIF5],
 321         },
 322         CLKDEV_CON_ID("msiof0", &mstp_clks[HWBLK_MSIOF0]),
 323         CLKDEV_CON_ID("msiof1", &mstp_clks[HWBLK_MSIOF1]),
 324         CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
 325         CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
 326         CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC0]),
 327         CLKDEV_CON_ID("i2c1", &mstp_clks[HWBLK_IIC1]),
 328         CLKDEV_CON_ID("mmc0", &mstp_clks[HWBLK_MMC]),
 329         CLKDEV_CON_ID("eth0", &mstp_clks[HWBLK_ETHER]),
 330         CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]),
 331         CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]),
 332         CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]),
 333         CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]),
 334         CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]),
 335         CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]),
 336         CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
 337         CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI0]),
 338         CLKDEV_CON_ID("sdhi1", &mstp_clks[HWBLK_SDHI1]),
 339         CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]),
 340         CLKDEV_CON_ID("ceu1", &mstp_clks[HWBLK_CEU1]),
 341         CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]),
 342         CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]),
 343         CLKDEV_CON_ID("spu0", &mstp_clks[HWBLK_SPU]),
 344         CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
 345         CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
 346         CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]),
 347         CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU0]),
 348         CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]),
 349         CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
 350         CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
 351 };
 352
 353 int __init arch_clk_init(void)
 354 {
 355         int k, ret = 0;
 356
 357         /* autodetect extal or fll configuration */
 358         if (__raw_readl(PLLCR) & 0x1000)
 359                 pll_clk.parent = &fll_clk;
 360         else
 361                 pll_clk.parent = &extal_clk;
 362
 363         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 364                 ret = clk_register(main_clks[k]);
 365
 366         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 367
 368         if (!ret)
 369                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 370
 371         if (!ret)
 372                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 373
 374         if (!ret)
 375                 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 376
 377         return ret;
 378 }