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hwmon: (vt8231) Use pr_fmt and pr_<level>
[linux-2.6/libata-dev.git] / drivers / net / sky2.c
blob39996bf3b2475ced9edca53b909aede96e356396
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/ip.h>
36 #include <linux/slab.h>
37 #include <net/ip.h>
38 #include <linux/tcp.h>
39 #include <linux/in.h>
40 #include <linux/delay.h>
41 #include <linux/workqueue.h>
42 #include <linux/if_vlan.h>
43 #include <linux/prefetch.h>
44 #include <linux/debugfs.h>
45 #include <linux/mii.h>
46
47 #include <asm/irq.h>
48
49 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
50 #define SKY2_VLAN_TAG_USED 1
51 #endif
52
53 #include "sky2.h"
54
55 #define DRV_NAME "sky2"
56 #define DRV_VERSION "1.28"
57
58 /*
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
61 * similar to Tigon3.
62 */
63
64 #define RX_LE_SIZE 1024
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68
69 /* This is the worst case number of transmit list elements for a single skb:
70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
71 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
72 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
73 #define TX_MAX_PENDING 1024
74 #define TX_DEF_PENDING 127
75
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
79
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
81
82 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
143 { 0 }
144 };
145
146 MODULE_DEVICE_TABLE(pci, sky2_id_table);
147
148 /* Avoid conditionals by using array */
149 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
150 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
151 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
152
153 static void sky2_set_multicast(struct net_device *dev);
154
155 /* Access to PHY via serial interconnect */
156 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
157 {
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
166 if (ctrl == 0xffff)
167 goto io_error;
168
169 if (!(ctrl & GM_SMI_CT_BUSY))
170 return 0;
171
172 udelay(10);
173 }
174
175 dev_warn(&hw->pdev->dev, "%s: phy write timeout\n", hw->dev[port]->name);
176 return -ETIMEDOUT;
177
178 io_error:
179 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
180 return -EIO;
181 }
182
183 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
184 {
185 int i;
186
187 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
188 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
189
190 for (i = 0; i < PHY_RETRIES; i++) {
191 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
192 if (ctrl == 0xffff)
193 goto io_error;
194
195 if (ctrl & GM_SMI_CT_RD_VAL) {
196 *val = gma_read16(hw, port, GM_SMI_DATA);
197 return 0;
198 }
199
200 udelay(10);
201 }
202
203 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
204 return -ETIMEDOUT;
205 io_error:
206 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
207 return -EIO;
208 }
209
210 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
211 {
212 u16 v;
213 __gm_phy_read(hw, port, reg, &v);
214 return v;
215 }
216
217
218 static void sky2_power_on(struct sky2_hw *hw)
219 {
220 /* switch power to VCC (WA for VAUX problem) */
221 sky2_write8(hw, B0_POWER_CTRL,
222 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
223
224 /* disable Core Clock Division, */
225 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
226
227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
228 /* enable bits are inverted */
229 sky2_write8(hw, B2_Y2_CLK_GATE,
230 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
231 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
232 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
233 else
234 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
235
236 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
237 u32 reg;
238
239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
240
241 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
242 /* set all bits to 0 except bits 15..12 and 8 */
243 reg &= P_ASPM_CONTROL_MSK;
244 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
245
246 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
247 /* set all bits to 0 except bits 28 & 27 */
248 reg &= P_CTL_TIM_VMAIN_AV_MSK;
249 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
250
251 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
252
253 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
254
255 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
256 reg = sky2_read32(hw, B2_GP_IO);
257 reg |= GLB_GPIO_STAT_RACE_DIS;
258 sky2_write32(hw, B2_GP_IO, reg);
259
260 sky2_read32(hw, B2_GP_IO);
261 }
262
263 /* Turn on "driver loaded" LED */
264 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
265 }
266
267 static void sky2_power_aux(struct sky2_hw *hw)
268 {
269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 else
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277
278 /* switch power to VAUX if supported and PME from D3cold */
279 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
280 pci_pme_capable(hw->pdev, PCI_D3cold))
281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
284
285 /* turn off "driver loaded LED" */
286 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
287 }
288
289 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
290 {
291 u16 reg;
292
293 /* disable all GMAC IRQ's */
294 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
295
296 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
297 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
300
301 reg = gma_read16(hw, port, GM_RX_CTRL);
302 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
303 gma_write16(hw, port, GM_RX_CTRL, reg);
304 }
305
306 /* flow control to advertise bits */
307 static const u16 copper_fc_adv[] = {
308 [FC_NONE] = 0,
309 [FC_TX] = PHY_M_AN_ASP,
310 [FC_RX] = PHY_M_AN_PC,
311 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
312 };
313
314 /* flow control to advertise bits when using 1000BaseX */
315 static const u16 fiber_fc_adv[] = {
316 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
317 [FC_TX] = PHY_M_P_ASYM_MD_X,
318 [FC_RX] = PHY_M_P_SYM_MD_X,
319 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
320 };
321
322 /* flow control to GMA disable bits */
323 static const u16 gm_fc_disable[] = {
324 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
325 [FC_TX] = GM_GPCR_FC_RX_DIS,
326 [FC_RX] = GM_GPCR_FC_TX_DIS,
327 [FC_BOTH] = 0,
328 };
329
330
331 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
332 {
333 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
334 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
335
336 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
337 !(hw->flags & SKY2_HW_NEWER_PHY)) {
338 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
339
340 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
341 PHY_M_EC_MAC_S_MSK);
342 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
343
344 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
345 if (hw->chip_id == CHIP_ID_YUKON_EC)
346 /* set downshift counter to 3x and enable downshift */
347 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
348 else
349 /* set master & slave downshift counter to 1x */
350 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
351
352 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
353 }
354
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 if (sky2_is_copper(hw)) {
357 if (!(hw->flags & SKY2_HW_GIGABIT)) {
358 /* enable automatic crossover */
359 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
360
361 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
362 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
363 u16 spec;
364
365 /* Enable Class A driver for FE+ A0 */
366 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
367 spec |= PHY_M_FESC_SEL_CL_A;
368 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
369 }
370 } else {
371 /* disable energy detect */
372 ctrl &= ~PHY_M_PC_EN_DET_MSK;
373
374 /* enable automatic crossover */
375 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
376
377 /* downshift on PHY 88E1112 and 88E1149 is changed */
378 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
379 (hw->flags & SKY2_HW_NEWER_PHY)) {
380 /* set downshift counter to 3x and enable downshift */
381 ctrl &= ~PHY_M_PC_DSC_MSK;
382 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
383 }
384 }
385 } else {
386 /* workaround for deviation #4.88 (CRC errors) */
387 /* disable Automatic Crossover */
388
389 ctrl &= ~PHY_M_PC_MDIX_MSK;
390 }
391
392 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393
394 /* special setup for PHY 88E1112 Fiber */
395 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
396 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
397
398 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
399 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
400 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
401 ctrl &= ~PHY_M_MAC_MD_MSK;
402 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
403 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
404
405 if (hw->pmd_type == 'P') {
406 /* select page 1 to access Fiber registers */
407 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
408
409 /* for SFP-module set SIGDET polarity to low */
410 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
411 ctrl |= PHY_M_FIB_SIGD_POL;
412 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
413 }
414
415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
416 }
417
418 ctrl = PHY_CT_RESET;
419 ct1000 = 0;
420 adv = PHY_AN_CSMA;
421 reg = 0;
422
423 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
424 if (sky2_is_copper(hw)) {
425 if (sky2->advertising & ADVERTISED_1000baseT_Full)
426 ct1000 |= PHY_M_1000C_AFD;
427 if (sky2->advertising & ADVERTISED_1000baseT_Half)
428 ct1000 |= PHY_M_1000C_AHD;
429 if (sky2->advertising & ADVERTISED_100baseT_Full)
430 adv |= PHY_M_AN_100_FD;
431 if (sky2->advertising & ADVERTISED_100baseT_Half)
432 adv |= PHY_M_AN_100_HD;
433 if (sky2->advertising & ADVERTISED_10baseT_Full)
434 adv |= PHY_M_AN_10_FD;
435 if (sky2->advertising & ADVERTISED_10baseT_Half)
436 adv |= PHY_M_AN_10_HD;
437
438 } else { /* special defines for FIBER (88E1040S only) */
439 if (sky2->advertising & ADVERTISED_1000baseT_Full)
440 adv |= PHY_M_AN_1000X_AFD;
441 if (sky2->advertising & ADVERTISED_1000baseT_Half)
442 adv |= PHY_M_AN_1000X_AHD;
443 }
444
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 } else {
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
450
451 /* Disable auto update for duplex flow control and duplex */
452 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
453
454 switch (sky2->speed) {
455 case SPEED_1000:
456 ctrl |= PHY_CT_SP1000;
457 reg |= GM_GPCR_SPEED_1000;
458 break;
459 case SPEED_100:
460 ctrl |= PHY_CT_SP100;
461 reg |= GM_GPCR_SPEED_100;
462 break;
463 }
464
465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
470 }
471
472 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
473 if (sky2_is_copper(hw))
474 adv |= copper_fc_adv[sky2->flow_mode];
475 else
476 adv |= fiber_fc_adv[sky2->flow_mode];
477 } else {
478 reg |= GM_GPCR_AU_FCT_DIS;
479 reg |= gm_fc_disable[sky2->flow_mode];
480
481 /* Forward pause packets to GMAC? */
482 if (sky2->flow_mode & FC_RX)
483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
484 else
485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
486 }
487
488 gma_write16(hw, port, GM_GP_CTRL, reg);
489
490 if (hw->flags & SKY2_HW_GIGABIT)
491 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
492
493 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
494 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
495
496 /* Setup Phy LED's */
497 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
498 ledover = 0;
499
500 switch (hw->chip_id) {
501 case CHIP_ID_YUKON_FE:
502 /* on 88E3082 these bits are at 11..9 (shifted left) */
503 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
504
505 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
506
507 /* delete ACT LED control bits */
508 ctrl &= ~PHY_M_FELP_LED1_MSK;
509 /* change ACT LED control to blink mode */
510 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
511 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
512 break;
513
514 case CHIP_ID_YUKON_FE_P:
515 /* Enable Link Partner Next Page */
516 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
517 ctrl |= PHY_M_PC_ENA_LIP_NP;
518
519 /* disable Energy Detect and enable scrambler */
520 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
521 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
522
523 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
524 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
525 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
526 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
527
528 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
529 break;
530
531 case CHIP_ID_YUKON_XL:
532 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
533
534 /* select page 3 to access LED control register */
535 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
536
537 /* set LED Function Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
539 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
540 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
541 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
542 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
543
544 /* set Polarity Control register */
545 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
546 (PHY_M_POLC_LS1_P_MIX(4) |
547 PHY_M_POLC_IS0_P_MIX(4) |
548 PHY_M_POLC_LOS_CTRL(2) |
549 PHY_M_POLC_INIT_CTRL(2) |
550 PHY_M_POLC_STA1_CTRL(2) |
551 PHY_M_POLC_STA0_CTRL(2)));
552
553 /* restore page register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
555 break;
556
557 case CHIP_ID_YUKON_EC_U:
558 case CHIP_ID_YUKON_EX:
559 case CHIP_ID_YUKON_SUPR:
560 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
561
562 /* select page 3 to access LED control register */
563 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
564
565 /* set LED Function Control register */
566 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
567 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
568 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
569 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
570 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
571
572 /* set Blink Rate in LED Timer Control Register */
573 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
574 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
575 /* restore page register */
576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
577 break;
578
579 default:
580 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
581 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
582
583 /* turn off the Rx LED (LED_RX) */
584 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
585 }
586
587 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
588 /* apply fixes in PHY AFE */
589 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
590
591 /* increase differential signal amplitude in 10BASE-T */
592 gm_phy_write(hw, port, 0x18, 0xaa99);
593 gm_phy_write(hw, port, 0x17, 0x2011);
594
595 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
596 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
597 gm_phy_write(hw, port, 0x18, 0xa204);
598 gm_phy_write(hw, port, 0x17, 0x2002);
599 }
600
601 /* set page register to 0 */
602 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
603 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
604 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
605 /* apply workaround for integrated resistors calibration */
606 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
607 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
608 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
609 /* apply fixes in PHY AFE */
610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
611
612 /* apply RDAC termination workaround */
613 gm_phy_write(hw, port, 24, 0x2800);
614 gm_phy_write(hw, port, 23, 0x2001);
615
616 /* set page register back to 0 */
617 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
618 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
619 hw->chip_id < CHIP_ID_YUKON_SUPR) {
620 /* no effect on Yukon-XL */
621 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
622
623 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
624 sky2->speed == SPEED_100) {
625 /* turn on 100 Mbps LED (LED_LINK100) */
626 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
627 }
628
629 if (ledover)
630 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
631
632 }
633
634 /* Enable phy interrupt on auto-negotiation complete (or link up) */
635 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
637 else
638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
639 }
640
641 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
642 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
643
644 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
645 {
646 u32 reg1;
647
648 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
649 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
650 reg1 &= ~phy_power[port];
651
652 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
653 reg1 |= coma_mode[port];
654
655 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
657 sky2_pci_read32(hw, PCI_DEV_REG1);
658
659 if (hw->chip_id == CHIP_ID_YUKON_FE)
660 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
661 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
662 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
663 }
664
665 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
666 {
667 u32 reg1;
668 u16 ctrl;
669
670 /* release GPHY Control reset */
671 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
672
673 /* release GMAC reset */
674 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
675
676 if (hw->flags & SKY2_HW_NEWER_PHY) {
677 /* select page 2 to access MAC control register */
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
679
680 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
681 /* allow GMII Power Down */
682 ctrl &= ~PHY_M_MAC_GMIF_PUP;
683 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
684
685 /* set page register back to 0 */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
687 }
688
689 /* setup General Purpose Control Register */
690 gma_write16(hw, port, GM_GP_CTRL,
691 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
692 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
693 GM_GPCR_AU_SPD_DIS);
694
695 if (hw->chip_id != CHIP_ID_YUKON_EC) {
696 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
697 /* select page 2 to access MAC control register */
698 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
699
700 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
701 /* enable Power Down */
702 ctrl |= PHY_M_PC_POW_D_ENA;
703 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
704
705 /* set page register back to 0 */
706 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
707 }
708
709 /* set IEEE compatible Power Down Mode (dev. #4.99) */
710 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
711 }
712
713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
714 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
715 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
716 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
717 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
718 }
719
720 /* Enable Rx/Tx */
721 static void sky2_enable_rx_tx(struct sky2_port *sky2)
722 {
723 struct sky2_hw *hw = sky2->hw;
724 unsigned port = sky2->port;
725 u16 reg;
726
727 reg = gma_read16(hw, port, GM_GP_CTRL);
728 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
729 gma_write16(hw, port, GM_GP_CTRL, reg);
730 }
731
732 /* Force a renegotiation */
733 static void sky2_phy_reinit(struct sky2_port *sky2)
734 {
735 spin_lock_bh(&sky2->phy_lock);
736 sky2_phy_init(sky2->hw, sky2->port);
737 sky2_enable_rx_tx(sky2);
738 spin_unlock_bh(&sky2->phy_lock);
739 }
740
741 /* Put device in state to listen for Wake On Lan */
742 static void sky2_wol_init(struct sky2_port *sky2)
743 {
744 struct sky2_hw *hw = sky2->hw;
745 unsigned port = sky2->port;
746 enum flow_control save_mode;
747 u16 ctrl;
748
749 /* Bring hardware out of reset */
750 sky2_write16(hw, B0_CTST, CS_RST_CLR);
751 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
752
753 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
754 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
755
756 /* Force to 10/100
757 * sky2_reset will re-enable on resume
758 */
759 save_mode = sky2->flow_mode;
760 ctrl = sky2->advertising;
761
762 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
763 sky2->flow_mode = FC_NONE;
764
765 spin_lock_bh(&sky2->phy_lock);
766 sky2_phy_power_up(hw, port);
767 sky2_phy_init(hw, port);
768 spin_unlock_bh(&sky2->phy_lock);
769
770 sky2->flow_mode = save_mode;
771 sky2->advertising = ctrl;
772
773 /* Set GMAC to no flow control and auto update for speed/duplex */
774 gma_write16(hw, port, GM_GP_CTRL,
775 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
776 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
777
778 /* Set WOL address */
779 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
780 sky2->netdev->dev_addr, ETH_ALEN);
781
782 /* Turn on appropriate WOL control bits */
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
784 ctrl = 0;
785 if (sky2->wol & WAKE_PHY)
786 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
787 else
788 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
789
790 if (sky2->wol & WAKE_MAGIC)
791 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
792 else
793 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
794
795 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
796 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
797
798 /* Disable PiG firmware */
799 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
800
801 /* block receiver */
802 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
803 }
804
805 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
806 {
807 struct net_device *dev = hw->dev[port];
808
809 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
810 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
811 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
812 /* Yukon-Extreme B0 and further Extreme devices */
813 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
814 } else if (dev->mtu > ETH_DATA_LEN) {
815 /* set Tx GMAC FIFO Almost Empty Threshold */
816 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
817 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
818
819 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
820 } else
821 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
822 }
823
824 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
825 {
826 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
827 u16 reg;
828 u32 rx_reg;
829 int i;
830 const u8 *addr = hw->dev[port]->dev_addr;
831
832 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
833 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
834
835 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
836
837 if (hw->chip_id == CHIP_ID_YUKON_XL &&
838 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
839 port == 1) {
840 /* WA DEV_472 -- looks like crossed wires on port 2 */
841 /* clear GMAC 1 Control reset */
842 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
843 do {
844 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
845 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
846 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
847 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
848 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
849 }
850
851 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
852
853 /* Enable Transmit FIFO Underrun */
854 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
855
856 spin_lock_bh(&sky2->phy_lock);
857 sky2_phy_power_up(hw, port);
858 sky2_phy_init(hw, port);
859 spin_unlock_bh(&sky2->phy_lock);
860
861 /* MIB clear */
862 reg = gma_read16(hw, port, GM_PHY_ADDR);
863 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
864
865 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
866 gma_read16(hw, port, i);
867 gma_write16(hw, port, GM_PHY_ADDR, reg);
868
869 /* transmit control */
870 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
871
872 /* receive control reg: unicast + multicast + no FCS */
873 gma_write16(hw, port, GM_RX_CTRL,
874 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
875
876 /* transmit flow control */
877 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
878
879 /* transmit parameter */
880 gma_write16(hw, port, GM_TX_PARAM,
881 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
882 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
883 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
884 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
885
886 /* serial mode register */
887 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
888 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
889
890 if (hw->dev[port]->mtu > ETH_DATA_LEN)
891 reg |= GM_SMOD_JUMBO_ENA;
892
893 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
894 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
895 reg |= GM_NEW_FLOW_CTRL;
896
897 gma_write16(hw, port, GM_SERIAL_MODE, reg);
898
899 /* virtual address for data */
900 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
901
902 /* physical address: used for pause frames */
903 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
904
905 /* ignore counter overflows */
906 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
907 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
908 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
909
910 /* Configure Rx MAC FIFO */
911 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
912 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
913 if (hw->chip_id == CHIP_ID_YUKON_EX ||
914 hw->chip_id == CHIP_ID_YUKON_FE_P)
915 rx_reg |= GMF_RX_OVER_ON;
916
917 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
918
919 if (hw->chip_id == CHIP_ID_YUKON_XL) {
920 /* Hardware errata - clear flush mask */
921 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
922 } else {
923 /* Flush Rx MAC FIFO on any flow control or error */
924 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
925 }
926
927 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
928 reg = RX_GMF_FL_THR_DEF + 1;
929 /* Another magic mystery workaround from sk98lin */
930 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
931 hw->chip_rev == CHIP_REV_YU_FE2_A0)
932 reg = 0x178;
933 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
934
935 /* Configure Tx MAC FIFO */
936 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
937 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
938
939 /* On chips without ram buffer, pause is controled by MAC level */
940 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
941 /* Pause threshold is scaled by 8 in bytes */
942 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
943 hw->chip_rev == CHIP_REV_YU_FE2_A0)
944 reg = 1568 / 8;
945 else
946 reg = 1024 / 8;
947 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
948 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
949
950 sky2_set_tx_stfwd(hw, port);
951 }
952
953 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
954 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
955 /* disable dynamic watermark */
956 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
957 reg &= ~TX_DYN_WM_ENA;
958 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
959 }
960 }
961
962 /* Assign Ram Buffer allocation to queue */
963 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
964 {
965 u32 end;
966
967 /* convert from K bytes to qwords used for hw register */
968 start *= 1024/8;
969 space *= 1024/8;
970 end = start + space - 1;
971
972 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
973 sky2_write32(hw, RB_ADDR(q, RB_START), start);
974 sky2_write32(hw, RB_ADDR(q, RB_END), end);
975 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
976 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
977
978 if (q == Q_R1 || q == Q_R2) {
979 u32 tp = space - space/4;
980
981 /* On receive queue's set the thresholds
982 * give receiver priority when > 3/4 full
983 * send pause when down to 2K
984 */
985 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
986 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
987
988 tp = space - 2048/8;
989 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
990 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
991 } else {
992 /* Enable store & forward on Tx queue's because
993 * Tx FIFO is only 1K on Yukon
994 */
995 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
996 }
997
998 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
999 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1000 }
1001
1002 /* Setup Bus Memory Interface */
1003 static void sky2_qset(struct sky2_hw *hw, u16 q)
1004 {
1005 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1006 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1007 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1008 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1009 }
1010
1011 /* Setup prefetch unit registers. This is the interface between
1012 * hardware and driver list elements
1013 */
1014 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1015 dma_addr_t addr, u32 last)
1016 {
1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1019 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1021 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1022 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1023
1024 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1025 }
1026
1027 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1028 {
1029 struct sky2_tx_le *le = sky2->tx_le + *slot;
1030
1031 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1032 le->ctrl = 0;
1033 return le;
1034 }
1035
1036 static void tx_init(struct sky2_port *sky2)
1037 {
1038 struct sky2_tx_le *le;
1039
1040 sky2->tx_prod = sky2->tx_cons = 0;
1041 sky2->tx_tcpsum = 0;
1042 sky2->tx_last_mss = 0;
1043
1044 le = get_tx_le(sky2, &sky2->tx_prod);
1045 le->addr = 0;
1046 le->opcode = OP_ADDR64 | HW_OWNER;
1047 sky2->tx_last_upper = 0;
1048 }
1049
1050 /* Update chip's next pointer */
1051 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1052 {
1053 /* Make sure write' to descriptors are complete before we tell hardware */
1054 wmb();
1055 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1056
1057 /* Synchronize I/O on since next processor may write to tail */
1058 mmiowb();
1059 }
1060
1061
1062 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1063 {
1064 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1065 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1066 le->ctrl = 0;
1067 return le;
1068 }
1069
1070 static unsigned sky2_get_rx_threshold(struct sky2_port *sky2)
1071 {
1072 unsigned size;
1073
1074 /* Space needed for frame data + headers rounded up */
1075 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1076
1077 /* Stopping point for hardware truncation */
1078 return (size - 8) / sizeof(u32);
1079 }
1080
1081 static unsigned sky2_get_rx_data_size(struct sky2_port *sky2)
1082 {
1083 struct rx_ring_info *re;
1084 unsigned size;
1085
1086 /* Space needed for frame data + headers rounded up */
1087 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1088
1089 sky2->rx_nfrags = size >> PAGE_SHIFT;
1090 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1091
1092 /* Compute residue after pages */
1093 size -= sky2->rx_nfrags << PAGE_SHIFT;
1094
1095 /* Optimize to handle small packets and headers */
1096 if (size < copybreak)
1097 size = copybreak;
1098 if (size < ETH_HLEN)
1099 size = ETH_HLEN;
1100
1101 return size;
1102 }
1103
1104 /* Build description to hardware for one receive segment */
1105 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1106 dma_addr_t map, unsigned len)
1107 {
1108 struct sky2_rx_le *le;
1109
1110 if (sizeof(dma_addr_t) > sizeof(u32)) {
1111 le = sky2_next_rx(sky2);
1112 le->addr = cpu_to_le32(upper_32_bits(map));
1113 le->opcode = OP_ADDR64 | HW_OWNER;
1114 }
1115
1116 le = sky2_next_rx(sky2);
1117 le->addr = cpu_to_le32(lower_32_bits(map));
1118 le->length = cpu_to_le16(len);
1119 le->opcode = op | HW_OWNER;
1120 }
1121
1122 /* Build description to hardware for one possibly fragmented skb */
1123 static void sky2_rx_submit(struct sky2_port *sky2,
1124 const struct rx_ring_info *re)
1125 {
1126 int i;
1127
1128 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1129
1130 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1131 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1132 }
1133
1134
1135 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1136 unsigned size)
1137 {
1138 struct sk_buff *skb = re->skb;
1139 int i;
1140
1141 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1142 if (pci_dma_mapping_error(pdev, re->data_addr))
1143 goto mapping_error;
1144
1145 dma_unmap_len_set(re, data_size, size);
1146
1147 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1148 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1149
1150 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1151 frag->page_offset,
1152 frag->size,
1153 PCI_DMA_FROMDEVICE);
1154
1155 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1156 goto map_page_error;
1157 }
1158 return 0;
1159
1160 map_page_error:
1161 while (--i >= 0) {
1162 pci_unmap_page(pdev, re->frag_addr[i],
1163 skb_shinfo(skb)->frags[i].size,
1164 PCI_DMA_FROMDEVICE);
1165 }
1166
1167 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1168 PCI_DMA_FROMDEVICE);
1169
1170 mapping_error:
1171 if (net_ratelimit())
1172 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1173 skb->dev->name);
1174 return -EIO;
1175 }
1176
1177 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1178 {
1179 struct sk_buff *skb = re->skb;
1180 int i;
1181
1182 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1183 PCI_DMA_FROMDEVICE);
1184
1185 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1186 pci_unmap_page(pdev, re->frag_addr[i],
1187 skb_shinfo(skb)->frags[i].size,
1188 PCI_DMA_FROMDEVICE);
1189 }
1190
1191 /* Tell chip where to start receive checksum.
1192 * Actually has two checksums, but set both same to avoid possible byte
1193 * order problems.
1194 */
1195 static void rx_set_checksum(struct sky2_port *sky2)
1196 {
1197 struct sky2_rx_le *le = sky2_next_rx(sky2);
1198
1199 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1200 le->ctrl = 0;
1201 le->opcode = OP_TCPSTART | HW_OWNER;
1202
1203 sky2_write32(sky2->hw,
1204 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1205 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1206 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1207 }
1208
1209 /* Enable/disable receive hash calculation (RSS) */
1210 static void rx_set_rss(struct net_device *dev)
1211 {
1212 struct sky2_port *sky2 = netdev_priv(dev);
1213 struct sky2_hw *hw = sky2->hw;
1214 int i, nkeys = 4;
1215
1216 /* Supports IPv6 and other modes */
1217 if (hw->flags & SKY2_HW_NEW_LE) {
1218 nkeys = 10;
1219 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1220 }
1221
1222 /* Program RSS initial values */
1223 if (dev->features & NETIF_F_RXHASH) {
1224 u32 key[nkeys];
1225
1226 get_random_bytes(key, nkeys * sizeof(u32));
1227 for (i = 0; i < nkeys; i++)
1228 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1229 key[i]);
1230
1231 /* Need to turn on (undocumented) flag to make hashing work */
1232 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1233 RX_STFW_ENA);
1234
1235 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1236 BMU_ENA_RX_RSS_HASH);
1237 } else
1238 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1239 BMU_DIS_RX_RSS_HASH);
1240 }
1241
1242 /*
1243 * The RX Stop command will not work for Yukon-2 if the BMU does not
1244 * reach the end of packet and since we can't make sure that we have
1245 * incoming data, we must reset the BMU while it is not doing a DMA
1246 * transfer. Since it is possible that the RX path is still active,
1247 * the RX RAM buffer will be stopped first, so any possible incoming
1248 * data will not trigger a DMA. After the RAM buffer is stopped, the
1249 * BMU is polled until any DMA in progress is ended and only then it
1250 * will be reset.
1251 */
1252 static void sky2_rx_stop(struct sky2_port *sky2)
1253 {
1254 struct sky2_hw *hw = sky2->hw;
1255 unsigned rxq = rxqaddr[sky2->port];
1256 int i;
1257
1258 /* disable the RAM Buffer receive queue */
1259 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1260
1261 for (i = 0; i < 0xffff; i++)
1262 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1263 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1264 goto stopped;
1265
1266 netdev_warn(sky2->netdev, "receiver stop failed\n");
1267 stopped:
1268 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1269
1270 /* reset the Rx prefetch unit */
1271 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1272 mmiowb();
1273 }
1274
1275 /* Clean out receive buffer area, assumes receiver hardware stopped */
1276 static void sky2_rx_clean(struct sky2_port *sky2)
1277 {
1278 unsigned i;
1279
1280 memset(sky2->rx_le, 0, RX_LE_BYTES);
1281 for (i = 0; i < sky2->rx_pending; i++) {
1282 struct rx_ring_info *re = sky2->rx_ring + i;
1283
1284 if (re->skb) {
1285 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1286 kfree_skb(re->skb);
1287 re->skb = NULL;
1288 }
1289 }
1290 }
1291
1292 /* Basic MII support */
1293 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1294 {
1295 struct mii_ioctl_data *data = if_mii(ifr);
1296 struct sky2_port *sky2 = netdev_priv(dev);
1297 struct sky2_hw *hw = sky2->hw;
1298 int err = -EOPNOTSUPP;
1299
1300 if (!netif_running(dev))
1301 return -ENODEV; /* Phy still in reset */
1302
1303 switch (cmd) {
1304 case SIOCGMIIPHY:
1305 data->phy_id = PHY_ADDR_MARV;
1306
1307 /* fallthru */
1308 case SIOCGMIIREG: {
1309 u16 val = 0;
1310
1311 spin_lock_bh(&sky2->phy_lock);
1312 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1313 spin_unlock_bh(&sky2->phy_lock);
1314
1315 data->val_out = val;
1316 break;
1317 }
1318
1319 case SIOCSMIIREG:
1320 spin_lock_bh(&sky2->phy_lock);
1321 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1322 data->val_in);
1323 spin_unlock_bh(&sky2->phy_lock);
1324 break;
1325 }
1326 return err;
1327 }
1328
1329 #ifdef SKY2_VLAN_TAG_USED
1330 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1331 {
1332 if (onoff) {
1333 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1334 RX_VLAN_STRIP_ON);
1335 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1336 TX_VLAN_TAG_ON);
1337 } else {
1338 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1339 RX_VLAN_STRIP_OFF);
1340 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1341 TX_VLAN_TAG_OFF);
1342 }
1343 }
1344
1345 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1346 {
1347 struct sky2_port *sky2 = netdev_priv(dev);
1348 struct sky2_hw *hw = sky2->hw;
1349 u16 port = sky2->port;
1350
1351 netif_tx_lock_bh(dev);
1352 napi_disable(&hw->napi);
1353
1354 sky2->vlgrp = grp;
1355 sky2_set_vlan_mode(hw, port, grp != NULL);
1356
1357 sky2_read32(hw, B0_Y2_SP_LISR);
1358 napi_enable(&hw->napi);
1359 netif_tx_unlock_bh(dev);
1360 }
1361 #endif
1362
1363 /* Amount of required worst case padding in rx buffer */
1364 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1365 {
1366 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1367 }
1368
1369 /*
1370 * Allocate an skb for receiving. If the MTU is large enough
1371 * make the skb non-linear with a fragment list of pages.
1372 */
1373 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1374 {
1375 struct sk_buff *skb;
1376 int i;
1377
1378 skb = netdev_alloc_skb(sky2->netdev,
1379 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1380 if (!skb)
1381 goto nomem;
1382
1383 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1384 unsigned char *start;
1385 /*
1386 * Workaround for a bug in FIFO that cause hang
1387 * if the FIFO if the receive buffer is not 64 byte aligned.
1388 * The buffer returned from netdev_alloc_skb is
1389 * aligned except if slab debugging is enabled.
1390 */
1391 start = PTR_ALIGN(skb->data, 8);
1392 skb_reserve(skb, start - skb->data);
1393 } else
1394 skb_reserve(skb, NET_IP_ALIGN);
1395
1396 for (i = 0; i < sky2->rx_nfrags; i++) {
1397 struct page *page = alloc_page(GFP_ATOMIC);
1398
1399 if (!page)
1400 goto free_partial;
1401 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1402 }
1403
1404 return skb;
1405 free_partial:
1406 kfree_skb(skb);
1407 nomem:
1408 return NULL;
1409 }
1410
1411 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1412 {
1413 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1414 }
1415
1416 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1417 {
1418 struct sky2_hw *hw = sky2->hw;
1419 unsigned i;
1420
1421 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1422
1423 /* Fill Rx ring */
1424 for (i = 0; i < sky2->rx_pending; i++) {
1425 struct rx_ring_info *re = sky2->rx_ring + i;
1426
1427 re->skb = sky2_rx_alloc(sky2);
1428 if (!re->skb)
1429 return -ENOMEM;
1430
1431 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1432 dev_kfree_skb(re->skb);
1433 re->skb = NULL;
1434 return -ENOMEM;
1435 }
1436 }
1437 return 0;
1438 }
1439
1440 /*
1441 * Setup receiver buffer pool.
1442 * Normal case this ends up creating one list element for skb
1443 * in the receive ring. Worst case if using large MTU and each
1444 * allocation falls on a different 64 bit region, that results
1445 * in 6 list elements per ring entry.
1446 * One element is used for checksum enable/disable, and one
1447 * extra to avoid wrap.
1448 */
1449 static void sky2_rx_start(struct sky2_port *sky2)
1450 {
1451 struct sky2_hw *hw = sky2->hw;
1452 struct rx_ring_info *re;
1453 unsigned rxq = rxqaddr[sky2->port];
1454 unsigned i, thresh;
1455
1456 sky2->rx_put = sky2->rx_next = 0;
1457 sky2_qset(hw, rxq);
1458
1459 /* On PCI express lowering the watermark gives better performance */
1460 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1461 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1462
1463 /* These chips have no ram buffer?
1464 * MAC Rx RAM Read is controlled by hardware */
1465 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1466 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1467 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1468
1469 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1470
1471 if (!(hw->flags & SKY2_HW_NEW_LE))
1472 rx_set_checksum(sky2);
1473
1474 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1475 rx_set_rss(sky2->netdev);
1476
1477 /* submit Rx ring */
1478 for (i = 0; i < sky2->rx_pending; i++) {
1479 re = sky2->rx_ring + i;
1480 sky2_rx_submit(sky2, re);
1481 }
1482
1483 /*
1484 * The receiver hangs if it receives frames larger than the
1485 * packet buffer. As a workaround, truncate oversize frames, but
1486 * the register is limited to 9 bits, so if you do frames > 2052
1487 * you better get the MTU right!
1488 */
1489 thresh = sky2_get_rx_threshold(sky2);
1490 if (thresh > 0x1ff)
1491 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1492 else {
1493 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1494 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1495 }
1496
1497 /* Tell chip about available buffers */
1498 sky2_rx_update(sky2, rxq);
1499
1500 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1501 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1502 /*
1503 * Disable flushing of non ASF packets;
1504 * must be done after initializing the BMUs;
1505 * drivers without ASF support should do this too, otherwise
1506 * it may happen that they cannot run on ASF devices;
1507 * remember that the MAC FIFO isn't reset during initialization.
1508 */
1509 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1510 }
1511
1512 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1513 /* Enable RX Home Address & Routing Header checksum fix */
1514 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1515 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1516
1517 /* Enable TX Home Address & Routing Header checksum fix */
1518 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1519 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1520 }
1521 }
1522
1523 static int sky2_alloc_buffers(struct sky2_port *sky2)
1524 {
1525 struct sky2_hw *hw = sky2->hw;
1526
1527 /* must be power of 2 */
1528 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1529 sky2->tx_ring_size *
1530 sizeof(struct sky2_tx_le),
1531 &sky2->tx_le_map);
1532 if (!sky2->tx_le)
1533 goto nomem;
1534
1535 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1536 GFP_KERNEL);
1537 if (!sky2->tx_ring)
1538 goto nomem;
1539
1540 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1541 &sky2->rx_le_map);
1542 if (!sky2->rx_le)
1543 goto nomem;
1544 memset(sky2->rx_le, 0, RX_LE_BYTES);
1545
1546 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1547 GFP_KERNEL);
1548 if (!sky2->rx_ring)
1549 goto nomem;
1550
1551 return sky2_alloc_rx_skbs(sky2);
1552 nomem:
1553 return -ENOMEM;
1554 }
1555
1556 static void sky2_free_buffers(struct sky2_port *sky2)
1557 {
1558 struct sky2_hw *hw = sky2->hw;
1559
1560 sky2_rx_clean(sky2);
1561
1562 if (sky2->rx_le) {
1563 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1564 sky2->rx_le, sky2->rx_le_map);
1565 sky2->rx_le = NULL;
1566 }
1567 if (sky2->tx_le) {
1568 pci_free_consistent(hw->pdev,
1569 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1570 sky2->tx_le, sky2->tx_le_map);
1571 sky2->tx_le = NULL;
1572 }
1573 kfree(sky2->tx_ring);
1574 kfree(sky2->rx_ring);
1575
1576 sky2->tx_ring = NULL;
1577 sky2->rx_ring = NULL;
1578 }
1579
1580 static void sky2_hw_up(struct sky2_port *sky2)
1581 {
1582 struct sky2_hw *hw = sky2->hw;
1583 unsigned port = sky2->port;
1584 u32 ramsize;
1585 int cap;
1586 struct net_device *otherdev = hw->dev[sky2->port^1];
1587
1588 tx_init(sky2);
1589
1590 /*
1591 * On dual port PCI-X card, there is an problem where status
1592 * can be received out of order due to split transactions
1593 */
1594 if (otherdev && netif_running(otherdev) &&
1595 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1596 u16 cmd;
1597
1598 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1599 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1600 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1601 }
1602
1603 sky2_mac_init(hw, port);
1604
1605 /* Register is number of 4K blocks on internal RAM buffer. */
1606 ramsize = sky2_read8(hw, B2_E_0) * 4;
1607 if (ramsize > 0) {
1608 u32 rxspace;
1609
1610 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1611 if (ramsize < 16)
1612 rxspace = ramsize / 2;
1613 else
1614 rxspace = 8 + (2*(ramsize - 16))/3;
1615
1616 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1617 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1618
1619 /* Make sure SyncQ is disabled */
1620 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1621 RB_RST_SET);
1622 }
1623
1624 sky2_qset(hw, txqaddr[port]);
1625
1626 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1627 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1628 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1629
1630 /* Set almost empty threshold */
1631 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1632 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1633 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1634
1635 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1636 sky2->tx_ring_size - 1);
1637
1638 #ifdef SKY2_VLAN_TAG_USED
1639 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1640 #endif
1641
1642 sky2_rx_start(sky2);
1643 }
1644
1645 /* Bring up network interface. */
1646 static int sky2_up(struct net_device *dev)
1647 {
1648 struct sky2_port *sky2 = netdev_priv(dev);
1649 struct sky2_hw *hw = sky2->hw;
1650 unsigned port = sky2->port;
1651 u32 imask;
1652 int err;
1653
1654 netif_carrier_off(dev);
1655
1656 err = sky2_alloc_buffers(sky2);
1657 if (err)
1658 goto err_out;
1659
1660 sky2_hw_up(sky2);
1661
1662 /* Enable interrupts from phy/mac for port */
1663 imask = sky2_read32(hw, B0_IMSK);
1664 imask |= portirq_msk[port];
1665 sky2_write32(hw, B0_IMSK, imask);
1666 sky2_read32(hw, B0_IMSK);
1667
1668 netif_info(sky2, ifup, dev, "enabling interface\n");
1669
1670 return 0;
1671
1672 err_out:
1673 sky2_free_buffers(sky2);
1674 return err;
1675 }
1676
1677 /* Modular subtraction in ring */
1678 static inline int tx_inuse(const struct sky2_port *sky2)
1679 {
1680 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1681 }
1682
1683 /* Number of list elements available for next tx */
1684 static inline int tx_avail(const struct sky2_port *sky2)
1685 {
1686 return sky2->tx_pending - tx_inuse(sky2);
1687 }
1688
1689 /* Estimate of number of transmit list elements required */
1690 static unsigned tx_le_req(const struct sk_buff *skb)
1691 {
1692 unsigned count;
1693
1694 count = (skb_shinfo(skb)->nr_frags + 1)
1695 * (sizeof(dma_addr_t) / sizeof(u32));
1696
1697 if (skb_is_gso(skb))
1698 ++count;
1699 else if (sizeof(dma_addr_t) == sizeof(u32))
1700 ++count; /* possible vlan */
1701
1702 if (skb->ip_summed == CHECKSUM_PARTIAL)
1703 ++count;
1704
1705 return count;
1706 }
1707
1708 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1709 {
1710 if (re->flags & TX_MAP_SINGLE)
1711 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1712 dma_unmap_len(re, maplen),
1713 PCI_DMA_TODEVICE);
1714 else if (re->flags & TX_MAP_PAGE)
1715 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1716 dma_unmap_len(re, maplen),
1717 PCI_DMA_TODEVICE);
1718 re->flags = 0;
1719 }
1720
1721 /*
1722 * Put one packet in ring for transmit.
1723 * A single packet can generate multiple list elements, and
1724 * the number of ring elements will probably be less than the number
1725 * of list elements used.
1726 */
1727 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1728 struct net_device *dev)
1729 {
1730 struct sky2_port *sky2 = netdev_priv(dev);
1731 struct sky2_hw *hw = sky2->hw;
1732 struct sky2_tx_le *le = NULL;
1733 struct tx_ring_info *re;
1734 unsigned i, len;
1735 dma_addr_t mapping;
1736 u32 upper;
1737 u16 slot;
1738 u16 mss;
1739 u8 ctrl;
1740
1741 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1742 return NETDEV_TX_BUSY;
1743
1744 len = skb_headlen(skb);
1745 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1746
1747 if (pci_dma_mapping_error(hw->pdev, mapping))
1748 goto mapping_error;
1749
1750 slot = sky2->tx_prod;
1751 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1752 "tx queued, slot %u, len %d\n", slot, skb->len);
1753
1754 /* Send high bits if needed */
1755 upper = upper_32_bits(mapping);
1756 if (upper != sky2->tx_last_upper) {
1757 le = get_tx_le(sky2, &slot);
1758 le->addr = cpu_to_le32(upper);
1759 sky2->tx_last_upper = upper;
1760 le->opcode = OP_ADDR64 | HW_OWNER;
1761 }
1762
1763 /* Check for TCP Segmentation Offload */
1764 mss = skb_shinfo(skb)->gso_size;
1765 if (mss != 0) {
1766
1767 if (!(hw->flags & SKY2_HW_NEW_LE))
1768 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1769
1770 if (mss != sky2->tx_last_mss) {
1771 le = get_tx_le(sky2, &slot);
1772 le->addr = cpu_to_le32(mss);
1773
1774 if (hw->flags & SKY2_HW_NEW_LE)
1775 le->opcode = OP_MSS | HW_OWNER;
1776 else
1777 le->opcode = OP_LRGLEN | HW_OWNER;
1778 sky2->tx_last_mss = mss;
1779 }
1780 }
1781
1782 ctrl = 0;
1783 #ifdef SKY2_VLAN_TAG_USED
1784 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1785 if (vlan_tx_tag_present(skb)) {
1786 if (!le) {
1787 le = get_tx_le(sky2, &slot);
1788 le->addr = 0;
1789 le->opcode = OP_VLAN|HW_OWNER;
1790 } else
1791 le->opcode |= OP_VLAN;
1792 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1793 ctrl |= INS_VLAN;
1794 }
1795 #endif
1796
1797 /* Handle TCP checksum offload */
1798 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1799 /* On Yukon EX (some versions) encoding change. */
1800 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1801 ctrl |= CALSUM; /* auto checksum */
1802 else {
1803 const unsigned offset = skb_transport_offset(skb);
1804 u32 tcpsum;
1805
1806 tcpsum = offset << 16; /* sum start */
1807 tcpsum |= offset + skb->csum_offset; /* sum write */
1808
1809 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1810 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1811 ctrl |= UDPTCP;
1812
1813 if (tcpsum != sky2->tx_tcpsum) {
1814 sky2->tx_tcpsum = tcpsum;
1815
1816 le = get_tx_le(sky2, &slot);
1817 le->addr = cpu_to_le32(tcpsum);
1818 le->length = 0; /* initial checksum value */
1819 le->ctrl = 1; /* one packet */
1820 le->opcode = OP_TCPLISW | HW_OWNER;
1821 }
1822 }
1823 }
1824
1825 re = sky2->tx_ring + slot;
1826 re->flags = TX_MAP_SINGLE;
1827 dma_unmap_addr_set(re, mapaddr, mapping);
1828 dma_unmap_len_set(re, maplen, len);
1829
1830 le = get_tx_le(sky2, &slot);
1831 le->addr = cpu_to_le32(lower_32_bits(mapping));
1832 le->length = cpu_to_le16(len);
1833 le->ctrl = ctrl;
1834 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1835
1836
1837 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1838 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1839
1840 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1841 frag->size, PCI_DMA_TODEVICE);
1842
1843 if (pci_dma_mapping_error(hw->pdev, mapping))
1844 goto mapping_unwind;
1845
1846 upper = upper_32_bits(mapping);
1847 if (upper != sky2->tx_last_upper) {
1848 le = get_tx_le(sky2, &slot);
1849 le->addr = cpu_to_le32(upper);
1850 sky2->tx_last_upper = upper;
1851 le->opcode = OP_ADDR64 | HW_OWNER;
1852 }
1853
1854 re = sky2->tx_ring + slot;
1855 re->flags = TX_MAP_PAGE;
1856 dma_unmap_addr_set(re, mapaddr, mapping);
1857 dma_unmap_len_set(re, maplen, frag->size);
1858
1859 le = get_tx_le(sky2, &slot);
1860 le->addr = cpu_to_le32(lower_32_bits(mapping));
1861 le->length = cpu_to_le16(frag->size);
1862 le->ctrl = ctrl;
1863 le->opcode = OP_BUFFER | HW_OWNER;
1864 }
1865
1866 re->skb = skb;
1867 le->ctrl |= EOP;
1868
1869 sky2->tx_prod = slot;
1870
1871 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1872 netif_stop_queue(dev);
1873
1874 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1875
1876 return NETDEV_TX_OK;
1877
1878 mapping_unwind:
1879 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1880 re = sky2->tx_ring + i;
1881
1882 sky2_tx_unmap(hw->pdev, re);
1883 }
1884
1885 mapping_error:
1886 if (net_ratelimit())
1887 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1888 dev_kfree_skb(skb);
1889 return NETDEV_TX_OK;
1890 }
1891
1892 /*
1893 * Free ring elements from starting at tx_cons until "done"
1894 *
1895 * NB:
1896 * 1. The hardware will tell us about partial completion of multi-part
1897 * buffers so make sure not to free skb to early.
1898 * 2. This may run in parallel start_xmit because the it only
1899 * looks at the tail of the queue of FIFO (tx_cons), not
1900 * the head (tx_prod)
1901 */
1902 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1903 {
1904 struct net_device *dev = sky2->netdev;
1905 unsigned idx;
1906
1907 BUG_ON(done >= sky2->tx_ring_size);
1908
1909 for (idx = sky2->tx_cons; idx != done;
1910 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1911 struct tx_ring_info *re = sky2->tx_ring + idx;
1912 struct sk_buff *skb = re->skb;
1913
1914 sky2_tx_unmap(sky2->hw->pdev, re);
1915
1916 if (skb) {
1917 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1918 "tx done %u\n", idx);
1919
1920 u64_stats_update_begin(&sky2->tx_stats.syncp);
1921 ++sky2->tx_stats.packets;
1922 sky2->tx_stats.bytes += skb->len;
1923 u64_stats_update_end(&sky2->tx_stats.syncp);
1924
1925 re->skb = NULL;
1926 dev_kfree_skb_any(skb);
1927
1928 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1929 }
1930 }
1931
1932 sky2->tx_cons = idx;
1933 smp_mb();
1934 }
1935
1936 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1937 {
1938 /* Disable Force Sync bit and Enable Alloc bit */
1939 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1940 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1941
1942 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1943 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1944 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1945
1946 /* Reset the PCI FIFO of the async Tx queue */
1947 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1948 BMU_RST_SET | BMU_FIFO_RST);
1949
1950 /* Reset the Tx prefetch units */
1951 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1952 PREF_UNIT_RST_SET);
1953
1954 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1955 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1956 }
1957
1958 static void sky2_hw_down(struct sky2_port *sky2)
1959 {
1960 struct sky2_hw *hw = sky2->hw;
1961 unsigned port = sky2->port;
1962 u16 ctrl;
1963
1964 /* Force flow control off */
1965 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1966
1967 /* Stop transmitter */
1968 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1969 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1970
1971 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1972 RB_RST_SET | RB_DIS_OP_MD);
1973
1974 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1975 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1976 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1977
1978 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1979
1980 /* Workaround shared GMAC reset */
1981 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1982 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1983 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1984
1985 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1986
1987 /* Force any delayed status interrrupt and NAPI */
1988 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1989 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1990 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1991 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1992
1993 sky2_rx_stop(sky2);
1994
1995 spin_lock_bh(&sky2->phy_lock);
1996 sky2_phy_power_down(hw, port);
1997 spin_unlock_bh(&sky2->phy_lock);
1998
1999 sky2_tx_reset(hw, port);
2000
2001 /* Free any pending frames stuck in HW queue */
2002 sky2_tx_complete(sky2, sky2->tx_prod);
2003 }
2004
2005 /* Network shutdown */
2006 static int sky2_down(struct net_device *dev)
2007 {
2008 struct sky2_port *sky2 = netdev_priv(dev);
2009 struct sky2_hw *hw = sky2->hw;
2010
2011 /* Never really got started! */
2012 if (!sky2->tx_le)
2013 return 0;
2014
2015 netif_info(sky2, ifdown, dev, "disabling interface\n");
2016
2017 /* Disable port IRQ */
2018 sky2_write32(hw, B0_IMSK,
2019 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2020 sky2_read32(hw, B0_IMSK);
2021
2022 synchronize_irq(hw->pdev->irq);
2023 napi_synchronize(&hw->napi);
2024
2025 sky2_hw_down(sky2);
2026
2027 sky2_free_buffers(sky2);
2028
2029 return 0;
2030 }
2031
2032 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2033 {
2034 if (hw->flags & SKY2_HW_FIBRE_PHY)
2035 return SPEED_1000;
2036
2037 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2038 if (aux & PHY_M_PS_SPEED_100)
2039 return SPEED_100;
2040 else
2041 return SPEED_10;
2042 }
2043
2044 switch (aux & PHY_M_PS_SPEED_MSK) {
2045 case PHY_M_PS_SPEED_1000:
2046 return SPEED_1000;
2047 case PHY_M_PS_SPEED_100:
2048 return SPEED_100;
2049 default:
2050 return SPEED_10;
2051 }
2052 }
2053
2054 static void sky2_link_up(struct sky2_port *sky2)
2055 {
2056 struct sky2_hw *hw = sky2->hw;
2057 unsigned port = sky2->port;
2058 static const char *fc_name[] = {
2059 [FC_NONE] = "none",
2060 [FC_TX] = "tx",
2061 [FC_RX] = "rx",
2062 [FC_BOTH] = "both",
2063 };
2064
2065 sky2_enable_rx_tx(sky2);
2066
2067 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2068
2069 netif_carrier_on(sky2->netdev);
2070
2071 mod_timer(&hw->watchdog_timer, jiffies + 1);
2072
2073 /* Turn on link LED */
2074 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2075 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2076
2077 netif_info(sky2, link, sky2->netdev,
2078 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2079 sky2->speed,
2080 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2081 fc_name[sky2->flow_status]);
2082 }
2083
2084 static void sky2_link_down(struct sky2_port *sky2)
2085 {
2086 struct sky2_hw *hw = sky2->hw;
2087 unsigned port = sky2->port;
2088 u16 reg;
2089
2090 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2091
2092 reg = gma_read16(hw, port, GM_GP_CTRL);
2093 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2094 gma_write16(hw, port, GM_GP_CTRL, reg);
2095
2096 netif_carrier_off(sky2->netdev);
2097
2098 /* Turn off link LED */
2099 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2100
2101 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2102
2103 sky2_phy_init(hw, port);
2104 }
2105
2106 static enum flow_control sky2_flow(int rx, int tx)
2107 {
2108 if (rx)
2109 return tx ? FC_BOTH : FC_RX;
2110 else
2111 return tx ? FC_TX : FC_NONE;
2112 }
2113
2114 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2115 {
2116 struct sky2_hw *hw = sky2->hw;
2117 unsigned port = sky2->port;
2118 u16 advert, lpa;
2119
2120 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2121 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2122 if (lpa & PHY_M_AN_RF) {
2123 netdev_err(sky2->netdev, "remote fault\n");
2124 return -1;
2125 }
2126
2127 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2128 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2129 return -1;
2130 }
2131
2132 sky2->speed = sky2_phy_speed(hw, aux);
2133 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2134
2135 /* Since the pause result bits seem to in different positions on
2136 * different chips. look at registers.
2137 */
2138 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2139 /* Shift for bits in fiber PHY */
2140 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2141 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2142
2143 if (advert & ADVERTISE_1000XPAUSE)
2144 advert |= ADVERTISE_PAUSE_CAP;
2145 if (advert & ADVERTISE_1000XPSE_ASYM)
2146 advert |= ADVERTISE_PAUSE_ASYM;
2147 if (lpa & LPA_1000XPAUSE)
2148 lpa |= LPA_PAUSE_CAP;
2149 if (lpa & LPA_1000XPAUSE_ASYM)
2150 lpa |= LPA_PAUSE_ASYM;
2151 }
2152
2153 sky2->flow_status = FC_NONE;
2154 if (advert & ADVERTISE_PAUSE_CAP) {
2155 if (lpa & LPA_PAUSE_CAP)
2156 sky2->flow_status = FC_BOTH;
2157 else if (advert & ADVERTISE_PAUSE_ASYM)
2158 sky2->flow_status = FC_RX;
2159 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2160 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2161 sky2->flow_status = FC_TX;
2162 }
2163
2164 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2165 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2166 sky2->flow_status = FC_NONE;
2167
2168 if (sky2->flow_status & FC_TX)
2169 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2170 else
2171 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2172
2173 return 0;
2174 }
2175
2176 /* Interrupt from PHY */
2177 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2178 {
2179 struct net_device *dev = hw->dev[port];
2180 struct sky2_port *sky2 = netdev_priv(dev);
2181 u16 istatus, phystat;
2182
2183 if (!netif_running(dev))
2184 return;
2185
2186 spin_lock(&sky2->phy_lock);
2187 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2188 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2189
2190 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2191 istatus, phystat);
2192
2193 if (istatus & PHY_M_IS_AN_COMPL) {
2194 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2195 !netif_carrier_ok(dev))
2196 sky2_link_up(sky2);
2197 goto out;
2198 }
2199
2200 if (istatus & PHY_M_IS_LSP_CHANGE)
2201 sky2->speed = sky2_phy_speed(hw, phystat);
2202
2203 if (istatus & PHY_M_IS_DUP_CHANGE)
2204 sky2->duplex =
2205 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2206
2207 if (istatus & PHY_M_IS_LST_CHANGE) {
2208 if (phystat & PHY_M_PS_LINK_UP)
2209 sky2_link_up(sky2);
2210 else
2211 sky2_link_down(sky2);
2212 }
2213 out:
2214 spin_unlock(&sky2->phy_lock);
2215 }
2216
2217 /* Special quick link interrupt (Yukon-2 Optima only) */
2218 static void sky2_qlink_intr(struct sky2_hw *hw)
2219 {
2220 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2221 u32 imask;
2222 u16 phy;
2223
2224 /* disable irq */
2225 imask = sky2_read32(hw, B0_IMSK);
2226 imask &= ~Y2_IS_PHY_QLNK;
2227 sky2_write32(hw, B0_IMSK, imask);
2228
2229 /* reset PHY Link Detect */
2230 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2231 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2232 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2233 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2234
2235 sky2_link_up(sky2);
2236 }
2237
2238 /* Transmit timeout is only called if we are running, carrier is up
2239 * and tx queue is full (stopped).
2240 */
2241 static void sky2_tx_timeout(struct net_device *dev)
2242 {
2243 struct sky2_port *sky2 = netdev_priv(dev);
2244 struct sky2_hw *hw = sky2->hw;
2245
2246 netif_err(sky2, timer, dev, "tx timeout\n");
2247
2248 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2249 sky2->tx_cons, sky2->tx_prod,
2250 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2251 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2252
2253 /* can't restart safely under softirq */
2254 schedule_work(&hw->restart_work);
2255 }
2256
2257 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2258 {
2259 struct sky2_port *sky2 = netdev_priv(dev);
2260 struct sky2_hw *hw = sky2->hw;
2261 unsigned port = sky2->port;
2262 int err;
2263 u16 ctl, mode;
2264 u32 imask;
2265
2266 /* MTU size outside the spec */
2267 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2268 return -EINVAL;
2269
2270 /* MTU > 1500 on yukon FE and FE+ not allowed */
2271 if (new_mtu > ETH_DATA_LEN &&
2272 (hw->chip_id == CHIP_ID_YUKON_FE ||
2273 hw->chip_id == CHIP_ID_YUKON_FE_P))
2274 return -EINVAL;
2275
2276 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2277 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2278 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2279
2280 if (!netif_running(dev)) {
2281 dev->mtu = new_mtu;
2282 return 0;
2283 }
2284
2285 imask = sky2_read32(hw, B0_IMSK);
2286 sky2_write32(hw, B0_IMSK, 0);
2287
2288 dev->trans_start = jiffies; /* prevent tx timeout */
2289 napi_disable(&hw->napi);
2290 netif_tx_disable(dev);
2291
2292 synchronize_irq(hw->pdev->irq);
2293
2294 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2295 sky2_set_tx_stfwd(hw, port);
2296
2297 ctl = gma_read16(hw, port, GM_GP_CTRL);
2298 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2299 sky2_rx_stop(sky2);
2300 sky2_rx_clean(sky2);
2301
2302 dev->mtu = new_mtu;
2303
2304 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2305 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2306
2307 if (dev->mtu > ETH_DATA_LEN)
2308 mode |= GM_SMOD_JUMBO_ENA;
2309
2310 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2311
2312 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2313
2314 err = sky2_alloc_rx_skbs(sky2);
2315 if (!err)
2316 sky2_rx_start(sky2);
2317 else
2318 sky2_rx_clean(sky2);
2319 sky2_write32(hw, B0_IMSK, imask);
2320
2321 sky2_read32(hw, B0_Y2_SP_LISR);
2322 napi_enable(&hw->napi);
2323
2324 if (err)
2325 dev_close(dev);
2326 else {
2327 gma_write16(hw, port, GM_GP_CTRL, ctl);
2328
2329 netif_wake_queue(dev);
2330 }
2331
2332 return err;
2333 }
2334
2335 /* For small just reuse existing skb for next receive */
2336 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2337 const struct rx_ring_info *re,
2338 unsigned length)
2339 {
2340 struct sk_buff *skb;
2341
2342 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2343 if (likely(skb)) {
2344 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2345 length, PCI_DMA_FROMDEVICE);
2346 skb_copy_from_linear_data(re->skb, skb->data, length);
2347 skb->ip_summed = re->skb->ip_summed;
2348 skb->csum = re->skb->csum;
2349 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2350 length, PCI_DMA_FROMDEVICE);
2351 re->skb->ip_summed = CHECKSUM_NONE;
2352 skb_put(skb, length);
2353 }
2354 return skb;
2355 }
2356
2357 /* Adjust length of skb with fragments to match received data */
2358 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2359 unsigned int length)
2360 {
2361 int i, num_frags;
2362 unsigned int size;
2363
2364 /* put header into skb */
2365 size = min(length, hdr_space);
2366 skb->tail += size;
2367 skb->len += size;
2368 length -= size;
2369
2370 num_frags = skb_shinfo(skb)->nr_frags;
2371 for (i = 0; i < num_frags; i++) {
2372 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2373
2374 if (length == 0) {
2375 /* don't need this page */
2376 __free_page(frag->page);
2377 --skb_shinfo(skb)->nr_frags;
2378 } else {
2379 size = min(length, (unsigned) PAGE_SIZE);
2380
2381 frag->size = size;
2382 skb->data_len += size;
2383 skb->truesize += size;
2384 skb->len += size;
2385 length -= size;
2386 }
2387 }
2388 }
2389
2390 /* Normal packet - take skb from ring element and put in a new one */
2391 static struct sk_buff *receive_new(struct sky2_port *sky2,
2392 struct rx_ring_info *re,
2393 unsigned int length)
2394 {
2395 struct sk_buff *skb;
2396 struct rx_ring_info nre;
2397 unsigned hdr_space = sky2->rx_data_size;
2398
2399 nre.skb = sky2_rx_alloc(sky2);
2400 if (unlikely(!nre.skb))
2401 goto nobuf;
2402
2403 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2404 goto nomap;
2405
2406 skb = re->skb;
2407 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2408 prefetch(skb->data);
2409 *re = nre;
2410
2411 if (skb_shinfo(skb)->nr_frags)
2412 skb_put_frags(skb, hdr_space, length);
2413 else
2414 skb_put(skb, length);
2415 return skb;
2416
2417 nomap:
2418 dev_kfree_skb(nre.skb);
2419 nobuf:
2420 return NULL;
2421 }
2422
2423 /*
2424 * Receive one packet.
2425 * For larger packets, get new buffer.
2426 */
2427 static struct sk_buff *sky2_receive(struct net_device *dev,
2428 u16 length, u32 status)
2429 {
2430 struct sky2_port *sky2 = netdev_priv(dev);
2431 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2432 struct sk_buff *skb = NULL;
2433 u16 count = (status & GMR_FS_LEN) >> 16;
2434
2435 #ifdef SKY2_VLAN_TAG_USED
2436 /* Account for vlan tag */
2437 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2438 count -= VLAN_HLEN;
2439 #endif
2440
2441 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2442 "rx slot %u status 0x%x len %d\n",
2443 sky2->rx_next, status, length);
2444
2445 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2446 prefetch(sky2->rx_ring + sky2->rx_next);
2447
2448 /* This chip has hardware problems that generates bogus status.
2449 * So do only marginal checking and expect higher level protocols
2450 * to handle crap frames.
2451 */
2452 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2453 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2454 length != count)
2455 goto okay;
2456
2457 if (status & GMR_FS_ANY_ERR)
2458 goto error;
2459
2460 if (!(status & GMR_FS_RX_OK))
2461 goto resubmit;
2462
2463 /* if length reported by DMA does not match PHY, packet was truncated */
2464 if (length != count)
2465 goto error;
2466
2467 okay:
2468 if (length < copybreak)
2469 skb = receive_copy(sky2, re, length);
2470 else
2471 skb = receive_new(sky2, re, length);
2472
2473 dev->stats.rx_dropped += (skb == NULL);
2474
2475 resubmit:
2476 sky2_rx_submit(sky2, re);
2477
2478 return skb;
2479
2480 error:
2481 ++dev->stats.rx_errors;
2482
2483 if (net_ratelimit())
2484 netif_info(sky2, rx_err, dev,
2485 "rx error, status 0x%x length %d\n", status, length);
2486
2487 goto resubmit;
2488 }
2489
2490 /* Transmit complete */
2491 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2492 {
2493 struct sky2_port *sky2 = netdev_priv(dev);
2494
2495 if (netif_running(dev)) {
2496 sky2_tx_complete(sky2, last);
2497
2498 /* Wake unless it's detached, and called e.g. from sky2_down() */
2499 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2500 netif_wake_queue(dev);
2501 }
2502 }
2503
2504 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2505 u32 status, struct sk_buff *skb)
2506 {
2507 #ifdef SKY2_VLAN_TAG_USED
2508 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2509 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2510 if (skb->ip_summed == CHECKSUM_NONE)
2511 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2512 else
2513 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2514 vlan_tag, skb);
2515 return;
2516 }
2517 #endif
2518 if (skb->ip_summed == CHECKSUM_NONE)
2519 netif_receive_skb(skb);
2520 else
2521 napi_gro_receive(&sky2->hw->napi, skb);
2522 }
2523
2524 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2525 unsigned packets, unsigned bytes)
2526 {
2527 struct net_device *dev = hw->dev[port];
2528 struct sky2_port *sky2 = netdev_priv(dev);
2529
2530 if (packets == 0)
2531 return;
2532
2533 u64_stats_update_begin(&sky2->rx_stats.syncp);
2534 sky2->rx_stats.packets += packets;
2535 sky2->rx_stats.bytes += bytes;
2536 u64_stats_update_end(&sky2->rx_stats.syncp);
2537
2538 dev->last_rx = jiffies;
2539 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2540 }
2541
2542 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2543 {
2544 /* If this happens then driver assuming wrong format for chip type */
2545 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2546
2547 /* Both checksum counters are programmed to start at
2548 * the same offset, so unless there is a problem they
2549 * should match. This failure is an early indication that
2550 * hardware receive checksumming won't work.
2551 */
2552 if (likely((u16)(status >> 16) == (u16)status)) {
2553 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2554 skb->ip_summed = CHECKSUM_COMPLETE;
2555 skb->csum = le16_to_cpu(status);
2556 } else {
2557 dev_notice(&sky2->hw->pdev->dev,
2558 "%s: receive checksum problem (status = %#x)\n",
2559 sky2->netdev->name, status);
2560
2561 /* Disable checksum offload */
2562 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2563 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2564 BMU_DIS_RX_CHKSUM);
2565 }
2566 }
2567
2568 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2569 {
2570 struct sk_buff *skb;
2571
2572 skb = sky2->rx_ring[sky2->rx_next].skb;
2573 skb->rxhash = le32_to_cpu(status);
2574 }
2575
2576 /* Process status response ring */
2577 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2578 {
2579 int work_done = 0;
2580 unsigned int total_bytes[2] = { 0 };
2581 unsigned int total_packets[2] = { 0 };
2582
2583 rmb();
2584 do {
2585 struct sky2_port *sky2;
2586 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2587 unsigned port;
2588 struct net_device *dev;
2589 struct sk_buff *skb;
2590 u32 status;
2591 u16 length;
2592 u8 opcode = le->opcode;
2593
2594 if (!(opcode & HW_OWNER))
2595 break;
2596
2597 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2598
2599 port = le->css & CSS_LINK_BIT;
2600 dev = hw->dev[port];
2601 sky2 = netdev_priv(dev);
2602 length = le16_to_cpu(le->length);
2603 status = le32_to_cpu(le->status);
2604
2605 le->opcode = 0;
2606 switch (opcode & ~HW_OWNER) {
2607 case OP_RXSTAT:
2608 total_packets[port]++;
2609 total_bytes[port] += length;
2610
2611 skb = sky2_receive(dev, length, status);
2612 if (!skb)
2613 break;
2614
2615 /* This chip reports checksum status differently */
2616 if (hw->flags & SKY2_HW_NEW_LE) {
2617 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2618 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2619 (le->css & CSS_TCPUDPCSOK))
2620 skb->ip_summed = CHECKSUM_UNNECESSARY;
2621 else
2622 skb->ip_summed = CHECKSUM_NONE;
2623 }
2624
2625 skb->protocol = eth_type_trans(skb, dev);
2626
2627 sky2_skb_rx(sky2, status, skb);
2628
2629 /* Stop after net poll weight */
2630 if (++work_done >= to_do)
2631 goto exit_loop;
2632 break;
2633
2634 #ifdef SKY2_VLAN_TAG_USED
2635 case OP_RXVLAN:
2636 sky2->rx_tag = length;
2637 break;
2638
2639 case OP_RXCHKSVLAN:
2640 sky2->rx_tag = length;
2641 /* fall through */
2642 #endif
2643 case OP_RXCHKS:
2644 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2645 sky2_rx_checksum(sky2, status);
2646 break;
2647
2648 case OP_RSS_HASH:
2649 sky2_rx_hash(sky2, status);
2650 break;
2651
2652 case OP_TXINDEXLE:
2653 /* TX index reports status for both ports */
2654 sky2_tx_done(hw->dev[0], status & 0xfff);
2655 if (hw->dev[1])
2656 sky2_tx_done(hw->dev[1],
2657 ((status >> 24) & 0xff)
2658 | (u16)(length & 0xf) << 8);
2659 break;
2660
2661 default:
2662 if (net_ratelimit())
2663 pr_warning("unknown status opcode 0x%x\n", opcode);
2664 }
2665 } while (hw->st_idx != idx);
2666
2667 /* Fully processed status ring so clear irq */
2668 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2669
2670 exit_loop:
2671 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2672 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2673
2674 return work_done;
2675 }
2676
2677 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2678 {
2679 struct net_device *dev = hw->dev[port];
2680
2681 if (net_ratelimit())
2682 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2683
2684 if (status & Y2_IS_PAR_RD1) {
2685 if (net_ratelimit())
2686 netdev_err(dev, "ram data read parity error\n");
2687 /* Clear IRQ */
2688 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2689 }
2690
2691 if (status & Y2_IS_PAR_WR1) {
2692 if (net_ratelimit())
2693 netdev_err(dev, "ram data write parity error\n");
2694
2695 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2696 }
2697
2698 if (status & Y2_IS_PAR_MAC1) {
2699 if (net_ratelimit())
2700 netdev_err(dev, "MAC parity error\n");
2701 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2702 }
2703
2704 if (status & Y2_IS_PAR_RX1) {
2705 if (net_ratelimit())
2706 netdev_err(dev, "RX parity error\n");
2707 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2708 }
2709
2710 if (status & Y2_IS_TCP_TXA1) {
2711 if (net_ratelimit())
2712 netdev_err(dev, "TCP segmentation error\n");
2713 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2714 }
2715 }
2716
2717 static void sky2_hw_intr(struct sky2_hw *hw)
2718 {
2719 struct pci_dev *pdev = hw->pdev;
2720 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2721 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2722
2723 status &= hwmsk;
2724
2725 if (status & Y2_IS_TIST_OV)
2726 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2727
2728 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2729 u16 pci_err;
2730
2731 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2732 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2733 if (net_ratelimit())
2734 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2735 pci_err);
2736
2737 sky2_pci_write16(hw, PCI_STATUS,
2738 pci_err | PCI_STATUS_ERROR_BITS);
2739 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2740 }
2741
2742 if (status & Y2_IS_PCI_EXP) {
2743 /* PCI-Express uncorrectable Error occurred */
2744 u32 err;
2745
2746 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2747 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2748 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2749 0xfffffffful);
2750 if (net_ratelimit())
2751 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2752
2753 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2754 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2755 }
2756
2757 if (status & Y2_HWE_L1_MASK)
2758 sky2_hw_error(hw, 0, status);
2759 status >>= 8;
2760 if (status & Y2_HWE_L1_MASK)
2761 sky2_hw_error(hw, 1, status);
2762 }
2763
2764 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2765 {
2766 struct net_device *dev = hw->dev[port];
2767 struct sky2_port *sky2 = netdev_priv(dev);
2768 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2769
2770 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2771
2772 if (status & GM_IS_RX_CO_OV)
2773 gma_read16(hw, port, GM_RX_IRQ_SRC);
2774
2775 if (status & GM_IS_TX_CO_OV)
2776 gma_read16(hw, port, GM_TX_IRQ_SRC);
2777
2778 if (status & GM_IS_RX_FF_OR) {
2779 ++dev->stats.rx_fifo_errors;
2780 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2781 }
2782
2783 if (status & GM_IS_TX_FF_UR) {
2784 ++dev->stats.tx_fifo_errors;
2785 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2786 }
2787 }
2788
2789 /* This should never happen it is a bug. */
2790 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2791 {
2792 struct net_device *dev = hw->dev[port];
2793 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2794
2795 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2796 dev->name, (unsigned) q, (unsigned) idx,
2797 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2798
2799 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2800 }
2801
2802 static int sky2_rx_hung(struct net_device *dev)
2803 {
2804 struct sky2_port *sky2 = netdev_priv(dev);
2805 struct sky2_hw *hw = sky2->hw;
2806 unsigned port = sky2->port;
2807 unsigned rxq = rxqaddr[port];
2808 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2809 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2810 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2811 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2812
2813 /* If idle and MAC or PCI is stuck */
2814 if (sky2->check.last == dev->last_rx &&
2815 ((mac_rp == sky2->check.mac_rp &&
2816 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2817 /* Check if the PCI RX hang */
2818 (fifo_rp == sky2->check.fifo_rp &&
2819 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2820 netdev_printk(KERN_DEBUG, dev,
2821 "hung mac %d:%d fifo %d (%d:%d)\n",
2822 mac_lev, mac_rp, fifo_lev,
2823 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2824 return 1;
2825 } else {
2826 sky2->check.last = dev->last_rx;
2827 sky2->check.mac_rp = mac_rp;
2828 sky2->check.mac_lev = mac_lev;
2829 sky2->check.fifo_rp = fifo_rp;
2830 sky2->check.fifo_lev = fifo_lev;
2831 return 0;
2832 }
2833 }
2834
2835 static void sky2_watchdog(unsigned long arg)
2836 {
2837 struct sky2_hw *hw = (struct sky2_hw *) arg;
2838
2839 /* Check for lost IRQ once a second */
2840 if (sky2_read32(hw, B0_ISRC)) {
2841 napi_schedule(&hw->napi);
2842 } else {
2843 int i, active = 0;
2844
2845 for (i = 0; i < hw->ports; i++) {
2846 struct net_device *dev = hw->dev[i];
2847 if (!netif_running(dev))
2848 continue;
2849 ++active;
2850
2851 /* For chips with Rx FIFO, check if stuck */
2852 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2853 sky2_rx_hung(dev)) {
2854 netdev_info(dev, "receiver hang detected\n");
2855 schedule_work(&hw->restart_work);
2856 return;
2857 }
2858 }
2859
2860 if (active == 0)
2861 return;
2862 }
2863
2864 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2865 }
2866
2867 /* Hardware/software error handling */
2868 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2869 {
2870 if (net_ratelimit())
2871 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2872
2873 if (status & Y2_IS_HW_ERR)
2874 sky2_hw_intr(hw);
2875
2876 if (status & Y2_IS_IRQ_MAC1)
2877 sky2_mac_intr(hw, 0);
2878
2879 if (status & Y2_IS_IRQ_MAC2)
2880 sky2_mac_intr(hw, 1);
2881
2882 if (status & Y2_IS_CHK_RX1)
2883 sky2_le_error(hw, 0, Q_R1);
2884
2885 if (status & Y2_IS_CHK_RX2)
2886 sky2_le_error(hw, 1, Q_R2);
2887
2888 if (status & Y2_IS_CHK_TXA1)
2889 sky2_le_error(hw, 0, Q_XA1);
2890
2891 if (status & Y2_IS_CHK_TXA2)
2892 sky2_le_error(hw, 1, Q_XA2);
2893 }
2894
2895 static int sky2_poll(struct napi_struct *napi, int work_limit)
2896 {
2897 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2898 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2899 int work_done = 0;
2900 u16 idx;
2901
2902 if (unlikely(status & Y2_IS_ERROR))
2903 sky2_err_intr(hw, status);
2904
2905 if (status & Y2_IS_IRQ_PHY1)
2906 sky2_phy_intr(hw, 0);
2907
2908 if (status & Y2_IS_IRQ_PHY2)
2909 sky2_phy_intr(hw, 1);
2910
2911 if (status & Y2_IS_PHY_QLNK)
2912 sky2_qlink_intr(hw);
2913
2914 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2915 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2916
2917 if (work_done >= work_limit)
2918 goto done;
2919 }
2920
2921 napi_complete(napi);
2922 sky2_read32(hw, B0_Y2_SP_LISR);
2923 done:
2924
2925 return work_done;
2926 }
2927
2928 static irqreturn_t sky2_intr(int irq, void *dev_id)
2929 {
2930 struct sky2_hw *hw = dev_id;
2931 u32 status;
2932
2933 /* Reading this mask interrupts as side effect */
2934 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2935 if (status == 0 || status == ~0)
2936 return IRQ_NONE;
2937
2938 prefetch(&hw->st_le[hw->st_idx]);
2939
2940 napi_schedule(&hw->napi);
2941
2942 return IRQ_HANDLED;
2943 }
2944
2945 #ifdef CONFIG_NET_POLL_CONTROLLER
2946 static void sky2_netpoll(struct net_device *dev)
2947 {
2948 struct sky2_port *sky2 = netdev_priv(dev);
2949
2950 napi_schedule(&sky2->hw->napi);
2951 }
2952 #endif
2953
2954 /* Chip internal frequency for clock calculations */
2955 static u32 sky2_mhz(const struct sky2_hw *hw)
2956 {
2957 switch (hw->chip_id) {
2958 case CHIP_ID_YUKON_EC:
2959 case CHIP_ID_YUKON_EC_U:
2960 case CHIP_ID_YUKON_EX:
2961 case CHIP_ID_YUKON_SUPR:
2962 case CHIP_ID_YUKON_UL_2:
2963 case CHIP_ID_YUKON_OPT:
2964 return 125;
2965
2966 case CHIP_ID_YUKON_FE:
2967 return 100;
2968
2969 case CHIP_ID_YUKON_FE_P:
2970 return 50;
2971
2972 case CHIP_ID_YUKON_XL:
2973 return 156;
2974
2975 default:
2976 BUG();
2977 }
2978 }
2979
2980 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2981 {
2982 return sky2_mhz(hw) * us;
2983 }
2984
2985 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2986 {
2987 return clk / sky2_mhz(hw);
2988 }
2989
2990
2991 static int __devinit sky2_init(struct sky2_hw *hw)
2992 {
2993 u8 t8;
2994
2995 /* Enable all clocks and check for bad PCI access */
2996 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2997
2998 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2999
3000 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3001 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3002
3003 switch (hw->chip_id) {
3004 case CHIP_ID_YUKON_XL:
3005 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3006 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3007 hw->flags |= SKY2_HW_RSS_BROKEN;
3008 break;
3009
3010 case CHIP_ID_YUKON_EC_U:
3011 hw->flags = SKY2_HW_GIGABIT
3012 | SKY2_HW_NEWER_PHY
3013 | SKY2_HW_ADV_POWER_CTL;
3014 break;
3015
3016 case CHIP_ID_YUKON_EX:
3017 hw->flags = SKY2_HW_GIGABIT
3018 | SKY2_HW_NEWER_PHY
3019 | SKY2_HW_NEW_LE
3020 | SKY2_HW_ADV_POWER_CTL;
3021
3022 /* New transmit checksum */
3023 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3024 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3025 break;
3026
3027 case CHIP_ID_YUKON_EC:
3028 /* This rev is really old, and requires untested workarounds */
3029 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3030 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3031 return -EOPNOTSUPP;
3032 }
3033 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3034 break;
3035
3036 case CHIP_ID_YUKON_FE:
3037 hw->flags = SKY2_HW_RSS_BROKEN;
3038 break;
3039
3040 case CHIP_ID_YUKON_FE_P:
3041 hw->flags = SKY2_HW_NEWER_PHY
3042 | SKY2_HW_NEW_LE
3043 | SKY2_HW_AUTO_TX_SUM
3044 | SKY2_HW_ADV_POWER_CTL;
3045 break;
3046
3047 case CHIP_ID_YUKON_SUPR:
3048 hw->flags = SKY2_HW_GIGABIT
3049 | SKY2_HW_NEWER_PHY
3050 | SKY2_HW_NEW_LE
3051 | SKY2_HW_AUTO_TX_SUM
3052 | SKY2_HW_ADV_POWER_CTL;
3053 break;
3054
3055 case CHIP_ID_YUKON_UL_2:
3056 hw->flags = SKY2_HW_GIGABIT
3057 | SKY2_HW_ADV_POWER_CTL;
3058 break;
3059
3060 case CHIP_ID_YUKON_OPT:
3061 hw->flags = SKY2_HW_GIGABIT
3062 | SKY2_HW_NEW_LE
3063 | SKY2_HW_ADV_POWER_CTL;
3064 break;
3065
3066 default:
3067 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3068 hw->chip_id);
3069 return -EOPNOTSUPP;
3070 }
3071
3072 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3073 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3074 hw->flags |= SKY2_HW_FIBRE_PHY;
3075
3076 hw->ports = 1;
3077 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3078 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3079 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3080 ++hw->ports;
3081 }
3082
3083 if (sky2_read8(hw, B2_E_0))
3084 hw->flags |= SKY2_HW_RAM_BUFFER;
3085
3086 return 0;
3087 }
3088
3089 static void sky2_reset(struct sky2_hw *hw)
3090 {
3091 struct pci_dev *pdev = hw->pdev;
3092 u16 status;
3093 int i, cap;
3094 u32 hwe_mask = Y2_HWE_ALL_MASK;
3095
3096 /* disable ASF */
3097 if (hw->chip_id == CHIP_ID_YUKON_EX
3098 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3099 sky2_write32(hw, CPU_WDOG, 0);
3100 status = sky2_read16(hw, HCU_CCSR);
3101 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3102 HCU_CCSR_UC_STATE_MSK);
3103 /*
3104 * CPU clock divider shouldn't be used because
3105 * - ASF firmware may malfunction
3106 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3107 */
3108 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3109 sky2_write16(hw, HCU_CCSR, status);
3110 sky2_write32(hw, CPU_WDOG, 0);
3111 } else
3112 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3113 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3114
3115 /* do a SW reset */
3116 sky2_write8(hw, B0_CTST, CS_RST_SET);
3117 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3118
3119 /* allow writes to PCI config */
3120 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3121
3122 /* clear PCI errors, if any */
3123 status = sky2_pci_read16(hw, PCI_STATUS);
3124 status |= PCI_STATUS_ERROR_BITS;
3125 sky2_pci_write16(hw, PCI_STATUS, status);
3126
3127 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3128
3129 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3130 if (cap) {
3131 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3132 0xfffffffful);
3133
3134 /* If error bit is stuck on ignore it */
3135 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3136 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3137 else
3138 hwe_mask |= Y2_IS_PCI_EXP;
3139 }
3140
3141 sky2_power_on(hw);
3142 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3143
3144 for (i = 0; i < hw->ports; i++) {
3145 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3146 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3147
3148 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3149 hw->chip_id == CHIP_ID_YUKON_SUPR)
3150 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3151 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3152 | GMC_BYP_RETR_ON);
3153
3154 }
3155
3156 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3157 /* enable MACSec clock gating */
3158 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3159 }
3160
3161 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3162 u16 reg;
3163 u32 msk;
3164
3165 if (hw->chip_rev == 0) {
3166 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3167 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3168
3169 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3170 reg = 10;
3171 } else {
3172 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3173 reg = 3;
3174 }
3175
3176 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3177
3178 /* reset PHY Link Detect */
3179 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3180 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3181 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3182 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3183
3184
3185 /* enable PHY Quick Link */
3186 msk = sky2_read32(hw, B0_IMSK);
3187 msk |= Y2_IS_PHY_QLNK;
3188 sky2_write32(hw, B0_IMSK, msk);
3189
3190 /* check if PSMv2 was running before */
3191 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3192 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3193 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3194 /* restore the PCIe Link Control register */
3195 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3196 }
3197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3198
3199 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3200 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3201 }
3202
3203 /* Clear I2C IRQ noise */
3204 sky2_write32(hw, B2_I2C_IRQ, 1);
3205
3206 /* turn off hardware timer (unused) */
3207 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3208 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3209
3210 /* Turn off descriptor polling */
3211 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3212
3213 /* Turn off receive timestamp */
3214 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3215 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3216
3217 /* enable the Tx Arbiters */
3218 for (i = 0; i < hw->ports; i++)
3219 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3220
3221 /* Initialize ram interface */
3222 for (i = 0; i < hw->ports; i++) {
3223 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3224
3225 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3226 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3227 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3228 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3229 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3230 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3231 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3232 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3233 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3234 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3235 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3236 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3237 }
3238
3239 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3240
3241 for (i = 0; i < hw->ports; i++)
3242 sky2_gmac_reset(hw, i);
3243
3244 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3245 hw->st_idx = 0;
3246
3247 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3248 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3249
3250 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3251 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3252
3253 /* Set the list last index */
3254 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3255
3256 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3257 sky2_write8(hw, STAT_FIFO_WM, 16);
3258
3259 /* set Status-FIFO ISR watermark */
3260 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3261 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3262 else
3263 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3264
3265 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3266 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3267 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3268
3269 /* enable status unit */
3270 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3271
3272 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3273 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3274 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3275 }
3276
3277 /* Take device down (offline).
3278 * Equivalent to doing dev_stop() but this does not
3279 * inform upper layers of the transistion.
3280 */
3281 static void sky2_detach(struct net_device *dev)
3282 {
3283 if (netif_running(dev)) {
3284 netif_tx_lock(dev);
3285 netif_device_detach(dev); /* stop txq */
3286 netif_tx_unlock(dev);
3287 sky2_down(dev);
3288 }
3289 }
3290
3291 /* Bring device back after doing sky2_detach */
3292 static int sky2_reattach(struct net_device *dev)
3293 {
3294 int err = 0;
3295
3296 if (netif_running(dev)) {
3297 err = sky2_up(dev);
3298 if (err) {
3299 netdev_info(dev, "could not restart %d\n", err);
3300 dev_close(dev);
3301 } else {
3302 netif_device_attach(dev);
3303 sky2_set_multicast(dev);
3304 }
3305 }
3306
3307 return err;
3308 }
3309
3310 static void sky2_all_down(struct sky2_hw *hw)
3311 {
3312 int i;
3313
3314 sky2_read32(hw, B0_IMSK);
3315 sky2_write32(hw, B0_IMSK, 0);
3316 synchronize_irq(hw->pdev->irq);
3317 napi_disable(&hw->napi);
3318
3319 for (i = 0; i < hw->ports; i++) {
3320 struct net_device *dev = hw->dev[i];
3321 struct sky2_port *sky2 = netdev_priv(dev);
3322
3323 if (!netif_running(dev))
3324 continue;
3325
3326 netif_carrier_off(dev);
3327 netif_tx_disable(dev);
3328 sky2_hw_down(sky2);
3329 }
3330 }
3331
3332 static void sky2_all_up(struct sky2_hw *hw)
3333 {
3334 u32 imask = Y2_IS_BASE;
3335 int i;
3336
3337 for (i = 0; i < hw->ports; i++) {
3338 struct net_device *dev = hw->dev[i];
3339 struct sky2_port *sky2 = netdev_priv(dev);
3340
3341 if (!netif_running(dev))
3342 continue;
3343
3344 sky2_hw_up(sky2);
3345 sky2_set_multicast(dev);
3346 imask |= portirq_msk[i];
3347 netif_wake_queue(dev);
3348 }
3349
3350 sky2_write32(hw, B0_IMSK, imask);
3351 sky2_read32(hw, B0_IMSK);
3352
3353 sky2_read32(hw, B0_Y2_SP_LISR);
3354 napi_enable(&hw->napi);
3355 }
3356
3357 static void sky2_restart(struct work_struct *work)
3358 {
3359 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3360
3361 rtnl_lock();
3362
3363 sky2_all_down(hw);
3364 sky2_reset(hw);
3365 sky2_all_up(hw);
3366
3367 rtnl_unlock();
3368 }
3369
3370 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3371 {
3372 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3373 }
3374
3375 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3376 {
3377 const struct sky2_port *sky2 = netdev_priv(dev);
3378
3379 wol->supported = sky2_wol_supported(sky2->hw);
3380 wol->wolopts = sky2->wol;
3381 }
3382
3383 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3384 {
3385 struct sky2_port *sky2 = netdev_priv(dev);
3386 struct sky2_hw *hw = sky2->hw;
3387 bool enable_wakeup = false;
3388 int i;
3389
3390 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3391 !device_can_wakeup(&hw->pdev->dev))
3392 return -EOPNOTSUPP;
3393
3394 sky2->wol = wol->wolopts;
3395
3396 for (i = 0; i < hw->ports; i++) {
3397 struct net_device *dev = hw->dev[i];
3398 struct sky2_port *sky2 = netdev_priv(dev);
3399
3400 if (sky2->wol)
3401 enable_wakeup = true;
3402 }
3403 device_set_wakeup_enable(&hw->pdev->dev, enable_wakeup);
3404
3405 return 0;
3406 }
3407
3408 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3409 {
3410 if (sky2_is_copper(hw)) {
3411 u32 modes = SUPPORTED_10baseT_Half
3412 | SUPPORTED_10baseT_Full
3413 | SUPPORTED_100baseT_Half
3414 | SUPPORTED_100baseT_Full
3415 | SUPPORTED_Autoneg | SUPPORTED_TP;
3416
3417 if (hw->flags & SKY2_HW_GIGABIT)
3418 modes |= SUPPORTED_1000baseT_Half
3419 | SUPPORTED_1000baseT_Full;
3420 return modes;
3421 } else
3422 return SUPPORTED_1000baseT_Half
3423 | SUPPORTED_1000baseT_Full
3424 | SUPPORTED_Autoneg
3425 | SUPPORTED_FIBRE;
3426 }
3427
3428 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3429 {
3430 struct sky2_port *sky2 = netdev_priv(dev);
3431 struct sky2_hw *hw = sky2->hw;
3432
3433 ecmd->transceiver = XCVR_INTERNAL;
3434 ecmd->supported = sky2_supported_modes(hw);
3435 ecmd->phy_address = PHY_ADDR_MARV;
3436 if (sky2_is_copper(hw)) {
3437 ecmd->port = PORT_TP;
3438 ecmd->speed = sky2->speed;
3439 } else {
3440 ecmd->speed = SPEED_1000;
3441 ecmd->port = PORT_FIBRE;
3442 }
3443
3444 ecmd->advertising = sky2->advertising;
3445 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3446 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3447 ecmd->duplex = sky2->duplex;
3448 return 0;
3449 }
3450
3451 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3452 {
3453 struct sky2_port *sky2 = netdev_priv(dev);
3454 const struct sky2_hw *hw = sky2->hw;
3455 u32 supported = sky2_supported_modes(hw);
3456
3457 if (ecmd->autoneg == AUTONEG_ENABLE) {
3458 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3459 ecmd->advertising = supported;
3460 sky2->duplex = -1;
3461 sky2->speed = -1;
3462 } else {
3463 u32 setting;
3464
3465 switch (ecmd->speed) {
3466 case SPEED_1000:
3467 if (ecmd->duplex == DUPLEX_FULL)
3468 setting = SUPPORTED_1000baseT_Full;
3469 else if (ecmd->duplex == DUPLEX_HALF)
3470 setting = SUPPORTED_1000baseT_Half;
3471 else
3472 return -EINVAL;
3473 break;
3474 case SPEED_100:
3475 if (ecmd->duplex == DUPLEX_FULL)
3476 setting = SUPPORTED_100baseT_Full;
3477 else if (ecmd->duplex == DUPLEX_HALF)
3478 setting = SUPPORTED_100baseT_Half;
3479 else
3480 return -EINVAL;
3481 break;
3482
3483 case SPEED_10:
3484 if (ecmd->duplex == DUPLEX_FULL)
3485 setting = SUPPORTED_10baseT_Full;
3486 else if (ecmd->duplex == DUPLEX_HALF)
3487 setting = SUPPORTED_10baseT_Half;
3488 else
3489 return -EINVAL;
3490 break;
3491 default:
3492 return -EINVAL;
3493 }
3494
3495 if ((setting & supported) == 0)
3496 return -EINVAL;
3497
3498 sky2->speed = ecmd->speed;
3499 sky2->duplex = ecmd->duplex;
3500 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3501 }
3502
3503 sky2->advertising = ecmd->advertising;
3504
3505 if (netif_running(dev)) {
3506 sky2_phy_reinit(sky2);
3507 sky2_set_multicast(dev);
3508 }
3509
3510 return 0;
3511 }
3512
3513 static void sky2_get_drvinfo(struct net_device *dev,
3514 struct ethtool_drvinfo *info)
3515 {
3516 struct sky2_port *sky2 = netdev_priv(dev);
3517
3518 strcpy(info->driver, DRV_NAME);
3519 strcpy(info->version, DRV_VERSION);
3520 strcpy(info->fw_version, "N/A");
3521 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3522 }
3523
3524 static const struct sky2_stat {
3525 char name[ETH_GSTRING_LEN];
3526 u16 offset;
3527 } sky2_stats[] = {
3528 { "tx_bytes", GM_TXO_OK_HI },
3529 { "rx_bytes", GM_RXO_OK_HI },
3530 { "tx_broadcast", GM_TXF_BC_OK },
3531 { "rx_broadcast", GM_RXF_BC_OK },
3532 { "tx_multicast", GM_TXF_MC_OK },
3533 { "rx_multicast", GM_RXF_MC_OK },
3534 { "tx_unicast", GM_TXF_UC_OK },
3535 { "rx_unicast", GM_RXF_UC_OK },
3536 { "tx_mac_pause", GM_TXF_MPAUSE },
3537 { "rx_mac_pause", GM_RXF_MPAUSE },
3538 { "collisions", GM_TXF_COL },
3539 { "late_collision",GM_TXF_LAT_COL },
3540 { "aborted", GM_TXF_ABO_COL },
3541 { "single_collisions", GM_TXF_SNG_COL },
3542 { "multi_collisions", GM_TXF_MUL_COL },
3543
3544 { "rx_short", GM_RXF_SHT },
3545 { "rx_runt", GM_RXE_FRAG },
3546 { "rx_64_byte_packets", GM_RXF_64B },
3547 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3548 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3549 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3550 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3551 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3552 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3553 { "rx_too_long", GM_RXF_LNG_ERR },
3554 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3555 { "rx_jabber", GM_RXF_JAB_PKT },
3556 { "rx_fcs_error", GM_RXF_FCS_ERR },
3557
3558 { "tx_64_byte_packets", GM_TXF_64B },
3559 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3560 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3561 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3562 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3563 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3564 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3565 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3566 };
3567
3568 static u32 sky2_get_rx_csum(struct net_device *dev)
3569 {
3570 struct sky2_port *sky2 = netdev_priv(dev);
3571
3572 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3573 }
3574
3575 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3576 {
3577 struct sky2_port *sky2 = netdev_priv(dev);
3578
3579 if (data)
3580 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3581 else
3582 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3583
3584 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3585 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3586
3587 return 0;
3588 }
3589
3590 static u32 sky2_get_msglevel(struct net_device *netdev)
3591 {
3592 struct sky2_port *sky2 = netdev_priv(netdev);
3593 return sky2->msg_enable;
3594 }
3595
3596 static int sky2_nway_reset(struct net_device *dev)
3597 {
3598 struct sky2_port *sky2 = netdev_priv(dev);
3599
3600 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3601 return -EINVAL;
3602
3603 sky2_phy_reinit(sky2);
3604 sky2_set_multicast(dev);
3605
3606 return 0;
3607 }
3608
3609 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3610 {
3611 struct sky2_hw *hw = sky2->hw;
3612 unsigned port = sky2->port;
3613 int i;
3614
3615 data[0] = get_stats64(hw, port, GM_TXO_OK_LO);
3616 data[1] = get_stats64(hw, port, GM_RXO_OK_LO);
3617
3618 for (i = 2; i < count; i++)
3619 data[i] = get_stats32(hw, port, sky2_stats[i].offset);
3620 }
3621
3622 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3623 {
3624 struct sky2_port *sky2 = netdev_priv(netdev);
3625 sky2->msg_enable = value;
3626 }
3627
3628 static int sky2_get_sset_count(struct net_device *dev, int sset)
3629 {
3630 switch (sset) {
3631 case ETH_SS_STATS:
3632 return ARRAY_SIZE(sky2_stats);
3633 default:
3634 return -EOPNOTSUPP;
3635 }
3636 }
3637
3638 static void sky2_get_ethtool_stats(struct net_device *dev,
3639 struct ethtool_stats *stats, u64 * data)
3640 {
3641 struct sky2_port *sky2 = netdev_priv(dev);
3642
3643 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3644 }
3645
3646 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3647 {
3648 int i;
3649
3650 switch (stringset) {
3651 case ETH_SS_STATS:
3652 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3653 memcpy(data + i * ETH_GSTRING_LEN,
3654 sky2_stats[i].name, ETH_GSTRING_LEN);
3655 break;
3656 }
3657 }
3658
3659 static int sky2_set_mac_address(struct net_device *dev, void *p)
3660 {
3661 struct sky2_port *sky2 = netdev_priv(dev);
3662 struct sky2_hw *hw = sky2->hw;
3663 unsigned port = sky2->port;
3664 const struct sockaddr *addr = p;
3665
3666 if (!is_valid_ether_addr(addr->sa_data))
3667 return -EADDRNOTAVAIL;
3668
3669 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3670 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3671 dev->dev_addr, ETH_ALEN);
3672 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3673 dev->dev_addr, ETH_ALEN);
3674
3675 /* virtual address for data */
3676 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3677
3678 /* physical address: used for pause frames */
3679 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3680
3681 return 0;
3682 }
3683
3684 static inline void sky2_add_filter(u8 filter[8], const u8 *addr)
3685 {
3686 u32 bit;
3687
3688 bit = ether_crc(ETH_ALEN, addr) & 63;
3689 filter[bit >> 3] |= 1 << (bit & 7);
3690 }
3691
3692 static void sky2_set_multicast(struct net_device *dev)
3693 {
3694 struct sky2_port *sky2 = netdev_priv(dev);
3695 struct sky2_hw *hw = sky2->hw;
3696 unsigned port = sky2->port;
3697 struct netdev_hw_addr *ha;
3698 u16 reg;
3699 u8 filter[8];
3700 int rx_pause;
3701 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3702
3703 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3704 memset(filter, 0, sizeof(filter));
3705
3706 reg = gma_read16(hw, port, GM_RX_CTRL);
3707 reg |= GM_RXCR_UCF_ENA;
3708
3709 if (dev->flags & IFF_PROMISC) /* promiscuous */
3710 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3711 else if (dev->flags & IFF_ALLMULTI)
3712 memset(filter, 0xff, sizeof(filter));
3713 else if (netdev_mc_empty(dev) && !rx_pause)
3714 reg &= ~GM_RXCR_MCF_ENA;
3715 else {
3716 reg |= GM_RXCR_MCF_ENA;
3717
3718 if (rx_pause)
3719 sky2_add_filter(filter, pause_mc_addr);
3720
3721 netdev_for_each_mc_addr(ha, dev)
3722 sky2_add_filter(filter, ha->addr);
3723 }
3724
3725 gma_write16(hw, port, GM_MC_ADDR_H1,
3726 (u16) filter[0] | ((u16) filter[1] << 8));
3727 gma_write16(hw, port, GM_MC_ADDR_H2,
3728 (u16) filter[2] | ((u16) filter[3] << 8));
3729 gma_write16(hw, port, GM_MC_ADDR_H3,
3730 (u16) filter[4] | ((u16) filter[5] << 8));
3731 gma_write16(hw, port, GM_MC_ADDR_H4,
3732 (u16) filter[6] | ((u16) filter[7] << 8));
3733
3734 gma_write16(hw, port, GM_RX_CTRL, reg);
3735 }
3736
3737 static struct rtnl_link_stats64 *sky2_get_stats(struct net_device *dev,
3738 struct rtnl_link_stats64 *stats)
3739 {
3740 struct sky2_port *sky2 = netdev_priv(dev);
3741 struct sky2_hw *hw = sky2->hw;
3742 unsigned port = sky2->port;
3743 unsigned int start;
3744 u64 _bytes, _packets;
3745
3746 do {
3747 start = u64_stats_fetch_begin_bh(&sky2->rx_stats.syncp);
3748 _bytes = sky2->rx_stats.bytes;
3749 _packets = sky2->rx_stats.packets;
3750 } while (u64_stats_fetch_retry_bh(&sky2->rx_stats.syncp, start));
3751
3752 stats->rx_packets = _packets;
3753 stats->rx_bytes = _bytes;
3754
3755 do {
3756 start = u64_stats_fetch_begin_bh(&sky2->tx_stats.syncp);
3757 _bytes = sky2->tx_stats.bytes;
3758 _packets = sky2->tx_stats.packets;
3759 } while (u64_stats_fetch_retry_bh(&sky2->tx_stats.syncp, start));
3760
3761 stats->tx_packets = _packets;
3762 stats->tx_bytes = _bytes;
3763
3764 stats->multicast = get_stats32(hw, port, GM_RXF_MC_OK)
3765 + get_stats32(hw, port, GM_RXF_BC_OK);
3766
3767 stats->collisions = get_stats32(hw, port, GM_TXF_COL);
3768
3769 stats->rx_length_errors = get_stats32(hw, port, GM_RXF_LNG_ERR);
3770 stats->rx_crc_errors = get_stats32(hw, port, GM_RXF_FCS_ERR);
3771 stats->rx_frame_errors = get_stats32(hw, port, GM_RXF_SHT)
3772 + get_stats32(hw, port, GM_RXE_FRAG);
3773 stats->rx_over_errors = get_stats32(hw, port, GM_RXE_FIFO_OV);
3774
3775 stats->rx_dropped = dev->stats.rx_dropped;
3776 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
3777 stats->tx_fifo_errors = dev->stats.tx_fifo_errors;
3778
3779 return stats;
3780 }
3781
3782 /* Can have one global because blinking is controlled by
3783 * ethtool and that is always under RTNL mutex
3784 */
3785 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3786 {
3787 struct sky2_hw *hw = sky2->hw;
3788 unsigned port = sky2->port;
3789
3790 spin_lock_bh(&sky2->phy_lock);
3791 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3792 hw->chip_id == CHIP_ID_YUKON_EX ||
3793 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3794 u16 pg;
3795 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3796 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3797
3798 switch (mode) {
3799 case MO_LED_OFF:
3800 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3801 PHY_M_LEDC_LOS_CTRL(8) |
3802 PHY_M_LEDC_INIT_CTRL(8) |
3803 PHY_M_LEDC_STA1_CTRL(8) |
3804 PHY_M_LEDC_STA0_CTRL(8));
3805 break;
3806 case MO_LED_ON:
3807 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3808 PHY_M_LEDC_LOS_CTRL(9) |
3809 PHY_M_LEDC_INIT_CTRL(9) |
3810 PHY_M_LEDC_STA1_CTRL(9) |
3811 PHY_M_LEDC_STA0_CTRL(9));
3812 break;
3813 case MO_LED_BLINK:
3814 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3815 PHY_M_LEDC_LOS_CTRL(0xa) |
3816 PHY_M_LEDC_INIT_CTRL(0xa) |
3817 PHY_M_LEDC_STA1_CTRL(0xa) |
3818 PHY_M_LEDC_STA0_CTRL(0xa));
3819 break;
3820 case MO_LED_NORM:
3821 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3822 PHY_M_LEDC_LOS_CTRL(1) |
3823 PHY_M_LEDC_INIT_CTRL(8) |
3824 PHY_M_LEDC_STA1_CTRL(7) |
3825 PHY_M_LEDC_STA0_CTRL(7));
3826 }
3827
3828 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3829 } else
3830 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3831 PHY_M_LED_MO_DUP(mode) |
3832 PHY_M_LED_MO_10(mode) |
3833 PHY_M_LED_MO_100(mode) |
3834 PHY_M_LED_MO_1000(mode) |
3835 PHY_M_LED_MO_RX(mode) |
3836 PHY_M_LED_MO_TX(mode));
3837
3838 spin_unlock_bh(&sky2->phy_lock);
3839 }
3840
3841 /* blink LED's for finding board */
3842 static int sky2_phys_id(struct net_device *dev, u32 data)
3843 {
3844 struct sky2_port *sky2 = netdev_priv(dev);
3845 unsigned int i;
3846
3847 if (data == 0)
3848 data = UINT_MAX;
3849
3850 for (i = 0; i < data; i++) {
3851 sky2_led(sky2, MO_LED_ON);
3852 if (msleep_interruptible(500))
3853 break;
3854 sky2_led(sky2, MO_LED_OFF);
3855 if (msleep_interruptible(500))
3856 break;
3857 }
3858 sky2_led(sky2, MO_LED_NORM);
3859
3860 return 0;
3861 }
3862
3863 static void sky2_get_pauseparam(struct net_device *dev,
3864 struct ethtool_pauseparam *ecmd)
3865 {
3866 struct sky2_port *sky2 = netdev_priv(dev);
3867
3868 switch (sky2->flow_mode) {
3869 case FC_NONE:
3870 ecmd->tx_pause = ecmd->rx_pause = 0;
3871 break;
3872 case FC_TX:
3873 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3874 break;
3875 case FC_RX:
3876 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3877 break;
3878 case FC_BOTH:
3879 ecmd->tx_pause = ecmd->rx_pause = 1;
3880 }
3881
3882 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3883 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3884 }
3885
3886 static int sky2_set_pauseparam(struct net_device *dev,
3887 struct ethtool_pauseparam *ecmd)
3888 {
3889 struct sky2_port *sky2 = netdev_priv(dev);
3890
3891 if (ecmd->autoneg == AUTONEG_ENABLE)
3892 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3893 else
3894 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3895
3896 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3897
3898 if (netif_running(dev))
3899 sky2_phy_reinit(sky2);
3900
3901 return 0;
3902 }
3903
3904 static int sky2_get_coalesce(struct net_device *dev,
3905 struct ethtool_coalesce *ecmd)
3906 {
3907 struct sky2_port *sky2 = netdev_priv(dev);
3908 struct sky2_hw *hw = sky2->hw;
3909
3910 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3911 ecmd->tx_coalesce_usecs = 0;
3912 else {
3913 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3914 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3915 }
3916 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3917
3918 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3919 ecmd->rx_coalesce_usecs = 0;
3920 else {
3921 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3922 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3923 }
3924 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3925
3926 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3927 ecmd->rx_coalesce_usecs_irq = 0;
3928 else {
3929 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3930 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3931 }
3932
3933 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3934
3935 return 0;
3936 }
3937
3938 /* Note: this affect both ports */
3939 static int sky2_set_coalesce(struct net_device *dev,
3940 struct ethtool_coalesce *ecmd)
3941 {
3942 struct sky2_port *sky2 = netdev_priv(dev);
3943 struct sky2_hw *hw = sky2->hw;
3944 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3945
3946 if (ecmd->tx_coalesce_usecs > tmax ||
3947 ecmd->rx_coalesce_usecs > tmax ||
3948 ecmd->rx_coalesce_usecs_irq > tmax)
3949 return -EINVAL;
3950
3951 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3952 return -EINVAL;
3953 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3954 return -EINVAL;
3955 if (ecmd->rx_max_coalesced_frames_irq > RX_MAX_PENDING)
3956 return -EINVAL;
3957
3958 if (ecmd->tx_coalesce_usecs == 0)
3959 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3960 else {
3961 sky2_write32(hw, STAT_TX_TIMER_INI,
3962 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3963 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3964 }
3965 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3966
3967 if (ecmd->rx_coalesce_usecs == 0)
3968 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3969 else {
3970 sky2_write32(hw, STAT_LEV_TIMER_INI,
3971 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3972 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3973 }
3974 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3975
3976 if (ecmd->rx_coalesce_usecs_irq == 0)
3977 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3978 else {
3979 sky2_write32(hw, STAT_ISR_TIMER_INI,
3980 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3981 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3982 }
3983 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3984 return 0;
3985 }
3986
3987 static void sky2_get_ringparam(struct net_device *dev,
3988 struct ethtool_ringparam *ering)
3989 {
3990 struct sky2_port *sky2 = netdev_priv(dev);
3991
3992 ering->rx_max_pending = RX_MAX_PENDING;
3993 ering->rx_mini_max_pending = 0;
3994 ering->rx_jumbo_max_pending = 0;
3995 ering->tx_max_pending = TX_MAX_PENDING;
3996
3997 ering->rx_pending = sky2->rx_pending;
3998 ering->rx_mini_pending = 0;
3999 ering->rx_jumbo_pending = 0;
4000 ering->tx_pending = sky2->tx_pending;
4001 }
4002
4003 static int sky2_set_ringparam(struct net_device *dev,
4004 struct ethtool_ringparam *ering)
4005 {
4006 struct sky2_port *sky2 = netdev_priv(dev);
4007
4008 if (ering->rx_pending > RX_MAX_PENDING ||
4009 ering->rx_pending < 8 ||
4010 ering->tx_pending < TX_MIN_PENDING ||
4011 ering->tx_pending > TX_MAX_PENDING)
4012 return -EINVAL;
4013
4014 sky2_detach(dev);
4015
4016 sky2->rx_pending = ering->rx_pending;
4017 sky2->tx_pending = ering->tx_pending;
4018 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
4019
4020 return sky2_reattach(dev);
4021 }
4022
4023 static int sky2_get_regs_len(struct net_device *dev)
4024 {
4025 return 0x4000;
4026 }
4027
4028 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
4029 {
4030 /* This complicated switch statement is to make sure and
4031 * only access regions that are unreserved.
4032 * Some blocks are only valid on dual port cards.
4033 */
4034 switch (b) {
4035 /* second port */
4036 case 5: /* Tx Arbiter 2 */
4037 case 9: /* RX2 */
4038 case 14 ... 15: /* TX2 */
4039 case 17: case 19: /* Ram Buffer 2 */
4040 case 22 ... 23: /* Tx Ram Buffer 2 */
4041 case 25: /* Rx MAC Fifo 1 */
4042 case 27: /* Tx MAC Fifo 2 */
4043 case 31: /* GPHY 2 */
4044 case 40 ... 47: /* Pattern Ram 2 */
4045 case 52: case 54: /* TCP Segmentation 2 */
4046 case 112 ... 116: /* GMAC 2 */
4047 return hw->ports > 1;
4048
4049 case 0: /* Control */
4050 case 2: /* Mac address */
4051 case 4: /* Tx Arbiter 1 */
4052 case 7: /* PCI express reg */
4053 case 8: /* RX1 */
4054 case 12 ... 13: /* TX1 */
4055 case 16: case 18:/* Rx Ram Buffer 1 */
4056 case 20 ... 21: /* Tx Ram Buffer 1 */
4057 case 24: /* Rx MAC Fifo 1 */
4058 case 26: /* Tx MAC Fifo 1 */
4059 case 28 ... 29: /* Descriptor and status unit */
4060 case 30: /* GPHY 1*/
4061 case 32 ... 39: /* Pattern Ram 1 */
4062 case 48: case 50: /* TCP Segmentation 1 */
4063 case 56 ... 60: /* PCI space */
4064 case 80 ... 84: /* GMAC 1 */
4065 return 1;
4066
4067 default:
4068 return 0;
4069 }
4070 }
4071
4072 /*
4073 * Returns copy of control register region
4074 * Note: ethtool_get_regs always provides full size (16k) buffer
4075 */
4076 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4077 void *p)
4078 {
4079 const struct sky2_port *sky2 = netdev_priv(dev);
4080 const void __iomem *io = sky2->hw->regs;
4081 unsigned int b;
4082
4083 regs->version = 1;
4084
4085 for (b = 0; b < 128; b++) {
4086 /* skip poisonous diagnostic ram region in block 3 */
4087 if (b == 3)
4088 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4089 else if (sky2_reg_access_ok(sky2->hw, b))
4090 memcpy_fromio(p, io, 128);
4091 else
4092 memset(p, 0, 128);
4093
4094 p += 128;
4095 io += 128;
4096 }
4097 }
4098
4099 /* In order to do Jumbo packets on these chips, need to turn off the
4100 * transmit store/forward. Therefore checksum offload won't work.
4101 */
4102 static int no_tx_offload(struct net_device *dev)
4103 {
4104 const struct sky2_port *sky2 = netdev_priv(dev);
4105 const struct sky2_hw *hw = sky2->hw;
4106
4107 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
4108 }
4109
4110 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
4111 {
4112 if (data && no_tx_offload(dev))
4113 return -EINVAL;
4114
4115 return ethtool_op_set_tx_csum(dev, data);
4116 }
4117
4118
4119 static int sky2_set_tso(struct net_device *dev, u32 data)
4120 {
4121 if (data && no_tx_offload(dev))
4122 return -EINVAL;
4123
4124 return ethtool_op_set_tso(dev, data);
4125 }
4126
4127 static int sky2_get_eeprom_len(struct net_device *dev)
4128 {
4129 struct sky2_port *sky2 = netdev_priv(dev);
4130 struct sky2_hw *hw = sky2->hw;
4131 u16 reg2;
4132
4133 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4134 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4135 }
4136
4137 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4138 {
4139 unsigned long start = jiffies;
4140
4141 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4142 /* Can take up to 10.6 ms for write */
4143 if (time_after(jiffies, start + HZ/4)) {
4144 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4145 return -ETIMEDOUT;
4146 }
4147 mdelay(1);
4148 }
4149
4150 return 0;
4151 }
4152
4153 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4154 u16 offset, size_t length)
4155 {
4156 int rc = 0;
4157
4158 while (length > 0) {
4159 u32 val;
4160
4161 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4162 rc = sky2_vpd_wait(hw, cap, 0);
4163 if (rc)
4164 break;
4165
4166 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4167
4168 memcpy(data, &val, min(sizeof(val), length));
4169 offset += sizeof(u32);
4170 data += sizeof(u32);
4171 length -= sizeof(u32);
4172 }
4173
4174 return rc;
4175 }
4176
4177 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4178 u16 offset, unsigned int length)
4179 {
4180 unsigned int i;
4181 int rc = 0;
4182
4183 for (i = 0; i < length; i += sizeof(u32)) {
4184 u32 val = *(u32 *)(data + i);
4185
4186 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4187 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4188
4189 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4190 if (rc)
4191 break;
4192 }
4193 return rc;
4194 }
4195
4196 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4197 u8 *data)
4198 {
4199 struct sky2_port *sky2 = netdev_priv(dev);
4200 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4201
4202 if (!cap)
4203 return -EINVAL;
4204
4205 eeprom->magic = SKY2_EEPROM_MAGIC;
4206
4207 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4208 }
4209
4210 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4211 u8 *data)
4212 {
4213 struct sky2_port *sky2 = netdev_priv(dev);
4214 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4215
4216 if (!cap)
4217 return -EINVAL;
4218
4219 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4220 return -EINVAL;
4221
4222 /* Partial writes not supported */
4223 if ((eeprom->offset & 3) || (eeprom->len & 3))
4224 return -EINVAL;
4225
4226 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4227 }
4228
4229 static int sky2_set_flags(struct net_device *dev, u32 data)
4230 {
4231 struct sky2_port *sky2 = netdev_priv(dev);
4232 u32 supported =
4233 (sky2->hw->flags & SKY2_HW_RSS_BROKEN) ? 0 : ETH_FLAG_RXHASH;
4234 int rc;
4235
4236 rc = ethtool_op_set_flags(dev, data, supported);
4237 if (rc)
4238 return rc;
4239
4240 rx_set_rss(dev);
4241
4242 return 0;
4243 }
4244
4245 static const struct ethtool_ops sky2_ethtool_ops = {
4246 .get_settings = sky2_get_settings,
4247 .set_settings = sky2_set_settings,
4248 .get_drvinfo = sky2_get_drvinfo,
4249 .get_wol = sky2_get_wol,
4250 .set_wol = sky2_set_wol,
4251 .get_msglevel = sky2_get_msglevel,
4252 .set_msglevel = sky2_set_msglevel,
4253 .nway_reset = sky2_nway_reset,
4254 .get_regs_len = sky2_get_regs_len,
4255 .get_regs = sky2_get_regs,
4256 .get_link = ethtool_op_get_link,
4257 .get_eeprom_len = sky2_get_eeprom_len,
4258 .get_eeprom = sky2_get_eeprom,
4259 .set_eeprom = sky2_set_eeprom,
4260 .set_sg = ethtool_op_set_sg,
4261 .set_tx_csum = sky2_set_tx_csum,
4262 .set_tso = sky2_set_tso,
4263 .get_rx_csum = sky2_get_rx_csum,
4264 .set_rx_csum = sky2_set_rx_csum,
4265 .get_strings = sky2_get_strings,
4266 .get_coalesce = sky2_get_coalesce,
4267 .set_coalesce = sky2_set_coalesce,
4268 .get_ringparam = sky2_get_ringparam,
4269 .set_ringparam = sky2_set_ringparam,
4270 .get_pauseparam = sky2_get_pauseparam,
4271 .set_pauseparam = sky2_set_pauseparam,
4272 .phys_id = sky2_phys_id,
4273 .get_sset_count = sky2_get_sset_count,
4274 .get_ethtool_stats = sky2_get_ethtool_stats,
4275 .set_flags = sky2_set_flags,
4276 };
4277
4278 #ifdef CONFIG_SKY2_DEBUG
4279
4280 static struct dentry *sky2_debug;
4281
4282
4283 /*
4284 * Read and parse the first part of Vital Product Data
4285 */
4286 #define VPD_SIZE 128
4287 #define VPD_MAGIC 0x82
4288
4289 static const struct vpd_tag {
4290 char tag[2];
4291 char *label;
4292 } vpd_tags[] = {
4293 { "PN", "Part Number" },
4294 { "EC", "Engineering Level" },
4295 { "MN", "Manufacturer" },
4296 { "SN", "Serial Number" },
4297 { "YA", "Asset Tag" },
4298 { "VL", "First Error Log Message" },
4299 { "VF", "Second Error Log Message" },
4300 { "VB", "Boot Agent ROM Configuration" },
4301 { "VE", "EFI UNDI Configuration" },
4302 };
4303
4304 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4305 {
4306 size_t vpd_size;
4307 loff_t offs;
4308 u8 len;
4309 unsigned char *buf;
4310 u16 reg2;
4311
4312 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4313 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4314
4315 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4316 buf = kmalloc(vpd_size, GFP_KERNEL);
4317 if (!buf) {
4318 seq_puts(seq, "no memory!\n");
4319 return;
4320 }
4321
4322 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4323 seq_puts(seq, "VPD read failed\n");
4324 goto out;
4325 }
4326
4327 if (buf[0] != VPD_MAGIC) {
4328 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4329 goto out;
4330 }
4331 len = buf[1];
4332 if (len == 0 || len > vpd_size - 4) {
4333 seq_printf(seq, "Invalid id length: %d\n", len);
4334 goto out;
4335 }
4336
4337 seq_printf(seq, "%.*s\n", len, buf + 3);
4338 offs = len + 3;
4339
4340 while (offs < vpd_size - 4) {
4341 int i;
4342
4343 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4344 break;
4345 len = buf[offs + 2];
4346 if (offs + len + 3 >= vpd_size)
4347 break;
4348
4349 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4350 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4351 seq_printf(seq, " %s: %.*s\n",
4352 vpd_tags[i].label, len, buf + offs + 3);
4353 break;
4354 }
4355 }
4356 offs += len + 3;
4357 }
4358 out:
4359 kfree(buf);
4360 }
4361
4362 static int sky2_debug_show(struct seq_file *seq, void *v)
4363 {
4364 struct net_device *dev = seq->private;
4365 const struct sky2_port *sky2 = netdev_priv(dev);
4366 struct sky2_hw *hw = sky2->hw;
4367 unsigned port = sky2->port;
4368 unsigned idx, last;
4369 int sop;
4370
4371 sky2_show_vpd(seq, hw);
4372
4373 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4374 sky2_read32(hw, B0_ISRC),
4375 sky2_read32(hw, B0_IMSK),
4376 sky2_read32(hw, B0_Y2_SP_ICR));
4377
4378 if (!netif_running(dev)) {
4379 seq_printf(seq, "network not running\n");
4380 return 0;
4381 }
4382
4383 napi_disable(&hw->napi);
4384 last = sky2_read16(hw, STAT_PUT_IDX);
4385
4386 seq_printf(seq, "Status ring %u\n", hw->st_size);
4387 if (hw->st_idx == last)
4388 seq_puts(seq, "Status ring (empty)\n");
4389 else {
4390 seq_puts(seq, "Status ring\n");
4391 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4392 idx = RING_NEXT(idx, hw->st_size)) {
4393 const struct sky2_status_le *le = hw->st_le + idx;
4394 seq_printf(seq, "[%d] %#x %d %#x\n",
4395 idx, le->opcode, le->length, le->status);
4396 }
4397 seq_puts(seq, "\n");
4398 }
4399
4400 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4401 sky2->tx_cons, sky2->tx_prod,
4402 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4403 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4404
4405 /* Dump contents of tx ring */
4406 sop = 1;
4407 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4408 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4409 const struct sky2_tx_le *le = sky2->tx_le + idx;
4410 u32 a = le32_to_cpu(le->addr);
4411
4412 if (sop)
4413 seq_printf(seq, "%u:", idx);
4414 sop = 0;
4415
4416 switch (le->opcode & ~HW_OWNER) {
4417 case OP_ADDR64:
4418 seq_printf(seq, " %#x:", a);
4419 break;
4420 case OP_LRGLEN:
4421 seq_printf(seq, " mtu=%d", a);
4422 break;
4423 case OP_VLAN:
4424 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4425 break;
4426 case OP_TCPLISW:
4427 seq_printf(seq, " csum=%#x", a);
4428 break;
4429 case OP_LARGESEND:
4430 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4431 break;
4432 case OP_PACKET:
4433 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4434 break;
4435 case OP_BUFFER:
4436 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4437 break;
4438 default:
4439 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4440 a, le16_to_cpu(le->length));
4441 }
4442
4443 if (le->ctrl & EOP) {
4444 seq_putc(seq, '\n');
4445 sop = 1;
4446 }
4447 }
4448
4449 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4450 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4451 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4452 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4453
4454 sky2_read32(hw, B0_Y2_SP_LISR);
4455 napi_enable(&hw->napi);
4456 return 0;
4457 }
4458
4459 static int sky2_debug_open(struct inode *inode, struct file *file)
4460 {
4461 return single_open(file, sky2_debug_show, inode->i_private);
4462 }
4463
4464 static const struct file_operations sky2_debug_fops = {
4465 .owner = THIS_MODULE,
4466 .open = sky2_debug_open,
4467 .read = seq_read,
4468 .llseek = seq_lseek,
4469 .release = single_release,
4470 };
4471
4472 /*
4473 * Use network device events to create/remove/rename
4474 * debugfs file entries
4475 */
4476 static int sky2_device_event(struct notifier_block *unused,
4477 unsigned long event, void *ptr)
4478 {
4479 struct net_device *dev = ptr;
4480 struct sky2_port *sky2 = netdev_priv(dev);
4481
4482 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4483 return NOTIFY_DONE;
4484
4485 switch (event) {
4486 case NETDEV_CHANGENAME:
4487 if (sky2->debugfs) {
4488 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4489 sky2_debug, dev->name);
4490 }
4491 break;
4492
4493 case NETDEV_GOING_DOWN:
4494 if (sky2->debugfs) {
4495 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4496 debugfs_remove(sky2->debugfs);
4497 sky2->debugfs = NULL;
4498 }
4499 break;
4500
4501 case NETDEV_UP:
4502 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4503 sky2_debug, dev,
4504 &sky2_debug_fops);
4505 if (IS_ERR(sky2->debugfs))
4506 sky2->debugfs = NULL;
4507 }
4508
4509 return NOTIFY_DONE;
4510 }
4511
4512 static struct notifier_block sky2_notifier = {
4513 .notifier_call = sky2_device_event,
4514 };
4515
4516
4517 static __init void sky2_debug_init(void)
4518 {
4519 struct dentry *ent;
4520
4521 ent = debugfs_create_dir("sky2", NULL);
4522 if (!ent || IS_ERR(ent))
4523 return;
4524
4525 sky2_debug = ent;
4526 register_netdevice_notifier(&sky2_notifier);
4527 }
4528
4529 static __exit void sky2_debug_cleanup(void)
4530 {
4531 if (sky2_debug) {
4532 unregister_netdevice_notifier(&sky2_notifier);
4533 debugfs_remove(sky2_debug);
4534 sky2_debug = NULL;
4535 }
4536 }
4537
4538 #else
4539 #define sky2_debug_init()
4540 #define sky2_debug_cleanup()
4541 #endif
4542
4543 /* Two copies of network device operations to handle special case of
4544 not allowing netpoll on second port */
4545 static const struct net_device_ops sky2_netdev_ops[2] = {
4546 {
4547 .ndo_open = sky2_up,
4548 .ndo_stop = sky2_down,
4549 .ndo_start_xmit = sky2_xmit_frame,
4550 .ndo_do_ioctl = sky2_ioctl,
4551 .ndo_validate_addr = eth_validate_addr,
4552 .ndo_set_mac_address = sky2_set_mac_address,
4553 .ndo_set_multicast_list = sky2_set_multicast,
4554 .ndo_change_mtu = sky2_change_mtu,
4555 .ndo_tx_timeout = sky2_tx_timeout,
4556 .ndo_get_stats64 = sky2_get_stats,
4557 #ifdef SKY2_VLAN_TAG_USED
4558 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4559 #endif
4560 #ifdef CONFIG_NET_POLL_CONTROLLER
4561 .ndo_poll_controller = sky2_netpoll,
4562 #endif
4563 },
4564 {
4565 .ndo_open = sky2_up,
4566 .ndo_stop = sky2_down,
4567 .ndo_start_xmit = sky2_xmit_frame,
4568 .ndo_do_ioctl = sky2_ioctl,
4569 .ndo_validate_addr = eth_validate_addr,
4570 .ndo_set_mac_address = sky2_set_mac_address,
4571 .ndo_set_multicast_list = sky2_set_multicast,
4572 .ndo_change_mtu = sky2_change_mtu,
4573 .ndo_tx_timeout = sky2_tx_timeout,
4574 .ndo_get_stats64 = sky2_get_stats,
4575 #ifdef SKY2_VLAN_TAG_USED
4576 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4577 #endif
4578 },
4579 };
4580
4581 /* Initialize network device */
4582 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4583 unsigned port,
4584 int highmem, int wol)
4585 {
4586 struct sky2_port *sky2;
4587 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4588
4589 if (!dev) {
4590 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4591 return NULL;
4592 }
4593
4594 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4595 dev->irq = hw->pdev->irq;
4596 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4597 dev->watchdog_timeo = TX_WATCHDOG;
4598 dev->netdev_ops = &sky2_netdev_ops[port];
4599
4600 sky2 = netdev_priv(dev);
4601 sky2->netdev = dev;
4602 sky2->hw = hw;
4603 sky2->msg_enable = netif_msg_init(debug, default_msg);
4604
4605 /* Auto speed and flow control */
4606 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4607 if (hw->chip_id != CHIP_ID_YUKON_XL)
4608 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4609
4610 sky2->flow_mode = FC_BOTH;
4611
4612 sky2->duplex = -1;
4613 sky2->speed = -1;
4614 sky2->advertising = sky2_supported_modes(hw);
4615 sky2->wol = wol;
4616
4617 spin_lock_init(&sky2->phy_lock);
4618
4619 sky2->tx_pending = TX_DEF_PENDING;
4620 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4621 sky2->rx_pending = RX_DEF_PENDING;
4622
4623 hw->dev[port] = dev;
4624
4625 sky2->port = port;
4626
4627 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG
4628 | NETIF_F_TSO | NETIF_F_GRO;
4629 if (highmem)
4630 dev->features |= NETIF_F_HIGHDMA;
4631
4632 /* Enable receive hashing unless hardware is known broken */
4633 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4634 dev->features |= NETIF_F_RXHASH;
4635
4636 #ifdef SKY2_VLAN_TAG_USED
4637 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4638 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4639 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4640 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4641 }
4642 #endif
4643
4644 /* read the mac address */
4645 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4646 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4647
4648 return dev;
4649 }
4650
4651 static void __devinit sky2_show_addr(struct net_device *dev)
4652 {
4653 const struct sky2_port *sky2 = netdev_priv(dev);
4654
4655 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4656 }
4657
4658 /* Handle software interrupt used during MSI test */
4659 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4660 {
4661 struct sky2_hw *hw = dev_id;
4662 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4663
4664 if (status == 0)
4665 return IRQ_NONE;
4666
4667 if (status & Y2_IS_IRQ_SW) {
4668 hw->flags |= SKY2_HW_USE_MSI;
4669 wake_up(&hw->msi_wait);
4670 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4671 }
4672 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4673
4674 return IRQ_HANDLED;
4675 }
4676
4677 /* Test interrupt path by forcing a a software IRQ */
4678 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4679 {
4680 struct pci_dev *pdev = hw->pdev;
4681 int err;
4682
4683 init_waitqueue_head(&hw->msi_wait);
4684
4685 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4686
4687 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4688 if (err) {
4689 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4690 return err;
4691 }
4692
4693 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4694 sky2_read8(hw, B0_CTST);
4695
4696 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4697
4698 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4699 /* MSI test failed, go back to INTx mode */
4700 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4701 "switching to INTx mode.\n");
4702
4703 err = -EOPNOTSUPP;
4704 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4705 }
4706
4707 sky2_write32(hw, B0_IMSK, 0);
4708 sky2_read32(hw, B0_IMSK);
4709
4710 free_irq(pdev->irq, hw);
4711
4712 return err;
4713 }
4714
4715 /* This driver supports yukon2 chipset only */
4716 static const char *sky2_name(u8 chipid, char *buf, int sz)
4717 {
4718 const char *name[] = {
4719 "XL", /* 0xb3 */
4720 "EC Ultra", /* 0xb4 */
4721 "Extreme", /* 0xb5 */
4722 "EC", /* 0xb6 */
4723 "FE", /* 0xb7 */
4724 "FE+", /* 0xb8 */
4725 "Supreme", /* 0xb9 */
4726 "UL 2", /* 0xba */
4727 "Unknown", /* 0xbb */
4728 "Optima", /* 0xbc */
4729 };
4730
4731 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4732 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4733 else
4734 snprintf(buf, sz, "(chip %#x)", chipid);
4735 return buf;
4736 }
4737
4738 static int __devinit sky2_probe(struct pci_dev *pdev,
4739 const struct pci_device_id *ent)
4740 {
4741 struct net_device *dev;
4742 struct sky2_hw *hw;
4743 int err, using_dac = 0, wol_default;
4744 u32 reg;
4745 char buf1[16];
4746
4747 err = pci_enable_device(pdev);
4748 if (err) {
4749 dev_err(&pdev->dev, "cannot enable PCI device\n");
4750 goto err_out;
4751 }
4752
4753 /* Get configuration information
4754 * Note: only regular PCI config access once to test for HW issues
4755 * other PCI access through shared memory for speed and to
4756 * avoid MMCONFIG problems.
4757 */
4758 err = pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
4759 if (err) {
4760 dev_err(&pdev->dev, "PCI read config failed\n");
4761 goto err_out;
4762 }
4763
4764 if (~reg == 0) {
4765 dev_err(&pdev->dev, "PCI configuration read error\n");
4766 goto err_out;
4767 }
4768
4769 err = pci_request_regions(pdev, DRV_NAME);
4770 if (err) {
4771 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4772 goto err_out_disable;
4773 }
4774
4775 pci_set_master(pdev);
4776
4777 if (sizeof(dma_addr_t) > sizeof(u32) &&
4778 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4779 using_dac = 1;
4780 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4781 if (err < 0) {
4782 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4783 "for consistent allocations\n");
4784 goto err_out_free_regions;
4785 }
4786 } else {
4787 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4788 if (err) {
4789 dev_err(&pdev->dev, "no usable DMA configuration\n");
4790 goto err_out_free_regions;
4791 }
4792 }
4793
4794
4795 #ifdef __BIG_ENDIAN
4796 /* The sk98lin vendor driver uses hardware byte swapping but
4797 * this driver uses software swapping.
4798 */
4799 reg &= ~PCI_REV_DESC;
4800 err = pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
4801 if (err) {
4802 dev_err(&pdev->dev, "PCI write config failed\n");
4803 goto err_out_free_regions;
4804 }
4805 #endif
4806
4807 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4808
4809 err = -ENOMEM;
4810
4811 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4812 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4813 if (!hw) {
4814 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4815 goto err_out_free_regions;
4816 }
4817
4818 hw->pdev = pdev;
4819 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4820
4821 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4822 if (!hw->regs) {
4823 dev_err(&pdev->dev, "cannot map device registers\n");
4824 goto err_out_free_hw;
4825 }
4826
4827 err = sky2_init(hw);
4828 if (err)
4829 goto err_out_iounmap;
4830
4831 /* ring for status responses */
4832 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4833 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4834 &hw->st_dma);
4835 if (!hw->st_le)
4836 goto err_out_reset;
4837
4838 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4839 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4840
4841 sky2_reset(hw);
4842
4843 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4844 if (!dev) {
4845 err = -ENOMEM;
4846 goto err_out_free_pci;
4847 }
4848
4849 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4850 err = sky2_test_msi(hw);
4851 if (err == -EOPNOTSUPP)
4852 pci_disable_msi(pdev);
4853 else if (err)
4854 goto err_out_free_netdev;
4855 }
4856
4857 err = register_netdev(dev);
4858 if (err) {
4859 dev_err(&pdev->dev, "cannot register net device\n");
4860 goto err_out_free_netdev;
4861 }
4862
4863 netif_carrier_off(dev);
4864
4865 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4866
4867 err = request_irq(pdev->irq, sky2_intr,
4868 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4869 hw->irq_name, hw);
4870 if (err) {
4871 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4872 goto err_out_unregister;
4873 }
4874 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4875 napi_enable(&hw->napi);
4876
4877 sky2_show_addr(dev);
4878
4879 if (hw->ports > 1) {
4880 struct net_device *dev1;
4881
4882 err = -ENOMEM;
4883 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4884 if (dev1 && (err = register_netdev(dev1)) == 0)
4885 sky2_show_addr(dev1);
4886 else {
4887 dev_warn(&pdev->dev,
4888 "register of second port failed (%d)\n", err);
4889 hw->dev[1] = NULL;
4890 hw->ports = 1;
4891 if (dev1)
4892 free_netdev(dev1);
4893 }
4894 }
4895
4896 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4897 INIT_WORK(&hw->restart_work, sky2_restart);
4898
4899 pci_set_drvdata(pdev, hw);
4900 pdev->d3_delay = 150;
4901
4902 return 0;
4903
4904 err_out_unregister:
4905 if (hw->flags & SKY2_HW_USE_MSI)
4906 pci_disable_msi(pdev);
4907 unregister_netdev(dev);
4908 err_out_free_netdev:
4909 free_netdev(dev);
4910 err_out_free_pci:
4911 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4912 hw->st_le, hw->st_dma);
4913 err_out_reset:
4914 sky2_write8(hw, B0_CTST, CS_RST_SET);
4915 err_out_iounmap:
4916 iounmap(hw->regs);
4917 err_out_free_hw:
4918 kfree(hw);
4919 err_out_free_regions:
4920 pci_release_regions(pdev);
4921 err_out_disable:
4922 pci_disable_device(pdev);
4923 err_out:
4924 pci_set_drvdata(pdev, NULL);
4925 return err;
4926 }
4927
4928 static void __devexit sky2_remove(struct pci_dev *pdev)
4929 {
4930 struct sky2_hw *hw = pci_get_drvdata(pdev);
4931 int i;
4932
4933 if (!hw)
4934 return;
4935
4936 del_timer_sync(&hw->watchdog_timer);
4937 cancel_work_sync(&hw->restart_work);
4938
4939 for (i = hw->ports-1; i >= 0; --i)
4940 unregister_netdev(hw->dev[i]);
4941
4942 sky2_write32(hw, B0_IMSK, 0);
4943
4944 sky2_power_aux(hw);
4945
4946 sky2_write8(hw, B0_CTST, CS_RST_SET);
4947 sky2_read8(hw, B0_CTST);
4948
4949 free_irq(pdev->irq, hw);
4950 if (hw->flags & SKY2_HW_USE_MSI)
4951 pci_disable_msi(pdev);
4952 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4953 hw->st_le, hw->st_dma);
4954 pci_release_regions(pdev);
4955 pci_disable_device(pdev);
4956
4957 for (i = hw->ports-1; i >= 0; --i)
4958 free_netdev(hw->dev[i]);
4959
4960 iounmap(hw->regs);
4961 kfree(hw);
4962
4963 pci_set_drvdata(pdev, NULL);
4964 }
4965
4966 static int sky2_suspend(struct device *dev)
4967 {
4968 struct pci_dev *pdev = to_pci_dev(dev);
4969 struct sky2_hw *hw = pci_get_drvdata(pdev);
4970 int i;
4971
4972 if (!hw)
4973 return 0;
4974
4975 del_timer_sync(&hw->watchdog_timer);
4976 cancel_work_sync(&hw->restart_work);
4977
4978 rtnl_lock();
4979
4980 sky2_all_down(hw);
4981 for (i = 0; i < hw->ports; i++) {
4982 struct net_device *dev = hw->dev[i];
4983 struct sky2_port *sky2 = netdev_priv(dev);
4984
4985 if (sky2->wol)
4986 sky2_wol_init(sky2);
4987 }
4988
4989 sky2_power_aux(hw);
4990 rtnl_unlock();
4991
4992 return 0;
4993 }
4994
4995 #ifdef CONFIG_PM
4996 static int sky2_resume(struct device *dev)
4997 {
4998 struct pci_dev *pdev = to_pci_dev(dev);
4999 struct sky2_hw *hw = pci_get_drvdata(pdev);
5000 int err;
5001
5002 if (!hw)
5003 return 0;
5004
5005 /* Re-enable all clocks */
5006 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
5007 if (err) {
5008 dev_err(&pdev->dev, "PCI write config failed\n");
5009 goto out;
5010 }
5011
5012 rtnl_lock();
5013 sky2_reset(hw);
5014 sky2_all_up(hw);
5015 rtnl_unlock();
5016
5017 return 0;
5018 out:
5019
5020 dev_err(&pdev->dev, "resume failed (%d)\n", err);
5021 pci_disable_device(pdev);
5022 return err;
5023 }
5024
5025 static SIMPLE_DEV_PM_OPS(sky2_pm_ops, sky2_suspend, sky2_resume);
5026 #define SKY2_PM_OPS (&sky2_pm_ops)
5027
5028 #else
5029
5030 #define SKY2_PM_OPS NULL
5031 #endif
5032
5033 static void sky2_shutdown(struct pci_dev *pdev)
5034 {
5035 sky2_suspend(&pdev->dev);
5036 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
5037 pci_set_power_state(pdev, PCI_D3hot);
5038 }
5039
5040 static struct pci_driver sky2_driver = {
5041 .name = DRV_NAME,
5042 .id_table = sky2_id_table,
5043 .probe = sky2_probe,
5044 .remove = __devexit_p(sky2_remove),
5045 .shutdown = sky2_shutdown,
5046 .driver.pm = SKY2_PM_OPS,
5047 };
5048
5049 static int __init sky2_init_module(void)
5050 {
5051 pr_info("driver version " DRV_VERSION "\n");
5052
5053 sky2_debug_init();
5054 return pci_register_driver(&sky2_driver);
5055 }
5056
5057 static void __exit sky2_cleanup_module(void)
5058 {
5059 pci_unregister_driver(&sky2_driver);
5060 sky2_debug_cleanup();
5061 }
5062
5063 module_init(sky2_init_module);
5064 module_exit(sky2_cleanup_module);
5065
5066 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5067 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5068 MODULE_LICENSE("GPL");
5069 MODULE_VERSION(DRV_VERSION);
Linux 2.6 libata-dev (mirror)