drm/radeon/kms/atom: cleanup and unify DVO handling
[linux-2.6/libata-dev.git] / drivers / net / irda / bfin_sir.h
blobb54a6f08db45917ebf25890bf45040b7be5c4a2c
1 /*
2 * Blackfin Infra-red Driver
4 * Copyright 2006-2009 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
12 #include <linux/serial.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/delay.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
21 #include <net/irda/irda.h>
22 #include <net/irda/wrapper.h>
23 #include <net/irda/irda_device.h>
25 #include <asm/irq.h>
26 #include <asm/cacheflush.h>
27 #include <asm/dma.h>
28 #include <asm/portmux.h>
30 #ifdef CONFIG_SIR_BFIN_DMA
31 struct dma_rx_buf {
32 char *buf;
33 int head;
34 int tail;
36 #endif
38 struct bfin_sir_port {
39 unsigned char __iomem *membase;
40 unsigned int irq;
41 unsigned int lsr;
42 unsigned long clk;
43 struct net_device *dev;
44 #ifdef CONFIG_SIR_BFIN_DMA
45 int tx_done;
46 struct dma_rx_buf rx_dma_buf;
47 struct timer_list rx_dma_timer;
48 int rx_dma_nrows;
49 #endif
50 unsigned int tx_dma_channel;
51 unsigned int rx_dma_channel;
54 struct bfin_sir_port_res {
55 unsigned long base_addr;
56 int irq;
57 unsigned int rx_dma_channel;
58 unsigned int tx_dma_channel;
61 struct bfin_sir_self {
62 struct bfin_sir_port *sir_port;
63 spinlock_t lock;
64 unsigned int open;
65 int speed;
66 int newspeed;
68 struct sk_buff *txskb;
69 struct sk_buff *rxskb;
70 struct net_device_stats stats;
71 struct device *dev;
72 struct irlap_cb *irlap;
73 struct qos_info qos;
75 iobuff_t tx_buff;
76 iobuff_t rx_buff;
78 struct work_struct work;
79 int mtt;
82 #define DRIVER_NAME "bfin_sir"
84 #define SIR_UART_GET_CHAR(port) bfin_read16((port)->membase + OFFSET_RBR)
85 #define SIR_UART_GET_DLL(port) bfin_read16((port)->membase + OFFSET_DLL)
86 #define SIR_UART_GET_DLH(port) bfin_read16((port)->membase + OFFSET_DLH)
87 #define SIR_UART_GET_LCR(port) bfin_read16((port)->membase + OFFSET_LCR)
88 #define SIR_UART_GET_GCTL(port) bfin_read16((port)->membase + OFFSET_GCTL)
90 #define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
91 #define SIR_UART_PUT_DLL(port, v) bfin_write16(((port)->membase + OFFSET_DLL), v)
92 #define SIR_UART_PUT_DLH(port, v) bfin_write16(((port)->membase + OFFSET_DLH), v)
93 #define SIR_UART_PUT_LCR(port, v) bfin_write16(((port)->membase + OFFSET_LCR), v)
94 #define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
96 #ifdef CONFIG_BF54x
97 #define SIR_UART_GET_LSR(port) bfin_read16((port)->membase + OFFSET_LSR)
98 #define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER_SET)
99 #define SIR_UART_SET_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_SET), v)
100 #define SIR_UART_CLEAR_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
101 #define SIR_UART_PUT_LSR(port, v) bfin_write16(((port)->membase + OFFSET_LSR), v)
102 #define SIR_UART_CLEAR_LSR(port) bfin_write16(((port)->membase + OFFSET_LSR), -1)
104 #define SIR_UART_SET_DLAB(port)
105 #define SIR_UART_CLEAR_DLAB(port)
107 #define SIR_UART_ENABLE_INTS(port, v) SIR_UART_SET_IER(port, v)
108 #define SIR_UART_DISABLE_INTS(port) SIR_UART_CLEAR_IER(port, 0xF)
109 #define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_LSR(port, TFI); SIR_UART_CLEAR_IER(port, ETBEI); } while (0)
110 #define SIR_UART_ENABLE_TX(port) do { SIR_UART_SET_IER(port, ETBEI); } while (0)
111 #define SIR_UART_STOP_RX(port) do { SIR_UART_CLEAR_IER(port, ERBFI); } while (0)
112 #define SIR_UART_ENABLE_RX(port) do { SIR_UART_SET_IER(port, ERBFI); } while (0)
113 #else
115 #define SIR_UART_GET_IIR(port) bfin_read16((port)->membase + OFFSET_IIR)
116 #define SIR_UART_GET_IER(port) bfin_read16((port)->membase + OFFSET_IER)
117 #define SIR_UART_PUT_IER(port, v) bfin_write16(((port)->membase + OFFSET_IER), v)
119 #define SIR_UART_SET_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) | DLAB); } while (0)
120 #define SIR_UART_CLEAR_DLAB(port) do { SIR_UART_PUT_LCR(port, SIR_UART_GET_LCR(port) & ~DLAB); } while (0)
122 #define SIR_UART_ENABLE_INTS(port, v) SIR_UART_PUT_IER(port, v)
123 #define SIR_UART_DISABLE_INTS(port) SIR_UART_PUT_IER(port, 0)
124 #define SIR_UART_STOP_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ETBEI); } while (0)
125 #define SIR_UART_ENABLE_TX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ETBEI); } while (0)
126 #define SIR_UART_STOP_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) & ~ERBFI); } while (0)
127 #define SIR_UART_ENABLE_RX(port) do { SIR_UART_PUT_IER(port, SIR_UART_GET_IER(port) | ERBFI); } while (0)
129 static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
131 unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
132 port->lsr |= (lsr & (BI|FE|PE|OE));
133 return lsr | port->lsr;
136 static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
138 port->lsr = 0;
139 bfin_read16(port->membase + OFFSET_LSR);
141 #endif
143 static const unsigned short per[][4] = {
144 /* rx pin tx pin NULL uart_number */
145 {P_UART0_RX, P_UART0_TX, 0, 0},
146 {P_UART1_RX, P_UART1_TX, 0, 1},
147 {P_UART2_RX, P_UART2_TX, 0, 2},
148 {P_UART3_RX, P_UART3_TX, 0, 3},