arch/mips/pmc-sierra/yosemite/smp.c

   1 #include <linux/linkage.h>
   2 #include <linux/sched.h>
   3
   4 #include <asm/pmon.h>
   5 #include <asm/titan_dep.h>
   6
   7 extern unsigned int (*mips_hpt_read)(void);
   8 extern void (*mips_hpt_init)(unsigned int);
   9
  10 #define LAUNCHSTACK_SIZE 256
  11
  12 static __initdata DEFINE_SPINLOCK(launch_lock);
  13
  14 static unsigned long secondary_sp __initdata;
  15 static unsigned long secondary_gp __initdata;
  16
  17 static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
  18         __attribute__((aligned(2 * sizeof(long))));
  19
  20 static void __init prom_smp_bootstrap(void)
  21 {
  22         local_irq_disable();
  23
  24         while (spin_is_locked(&launch_lock));
  25
  26         __asm__ __volatile__(
  27         "       move    $sp, %0         \n"
  28         "       move    $gp, %1         \n"
  29         "       j       smp_bootstrap   \n"
  30         :
  31         : "r" (secondary_sp), "r" (secondary_gp));
  32 }
  33
  34 /*
  35  * PMON is a fragile beast.  It'll blow up once the mappings it's littering
  36  * right into the middle of KSEG3 are blown away so we have to grab the slave
  37  * core early and keep it in a waiting loop.
  38  */
  39 void __init prom_grab_secondary(void)
  40 {
  41         spin_lock(&launch_lock);
  42
  43         pmon_cpustart(1, &prom_smp_bootstrap,
  44                       launchstack + LAUNCHSTACK_SIZE, 0);
  45 }
  46
  47 /*
  48  * Detect available CPUs, populate phys_cpu_present_map before smp_init
  49  *
  50  * We don't want to start the secondary CPU yet nor do we have a nice probing
  51  * feature in PMON so we just assume presence of the secondary core.
  52  */
  53 void __init plat_smp_setup(void)
  54 {
  55         int i;
  56
  57         cpus_clear(phys_cpu_present_map);
  58
  59         for (i = 0; i < 2; i++) {
  60                 cpu_set(i, phys_cpu_present_map);
  61                 __cpu_number_map[i]     = i;
  62                 __cpu_logical_map[i]    = i;
  63         }
  64 }
  65
  66 void __init plat_prepare_cpus(unsigned int max_cpus)
  67 {
  68         /*
  69          * Be paranoid.  Enable the IPI only if we're really about to go SMP.
  70          */
  71         if (cpus_weight(cpu_possible_map))
  72                 set_c0_status(STATUSF_IP5);
  73 }
  74
  75 /*
  76  * Firmware CPU startup hook
  77  * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
  78  * It launches the next * available CPU and copies some information on the
  79  * stack so the first thing we do is throw away that stuff and load useful
  80  * values into the registers ...
  81  */
  82 void prom_boot_secondary(int cpu, struct task_struct *idle)
  83 {
  84         unsigned long gp = (unsigned long) task_thread_info(idle);
  85         unsigned long sp = __KSTK_TOS(idle);
  86
  87         secondary_sp = sp;
  88         secondary_gp = gp;
  89
  90         spin_unlock(&launch_lock);
  91 }
  92
  93 /* Hook for after all CPUs are online */
  94 void prom_cpus_done(void)
  95 {
  96 }
  97
  98 /*
  99  *  After we've done initial boot, this function is called to allow the
 100  *  board code to clean up state, if needed
 101  */
 102 void prom_init_secondary(void)
 103 {
 104         mips_hpt_init(mips_hpt_read());
 105
 106         set_c0_status(ST0_CO | ST0_IE | ST0_IM);
 107 }
 108
 109 void prom_smp_finish(void)
 110 {
 111 }
 112
 113 asmlinkage void titan_mailbox_irq(void)
 114 {
 115         int cpu = smp_processor_id();
 116         unsigned long status;
 117
 118         if (cpu == 0) {
 119                 status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
 120                 OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
 121         }
 122
 123         if (cpu == 1) {
 124                 status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
 125                 OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
 126         }
 127
 128         if (status & 0x2)
 129                 smp_call_function_interrupt();
 130 }
 131
 132 /*
 133  * Send inter-processor interrupt
 134  */
 135 void core_send_ipi(int cpu, unsigned int action)
 136 {
 137         /*
 138          * Generate an INTMSG so that it can be sent over to the
 139          * destination CPU. The INTMSG will put the STATUS bits
 140          * based on the action desired. An alternative strategy
 141          * is to write to the Interrupt Set register, read the
 142          * Interrupt Status register and clear the Interrupt
 143          * Clear register. The latter is preffered.
 144          */
 145         switch (action) {
 146         case SMP_RESCHEDULE_YOURSELF:
 147                 if (cpu == 1)
 148                         OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
 149                 else
 150                         OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
 151                 break;
 152
 153         case SMP_CALL_FUNCTION:
 154                 if (cpu == 1)
 155                         OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
 156                 else
 157                         OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
 158                 break;
 159         }
 160 }