arch/sparc/kernel/sun4m_smp.c

   1 /* sun4m_smp.c: Sparc SUN4M SMP support.
   2  *
   3  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5
   6 #include <asm/head.h>
   7
   8 #include <linux/kernel.h>
   9 #include <linux/sched.h>
  10 #include <linux/threads.h>
  11 #include <linux/smp.h>
  12 #include <linux/smp_lock.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/init.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/mm.h>
  18 #include <linux/swap.h>
  19 #include <linux/profile.h>
  20 #include <asm/cacheflush.h>
  21 #include <asm/tlbflush.h>
  22
  23 #include <asm/ptrace.h>
  24 #include <asm/atomic.h>
  25
  26 #include <asm/delay.h>
  27 #include <asm/irq.h>
  28 #include <asm/page.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/oplib.h>
  32 #include <asm/cpudata.h>
  33
  34 #define IRQ_RESCHEDULE          13
  35 #define IRQ_STOP_CPU            14
  36 #define IRQ_CROSS_CALL          15
  37
  38 extern ctxd_t *srmmu_ctx_table_phys;
  39
  40 extern void calibrate_delay(void);
  41
  42 extern volatile int smp_processors_ready;
  43 extern volatile unsigned long cpu_callin_map[NR_CPUS];
  44 extern unsigned char boot_cpu_id;
  45
  46 extern cpumask_t smp_commenced_mask;
  47
  48 extern int __smp4m_processor_id(void);
  49
  50 /*#define SMP_DEBUG*/
  51
  52 #ifdef SMP_DEBUG
  53 #define SMP_PRINTK(x)   printk x
  54 #else
  55 #define SMP_PRINTK(x)
  56 #endif
  57
  58 static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val)
  59 {
  60         __asm__ __volatile__("swap [%1], %0\n\t" :
  61                              "=&r" (val), "=&r" (ptr) :
  62                              "0" (val), "1" (ptr));
  63         return val;
  64 }
  65
  66 static void smp_setup_percpu_timer(void);
  67 extern void cpu_probe(void);
  68
  69 void __cpuinit smp4m_callin(void)
  70 {
  71         int cpuid = hard_smp_processor_id();
  72
  73         local_flush_cache_all();
  74         local_flush_tlb_all();
  75
  76         /* Get our local ticker going. */
  77         smp_setup_percpu_timer();
  78
  79         calibrate_delay();
  80         smp_store_cpu_info(cpuid);
  81
  82         local_flush_cache_all();
  83         local_flush_tlb_all();
  84
  85         /*
  86          * Unblock the master CPU _only_ when the scheduler state
  87          * of all secondary CPUs will be up-to-date, so after
  88          * the SMP initialization the master will be just allowed
  89          * to call the scheduler code.
  90          */
  91         /* Allow master to continue. */
  92         swap(&cpu_callin_map[cpuid], 1);
  93
  94         /* XXX: What's up with all the flushes? */
  95         local_flush_cache_all();
  96         local_flush_tlb_all();
  97
  98         cpu_probe();
  99
 100         /* Fix idle thread fields. */
 101         __asm__ __volatile__("ld [%0], %%g6\n\t"
 102                              : : "r" (&current_set[cpuid])
 103                              : "memory" /* paranoid */);
 104
 105         /* Attach to the address space of init_task. */
 106         atomic_inc(&init_mm.mm_count);
 107         current->active_mm = &init_mm;
 108
 109         while (!cpu_isset(cpuid, smp_commenced_mask))
 110                 mb();
 111
 112         local_irq_enable();
 113
 114         cpu_set(cpuid, cpu_online_map);
 115 }
 116
 117 /*
 118  *      Cycle through the processors asking the PROM to start each one.
 119  */
 120
 121 extern struct linux_prom_registers smp_penguin_ctable;
 122 extern unsigned long trapbase_cpu1[];
 123 extern unsigned long trapbase_cpu2[];
 124 extern unsigned long trapbase_cpu3[];
 125
 126 void __init smp4m_boot_cpus(void)
 127 {
 128         smp_setup_percpu_timer();
 129         local_flush_cache_all();
 130 }
 131
 132 int __cpuinit smp4m_boot_one_cpu(int i)
 133 {
 134         extern unsigned long sun4m_cpu_startup;
 135         unsigned long *entry = &sun4m_cpu_startup;
 136         struct task_struct *p;
 137         int timeout;
 138         int cpu_node;
 139
 140         cpu_find_by_mid(i, &cpu_node);
 141
 142         /* Cook up an idler for this guy. */
 143         p = fork_idle(i);
 144         current_set[i] = task_thread_info(p);
 145         /* See trampoline.S for details... */
 146         entry += ((i-1) * 3);
 147
 148         /*
 149          * Initialize the contexts table
 150          * Since the call to prom_startcpu() trashes the structure,
 151          * we need to re-initialize it for each cpu
 152          */
 153         smp_penguin_ctable.which_io = 0;
 154         smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
 155         smp_penguin_ctable.reg_size = 0;
 156
 157         /* whirrr, whirrr, whirrrrrrrrr... */
 158         printk("Starting CPU %d at %p\n", i, entry);
 159         local_flush_cache_all();
 160         prom_startcpu(cpu_node,
 161                       &smp_penguin_ctable, 0, (char *)entry);
 162
 163         /* wheee... it's going... */
 164         for(timeout = 0; timeout < 10000; timeout++) {
 165                 if(cpu_callin_map[i])
 166                         break;
 167                 udelay(200);
 168         }
 169
 170         if (!(cpu_callin_map[i])) {
 171                 printk("Processor %d is stuck.\n", i);
 172                 return -ENODEV;
 173         }
 174
 175         local_flush_cache_all();
 176         return 0;
 177 }
 178
 179 void __init smp4m_smp_done(void)
 180 {
 181         int i, first;
 182         int *prev;
 183
 184         /* setup cpu list for irq rotation */
 185         first = 0;
 186         prev = &first;
 187         for (i = 0; i < NR_CPUS; i++) {
 188                 if (cpu_online(i)) {
 189                         *prev = i;
 190                         prev = &cpu_data(i).next;
 191                 }
 192         }
 193         *prev = first;
 194         local_flush_cache_all();
 195
 196         /* Free unneeded trap tables */
 197         if (!cpu_isset(1, cpu_present_map)) {
 198                 ClearPageReserved(virt_to_page(trapbase_cpu1));
 199                 init_page_count(virt_to_page(trapbase_cpu1));
 200                 free_page((unsigned long)trapbase_cpu1);
 201                 totalram_pages++;
 202                 num_physpages++;
 203         }
 204         if (!cpu_isset(2, cpu_present_map)) {
 205                 ClearPageReserved(virt_to_page(trapbase_cpu2));
 206                 init_page_count(virt_to_page(trapbase_cpu2));
 207                 free_page((unsigned long)trapbase_cpu2);
 208                 totalram_pages++;
 209                 num_physpages++;
 210         }
 211         if (!cpu_isset(3, cpu_present_map)) {
 212                 ClearPageReserved(virt_to_page(trapbase_cpu3));
 213                 init_page_count(virt_to_page(trapbase_cpu3));
 214                 free_page((unsigned long)trapbase_cpu3);
 215                 totalram_pages++;
 216                 num_physpages++;
 217         }
 218
 219         /* Ok, they are spinning and ready to go. */
 220         smp_processors_ready = 1;
 221 }
 222
 223 /* At each hardware IRQ, we get this called to forward IRQ reception
 224  * to the next processor.  The caller must disable the IRQ level being
 225  * serviced globally so that there are no double interrupts received.
 226  *
 227  * XXX See sparc64 irq.c.
 228  */
 229 void smp4m_irq_rotate(int cpu)
 230 {
 231         int next = cpu_data(cpu).next;
 232         if (next != cpu)
 233                 set_irq_udt(next);
 234 }
 235
 236 /* Cross calls, in order to work efficiently and atomically do all
 237  * the message passing work themselves, only stopcpu and reschedule
 238  * messages come through here.
 239  */
 240 void smp4m_message_pass(int target, int msg, unsigned long data, int wait)
 241 {
 242         static unsigned long smp_cpu_in_msg[NR_CPUS];
 243         cpumask_t mask;
 244         int me = smp_processor_id();
 245         int irq, i;
 246
 247         if(msg == MSG_RESCHEDULE) {
 248                 irq = IRQ_RESCHEDULE;
 249
 250                 if(smp_cpu_in_msg[me])
 251                         return;
 252         } else if(msg == MSG_STOP_CPU) {
 253                 irq = IRQ_STOP_CPU;
 254         } else {
 255                 goto barf;
 256         }
 257
 258         smp_cpu_in_msg[me]++;
 259         if(target == MSG_ALL_BUT_SELF || target == MSG_ALL) {
 260                 mask = cpu_online_map;
 261                 if(target == MSG_ALL_BUT_SELF)
 262                         cpu_clear(me, mask);
 263                 for(i = 0; i < 4; i++) {
 264                         if (cpu_isset(i, mask))
 265                                 set_cpu_int(i, irq);
 266                 }
 267         } else {
 268                 set_cpu_int(target, irq);
 269         }
 270         smp_cpu_in_msg[me]--;
 271
 272         return;
 273 barf:
 274         printk("Yeeee, trying to send SMP msg(%d) on cpu %d\n", msg, me);
 275         panic("Bogon SMP message pass.");
 276 }
 277
 278 static struct smp_funcall {
 279         smpfunc_t func;
 280         unsigned long arg1;
 281         unsigned long arg2;
 282         unsigned long arg3;
 283         unsigned long arg4;
 284         unsigned long arg5;
 285         unsigned long processors_in[SUN4M_NCPUS];  /* Set when ipi entered. */
 286         unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */
 287 } ccall_info;
 288
 289 static DEFINE_SPINLOCK(cross_call_lock);
 290
 291 /* Cross calls must be serialized, at least currently. */
 292 void smp4m_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2,
 293                     unsigned long arg3, unsigned long arg4, unsigned long arg5)
 294 {
 295                 register int ncpus = SUN4M_NCPUS;
 296                 unsigned long flags;
 297
 298                 spin_lock_irqsave(&cross_call_lock, flags);
 299
 300                 /* Init function glue. */
 301                 ccall_info.func = func;
 302                 ccall_info.arg1 = arg1;
 303                 ccall_info.arg2 = arg2;
 304                 ccall_info.arg3 = arg3;
 305                 ccall_info.arg4 = arg4;
 306                 ccall_info.arg5 = arg5;
 307
 308                 /* Init receive/complete mapping, plus fire the IPI's off. */
 309                 {
 310                         cpumask_t mask = cpu_online_map;
 311                         register int i;
 312
 313                         cpu_clear(smp_processor_id(), mask);
 314                         for(i = 0; i < ncpus; i++) {
 315                                 if (cpu_isset(i, mask)) {
 316                                         ccall_info.processors_in[i] = 0;
 317                                         ccall_info.processors_out[i] = 0;
 318                                         set_cpu_int(i, IRQ_CROSS_CALL);
 319                                 } else {
 320                                         ccall_info.processors_in[i] = 1;
 321                                         ccall_info.processors_out[i] = 1;
 322                                 }
 323                         }
 324                 }
 325
 326                 {
 327                         register int i;
 328
 329                         i = 0;
 330                         do {
 331                                 while(!ccall_info.processors_in[i])
 332                                         barrier();
 333                         } while(++i < ncpus);
 334
 335                         i = 0;
 336                         do {
 337                                 while(!ccall_info.processors_out[i])
 338                                         barrier();
 339                         } while(++i < ncpus);
 340                 }
 341
 342                 spin_unlock_irqrestore(&cross_call_lock, flags);
 343 }
 344
 345 /* Running cross calls. */
 346 void smp4m_cross_call_irq(void)
 347 {
 348         int i = smp_processor_id();
 349
 350         ccall_info.processors_in[i] = 1;
 351         ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3,
 352                         ccall_info.arg4, ccall_info.arg5);
 353         ccall_info.processors_out[i] = 1;
 354 }
 355
 356 void smp4m_percpu_timer_interrupt(struct pt_regs *regs)
 357 {
 358         int cpu = smp_processor_id();
 359
 360         clear_profile_irq(cpu);
 361
 362         profile_tick(CPU_PROFILING, regs);
 363
 364         if(!--prof_counter(cpu)) {
 365                 int user = user_mode(regs);
 366
 367                 irq_enter();
 368                 update_process_times(user);
 369                 irq_exit();
 370
 371                 prof_counter(cpu) = prof_multiplier(cpu);
 372         }
 373 }
 374
 375 extern unsigned int lvl14_resolution;
 376
 377 static void __init smp_setup_percpu_timer(void)
 378 {
 379         int cpu = smp_processor_id();
 380
 381         prof_counter(cpu) = prof_multiplier(cpu) = 1;
 382         load_profile_irq(cpu, lvl14_resolution);
 383
 384         if(cpu == boot_cpu_id)
 385                 enable_pil_irq(14);
 386 }
 387
 388 void __init smp4m_blackbox_id(unsigned *addr)
 389 {
 390         int rd = *addr & 0x3e000000;
 391         int rs1 = rd >> 11;
 392
 393         addr[0] = 0x81580000 | rd;              /* rd %tbr, reg */
 394         addr[1] = 0x8130200c | rd | rs1;        /* srl reg, 0xc, reg */
 395         addr[2] = 0x80082003 | rd | rs1;        /* and reg, 3, reg */
 396 }
 397
 398 void __init smp4m_blackbox_current(unsigned *addr)
 399 {
 400         int rd = *addr & 0x3e000000;
 401         int rs1 = rd >> 11;
 402
 403         addr[0] = 0x81580000 | rd;              /* rd %tbr, reg */
 404         addr[2] = 0x8130200a | rd | rs1;        /* srl reg, 0xa, reg */
 405         addr[4] = 0x8008200c | rd | rs1;        /* and reg, 3, reg */
 406 }
 407
 408 void __init sun4m_init_smp(void)
 409 {
 410         BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4m_blackbox_id);
 411         BTFIXUPSET_BLACKBOX(load_current, smp4m_blackbox_current);
 412         BTFIXUPSET_CALL(smp_cross_call, smp4m_cross_call, BTFIXUPCALL_NORM);
 413         BTFIXUPSET_CALL(smp_message_pass, smp4m_message_pass, BTFIXUPCALL_NORM);
 414         BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4m_processor_id, BTFIXUPCALL_NORM);
 415 }