drivers/net/benet/be.h

   1 /*
   2  * Copyright (C) 2005 - 2010 ServerEngines
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@serverengines.com
  12  *
  13  * ServerEngines
  14  * 209 N. Fair Oaks Ave
  15  * Sunnyvale, CA 94085
  16  */
  17
  18 #ifndef BE_H
  19 #define BE_H
  20
  21 #include <linux/pci.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/version.h>
  24 #include <linux/delay.h>
  25 #include <net/tcp.h>
  26 #include <net/ip.h>
  27 #include <net/ipv6.h>
  28 #include <linux/if_vlan.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/firmware.h>
  32
  33 #include "be_hw.h"
  34
  35 #define DRV_VER                 "2.101.346u"
  36 #define DRV_NAME                "be2net"
  37 #define BE_NAME                 "ServerEngines BladeEngine2 10Gbps NIC"
  38 #define BE3_NAME                "ServerEngines BladeEngine3 10Gbps NIC"
  39 #define OC_NAME                 "Emulex OneConnect 10Gbps NIC"
  40 #define OC_NAME1                "Emulex OneConnect 10Gbps NIC (be3)"
  41 #define DRV_DESC                "ServerEngines BladeEngine 10Gbps NIC Driver"
  42
  43 #define BE_VENDOR_ID            0x19a2
  44 #define BE_DEVICE_ID1           0x211
  45 #define BE_DEVICE_ID2           0x221
  46 #define OC_DEVICE_ID1           0x700
  47 #define OC_DEVICE_ID2           0x710
  48
  49 static inline char *nic_name(struct pci_dev *pdev)
  50 {
  51         switch (pdev->device) {
  52         case OC_DEVICE_ID1:
  53                 return OC_NAME;
  54         case OC_DEVICE_ID2:
  55                 return OC_NAME1;
  56         case BE_DEVICE_ID2:
  57                 return BE3_NAME;
  58         default:
  59                 return BE_NAME;
  60         }
  61 }
  62
  63 /* Number of bytes of an RX frame that are copied to skb->data */
  64 #define BE_HDR_LEN              64
  65 #define BE_MAX_JUMBO_FRAME_SIZE 9018
  66 #define BE_MIN_MTU              256
  67
  68 #define BE_NUM_VLANS_SUPPORTED  64
  69 #define BE_MAX_EQD              96
  70 #define BE_MAX_TX_FRAG_COUNT    30
  71
  72 #define EVNT_Q_LEN              1024
  73 #define TX_Q_LEN                2048
  74 #define TX_CQ_LEN               1024
  75 #define RX_Q_LEN                1024    /* Does not support any other value */
  76 #define RX_CQ_LEN               1024
  77 #define MCC_Q_LEN               128     /* total size not to exceed 8 pages */
  78 #define MCC_CQ_LEN              256
  79
  80 #define BE_NAPI_WEIGHT          64
  81 #define MAX_RX_POST             BE_NAPI_WEIGHT /* Frags posted at a time */
  82 #define RX_FRAGS_REFILL_WM      (RX_Q_LEN - MAX_RX_POST)
  83
  84 #define FW_VER_LEN              32
  85
  86 struct be_dma_mem {
  87         void *va;
  88         dma_addr_t dma;
  89         u32 size;
  90 };
  91
  92 struct be_queue_info {
  93         struct be_dma_mem dma_mem;
  94         u16 len;
  95         u16 entry_size; /* Size of an element in the queue */
  96         u16 id;
  97         u16 tail, head;
  98         bool created;
  99         atomic_t used;  /* Number of valid elements in the queue */
 100 };
 101
 102 static inline u32 MODULO(u16 val, u16 limit)
 103 {
 104         BUG_ON(limit & (limit - 1));
 105         return val & (limit - 1);
 106 }
 107
 108 static inline void index_adv(u16 *index, u16 val, u16 limit)
 109 {
 110         *index = MODULO((*index + val), limit);
 111 }
 112
 113 static inline void index_inc(u16 *index, u16 limit)
 114 {
 115         *index = MODULO((*index + 1), limit);
 116 }
 117
 118 static inline void *queue_head_node(struct be_queue_info *q)
 119 {
 120         return q->dma_mem.va + q->head * q->entry_size;
 121 }
 122
 123 static inline void *queue_tail_node(struct be_queue_info *q)
 124 {
 125         return q->dma_mem.va + q->tail * q->entry_size;
 126 }
 127
 128 static inline void queue_head_inc(struct be_queue_info *q)
 129 {
 130         index_inc(&q->head, q->len);
 131 }
 132
 133 static inline void queue_tail_inc(struct be_queue_info *q)
 134 {
 135         index_inc(&q->tail, q->len);
 136 }
 137
 138 struct be_eq_obj {
 139         struct be_queue_info q;
 140         char desc[32];
 141
 142         /* Adaptive interrupt coalescing (AIC) info */
 143         bool enable_aic;
 144         u16 min_eqd;            /* in usecs */
 145         u16 max_eqd;            /* in usecs */
 146         u16 cur_eqd;            /* in usecs */
 147
 148         struct napi_struct napi;
 149 };
 150
 151 struct be_mcc_obj {
 152         struct be_queue_info q;
 153         struct be_queue_info cq;
 154         bool rearm_cq;
 155 };
 156
 157 struct be_drvr_stats {
 158         u32 be_tx_reqs;         /* number of TX requests initiated */
 159         u32 be_tx_stops;        /* number of times TX Q was stopped */
 160         u32 be_fwd_reqs;        /* number of send reqs through forwarding i/f */
 161         u32 be_tx_wrbs;         /* number of tx WRBs used */
 162         u32 be_tx_events;       /* number of tx completion events  */
 163         u32 be_tx_compl;        /* number of tx completion entries processed */
 164         ulong be_tx_jiffies;
 165         u64 be_tx_bytes;
 166         u64 be_tx_bytes_prev;
 167         u64 be_tx_pkts;
 168         u32 be_tx_rate;
 169
 170         u32 cache_barrier[16];
 171
 172         u32 be_ethrx_post_fail;/* number of ethrx buffer alloc failures */
 173         u32 be_rx_polls;        /* number of times NAPI called poll function */
 174         u32 be_rx_events;       /* number of ucast rx completion events  */
 175         u32 be_rx_compl;        /* number of rx completion entries processed */
 176         ulong be_rx_jiffies;
 177         u64 be_rx_bytes;
 178         u64 be_rx_bytes_prev;
 179         u64 be_rx_pkts;
 180         u32 be_rx_rate;
 181         /* number of non ether type II frames dropped where
 182          * frame len > length field of Mac Hdr */
 183         u32 be_802_3_dropped_frames;
 184         /* number of non ether type II frames malformed where
 185          * in frame len < length field of Mac Hdr */
 186         u32 be_802_3_malformed_frames;
 187         u32 be_rxcp_err;        /* Num rx completion entries w/ err set. */
 188         ulong rx_fps_jiffies;   /* jiffies at last FPS calc */
 189         u32 be_rx_frags;
 190         u32 be_prev_rx_frags;
 191         u32 be_rx_fps;          /* Rx frags per second */
 192 };
 193
 194 struct be_stats_obj {
 195         struct be_drvr_stats drvr_stats;
 196         struct be_dma_mem cmd;
 197 };
 198
 199 struct be_tx_obj {
 200         struct be_queue_info q;
 201         struct be_queue_info cq;
 202         /* Remember the skbs that were transmitted */
 203         struct sk_buff *sent_skb_list[TX_Q_LEN];
 204 };
 205
 206 /* Struct to remember the pages posted for rx frags */
 207 struct be_rx_page_info {
 208         struct page *page;
 209         dma_addr_t bus;
 210         u16 page_offset;
 211         bool last_page_user;
 212 };
 213
 214 struct be_rx_obj {
 215         struct be_queue_info q;
 216         struct be_queue_info cq;
 217         struct be_rx_page_info page_info_tbl[RX_Q_LEN];
 218 };
 219
 220 #define BE_NUM_MSIX_VECTORS             2       /* 1 each for Tx and Rx */
 221 struct be_adapter {
 222         struct pci_dev *pdev;
 223         struct net_device *netdev;
 224
 225         u8 __iomem *csr;
 226         u8 __iomem *db;         /* Door Bell */
 227         u8 __iomem *pcicfg;     /* PCI config space */
 228
 229         spinlock_t mbox_lock;   /* For serializing mbox cmds to BE card */
 230         struct be_dma_mem mbox_mem;
 231         /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
 232          * is stored for freeing purpose */
 233         struct be_dma_mem mbox_mem_alloced;
 234
 235         struct be_mcc_obj mcc_obj;
 236         spinlock_t mcc_lock;    /* For serializing mcc cmds to BE card */
 237         spinlock_t mcc_cq_lock;
 238
 239         struct msix_entry msix_entries[BE_NUM_MSIX_VECTORS];
 240         bool msix_enabled;
 241         bool isr_registered;
 242
 243         /* TX Rings */
 244         struct be_eq_obj tx_eq;
 245         struct be_tx_obj tx_obj;
 246
 247         u32 cache_line_break[8];
 248
 249         /* Rx rings */
 250         struct be_eq_obj rx_eq;
 251         struct be_rx_obj rx_obj;
 252         u32 big_page_size;      /* Compounded page size shared by rx wrbs */
 253         bool rx_post_starved;   /* Zero rx frags have been posted to BE */
 254
 255         struct vlan_group *vlan_grp;
 256         u16 vlans_added;
 257         u16 max_vlans;  /* Number of vlans supported */
 258         u8 vlan_tag[VLAN_GROUP_ARRAY_LEN];
 259         struct be_dma_mem mc_cmd_mem;
 260
 261         struct be_stats_obj stats;
 262         /* Work queue used to perform periodic tasks like getting statistics */
 263         struct delayed_work work;
 264
 265         /* Ethtool knobs and info */
 266         bool rx_csum;           /* BE card must perform rx-checksumming */
 267         char fw_ver[FW_VER_LEN];
 268         u32 if_handle;          /* Used to configure filtering */
 269         u32 pmac_id;            /* MAC addr handle used by BE card */
 270
 271         bool eeh_err;
 272         bool link_up;
 273         u32 port_num;
 274         bool promiscuous;
 275         bool wol;
 276         u32 cap;
 277         u32 rx_fc;              /* Rx flow control */
 278         u32 tx_fc;              /* Tx flow control */
 279         int link_speed;
 280         u8 port_type;
 281         u8 transceiver;
 282         u8 generation;          /* BladeEngine ASIC generation */
 283 };
 284
 285 /* BladeEngine Generation numbers */
 286 #define BE_GEN2 2
 287 #define BE_GEN3 3
 288
 289 extern const struct ethtool_ops be_ethtool_ops;
 290
 291 #define drvr_stats(adapter)             (&adapter->stats.drvr_stats)
 292
 293 static inline unsigned int be_pci_func(struct be_adapter *adapter)
 294 {
 295         return PCI_FUNC(adapter->pdev->devfn);
 296 }
 297
 298 #define BE_SET_NETDEV_OPS(netdev, ops)  (netdev->netdev_ops = ops)
 299
 300 #define PAGE_SHIFT_4K           12
 301 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 302
 303 /* Returns number of pages spanned by the data starting at the given addr */
 304 #define PAGES_4K_SPANNED(_address, size)                                \
 305                 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 306                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 307
 308 /* Byte offset into the page corresponding to given address */
 309 #define OFFSET_IN_PAGE(addr)                                            \
 310                  ((size_t)(addr) & (PAGE_SIZE_4K-1))
 311
 312 /* Returns bit offset within a DWORD of a bitfield */
 313 #define AMAP_BIT_OFFSET(_struct, field)                                 \
 314                 (((size_t)&(((_struct *)0)->field))%32)
 315
 316 /* Returns the bit mask of the field that is NOT shifted into location. */
 317 static inline u32 amap_mask(u32 bitsize)
 318 {
 319         return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
 320 }
 321
 322 static inline void
 323 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
 324 {
 325         u32 *dw = (u32 *) ptr + dw_offset;
 326         *dw &= ~(mask << offset);
 327         *dw |= (mask & value) << offset;
 328 }
 329
 330 #define AMAP_SET_BITS(_struct, field, ptr, val)                         \
 331                 amap_set(ptr,                                           \
 332                         offsetof(_struct, field)/32,                    \
 333                         amap_mask(sizeof(((_struct *)0)->field)),       \
 334                         AMAP_BIT_OFFSET(_struct, field),                \
 335                         val)
 336
 337 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
 338 {
 339         u32 *dw = (u32 *) ptr;
 340         return mask & (*(dw + dw_offset) >> offset);
 341 }
 342
 343 #define AMAP_GET_BITS(_struct, field, ptr)                              \
 344                 amap_get(ptr,                                           \
 345                         offsetof(_struct, field)/32,                    \
 346                         amap_mask(sizeof(((_struct *)0)->field)),       \
 347                         AMAP_BIT_OFFSET(_struct, field))
 348
 349 #define be_dws_cpu_to_le(wrb, len)      swap_dws(wrb, len)
 350 #define be_dws_le_to_cpu(wrb, len)      swap_dws(wrb, len)
 351 static inline void swap_dws(void *wrb, int len)
 352 {
 353 #ifdef __BIG_ENDIAN
 354         u32 *dw = wrb;
 355         BUG_ON(len % 4);
 356         do {
 357                 *dw = cpu_to_le32(*dw);
 358                 dw++;
 359                 len -= 4;
 360         } while (len);
 361 #endif                          /* __BIG_ENDIAN */
 362 }
 363
 364 static inline u8 is_tcp_pkt(struct sk_buff *skb)
 365 {
 366         u8 val = 0;
 367
 368         if (ip_hdr(skb)->version == 4)
 369                 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
 370         else if (ip_hdr(skb)->version == 6)
 371                 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
 372
 373         return val;
 374 }
 375
 376 static inline u8 is_udp_pkt(struct sk_buff *skb)
 377 {
 378         u8 val = 0;
 379
 380         if (ip_hdr(skb)->version == 4)
 381                 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
 382         else if (ip_hdr(skb)->version == 6)
 383                 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
 384
 385         return val;
 386 }
 387
 388 extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
 389                 u16 num_popped);
 390 extern void be_link_status_update(struct be_adapter *adapter, bool link_up);
 391 extern void netdev_stats_update(struct be_adapter *adapter);
 392 extern int be_load_fw(struct be_adapter *adapter, u8 *func);
 393 #endif                          /* BE_H */