2 * include/linux/mmc/sh_mmcif.h
4 * platform data for eMMC driver
6 * Copyright (C) 2010 Renesas Solutions Corp.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License.
14 #ifndef LINUX_MMC_SH_MMCIF_H
15 #define LINUX_MMC_SH_MMCIF_H
18 #include <linux/platform_device.h>
19 #include <linux/sh_dma.h>
22 * MMCIF : CE_CLK_CTRL [19:16]
23 * 1000 : Peripheral clock / 512
24 * 0111 : Peripheral clock / 256
25 * 0110 : Peripheral clock / 128
26 * 0101 : Peripheral clock / 64
27 * 0100 : Peripheral clock / 32
28 * 0011 : Peripheral clock / 16
29 * 0010 : Peripheral clock / 8
30 * 0001 : Peripheral clock / 4
31 * 0000 : Peripheral clock / 2
32 * 1111 : Peripheral clock (sup_pclk set '1')
35 struct sh_mmcif_plat_data
{
36 void (*set_pwr
)(struct platform_device
*pdev
, int state
);
37 void (*down_pwr
)(struct platform_device
*pdev
);
38 int (*get_cd
)(struct platform_device
*pdef
);
39 unsigned int slave_id_tx
; /* embedded slave_id_[tr]x */
40 unsigned int slave_id_rx
;
41 u8 sup_pclk
; /* 1 :SH7757, 0: SH7724/SH7372 */
46 #define MMCIF_CE_CMD_SET 0x00000000
47 #define MMCIF_CE_ARG 0x00000008
48 #define MMCIF_CE_ARG_CMD12 0x0000000C
49 #define MMCIF_CE_CMD_CTRL 0x00000010
50 #define MMCIF_CE_BLOCK_SET 0x00000014
51 #define MMCIF_CE_CLK_CTRL 0x00000018
52 #define MMCIF_CE_BUF_ACC 0x0000001C
53 #define MMCIF_CE_RESP3 0x00000020
54 #define MMCIF_CE_RESP2 0x00000024
55 #define MMCIF_CE_RESP1 0x00000028
56 #define MMCIF_CE_RESP0 0x0000002C
57 #define MMCIF_CE_RESP_CMD12 0x00000030
58 #define MMCIF_CE_DATA 0x00000034
59 #define MMCIF_CE_INT 0x00000040
60 #define MMCIF_CE_INT_MASK 0x00000044
61 #define MMCIF_CE_HOST_STS1 0x00000048
62 #define MMCIF_CE_HOST_STS2 0x0000004C
63 #define MMCIF_CE_VERSION 0x0000007C
66 #define BUF_ACC_DMAWEN (1 << 25)
67 #define BUF_ACC_DMAREN (1 << 24)
68 #define BUF_ACC_BUSW_32 (0 << 17)
69 #define BUF_ACC_BUSW_16 (1 << 17)
70 #define BUF_ACC_ATYP (1 << 16)
73 #define CLK_ENABLE (1 << 24) /* 1: output mmc clock */
74 #define CLK_CLEAR (0xf << 16)
75 #define CLK_SUP_PCLK (0xf << 16)
76 #define CLKDIV_4 (1 << 16) /* mmc clock frequency.
77 * n: bus clock/(2^(n+1)) */
78 #define CLKDIV_256 (7 << 16) /* mmc clock frequency. (see above) */
79 #define SRSPTO_256 (2 << 12) /* resp timeout */
80 #define SRBSYTO_29 (0xf << 8) /* resp busy timeout */
81 #define SRWDTO_29 (0xf << 4) /* read/write timeout */
82 #define SCCSTO_29 (0xf << 0) /* ccs timeout */
85 #define SOFT_RST_ON (1 << 31)
86 #define SOFT_RST_OFF 0
88 static inline u32
sh_mmcif_readl(void __iomem
*addr
, int reg
)
90 return __raw_readl(addr
+ reg
);
93 static inline void sh_mmcif_writel(void __iomem
*addr
, int reg
, u32 val
)
95 __raw_writel(val
, addr
+ reg
);
98 #define SH_MMCIF_BBS 512 /* boot block size */
100 static inline void sh_mmcif_boot_cmd_send(void __iomem
*base
,
101 unsigned long cmd
, unsigned long arg
)
103 sh_mmcif_writel(base
, MMCIF_CE_INT
, 0);
104 sh_mmcif_writel(base
, MMCIF_CE_ARG
, arg
);
105 sh_mmcif_writel(base
, MMCIF_CE_CMD_SET
, cmd
);
108 static inline int sh_mmcif_boot_cmd_poll(void __iomem
*base
, unsigned long mask
)
113 for (cnt
= 0; cnt
< 1000000; cnt
++) {
114 tmp
= sh_mmcif_readl(base
, MMCIF_CE_INT
);
116 sh_mmcif_writel(base
, MMCIF_CE_INT
, tmp
& ~mask
);
124 static inline int sh_mmcif_boot_cmd(void __iomem
*base
,
125 unsigned long cmd
, unsigned long arg
)
127 sh_mmcif_boot_cmd_send(base
, cmd
, arg
);
128 return sh_mmcif_boot_cmd_poll(base
, 0x00010000);
131 static inline int sh_mmcif_boot_do_read_single(void __iomem
*base
,
132 unsigned int block_nr
,
138 sh_mmcif_boot_cmd(base
, 0x0d400000, 0x00010000);
140 if (sh_mmcif_readl(base
, MMCIF_CE_RESP0
) != 0x0900)
144 sh_mmcif_boot_cmd(base
, 0x11480000, block_nr
* SH_MMCIF_BBS
);
145 if (sh_mmcif_boot_cmd_poll(base
, 0x00100000) < 0)
148 for (k
= 0; k
< (SH_MMCIF_BBS
/ 4); k
++)
149 buf
[k
] = sh_mmcif_readl(base
, MMCIF_CE_DATA
);
154 static inline int sh_mmcif_boot_do_read(void __iomem
*base
,
155 unsigned long first_block
,
156 unsigned long nr_blocks
,
162 /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
163 sh_mmcif_writel(base
, MMCIF_CE_CLK_CTRL
,
164 CLK_ENABLE
| CLKDIV_4
| SRSPTO_256
|
165 SRBSYTO_29
| SRWDTO_29
| SCCSTO_29
);
168 sh_mmcif_boot_cmd(base
, 0x09806000, 0x00010000);
170 /* CMD7 - Select the card */
171 sh_mmcif_boot_cmd(base
, 0x07400000, 0x00010000);
173 /* CMD16 - Set the block size */
174 sh_mmcif_boot_cmd(base
, 0x10400000, SH_MMCIF_BBS
);
176 for (k
= 0; !ret
&& k
< nr_blocks
; k
++)
177 ret
= sh_mmcif_boot_do_read_single(base
, first_block
+ k
,
178 buf
+ (k
* SH_MMCIF_BBS
));
183 static inline void sh_mmcif_boot_init(void __iomem
*base
)
186 sh_mmcif_writel(base
, MMCIF_CE_VERSION
, SOFT_RST_ON
);
187 sh_mmcif_writel(base
, MMCIF_CE_VERSION
, SOFT_RST_OFF
);
190 sh_mmcif_writel(base
, MMCIF_CE_BUF_ACC
, BUF_ACC_ATYP
);
192 /* Set block size in MMCIF hardware */
193 sh_mmcif_writel(base
, MMCIF_CE_BLOCK_SET
, SH_MMCIF_BBS
);
195 /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
196 sh_mmcif_writel(base
, MMCIF_CE_CLK_CTRL
,
197 CLK_ENABLE
| CLKDIV_256
| SRSPTO_256
|
198 SRBSYTO_29
| SRWDTO_29
| SCCSTO_29
);
201 sh_mmcif_boot_cmd(base
, 0x00000040, 0);
205 sh_mmcif_boot_cmd(base
, 0x01405040, 0x40300000); /* CMD1 */
206 } while ((sh_mmcif_readl(base
, MMCIF_CE_RESP0
) & 0x80000000)
210 sh_mmcif_boot_cmd(base
, 0x02806040, 0);
212 /* CMD3 - Set card relative address */
213 sh_mmcif_boot_cmd(base
, 0x03400040, 0x00010000);
216 #endif /* LINUX_MMC_SH_MMCIF_H */