2 * V4L2 Driver for i.MX27/i.MX25 camera host
4 * Copyright (C) 2008, Sascha Hauer, Pengutronix
5 * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
6 * Copyright (C) 2012, Javier Martin, Vista Silicon S.L.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/module.h>
17 #include <linux/delay.h>
18 #include <linux/slab.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/errno.h>
22 #include <linux/gcd.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
26 #include <linux/moduleparam.h>
27 #include <linux/time.h>
28 #include <linux/device.h>
29 #include <linux/platform_device.h>
30 #include <linux/mutex.h>
31 #include <linux/clk.h>
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-dev.h>
35 #include <media/videobuf2-core.h>
36 #include <media/videobuf2-dma-contig.h>
37 #include <media/soc_camera.h>
38 #include <media/soc_mediabus.h>
40 #include <linux/videodev2.h>
42 #include <mach/mx2_cam.h>
43 #include <mach/hardware.h>
47 #define MX2_CAM_DRV_NAME "mx2-camera"
48 #define MX2_CAM_VERSION "0.0.6"
49 #define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
52 #define CSICR1_RESET_VAL 0x40000800
53 #define CSICR2_RESET_VAL 0x0
54 #define CSICR3_RESET_VAL 0x0
56 /* csi control reg 1 */
57 #define CSICR1_SWAP16_EN (1 << 31)
58 #define CSICR1_EXT_VSYNC (1 << 30)
59 #define CSICR1_EOF_INTEN (1 << 29)
60 #define CSICR1_PRP_IF_EN (1 << 28)
61 #define CSICR1_CCIR_MODE (1 << 27)
62 #define CSICR1_COF_INTEN (1 << 26)
63 #define CSICR1_SF_OR_INTEN (1 << 25)
64 #define CSICR1_RF_OR_INTEN (1 << 24)
65 #define CSICR1_STATFF_LEVEL (3 << 22)
66 #define CSICR1_STATFF_INTEN (1 << 21)
67 #define CSICR1_RXFF_LEVEL(l) (((l) & 3) << 19) /* MX27 */
68 #define CSICR1_FB2_DMA_INTEN (1 << 20) /* MX25 */
69 #define CSICR1_FB1_DMA_INTEN (1 << 19) /* MX25 */
70 #define CSICR1_RXFF_INTEN (1 << 18)
71 #define CSICR1_SOF_POL (1 << 17)
72 #define CSICR1_SOF_INTEN (1 << 16)
73 #define CSICR1_MCLKDIV(d) (((d) & 0xF) << 12)
74 #define CSICR1_HSYNC_POL (1 << 11)
75 #define CSICR1_CCIR_EN (1 << 10)
76 #define CSICR1_MCLKEN (1 << 9)
77 #define CSICR1_FCC (1 << 8)
78 #define CSICR1_PACK_DIR (1 << 7)
79 #define CSICR1_CLR_STATFIFO (1 << 6)
80 #define CSICR1_CLR_RXFIFO (1 << 5)
81 #define CSICR1_GCLK_MODE (1 << 4)
82 #define CSICR1_INV_DATA (1 << 3)
83 #define CSICR1_INV_PCLK (1 << 2)
84 #define CSICR1_REDGE (1 << 1)
86 #define SHIFT_STATFF_LEVEL 22
87 #define SHIFT_RXFF_LEVEL 19
88 #define SHIFT_MCLKDIV 12
91 #define CSICR3_FRMCNT (0xFFFF << 16)
92 #define CSICR3_FRMCNT_RST (1 << 15)
93 #define CSICR3_DMA_REFLASH_RFF (1 << 14)
94 #define CSICR3_DMA_REFLASH_SFF (1 << 13)
95 #define CSICR3_DMA_REQ_EN_RFF (1 << 12)
96 #define CSICR3_DMA_REQ_EN_SFF (1 << 11)
97 #define CSICR3_RXFF_LEVEL(l) (((l) & 7) << 4) /* MX25 */
98 #define CSICR3_CSI_SUP (1 << 3)
99 #define CSICR3_ZERO_PACK_EN (1 << 2)
100 #define CSICR3_ECC_INT_EN (1 << 1)
101 #define CSICR3_ECC_AUTO_EN (1 << 0)
103 #define SHIFT_FRMCNT 16
106 #define CSISR_SFF_OR_INT (1 << 25)
107 #define CSISR_RFF_OR_INT (1 << 24)
108 #define CSISR_STATFF_INT (1 << 21)
109 #define CSISR_DMA_TSF_FB2_INT (1 << 20) /* MX25 */
110 #define CSISR_DMA_TSF_FB1_INT (1 << 19) /* MX25 */
111 #define CSISR_RXFF_INT (1 << 18)
112 #define CSISR_EOF_INT (1 << 17)
113 #define CSISR_SOF_INT (1 << 16)
114 #define CSISR_F2_INT (1 << 15)
115 #define CSISR_F1_INT (1 << 14)
116 #define CSISR_COF_INT (1 << 13)
117 #define CSISR_ECC_INT (1 << 1)
118 #define CSISR_DRDY (1 << 0)
122 #define CSISR (cpu_is_mx27() ? 0x08 : 0x18)
123 #define CSISTATFIFO 0x0c
124 #define CSIRFIFO 0x10
125 #define CSIRXCNT 0x14
126 #define CSICR3 (cpu_is_mx27() ? 0x1C : 0x08)
127 #define CSIDMASA_STATFIFO 0x20
128 #define CSIDMATA_STATFIFO 0x24
129 #define CSIDMASA_FB1 0x28
130 #define CSIDMASA_FB2 0x2c
131 #define CSIFBUF_PARA 0x30
132 #define CSIIMAG_PARA 0x34
135 #define PRP_CNTL 0x00
136 #define PRP_INTR_CNTL 0x04
137 #define PRP_INTRSTATUS 0x08
138 #define PRP_SOURCE_Y_PTR 0x0c
139 #define PRP_SOURCE_CB_PTR 0x10
140 #define PRP_SOURCE_CR_PTR 0x14
141 #define PRP_DEST_RGB1_PTR 0x18
142 #define PRP_DEST_RGB2_PTR 0x1c
143 #define PRP_DEST_Y_PTR 0x20
144 #define PRP_DEST_CB_PTR 0x24
145 #define PRP_DEST_CR_PTR 0x28
146 #define PRP_SRC_FRAME_SIZE 0x2c
147 #define PRP_DEST_CH1_LINE_STRIDE 0x30
148 #define PRP_SRC_PIXEL_FORMAT_CNTL 0x34
149 #define PRP_CH1_PIXEL_FORMAT_CNTL 0x38
150 #define PRP_CH1_OUT_IMAGE_SIZE 0x3c
151 #define PRP_CH2_OUT_IMAGE_SIZE 0x40
152 #define PRP_SRC_LINE_STRIDE 0x44
153 #define PRP_CSC_COEF_012 0x48
154 #define PRP_CSC_COEF_345 0x4c
155 #define PRP_CSC_COEF_678 0x50
156 #define PRP_CH1_RZ_HORI_COEF1 0x54
157 #define PRP_CH1_RZ_HORI_COEF2 0x58
158 #define PRP_CH1_RZ_HORI_VALID 0x5c
159 #define PRP_CH1_RZ_VERT_COEF1 0x60
160 #define PRP_CH1_RZ_VERT_COEF2 0x64
161 #define PRP_CH1_RZ_VERT_VALID 0x68
162 #define PRP_CH2_RZ_HORI_COEF1 0x6c
163 #define PRP_CH2_RZ_HORI_COEF2 0x70
164 #define PRP_CH2_RZ_HORI_VALID 0x74
165 #define PRP_CH2_RZ_VERT_COEF1 0x78
166 #define PRP_CH2_RZ_VERT_COEF2 0x7c
167 #define PRP_CH2_RZ_VERT_VALID 0x80
169 #define PRP_CNTL_CH1EN (1 << 0)
170 #define PRP_CNTL_CH2EN (1 << 1)
171 #define PRP_CNTL_CSIEN (1 << 2)
172 #define PRP_CNTL_DATA_IN_YUV420 (0 << 3)
173 #define PRP_CNTL_DATA_IN_YUV422 (1 << 3)
174 #define PRP_CNTL_DATA_IN_RGB16 (2 << 3)
175 #define PRP_CNTL_DATA_IN_RGB32 (3 << 3)
176 #define PRP_CNTL_CH1_OUT_RGB8 (0 << 5)
177 #define PRP_CNTL_CH1_OUT_RGB16 (1 << 5)
178 #define PRP_CNTL_CH1_OUT_RGB32 (2 << 5)
179 #define PRP_CNTL_CH1_OUT_YUV422 (3 << 5)
180 #define PRP_CNTL_CH2_OUT_YUV420 (0 << 7)
181 #define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
182 #define PRP_CNTL_CH2_OUT_YUV444 (2 << 7)
183 #define PRP_CNTL_CH1_LEN (1 << 9)
184 #define PRP_CNTL_CH2_LEN (1 << 10)
185 #define PRP_CNTL_SKIP_FRAME (1 << 11)
186 #define PRP_CNTL_SWRST (1 << 12)
187 #define PRP_CNTL_CLKEN (1 << 13)
188 #define PRP_CNTL_WEN (1 << 14)
189 #define PRP_CNTL_CH1BYP (1 << 15)
190 #define PRP_CNTL_IN_TSKIP(x) ((x) << 16)
191 #define PRP_CNTL_CH1_TSKIP(x) ((x) << 19)
192 #define PRP_CNTL_CH2_TSKIP(x) ((x) << 22)
193 #define PRP_CNTL_INPUT_FIFO_LEVEL(x) ((x) << 25)
194 #define PRP_CNTL_RZ_FIFO_LEVEL(x) ((x) << 27)
195 #define PRP_CNTL_CH2B1EN (1 << 29)
196 #define PRP_CNTL_CH2B2EN (1 << 30)
197 #define PRP_CNTL_CH2FEN (1 << 31)
199 /* IRQ Enable and status register */
200 #define PRP_INTR_RDERR (1 << 0)
201 #define PRP_INTR_CH1WERR (1 << 1)
202 #define PRP_INTR_CH2WERR (1 << 2)
203 #define PRP_INTR_CH1FC (1 << 3)
204 #define PRP_INTR_CH2FC (1 << 5)
205 #define PRP_INTR_LBOVF (1 << 7)
206 #define PRP_INTR_CH2OVF (1 << 8)
208 /* Resizing registers */
209 #define PRP_RZ_VALID_TBL_LEN(x) ((x) << 24)
210 #define PRP_RZ_VALID_BILINEAR (1 << 31)
212 #define MAX_VIDEO_MEM 16
214 #define RESIZE_NUM_MIN 1
215 #define RESIZE_NUM_MAX 20
217 #define SZ_COEF (1 << BC_COEF)
219 #define RESIZE_DIR_H 0
220 #define RESIZE_DIR_V 1
222 #define RESIZE_ALGO_BILINEAR 0
223 #define RESIZE_ALGO_AVERAGING 1
234 /* prp resizing parameters */
235 struct emma_prp_resize
{
236 int algo
; /* type of algorithm used */
237 int len
; /* number of coefficients */
238 unsigned char s
[RESIZE_NUM_MAX
]; /* table of coefficients */
241 /* prp configuration for a client-host fmt pair */
243 enum v4l2_mbus_pixelcode in_fmt
;
245 struct mx2_prp_cfg cfg
;
248 enum mx2_buffer_state
{
254 struct mx2_buf_internal
{
255 struct list_head queue
;
260 /* buffer for one video frame */
262 /* common v4l buffer stuff -- must be first */
263 struct vb2_buffer vb
;
264 enum mx2_buffer_state state
;
265 struct mx2_buf_internal internal
;
268 struct mx2_camera_dev
{
270 struct soc_camera_host soc_host
;
271 struct soc_camera_device
*icd
;
272 struct clk
*clk_csi
, *clk_emma
;
274 unsigned int irq_csi
, irq_emma
;
275 void __iomem
*base_csi
, *base_emma
;
276 unsigned long base_dma
;
278 struct mx2_camera_platform_data
*pdata
;
279 struct resource
*res_csi
, *res_emma
;
280 unsigned long platform_flags
;
282 struct list_head capture
;
283 struct list_head active_bufs
;
284 struct list_head discard
;
289 struct mx2_buffer
*active
;
290 struct mx2_buffer
*fb1_active
;
291 struct mx2_buffer
*fb2_active
;
295 struct mx2_buf_internal buf_discard
[2];
296 void *discard_buffer
;
297 dma_addr_t discard_buffer_dma
;
299 struct mx2_fmt_cfg
*emma_prp
;
300 struct emma_prp_resize resizing
[2];
301 unsigned int s_width
, s_height
;
303 struct vb2_alloc_ctx
*alloc_ctx
;
306 static struct mx2_buffer
*mx2_ibuf_to_buf(struct mx2_buf_internal
*int_buf
)
308 return container_of(int_buf
, struct mx2_buffer
, internal
);
311 static struct mx2_fmt_cfg mx27_emma_prp_table
[] = {
313 * This is a generic configuration which is valid for most
314 * prp input-output format combinations.
315 * We set the incomming and outgoing pixelformat to a
316 * 16 Bit wide format and adjust the bytesperline
317 * accordingly. With this configuration the inputdata
318 * will not be changed by the emma and could be any type
319 * of 16 Bit Pixelformat.
326 .in_fmt
= PRP_CNTL_DATA_IN_RGB16
,
327 .out_fmt
= PRP_CNTL_CH1_OUT_RGB16
,
328 .src_pixel
= 0x2ca00565, /* RGB565 */
329 .ch1_pixel
= 0x2ca00565, /* RGB565 */
330 .irq_flags
= PRP_INTR_RDERR
| PRP_INTR_CH1WERR
|
331 PRP_INTR_CH1FC
| PRP_INTR_LBOVF
,
335 .in_fmt
= V4L2_MBUS_FMT_YUYV8_2X8
,
336 .out_fmt
= V4L2_PIX_FMT_YUV420
,
339 .in_fmt
= PRP_CNTL_DATA_IN_YUV422
,
340 .out_fmt
= PRP_CNTL_CH2_OUT_YUV420
,
341 .src_pixel
= 0x22000888, /* YUV422 (YUYV) */
342 .irq_flags
= PRP_INTR_RDERR
| PRP_INTR_CH2WERR
|
343 PRP_INTR_CH2FC
| PRP_INTR_LBOVF
|
348 .in_fmt
= V4L2_MBUS_FMT_UYVY8_2X8
,
349 .out_fmt
= V4L2_PIX_FMT_YUV420
,
352 .in_fmt
= PRP_CNTL_DATA_IN_YUV422
,
353 .out_fmt
= PRP_CNTL_CH2_OUT_YUV420
,
354 .src_pixel
= 0x22000888, /* YUV422 (YUYV) */
355 .irq_flags
= PRP_INTR_RDERR
| PRP_INTR_CH2WERR
|
356 PRP_INTR_CH2FC
| PRP_INTR_LBOVF
|
362 static struct mx2_fmt_cfg
*mx27_emma_prp_get_format(
363 enum v4l2_mbus_pixelcode in_fmt
,
368 for (i
= 1; i
< ARRAY_SIZE(mx27_emma_prp_table
); i
++)
369 if ((mx27_emma_prp_table
[i
].in_fmt
== in_fmt
) &&
370 (mx27_emma_prp_table
[i
].out_fmt
== out_fmt
)) {
371 return &mx27_emma_prp_table
[i
];
373 /* If no match return the most generic configuration */
374 return &mx27_emma_prp_table
[0];
377 static void mx27_update_emma_buf(struct mx2_camera_dev
*pcdev
,
378 unsigned long phys
, int bufnum
)
380 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
382 if (prp
->cfg
.channel
== 1) {
383 writel(phys
, pcdev
->base_emma
+
384 PRP_DEST_RGB1_PTR
+ 4 * bufnum
);
386 writel(phys
, pcdev
->base_emma
+
387 PRP_DEST_Y_PTR
- 0x14 * bufnum
);
388 if (prp
->out_fmt
== V4L2_PIX_FMT_YUV420
) {
389 u32 imgsize
= pcdev
->icd
->user_height
*
390 pcdev
->icd
->user_width
;
392 writel(phys
+ imgsize
, pcdev
->base_emma
+
393 PRP_DEST_CB_PTR
- 0x14 * bufnum
);
394 writel(phys
+ ((5 * imgsize
) / 4), pcdev
->base_emma
+
395 PRP_DEST_CR_PTR
- 0x14 * bufnum
);
400 static void mx2_camera_deactivate(struct mx2_camera_dev
*pcdev
)
404 clk_disable(pcdev
->clk_csi
);
405 writel(0, pcdev
->base_csi
+ CSICR1
);
407 writel(0, pcdev
->base_emma
+ PRP_CNTL
);
408 } else if (cpu_is_mx25()) {
409 spin_lock_irqsave(&pcdev
->lock
, flags
);
410 pcdev
->fb1_active
= NULL
;
411 pcdev
->fb2_active
= NULL
;
412 writel(0, pcdev
->base_csi
+ CSIDMASA_FB1
);
413 writel(0, pcdev
->base_csi
+ CSIDMASA_FB2
);
414 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
419 * The following two functions absolutely depend on the fact, that
420 * there can be only one camera on mx2 camera sensor interface
422 static int mx2_camera_add_device(struct soc_camera_device
*icd
)
424 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
425 struct mx2_camera_dev
*pcdev
= ici
->priv
;
432 ret
= clk_enable(pcdev
->clk_csi
);
436 csicr1
= CSICR1_MCLKEN
;
439 csicr1
|= CSICR1_PRP_IF_EN
| CSICR1_FCC
|
440 CSICR1_RXFF_LEVEL(0);
441 } else if (cpu_is_mx27())
442 csicr1
|= CSICR1_SOF_INTEN
| CSICR1_RXFF_LEVEL(2);
444 pcdev
->csicr1
= csicr1
;
445 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
448 pcdev
->frame_count
= 0;
450 dev_info(icd
->parent
, "Camera driver attached to camera %d\n",
456 static void mx2_camera_remove_device(struct soc_camera_device
*icd
)
458 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
459 struct mx2_camera_dev
*pcdev
= ici
->priv
;
461 BUG_ON(icd
!= pcdev
->icd
);
463 dev_info(icd
->parent
, "Camera driver detached from camera %d\n",
466 mx2_camera_deactivate(pcdev
);
471 static void mx25_camera_frame_done(struct mx2_camera_dev
*pcdev
, int fb
,
474 struct vb2_buffer
*vb
;
475 struct mx2_buffer
*buf
;
476 struct mx2_buffer
**fb_active
= fb
== 1 ? &pcdev
->fb1_active
:
478 u32 fb_reg
= fb
== 1 ? CSIDMASA_FB1
: CSIDMASA_FB2
;
481 spin_lock_irqsave(&pcdev
->lock
, flags
);
483 if (*fb_active
== NULL
)
486 vb
= &(*fb_active
)->vb
;
487 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%p %lu\n", __func__
,
488 vb
, vb2_plane_vaddr(vb
, 0), vb2_get_plane_payload(vb
, 0));
490 do_gettimeofday(&vb
->v4l2_buf
.timestamp
);
491 vb
->v4l2_buf
.sequence
++;
492 vb2_buffer_done(vb
, VB2_BUF_STATE_DONE
);
494 if (list_empty(&pcdev
->capture
)) {
496 writel(0, pcdev
->base_csi
+ fb_reg
);
498 buf
= list_first_entry(&pcdev
->capture
, struct mx2_buffer
,
501 list_del(&buf
->internal
.queue
);
502 buf
->state
= MX2_STATE_ACTIVE
;
503 writel(vb2_dma_contig_plane_dma_addr(vb
, 0),
504 pcdev
->base_csi
+ fb_reg
);
510 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
513 static irqreturn_t
mx25_camera_irq(int irq_csi
, void *data
)
515 struct mx2_camera_dev
*pcdev
= data
;
516 u32 status
= readl(pcdev
->base_csi
+ CSISR
);
518 if (status
& CSISR_DMA_TSF_FB1_INT
)
519 mx25_camera_frame_done(pcdev
, 1, MX2_STATE_DONE
);
520 else if (status
& CSISR_DMA_TSF_FB2_INT
)
521 mx25_camera_frame_done(pcdev
, 2, MX2_STATE_DONE
);
523 /* FIXME: handle CSISR_RFF_OR_INT */
525 writel(status
, pcdev
->base_csi
+ CSISR
);
531 * Videobuf operations
533 static int mx2_videobuf_setup(struct vb2_queue
*vq
,
534 const struct v4l2_format
*fmt
,
535 unsigned int *count
, unsigned int *num_planes
,
536 unsigned int sizes
[], void *alloc_ctxs
[])
538 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vq
);
539 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
540 struct mx2_camera_dev
*pcdev
= ici
->priv
;
542 dev_dbg(icd
->parent
, "count=%d, size=%d\n", *count
, sizes
[0]);
544 /* TODO: support for VIDIOC_CREATE_BUFS not ready */
548 alloc_ctxs
[0] = pcdev
->alloc_ctx
;
550 sizes
[0] = icd
->sizeimage
;
555 sizes
[0] * *count
> MAX_VIDEO_MEM
* 1024 * 1024)
556 *count
= (MAX_VIDEO_MEM
* 1024 * 1024) / sizes
[0];
563 static int mx2_videobuf_prepare(struct vb2_buffer
*vb
)
565 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
568 dev_dbg(icd
->parent
, "%s (vb=0x%p) 0x%p %lu\n", __func__
,
569 vb
, vb2_plane_vaddr(vb
, 0), vb2_get_plane_payload(vb
, 0));
573 * This can be useful if you want to see if we actually fill
574 * the buffer with something
576 memset((void *)vb2_plane_vaddr(vb
, 0),
577 0xaa, vb2_get_plane_payload(vb
, 0));
580 vb2_set_plane_payload(vb
, 0, icd
->sizeimage
);
581 if (vb2_plane_vaddr(vb
, 0) &&
582 vb2_get_plane_payload(vb
, 0) > vb2_plane_size(vb
, 0)) {
593 static void mx2_videobuf_queue(struct vb2_buffer
*vb
)
595 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
596 struct soc_camera_host
*ici
=
597 to_soc_camera_host(icd
->parent
);
598 struct mx2_camera_dev
*pcdev
= ici
->priv
;
599 struct mx2_buffer
*buf
= container_of(vb
, struct mx2_buffer
, vb
);
602 dev_dbg(icd
->parent
, "%s (vb=0x%p) 0x%p %lu\n", __func__
,
603 vb
, vb2_plane_vaddr(vb
, 0), vb2_get_plane_payload(vb
, 0));
605 spin_lock_irqsave(&pcdev
->lock
, flags
);
607 buf
->state
= MX2_STATE_QUEUED
;
608 list_add_tail(&buf
->internal
.queue
, &pcdev
->capture
);
611 u32 csicr3
, dma_inten
= 0;
613 if (pcdev
->fb1_active
== NULL
) {
614 writel(vb2_dma_contig_plane_dma_addr(vb
, 0),
615 pcdev
->base_csi
+ CSIDMASA_FB1
);
616 pcdev
->fb1_active
= buf
;
617 dma_inten
= CSICR1_FB1_DMA_INTEN
;
618 } else if (pcdev
->fb2_active
== NULL
) {
619 writel(vb2_dma_contig_plane_dma_addr(vb
, 0),
620 pcdev
->base_csi
+ CSIDMASA_FB2
);
621 pcdev
->fb2_active
= buf
;
622 dma_inten
= CSICR1_FB2_DMA_INTEN
;
626 list_del(&buf
->internal
.queue
);
627 buf
->state
= MX2_STATE_ACTIVE
;
629 csicr3
= readl(pcdev
->base_csi
+ CSICR3
);
632 writel(csicr3
| CSICR3_DMA_REFLASH_RFF
,
633 pcdev
->base_csi
+ CSICR3
);
635 /* clear & enable interrupts */
636 writel(dma_inten
, pcdev
->base_csi
+ CSISR
);
637 pcdev
->csicr1
|= dma_inten
;
638 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
641 csicr3
|= CSICR3_DMA_REQ_EN_RFF
| CSICR3_RXFF_LEVEL(1);
642 writel(csicr3
, pcdev
->base_csi
+ CSICR3
);
646 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
649 static void mx2_videobuf_release(struct vb2_buffer
*vb
)
651 struct soc_camera_device
*icd
= soc_camera_from_vb2q(vb
->vb2_queue
);
652 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
653 struct mx2_camera_dev
*pcdev
= ici
->priv
;
654 struct mx2_buffer
*buf
= container_of(vb
, struct mx2_buffer
, vb
);
658 dev_dbg(icd
->parent
, "%s (vb=0x%p) 0x%p %lu\n", __func__
,
659 vb
, vb2_plane_vaddr(vb
, 0), vb2_get_plane_payload(vb
, 0));
661 switch (buf
->state
) {
662 case MX2_STATE_ACTIVE
:
663 dev_info(icd
->parent
, "%s (active)\n", __func__
);
665 case MX2_STATE_QUEUED
:
666 dev_info(icd
->parent
, "%s (queued)\n", __func__
);
669 dev_info(icd
->parent
, "%s (unknown) %d\n", __func__
,
676 * Terminate only queued but inactive buffers. Active buffers are
677 * released when they become inactive after videobuf_waiton().
679 * FIXME: implement forced termination of active buffers for mx27 and
680 * mx27 eMMA, so that the user won't get stuck in an uninterruptible
681 * state. This requires a specific handling for each of the these DMA
685 spin_lock_irqsave(&pcdev
->lock
, flags
);
686 if (cpu_is_mx25() && buf
->state
== MX2_STATE_ACTIVE
) {
687 if (pcdev
->fb1_active
== buf
) {
688 pcdev
->csicr1
&= ~CSICR1_FB1_DMA_INTEN
;
689 writel(0, pcdev
->base_csi
+ CSIDMASA_FB1
);
690 pcdev
->fb1_active
= NULL
;
691 } else if (pcdev
->fb2_active
== buf
) {
692 pcdev
->csicr1
&= ~CSICR1_FB2_DMA_INTEN
;
693 writel(0, pcdev
->base_csi
+ CSIDMASA_FB2
);
694 pcdev
->fb2_active
= NULL
;
696 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
698 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
701 static void mx27_camera_emma_buf_init(struct soc_camera_device
*icd
,
704 struct soc_camera_host
*ici
=
705 to_soc_camera_host(icd
->parent
);
706 struct mx2_camera_dev
*pcdev
= ici
->priv
;
707 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
709 writel((pcdev
->s_width
<< 16) | pcdev
->s_height
,
710 pcdev
->base_emma
+ PRP_SRC_FRAME_SIZE
);
711 writel(prp
->cfg
.src_pixel
,
712 pcdev
->base_emma
+ PRP_SRC_PIXEL_FORMAT_CNTL
);
713 if (prp
->cfg
.channel
== 1) {
714 writel((icd
->user_width
<< 16) | icd
->user_height
,
715 pcdev
->base_emma
+ PRP_CH1_OUT_IMAGE_SIZE
);
717 pcdev
->base_emma
+ PRP_DEST_CH1_LINE_STRIDE
);
718 writel(prp
->cfg
.ch1_pixel
,
719 pcdev
->base_emma
+ PRP_CH1_PIXEL_FORMAT_CNTL
);
720 } else { /* channel 2 */
721 writel((icd
->user_width
<< 16) | icd
->user_height
,
722 pcdev
->base_emma
+ PRP_CH2_OUT_IMAGE_SIZE
);
725 /* Enable interrupts */
726 writel(prp
->cfg
.irq_flags
, pcdev
->base_emma
+ PRP_INTR_CNTL
);
729 static void mx2_prp_resize_commit(struct mx2_camera_dev
*pcdev
)
733 for (dir
= RESIZE_DIR_H
; dir
<= RESIZE_DIR_V
; dir
++) {
734 unsigned char *s
= pcdev
->resizing
[dir
].s
;
735 int len
= pcdev
->resizing
[dir
].len
;
736 unsigned int coeff
[2] = {0, 0};
737 unsigned int valid
= 0;
743 for (i
= RESIZE_NUM_MAX
- 1; i
>= 0; i
--) {
747 coeff
[j
] = (coeff
[j
] << BC_COEF
) |
748 (s
[i
] & (SZ_COEF
- 1));
750 if (i
== 5 || i
== 15)
753 valid
= (valid
<< 1) | (s
[i
] >> BC_COEF
);
756 valid
|= PRP_RZ_VALID_TBL_LEN(len
);
758 if (pcdev
->resizing
[dir
].algo
== RESIZE_ALGO_BILINEAR
)
759 valid
|= PRP_RZ_VALID_BILINEAR
;
761 if (pcdev
->emma_prp
->cfg
.channel
== 1) {
762 if (dir
== RESIZE_DIR_H
) {
763 writel(coeff
[0], pcdev
->base_emma
+
764 PRP_CH1_RZ_HORI_COEF1
);
765 writel(coeff
[1], pcdev
->base_emma
+
766 PRP_CH1_RZ_HORI_COEF2
);
767 writel(valid
, pcdev
->base_emma
+
768 PRP_CH1_RZ_HORI_VALID
);
770 writel(coeff
[0], pcdev
->base_emma
+
771 PRP_CH1_RZ_VERT_COEF1
);
772 writel(coeff
[1], pcdev
->base_emma
+
773 PRP_CH1_RZ_VERT_COEF2
);
774 writel(valid
, pcdev
->base_emma
+
775 PRP_CH1_RZ_VERT_VALID
);
778 if (dir
== RESIZE_DIR_H
) {
779 writel(coeff
[0], pcdev
->base_emma
+
780 PRP_CH2_RZ_HORI_COEF1
);
781 writel(coeff
[1], pcdev
->base_emma
+
782 PRP_CH2_RZ_HORI_COEF2
);
783 writel(valid
, pcdev
->base_emma
+
784 PRP_CH2_RZ_HORI_VALID
);
786 writel(coeff
[0], pcdev
->base_emma
+
787 PRP_CH2_RZ_VERT_COEF1
);
788 writel(coeff
[1], pcdev
->base_emma
+
789 PRP_CH2_RZ_VERT_COEF2
);
790 writel(valid
, pcdev
->base_emma
+
791 PRP_CH2_RZ_VERT_VALID
);
797 static int mx2_start_streaming(struct vb2_queue
*q
, unsigned int count
)
799 struct soc_camera_device
*icd
= soc_camera_from_vb2q(q
);
800 struct soc_camera_host
*ici
=
801 to_soc_camera_host(icd
->parent
);
802 struct mx2_camera_dev
*pcdev
= ici
->priv
;
803 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
804 struct vb2_buffer
*vb
;
805 struct mx2_buffer
*buf
;
814 spin_lock_irqsave(&pcdev
->lock
, flags
);
816 buf
= list_first_entry(&pcdev
->capture
, struct mx2_buffer
,
818 buf
->internal
.bufnum
= 0;
820 buf
->state
= MX2_STATE_ACTIVE
;
822 phys
= vb2_dma_contig_plane_dma_addr(vb
, 0);
823 mx27_update_emma_buf(pcdev
, phys
, buf
->internal
.bufnum
);
824 list_move_tail(pcdev
->capture
.next
, &pcdev
->active_bufs
);
826 buf
= list_first_entry(&pcdev
->capture
, struct mx2_buffer
,
828 buf
->internal
.bufnum
= 1;
830 buf
->state
= MX2_STATE_ACTIVE
;
832 phys
= vb2_dma_contig_plane_dma_addr(vb
, 0);
833 mx27_update_emma_buf(pcdev
, phys
, buf
->internal
.bufnum
);
834 list_move_tail(pcdev
->capture
.next
, &pcdev
->active_bufs
);
836 bytesperline
= soc_mbus_bytes_per_line(icd
->user_width
,
837 icd
->current_fmt
->host_fmt
);
838 if (bytesperline
< 0)
842 * I didn't manage to properly enable/disable the prp
843 * on a per frame basis during running transfers,
844 * thus we allocate a buffer here and use it to
845 * discard frames when no buffer is available.
846 * Feel free to work on this ;)
848 pcdev
->discard_size
= icd
->user_height
* bytesperline
;
849 pcdev
->discard_buffer
= dma_alloc_coherent(ici
->v4l2_dev
.dev
,
850 pcdev
->discard_size
, &pcdev
->discard_buffer_dma
,
852 if (!pcdev
->discard_buffer
)
855 pcdev
->buf_discard
[0].discard
= true;
856 list_add_tail(&pcdev
->buf_discard
[0].queue
,
859 pcdev
->buf_discard
[1].discard
= true;
860 list_add_tail(&pcdev
->buf_discard
[1].queue
,
863 mx2_prp_resize_commit(pcdev
);
865 mx27_camera_emma_buf_init(icd
, bytesperline
);
867 if (prp
->cfg
.channel
== 1) {
868 writel(PRP_CNTL_CH1EN
|
874 PRP_CNTL_CH1_TSKIP(0) |
875 PRP_CNTL_IN_TSKIP(0),
876 pcdev
->base_emma
+ PRP_CNTL
);
878 writel(PRP_CNTL_CH2EN
|
883 PRP_CNTL_CH2_TSKIP(0) |
884 PRP_CNTL_IN_TSKIP(0),
885 pcdev
->base_emma
+ PRP_CNTL
);
887 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
893 static int mx2_stop_streaming(struct vb2_queue
*q
)
895 struct soc_camera_device
*icd
= soc_camera_from_vb2q(q
);
896 struct soc_camera_host
*ici
=
897 to_soc_camera_host(icd
->parent
);
898 struct mx2_camera_dev
*pcdev
= ici
->priv
;
899 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
905 spin_lock_irqsave(&pcdev
->lock
, flags
);
907 cntl
= readl(pcdev
->base_emma
+ PRP_CNTL
);
908 if (prp
->cfg
.channel
== 1) {
909 writel(cntl
& ~PRP_CNTL_CH1EN
,
910 pcdev
->base_emma
+ PRP_CNTL
);
912 writel(cntl
& ~PRP_CNTL_CH2EN
,
913 pcdev
->base_emma
+ PRP_CNTL
);
915 INIT_LIST_HEAD(&pcdev
->capture
);
916 INIT_LIST_HEAD(&pcdev
->active_bufs
);
917 INIT_LIST_HEAD(&pcdev
->discard
);
919 b
= pcdev
->discard_buffer
;
920 pcdev
->discard_buffer
= NULL
;
922 spin_unlock_irqrestore(&pcdev
->lock
, flags
);
924 dma_free_coherent(ici
->v4l2_dev
.dev
,
925 pcdev
->discard_size
, b
, pcdev
->discard_buffer_dma
);
931 static struct vb2_ops mx2_videobuf_ops
= {
932 .queue_setup
= mx2_videobuf_setup
,
933 .buf_prepare
= mx2_videobuf_prepare
,
934 .buf_queue
= mx2_videobuf_queue
,
935 .buf_cleanup
= mx2_videobuf_release
,
936 .start_streaming
= mx2_start_streaming
,
937 .stop_streaming
= mx2_stop_streaming
,
940 static int mx2_camera_init_videobuf(struct vb2_queue
*q
,
941 struct soc_camera_device
*icd
)
943 q
->type
= V4L2_BUF_TYPE_VIDEO_CAPTURE
;
944 q
->io_modes
= VB2_MMAP
| VB2_USERPTR
;
946 q
->ops
= &mx2_videobuf_ops
;
947 q
->mem_ops
= &vb2_dma_contig_memops
;
948 q
->buf_struct_size
= sizeof(struct mx2_buffer
);
950 return vb2_queue_init(q
);
953 #define MX2_BUS_FLAGS (V4L2_MBUS_MASTER | \
954 V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
955 V4L2_MBUS_VSYNC_ACTIVE_LOW | \
956 V4L2_MBUS_HSYNC_ACTIVE_HIGH | \
957 V4L2_MBUS_HSYNC_ACTIVE_LOW | \
958 V4L2_MBUS_PCLK_SAMPLE_RISING | \
959 V4L2_MBUS_PCLK_SAMPLE_FALLING | \
960 V4L2_MBUS_DATA_ACTIVE_HIGH | \
961 V4L2_MBUS_DATA_ACTIVE_LOW)
963 static int mx27_camera_emma_prp_reset(struct mx2_camera_dev
*pcdev
)
968 cntl
= readl(pcdev
->base_emma
+ PRP_CNTL
);
969 writel(PRP_CNTL_SWRST
, pcdev
->base_emma
+ PRP_CNTL
);
970 while (count
++ < 100) {
971 if (!(readl(pcdev
->base_emma
+ PRP_CNTL
) & PRP_CNTL_SWRST
))
980 static int mx2_camera_set_bus_param(struct soc_camera_device
*icd
)
982 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
983 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
984 struct mx2_camera_dev
*pcdev
= ici
->priv
;
985 struct v4l2_mbus_config cfg
= {.type
= V4L2_MBUS_PARALLEL
,};
986 const struct soc_camera_format_xlate
*xlate
;
987 unsigned long common_flags
;
990 u32 csicr1
= pcdev
->csicr1
;
992 ret
= v4l2_subdev_call(sd
, video
, g_mbus_config
, &cfg
);
994 common_flags
= soc_mbus_config_compatible(&cfg
, MX2_BUS_FLAGS
);
996 dev_warn(icd
->parent
,
997 "Flags incompatible: camera 0x%x, host 0x%x\n",
998 cfg
.flags
, MX2_BUS_FLAGS
);
1001 } else if (ret
!= -ENOIOCTLCMD
) {
1004 common_flags
= MX2_BUS_FLAGS
;
1007 if ((common_flags
& V4L2_MBUS_HSYNC_ACTIVE_HIGH
) &&
1008 (common_flags
& V4L2_MBUS_HSYNC_ACTIVE_LOW
)) {
1009 if (pcdev
->platform_flags
& MX2_CAMERA_HSYNC_HIGH
)
1010 common_flags
&= ~V4L2_MBUS_HSYNC_ACTIVE_LOW
;
1012 common_flags
&= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH
;
1015 if ((common_flags
& V4L2_MBUS_PCLK_SAMPLE_RISING
) &&
1016 (common_flags
& V4L2_MBUS_PCLK_SAMPLE_FALLING
)) {
1017 if (pcdev
->platform_flags
& MX2_CAMERA_PCLK_SAMPLE_RISING
)
1018 common_flags
&= ~V4L2_MBUS_PCLK_SAMPLE_FALLING
;
1020 common_flags
&= ~V4L2_MBUS_PCLK_SAMPLE_RISING
;
1023 cfg
.flags
= common_flags
;
1024 ret
= v4l2_subdev_call(sd
, video
, s_mbus_config
, &cfg
);
1025 if (ret
< 0 && ret
!= -ENOIOCTLCMD
) {
1026 dev_dbg(icd
->parent
, "camera s_mbus_config(0x%lx) returned %d\n",
1031 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
1033 dev_warn(icd
->parent
, "Format %x not found\n", pixfmt
);
1037 if (xlate
->code
== V4L2_MBUS_FMT_YUYV8_2X8
) {
1038 csicr1
|= CSICR1_PACK_DIR
;
1039 csicr1
&= ~CSICR1_SWAP16_EN
;
1040 dev_dbg(icd
->parent
, "already yuyv format, don't convert\n");
1041 } else if (xlate
->code
== V4L2_MBUS_FMT_UYVY8_2X8
) {
1042 csicr1
&= ~CSICR1_PACK_DIR
;
1043 csicr1
|= CSICR1_SWAP16_EN
;
1044 dev_dbg(icd
->parent
, "convert uyvy mbus format into yuyv\n");
1046 dev_warn(icd
->parent
, "mbus format not supported\n");
1050 if (common_flags
& V4L2_MBUS_PCLK_SAMPLE_RISING
)
1051 csicr1
|= CSICR1_REDGE
;
1052 if (common_flags
& V4L2_MBUS_VSYNC_ACTIVE_HIGH
)
1053 csicr1
|= CSICR1_SOF_POL
;
1054 if (common_flags
& V4L2_MBUS_HSYNC_ACTIVE_HIGH
)
1055 csicr1
|= CSICR1_HSYNC_POL
;
1056 if (pcdev
->platform_flags
& MX2_CAMERA_EXT_VSYNC
)
1057 csicr1
|= CSICR1_EXT_VSYNC
;
1058 if (pcdev
->platform_flags
& MX2_CAMERA_CCIR
)
1059 csicr1
|= CSICR1_CCIR_EN
;
1060 if (pcdev
->platform_flags
& MX2_CAMERA_CCIR_INTERLACE
)
1061 csicr1
|= CSICR1_CCIR_MODE
;
1062 if (pcdev
->platform_flags
& MX2_CAMERA_GATED_CLOCK
)
1063 csicr1
|= CSICR1_GCLK_MODE
;
1064 if (pcdev
->platform_flags
& MX2_CAMERA_INV_DATA
)
1065 csicr1
|= CSICR1_INV_DATA
;
1067 pcdev
->csicr1
= csicr1
;
1069 bytesperline
= soc_mbus_bytes_per_line(icd
->user_width
,
1070 icd
->current_fmt
->host_fmt
);
1071 if (bytesperline
< 0)
1072 return bytesperline
;
1074 if (cpu_is_mx27()) {
1075 ret
= mx27_camera_emma_prp_reset(pcdev
);
1078 } else if (cpu_is_mx25()) {
1079 writel((bytesperline
* icd
->user_height
) >> 2,
1080 pcdev
->base_csi
+ CSIRXCNT
);
1081 writel((bytesperline
<< 16) | icd
->user_height
,
1082 pcdev
->base_csi
+ CSIIMAG_PARA
);
1085 writel(pcdev
->csicr1
, pcdev
->base_csi
+ CSICR1
);
1090 static int mx2_camera_set_crop(struct soc_camera_device
*icd
,
1091 struct v4l2_crop
*a
)
1093 struct v4l2_rect
*rect
= &a
->c
;
1094 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
1095 struct v4l2_mbus_framefmt mf
;
1098 soc_camera_limit_side(&rect
->left
, &rect
->width
, 0, 2, 4096);
1099 soc_camera_limit_side(&rect
->top
, &rect
->height
, 0, 2, 4096);
1101 ret
= v4l2_subdev_call(sd
, video
, s_crop
, a
);
1105 /* The capture device might have changed its output */
1106 ret
= v4l2_subdev_call(sd
, video
, g_mbus_fmt
, &mf
);
1110 dev_dbg(icd
->parent
, "Sensor cropped %dx%d\n",
1111 mf
.width
, mf
.height
);
1113 icd
->user_width
= mf
.width
;
1114 icd
->user_height
= mf
.height
;
1119 static int mx2_camera_get_formats(struct soc_camera_device
*icd
,
1121 struct soc_camera_format_xlate
*xlate
)
1123 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
1124 const struct soc_mbus_pixelfmt
*fmt
;
1125 struct device
*dev
= icd
->parent
;
1126 enum v4l2_mbus_pixelcode code
;
1127 int ret
, formats
= 0;
1129 ret
= v4l2_subdev_call(sd
, video
, enum_mbus_fmt
, idx
, &code
);
1131 /* no more formats */
1134 fmt
= soc_mbus_get_fmtdesc(code
);
1136 dev_err(dev
, "Invalid format code #%u: %d\n", idx
, code
);
1140 if (code
== V4L2_MBUS_FMT_YUYV8_2X8
||
1141 code
== V4L2_MBUS_FMT_UYVY8_2X8
) {
1145 * CH2 can output YUV420 which is a standard format in
1149 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_1_5X8
);
1151 dev_dbg(dev
, "Providing host format %s for sensor code %d\n",
1152 xlate
->host_fmt
->name
, code
);
1157 if (code
== V4L2_MBUS_FMT_UYVY8_2X8
) {
1161 soc_mbus_get_fmtdesc(V4L2_MBUS_FMT_YUYV8_2X8
);
1163 dev_dbg(dev
, "Providing host format %s for sensor code %d\n",
1164 xlate
->host_fmt
->name
, code
);
1169 /* Generic pass-trough */
1172 xlate
->host_fmt
= fmt
;
1179 static int mx2_emmaprp_resize(struct mx2_camera_dev
*pcdev
,
1180 struct v4l2_mbus_framefmt
*mf_in
,
1181 struct v4l2_pix_format
*pix_out
, bool apply
)
1187 for (dir
= RESIZE_DIR_H
; dir
<= RESIZE_DIR_V
; dir
++) {
1188 struct emma_prp_resize tmprsz
;
1189 unsigned char *s
= tmprsz
.s
;
1193 if (dir
== RESIZE_DIR_H
) {
1195 out
= pix_out
->width
;
1198 out
= pix_out
->height
;
1206 /* Calculate ratio */
1210 if (num
> RESIZE_NUM_MAX
)
1213 if ((num
>= 2 * den
) && (den
== 1) &&
1214 (num
< 9) && (!(num
& 0x01))) {
1218 /* Average scaling for >= 2:1 ratios */
1219 /* Support can be added for num >=9 and odd values */
1221 tmprsz
.algo
= RESIZE_ALGO_AVERAGING
;
1224 for (i
= 0; i
< (len
/ 2); i
++)
1228 for (i
= 0; i
< (len
/ 2); i
++) {
1231 for (j
= 0; j
< (len
/ 2); j
++)
1238 for (i
= (len
/ 2); i
< len
; i
++)
1239 s
[i
] = s
[len
- i
- 1];
1241 s
[len
- 1] |= SZ_COEF
;
1243 /* bilinear scaling for < 2:1 ratios */
1244 int v
; /* overflow counter */
1245 int coeff
, nxt
; /* table output */
1246 int in_pos_inc
= 2 * den
;
1248 int out_pos_inc
= 2 * num
;
1249 int init_carry
= num
- den
;
1250 int carry
= init_carry
;
1252 tmprsz
.algo
= RESIZE_ALGO_BILINEAR
;
1253 v
= den
+ in_pos_inc
;
1255 coeff
= v
- out_pos
;
1256 out_pos
+= out_pos_inc
;
1257 carry
+= out_pos_inc
;
1258 for (nxt
= 0; v
< out_pos
; nxt
++) {
1260 carry
-= in_pos_inc
;
1263 if (len
> RESIZE_NUM_MAX
)
1266 coeff
= ((coeff
<< BC_COEF
) +
1267 (in_pos_inc
>> 1)) / in_pos_inc
;
1269 if (coeff
>= (SZ_COEF
- 1))
1273 s
[len
] = (unsigned char)coeff
;
1276 for (i
= 1; i
< nxt
; i
++) {
1277 if (len
>= RESIZE_NUM_MAX
)
1282 } while (carry
!= init_carry
);
1285 if (dir
== RESIZE_DIR_H
)
1286 mf_in
->width
= pix_out
->width
;
1288 mf_in
->height
= pix_out
->height
;
1291 memcpy(&pcdev
->resizing
[dir
], &tmprsz
, sizeof(tmprsz
));
1296 static int mx2_camera_set_fmt(struct soc_camera_device
*icd
,
1297 struct v4l2_format
*f
)
1299 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
1300 struct mx2_camera_dev
*pcdev
= ici
->priv
;
1301 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
1302 const struct soc_camera_format_xlate
*xlate
;
1303 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
1304 struct v4l2_mbus_framefmt mf
;
1307 dev_dbg(icd
->parent
, "%s: requested params: width = %d, height = %d\n",
1308 __func__
, pix
->width
, pix
->height
);
1310 xlate
= soc_camera_xlate_by_fourcc(icd
, pix
->pixelformat
);
1312 dev_warn(icd
->parent
, "Format %x not found\n",
1317 mf
.width
= pix
->width
;
1318 mf
.height
= pix
->height
;
1319 mf
.field
= pix
->field
;
1320 mf
.colorspace
= pix
->colorspace
;
1321 mf
.code
= xlate
->code
;
1323 ret
= v4l2_subdev_call(sd
, video
, s_mbus_fmt
, &mf
);
1324 if (ret
< 0 && ret
!= -ENOIOCTLCMD
)
1327 /* Store width and height returned by the sensor for resizing */
1328 pcdev
->s_width
= mf
.width
;
1329 pcdev
->s_height
= mf
.height
;
1330 dev_dbg(icd
->parent
, "%s: sensor params: width = %d, height = %d\n",
1331 __func__
, pcdev
->s_width
, pcdev
->s_height
);
1333 pcdev
->emma_prp
= mx27_emma_prp_get_format(xlate
->code
,
1334 xlate
->host_fmt
->fourcc
);
1336 memset(pcdev
->resizing
, 0, sizeof(pcdev
->resizing
));
1337 if ((mf
.width
!= pix
->width
|| mf
.height
!= pix
->height
) &&
1338 pcdev
->emma_prp
->cfg
.in_fmt
== PRP_CNTL_DATA_IN_YUV422
) {
1339 if (mx2_emmaprp_resize(pcdev
, &mf
, pix
, true) < 0)
1340 dev_dbg(icd
->parent
, "%s: can't resize\n", __func__
);
1343 if (mf
.code
!= xlate
->code
)
1346 pix
->width
= mf
.width
;
1347 pix
->height
= mf
.height
;
1348 pix
->field
= mf
.field
;
1349 pix
->colorspace
= mf
.colorspace
;
1350 icd
->current_fmt
= xlate
;
1352 dev_dbg(icd
->parent
, "%s: returned params: width = %d, height = %d\n",
1353 __func__
, pix
->width
, pix
->height
);
1358 static int mx2_camera_try_fmt(struct soc_camera_device
*icd
,
1359 struct v4l2_format
*f
)
1361 struct v4l2_subdev
*sd
= soc_camera_to_subdev(icd
);
1362 const struct soc_camera_format_xlate
*xlate
;
1363 struct v4l2_pix_format
*pix
= &f
->fmt
.pix
;
1364 struct v4l2_mbus_framefmt mf
;
1365 __u32 pixfmt
= pix
->pixelformat
;
1366 struct soc_camera_host
*ici
= to_soc_camera_host(icd
->parent
);
1367 struct mx2_camera_dev
*pcdev
= ici
->priv
;
1368 unsigned int width_limit
;
1371 dev_dbg(icd
->parent
, "%s: requested params: width = %d, height = %d\n",
1372 __func__
, pix
->width
, pix
->height
);
1374 xlate
= soc_camera_xlate_by_fourcc(icd
, pixfmt
);
1375 if (pixfmt
&& !xlate
) {
1376 dev_warn(icd
->parent
, "Format %x not found\n", pixfmt
);
1380 /* FIXME: implement MX27 limits */
1382 /* limit to MX25 hardware capabilities */
1383 if (cpu_is_mx25()) {
1384 if (xlate
->host_fmt
->bits_per_sample
<= 8)
1385 width_limit
= 0xffff * 4;
1387 width_limit
= 0xffff * 2;
1388 /* CSIIMAG_PARA limit */
1389 if (pix
->width
> width_limit
)
1390 pix
->width
= width_limit
;
1391 if (pix
->height
> 0xffff)
1392 pix
->height
= 0xffff;
1394 pix
->bytesperline
= soc_mbus_bytes_per_line(pix
->width
,
1396 if (pix
->bytesperline
< 0)
1397 return pix
->bytesperline
;
1398 pix
->sizeimage
= soc_mbus_image_size(xlate
->host_fmt
,
1399 pix
->bytesperline
, pix
->height
);
1400 /* Check against the CSIRXCNT limit */
1401 if (pix
->sizeimage
> 4 * 0x3ffff) {
1402 /* Adjust geometry, preserve aspect ratio */
1403 unsigned int new_height
= int_sqrt(4 * 0x3ffff *
1404 pix
->height
/ pix
->bytesperline
);
1405 pix
->width
= new_height
* pix
->width
/ pix
->height
;
1406 pix
->height
= new_height
;
1407 pix
->bytesperline
= soc_mbus_bytes_per_line(pix
->width
,
1409 BUG_ON(pix
->bytesperline
< 0);
1410 pix
->sizeimage
= soc_mbus_image_size(xlate
->host_fmt
,
1411 pix
->bytesperline
, pix
->height
);
1415 /* limit to sensor capabilities */
1416 mf
.width
= pix
->width
;
1417 mf
.height
= pix
->height
;
1418 mf
.field
= pix
->field
;
1419 mf
.colorspace
= pix
->colorspace
;
1420 mf
.code
= xlate
->code
;
1422 ret
= v4l2_subdev_call(sd
, video
, try_mbus_fmt
, &mf
);
1426 dev_dbg(icd
->parent
, "%s: sensor params: width = %d, height = %d\n",
1427 __func__
, pcdev
->s_width
, pcdev
->s_height
);
1429 /* If the sensor does not support image size try PrP resizing */
1430 pcdev
->emma_prp
= mx27_emma_prp_get_format(xlate
->code
,
1431 xlate
->host_fmt
->fourcc
);
1433 memset(pcdev
->resizing
, 0, sizeof(pcdev
->resizing
));
1434 if ((mf
.width
!= pix
->width
|| mf
.height
!= pix
->height
) &&
1435 pcdev
->emma_prp
->cfg
.in_fmt
== PRP_CNTL_DATA_IN_YUV422
) {
1436 if (mx2_emmaprp_resize(pcdev
, &mf
, pix
, false) < 0)
1437 dev_dbg(icd
->parent
, "%s: can't resize\n", __func__
);
1440 if (mf
.field
== V4L2_FIELD_ANY
)
1441 mf
.field
= V4L2_FIELD_NONE
;
1443 * Driver supports interlaced images provided they have
1444 * both fields so that they can be processed as if they
1447 if (mf
.field
!= V4L2_FIELD_NONE
&& !V4L2_FIELD_HAS_BOTH(mf
.field
)) {
1448 dev_err(icd
->parent
, "Field type %d unsupported.\n",
1453 pix
->width
= mf
.width
;
1454 pix
->height
= mf
.height
;
1455 pix
->field
= mf
.field
;
1456 pix
->colorspace
= mf
.colorspace
;
1458 dev_dbg(icd
->parent
, "%s: returned params: width = %d, height = %d\n",
1459 __func__
, pix
->width
, pix
->height
);
1464 static int mx2_camera_querycap(struct soc_camera_host
*ici
,
1465 struct v4l2_capability
*cap
)
1467 /* cap->name is set by the friendly caller:-> */
1468 strlcpy(cap
->card
, MX2_CAM_DRIVER_DESCRIPTION
, sizeof(cap
->card
));
1469 cap
->capabilities
= V4L2_CAP_VIDEO_CAPTURE
| V4L2_CAP_STREAMING
;
1474 static unsigned int mx2_camera_poll(struct file
*file
, poll_table
*pt
)
1476 struct soc_camera_device
*icd
= file
->private_data
;
1478 return vb2_poll(&icd
->vb2_vidq
, file
, pt
);
1481 static struct soc_camera_host_ops mx2_soc_camera_host_ops
= {
1482 .owner
= THIS_MODULE
,
1483 .add
= mx2_camera_add_device
,
1484 .remove
= mx2_camera_remove_device
,
1485 .set_fmt
= mx2_camera_set_fmt
,
1486 .set_crop
= mx2_camera_set_crop
,
1487 .get_formats
= mx2_camera_get_formats
,
1488 .try_fmt
= mx2_camera_try_fmt
,
1489 .init_videobuf2
= mx2_camera_init_videobuf
,
1490 .poll
= mx2_camera_poll
,
1491 .querycap
= mx2_camera_querycap
,
1492 .set_bus_param
= mx2_camera_set_bus_param
,
1495 static void mx27_camera_frame_done_emma(struct mx2_camera_dev
*pcdev
,
1496 int bufnum
, bool err
)
1499 struct mx2_fmt_cfg
*prp
= pcdev
->emma_prp
;
1501 struct mx2_buf_internal
*ibuf
;
1502 struct mx2_buffer
*buf
;
1503 struct vb2_buffer
*vb
;
1506 ibuf
= list_first_entry(&pcdev
->active_bufs
, struct mx2_buf_internal
,
1509 BUG_ON(ibuf
->bufnum
!= bufnum
);
1511 if (ibuf
->discard
) {
1513 * Discard buffer must not be returned to user space.
1514 * Just return it to the discard queue.
1516 list_move_tail(pcdev
->active_bufs
.next
, &pcdev
->discard
);
1518 buf
= mx2_ibuf_to_buf(ibuf
);
1522 phys
= vb2_dma_contig_plane_dma_addr(vb
, 0);
1523 if (prp
->cfg
.channel
== 1) {
1524 if (readl(pcdev
->base_emma
+ PRP_DEST_RGB1_PTR
+
1525 4 * bufnum
) != phys
) {
1526 dev_err(pcdev
->dev
, "%lx != %x\n", phys
,
1527 readl(pcdev
->base_emma
+
1528 PRP_DEST_RGB1_PTR
+ 4 * bufnum
));
1531 if (readl(pcdev
->base_emma
+ PRP_DEST_Y_PTR
-
1532 0x14 * bufnum
) != phys
) {
1533 dev_err(pcdev
->dev
, "%lx != %x\n", phys
,
1534 readl(pcdev
->base_emma
+
1535 PRP_DEST_Y_PTR
- 0x14 * bufnum
));
1539 dev_dbg(pcdev
->dev
, "%s (vb=0x%p) 0x%p %lu\n", __func__
, vb
,
1540 vb2_plane_vaddr(vb
, 0),
1541 vb2_get_plane_payload(vb
, 0));
1543 list_del_init(&buf
->internal
.queue
);
1544 do_gettimeofday(&vb
->v4l2_buf
.timestamp
);
1545 vb
->v4l2_buf
.sequence
= pcdev
->frame_count
;
1547 vb2_buffer_done(vb
, VB2_BUF_STATE_ERROR
);
1549 vb2_buffer_done(vb
, VB2_BUF_STATE_DONE
);
1552 pcdev
->frame_count
++;
1554 if (list_empty(&pcdev
->capture
)) {
1555 if (list_empty(&pcdev
->discard
)) {
1556 dev_warn(pcdev
->dev
, "%s: trying to access empty discard list\n",
1561 ibuf
= list_first_entry(&pcdev
->discard
,
1562 struct mx2_buf_internal
, queue
);
1563 ibuf
->bufnum
= bufnum
;
1565 list_move_tail(pcdev
->discard
.next
, &pcdev
->active_bufs
);
1566 mx27_update_emma_buf(pcdev
, pcdev
->discard_buffer_dma
, bufnum
);
1570 buf
= list_first_entry(&pcdev
->capture
, struct mx2_buffer
,
1573 buf
->internal
.bufnum
= bufnum
;
1575 list_move_tail(pcdev
->capture
.next
, &pcdev
->active_bufs
);
1578 buf
->state
= MX2_STATE_ACTIVE
;
1580 phys
= vb2_dma_contig_plane_dma_addr(vb
, 0);
1581 mx27_update_emma_buf(pcdev
, phys
, bufnum
);
1584 static irqreturn_t
mx27_camera_emma_irq(int irq_emma
, void *data
)
1586 struct mx2_camera_dev
*pcdev
= data
;
1587 unsigned int status
= readl(pcdev
->base_emma
+ PRP_INTRSTATUS
);
1588 struct mx2_buf_internal
*ibuf
;
1590 spin_lock(&pcdev
->lock
);
1592 if (list_empty(&pcdev
->active_bufs
)) {
1593 dev_warn(pcdev
->dev
, "%s: called while active list is empty\n",
1597 spin_unlock(&pcdev
->lock
);
1602 if (status
& (1 << 7)) { /* overflow */
1603 u32 cntl
= readl(pcdev
->base_emma
+ PRP_CNTL
);
1604 writel(cntl
& ~(PRP_CNTL_CH1EN
| PRP_CNTL_CH2EN
),
1605 pcdev
->base_emma
+ PRP_CNTL
);
1606 writel(cntl
, pcdev
->base_emma
+ PRP_CNTL
);
1608 ibuf
= list_first_entry(&pcdev
->active_bufs
,
1609 struct mx2_buf_internal
, queue
);
1610 mx27_camera_frame_done_emma(pcdev
,
1611 ibuf
->bufnum
, true);
1613 status
&= ~(1 << 7);
1614 } else if (((status
& (3 << 5)) == (3 << 5)) ||
1615 ((status
& (3 << 3)) == (3 << 3))) {
1617 * Both buffers have triggered, process the one we're expecting
1620 ibuf
= list_first_entry(&pcdev
->active_bufs
,
1621 struct mx2_buf_internal
, queue
);
1622 mx27_camera_frame_done_emma(pcdev
, ibuf
->bufnum
, false);
1623 status
&= ~(1 << (6 - ibuf
->bufnum
)); /* mark processed */
1624 } else if ((status
& (1 << 6)) || (status
& (1 << 4))) {
1625 mx27_camera_frame_done_emma(pcdev
, 0, false);
1626 } else if ((status
& (1 << 5)) || (status
& (1 << 3))) {
1627 mx27_camera_frame_done_emma(pcdev
, 1, false);
1630 spin_unlock(&pcdev
->lock
);
1631 writel(status
, pcdev
->base_emma
+ PRP_INTRSTATUS
);
1636 static int __devinit
mx27_camera_emma_init(struct mx2_camera_dev
*pcdev
)
1638 struct resource
*res_emma
= pcdev
->res_emma
;
1641 if (!request_mem_region(res_emma
->start
, resource_size(res_emma
),
1642 MX2_CAM_DRV_NAME
)) {
1647 pcdev
->base_emma
= ioremap(res_emma
->start
, resource_size(res_emma
));
1648 if (!pcdev
->base_emma
) {
1653 err
= request_irq(pcdev
->irq_emma
, mx27_camera_emma_irq
, 0,
1654 MX2_CAM_DRV_NAME
, pcdev
);
1656 dev_err(pcdev
->dev
, "Camera EMMA interrupt register failed \n");
1660 pcdev
->clk_emma
= clk_get(NULL
, "emma");
1661 if (IS_ERR(pcdev
->clk_emma
)) {
1662 err
= PTR_ERR(pcdev
->clk_emma
);
1666 clk_enable(pcdev
->clk_emma
);
1668 err
= mx27_camera_emma_prp_reset(pcdev
);
1670 goto exit_clk_emma_put
;
1675 clk_disable(pcdev
->clk_emma
);
1676 clk_put(pcdev
->clk_emma
);
1678 free_irq(pcdev
->irq_emma
, pcdev
);
1680 iounmap(pcdev
->base_emma
);
1682 release_mem_region(res_emma
->start
, resource_size(res_emma
));
1687 static int __devinit
mx2_camera_probe(struct platform_device
*pdev
)
1689 struct mx2_camera_dev
*pcdev
;
1690 struct resource
*res_csi
, *res_emma
;
1691 void __iomem
*base_csi
;
1692 int irq_csi
, irq_emma
;
1695 dev_dbg(&pdev
->dev
, "initialising\n");
1697 res_csi
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1698 irq_csi
= platform_get_irq(pdev
, 0);
1699 if (res_csi
== NULL
|| irq_csi
< 0) {
1700 dev_err(&pdev
->dev
, "Missing platform resources data\n");
1705 pcdev
= kzalloc(sizeof(*pcdev
), GFP_KERNEL
);
1707 dev_err(&pdev
->dev
, "Could not allocate pcdev\n");
1712 pcdev
->clk_csi
= clk_get(&pdev
->dev
, NULL
);
1713 if (IS_ERR(pcdev
->clk_csi
)) {
1714 dev_err(&pdev
->dev
, "Could not get csi clock\n");
1715 err
= PTR_ERR(pcdev
->clk_csi
);
1719 pcdev
->res_csi
= res_csi
;
1720 pcdev
->pdata
= pdev
->dev
.platform_data
;
1724 pcdev
->platform_flags
= pcdev
->pdata
->flags
;
1726 rate
= clk_round_rate(pcdev
->clk_csi
, pcdev
->pdata
->clk
* 2);
1731 err
= clk_set_rate(pcdev
->clk_csi
, rate
);
1736 INIT_LIST_HEAD(&pcdev
->capture
);
1737 INIT_LIST_HEAD(&pcdev
->active_bufs
);
1738 INIT_LIST_HEAD(&pcdev
->discard
);
1739 spin_lock_init(&pcdev
->lock
);
1742 * Request the regions.
1744 if (!request_mem_region(res_csi
->start
, resource_size(res_csi
),
1745 MX2_CAM_DRV_NAME
)) {
1750 base_csi
= ioremap(res_csi
->start
, resource_size(res_csi
));
1755 pcdev
->irq_csi
= irq_csi
;
1756 pcdev
->base_csi
= base_csi
;
1757 pcdev
->base_dma
= res_csi
->start
;
1758 pcdev
->dev
= &pdev
->dev
;
1760 if (cpu_is_mx25()) {
1761 err
= request_irq(pcdev
->irq_csi
, mx25_camera_irq
, 0,
1762 MX2_CAM_DRV_NAME
, pcdev
);
1764 dev_err(pcdev
->dev
, "Camera interrupt register failed \n");
1769 if (cpu_is_mx27()) {
1771 res_emma
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1772 irq_emma
= platform_get_irq(pdev
, 1);
1774 if (!res_emma
|| !irq_emma
) {
1775 dev_err(&pdev
->dev
, "no EMMA resources\n");
1779 pcdev
->res_emma
= res_emma
;
1780 pcdev
->irq_emma
= irq_emma
;
1781 if (mx27_camera_emma_init(pcdev
))
1785 pcdev
->soc_host
.drv_name
= MX2_CAM_DRV_NAME
,
1786 pcdev
->soc_host
.ops
= &mx2_soc_camera_host_ops
,
1787 pcdev
->soc_host
.priv
= pcdev
;
1788 pcdev
->soc_host
.v4l2_dev
.dev
= &pdev
->dev
;
1789 pcdev
->soc_host
.nr
= pdev
->id
;
1791 pcdev
->soc_host
.capabilities
= SOCAM_HOST_CAP_STRIDE
;
1793 pcdev
->alloc_ctx
= vb2_dma_contig_init_ctx(&pdev
->dev
);
1794 if (IS_ERR(pcdev
->alloc_ctx
)) {
1795 err
= PTR_ERR(pcdev
->alloc_ctx
);
1798 err
= soc_camera_host_register(&pcdev
->soc_host
);
1800 goto exit_free_emma
;
1802 dev_info(&pdev
->dev
, "MX2 Camera (CSI) driver probed, clock frequency: %ld\n",
1803 clk_get_rate(pcdev
->clk_csi
));
1808 vb2_dma_contig_cleanup_ctx(pcdev
->alloc_ctx
);
1810 if (cpu_is_mx27()) {
1811 free_irq(pcdev
->irq_emma
, pcdev
);
1812 clk_disable(pcdev
->clk_emma
);
1813 clk_put(pcdev
->clk_emma
);
1814 iounmap(pcdev
->base_emma
);
1815 release_mem_region(pcdev
->res_emma
->start
, resource_size(pcdev
->res_emma
));
1819 free_irq(pcdev
->irq_csi
, pcdev
);
1823 release_mem_region(res_csi
->start
, resource_size(res_csi
));
1825 clk_put(pcdev
->clk_csi
);
1832 static int __devexit
mx2_camera_remove(struct platform_device
*pdev
)
1834 struct soc_camera_host
*soc_host
= to_soc_camera_host(&pdev
->dev
);
1835 struct mx2_camera_dev
*pcdev
= container_of(soc_host
,
1836 struct mx2_camera_dev
, soc_host
);
1837 struct resource
*res
;
1839 clk_put(pcdev
->clk_csi
);
1841 free_irq(pcdev
->irq_csi
, pcdev
);
1843 free_irq(pcdev
->irq_emma
, pcdev
);
1845 soc_camera_host_unregister(&pcdev
->soc_host
);
1847 vb2_dma_contig_cleanup_ctx(pcdev
->alloc_ctx
);
1849 iounmap(pcdev
->base_csi
);
1851 if (cpu_is_mx27()) {
1852 clk_disable(pcdev
->clk_emma
);
1853 clk_put(pcdev
->clk_emma
);
1854 iounmap(pcdev
->base_emma
);
1855 res
= pcdev
->res_emma
;
1856 release_mem_region(res
->start
, resource_size(res
));
1859 res
= pcdev
->res_csi
;
1860 release_mem_region(res
->start
, resource_size(res
));
1864 dev_info(&pdev
->dev
, "MX2 Camera driver unloaded\n");
1869 static struct platform_driver mx2_camera_driver
= {
1871 .name
= MX2_CAM_DRV_NAME
,
1873 .remove
= __devexit_p(mx2_camera_remove
),
1877 static int __init
mx2_camera_init(void)
1879 return platform_driver_probe(&mx2_camera_driver
, &mx2_camera_probe
);
1882 static void __exit
mx2_camera_exit(void)
1884 return platform_driver_unregister(&mx2_camera_driver
);
1887 module_init(mx2_camera_init
);
1888 module_exit(mx2_camera_exit
);
1890 MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
1891 MODULE_AUTHOR("Sascha Hauer <sha@pengutronix.de>");
1892 MODULE_LICENSE("GPL");
1893 MODULE_VERSION(MX2_CAM_VERSION
);