arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c

   1 /*
   2  * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
   3  *
   4  * Copyright (C) 2011 Nokia Corporation
   5  * Paul Walmsley
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11 #include <plat/omap_hwmod.h>
  12 #include <plat/serial.h>
  13 #include <linux/platform_data/gpio-omap.h>
  14 #include <plat/dma.h>
  15 #include <plat/dmtimer.h>
  16 #include <linux/platform_data/spi-omap2-mcspi.h>
  17
  18 #include "omap_hwmod_common_data.h"
  19 #include "cm-regbits-24xx.h"
  20 #include "prm-regbits-24xx.h"
  21 #include "wd_timer.h"
  22
  23 struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
  24         { .irq = 48 + OMAP_INTC_START, },
  25         { .irq = -1 },
  26 };
  27
  28 struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
  29         { .name = "dispc", .dma_req = 5 },
  30         { .dma_req = -1 }
  31 };
  32
  33 /*
  34  * 'dispc' class
  35  * display controller
  36  */
  37
  38 static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
  39         .rev_offs       = 0x0000,
  40         .sysc_offs      = 0x0010,
  41         .syss_offs      = 0x0014,
  42         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
  43                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
  44         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
  45                            MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
  46         .sysc_fields    = &omap_hwmod_sysc_type1,
  47 };
  48
  49 struct omap_hwmod_class omap2_dispc_hwmod_class = {
  50         .name   = "dispc",
  51         .sysc   = &omap2_dispc_sysc,
  52 };
  53
  54 /* OMAP2xxx Timer Common */
  55 static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
  56         .rev_offs       = 0x0000,
  57         .sysc_offs      = 0x0010,
  58         .syss_offs      = 0x0014,
  59         .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
  60                            SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
  61                            SYSC_HAS_AUTOIDLE),
  62         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
  63         .sysc_fields    = &omap_hwmod_sysc_type1,
  64 };
  65
  66 struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
  67         .name   = "timer",
  68         .sysc   = &omap2xxx_timer_sysc,
  69 };
  70
  71 /*
  72  * 'wd_timer' class
  73  * 32-bit watchdog upward counter that generates a pulse on the reset pin on
  74  * overflow condition
  75  */
  76
  77 static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
  78         .rev_offs       = 0x0000,
  79         .sysc_offs      = 0x0010,
  80         .syss_offs      = 0x0014,
  81         .sysc_flags     = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
  82                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
  83         .sysc_fields    = &omap_hwmod_sysc_type1,
  84 };
  85
  86 struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
  87         .name           = "wd_timer",
  88         .sysc           = &omap2xxx_wd_timer_sysc,
  89         .pre_shutdown   = &omap2_wd_timer_disable,
  90         .reset          = &omap2_wd_timer_reset,
  91 };
  92
  93 /*
  94  * 'gpio' class
  95  * general purpose io module
  96  */
  97 static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
  98         .rev_offs       = 0x0000,
  99         .sysc_offs      = 0x0010,
 100         .syss_offs      = 0x0014,
 101         .sysc_flags     = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 102                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 103                            SYSS_HAS_RESET_STATUS),
 104         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 105         .sysc_fields    = &omap_hwmod_sysc_type1,
 106 };
 107
 108 struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
 109         .name = "gpio",
 110         .sysc = &omap2xxx_gpio_sysc,
 111         .rev = 0,
 112 };
 113
 114 /* system dma */
 115 static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
 116         .rev_offs       = 0x0000,
 117         .sysc_offs      = 0x002c,
 118         .syss_offs      = 0x0028,
 119         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
 120                            SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
 121                            SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 122         .idlemodes      = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 123         .sysc_fields    = &omap_hwmod_sysc_type1,
 124 };
 125
 126 struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
 127         .name   = "dma",
 128         .sysc   = &omap2xxx_dma_sysc,
 129 };
 130
 131 /*
 132  * 'mailbox' class
 133  * mailbox module allowing communication between the on-chip processors
 134  * using a queued mailbox-interrupt mechanism.
 135  */
 136
 137 static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
 138         .rev_offs       = 0x000,
 139         .sysc_offs      = 0x010,
 140         .syss_offs      = 0x014,
 141         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 142                            SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
 143         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 144         .sysc_fields    = &omap_hwmod_sysc_type1,
 145 };
 146
 147 struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
 148         .name   = "mailbox",
 149         .sysc   = &omap2xxx_mailbox_sysc,
 150 };
 151
 152 /*
 153  * 'mcspi' class
 154  * multichannel serial port interface (mcspi) / master/slave synchronous serial
 155  * bus
 156  */
 157
 158 static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
 159         .rev_offs       = 0x0000,
 160         .sysc_offs      = 0x0010,
 161         .syss_offs      = 0x0014,
 162         .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
 163                                 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
 164                                 SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
 165         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 166         .sysc_fields    = &omap_hwmod_sysc_type1,
 167 };
 168
 169 struct omap_hwmod_class omap2xxx_mcspi_class = {
 170         .name   = "mcspi",
 171         .sysc   = &omap2xxx_mcspi_sysc,
 172         .rev    = OMAP2_MCSPI_REV,
 173 };
 174
 175 /*
 176  * 'gpmc' class
 177  * general purpose memory controller
 178  */
 179
 180 static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
 181         .rev_offs       = 0x0000,
 182         .sysc_offs      = 0x0010,
 183         .syss_offs      = 0x0014,
 184         .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 185                            SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 186         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 187         .sysc_fields    = &omap_hwmod_sysc_type1,
 188 };
 189
 190 static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
 191         .name   = "gpmc",
 192         .sysc   = &omap2xxx_gpmc_sysc,
 193 };
 194
 195 /*
 196  * IP blocks
 197  */
 198
 199 /* L3 */
 200 struct omap_hwmod omap2xxx_l3_main_hwmod = {
 201         .name           = "l3_main",
 202         .class          = &l3_hwmod_class,
 203         .flags          = HWMOD_NO_IDLEST,
 204 };
 205
 206 /* L4 CORE */
 207 struct omap_hwmod omap2xxx_l4_core_hwmod = {
 208         .name           = "l4_core",
 209         .class          = &l4_hwmod_class,
 210         .flags          = HWMOD_NO_IDLEST,
 211 };
 212
 213 /* L4 WKUP */
 214 struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 215         .name           = "l4_wkup",
 216         .class          = &l4_hwmod_class,
 217         .flags          = HWMOD_NO_IDLEST,
 218 };
 219
 220 /* MPU */
 221 static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
 222         { .name = "pmu", .irq = 3 + OMAP_INTC_START },
 223         { .irq = -1 }
 224 };
 225
 226 struct omap_hwmod omap2xxx_mpu_hwmod = {
 227         .name           = "mpu",
 228         .mpu_irqs       = omap2xxx_mpu_irqs,
 229         .class          = &mpu_hwmod_class,
 230         .main_clk       = "mpu_ck",
 231 };
 232
 233 /* IVA2 */
 234 struct omap_hwmod omap2xxx_iva_hwmod = {
 235         .name           = "iva",
 236         .class          = &iva_hwmod_class,
 237 };
 238
 239 /* always-on timers dev attribute */
 240 static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = {
 241         .timer_capability       = OMAP_TIMER_ALWON,
 242 };
 243
 244 /* pwm timers dev attribute */
 245 static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 246         .timer_capability       = OMAP_TIMER_HAS_PWM,
 247 };
 248
 249 /* timers with DSP interrupt dev attribute */
 250 static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
 251         .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
 252 };
 253
 254 /* timer1 */
 255
 256 struct omap_hwmod omap2xxx_timer1_hwmod = {
 257         .name           = "timer1",
 258         .mpu_irqs       = omap2_timer1_mpu_irqs,
 259         .main_clk       = "gpt1_fck",
 260         .prcm           = {
 261                 .omap2 = {
 262                         .prcm_reg_id = 1,
 263                         .module_bit = OMAP24XX_EN_GPT1_SHIFT,
 264                         .module_offs = WKUP_MOD,
 265                         .idlest_reg_id = 1,
 266                         .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
 267                 },
 268         },
 269         .dev_attr       = &capability_alwon_dev_attr,
 270         .class          = &omap2xxx_timer_hwmod_class,
 271 };
 272
 273 /* timer2 */
 274
 275 struct omap_hwmod omap2xxx_timer2_hwmod = {
 276         .name           = "timer2",
 277         .mpu_irqs       = omap2_timer2_mpu_irqs,
 278         .main_clk       = "gpt2_fck",
 279         .prcm           = {
 280                 .omap2 = {
 281                         .prcm_reg_id = 1,
 282                         .module_bit = OMAP24XX_EN_GPT2_SHIFT,
 283                         .module_offs = CORE_MOD,
 284                         .idlest_reg_id = 1,
 285                         .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
 286                 },
 287         },
 288         .class          = &omap2xxx_timer_hwmod_class,
 289 };
 290
 291 /* timer3 */
 292
 293 struct omap_hwmod omap2xxx_timer3_hwmod = {
 294         .name           = "timer3",
 295         .mpu_irqs       = omap2_timer3_mpu_irqs,
 296         .main_clk       = "gpt3_fck",
 297         .prcm           = {
 298                 .omap2 = {
 299                         .prcm_reg_id = 1,
 300                         .module_bit = OMAP24XX_EN_GPT3_SHIFT,
 301                         .module_offs = CORE_MOD,
 302                         .idlest_reg_id = 1,
 303                         .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
 304                 },
 305         },
 306         .class          = &omap2xxx_timer_hwmod_class,
 307 };
 308
 309 /* timer4 */
 310
 311 struct omap_hwmod omap2xxx_timer4_hwmod = {
 312         .name           = "timer4",
 313         .mpu_irqs       = omap2_timer4_mpu_irqs,
 314         .main_clk       = "gpt4_fck",
 315         .prcm           = {
 316                 .omap2 = {
 317                         .prcm_reg_id = 1,
 318                         .module_bit = OMAP24XX_EN_GPT4_SHIFT,
 319                         .module_offs = CORE_MOD,
 320                         .idlest_reg_id = 1,
 321                         .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
 322                 },
 323         },
 324         .class          = &omap2xxx_timer_hwmod_class,
 325 };
 326
 327 /* timer5 */
 328
 329 struct omap_hwmod omap2xxx_timer5_hwmod = {
 330         .name           = "timer5",
 331         .mpu_irqs       = omap2_timer5_mpu_irqs,
 332         .main_clk       = "gpt5_fck",
 333         .prcm           = {
 334                 .omap2 = {
 335                         .prcm_reg_id = 1,
 336                         .module_bit = OMAP24XX_EN_GPT5_SHIFT,
 337                         .module_offs = CORE_MOD,
 338                         .idlest_reg_id = 1,
 339                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
 340                 },
 341         },
 342         .dev_attr       = &capability_dsp_dev_attr,
 343         .class          = &omap2xxx_timer_hwmod_class,
 344 };
 345
 346 /* timer6 */
 347
 348 struct omap_hwmod omap2xxx_timer6_hwmod = {
 349         .name           = "timer6",
 350         .mpu_irqs       = omap2_timer6_mpu_irqs,
 351         .main_clk       = "gpt6_fck",
 352         .prcm           = {
 353                 .omap2 = {
 354                         .prcm_reg_id = 1,
 355                         .module_bit = OMAP24XX_EN_GPT6_SHIFT,
 356                         .module_offs = CORE_MOD,
 357                         .idlest_reg_id = 1,
 358                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
 359                 },
 360         },
 361         .dev_attr       = &capability_dsp_dev_attr,
 362         .class          = &omap2xxx_timer_hwmod_class,
 363 };
 364
 365 /* timer7 */
 366
 367 struct omap_hwmod omap2xxx_timer7_hwmod = {
 368         .name           = "timer7",
 369         .mpu_irqs       = omap2_timer7_mpu_irqs,
 370         .main_clk       = "gpt7_fck",
 371         .prcm           = {
 372                 .omap2 = {
 373                         .prcm_reg_id = 1,
 374                         .module_bit = OMAP24XX_EN_GPT7_SHIFT,
 375                         .module_offs = CORE_MOD,
 376                         .idlest_reg_id = 1,
 377                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
 378                 },
 379         },
 380         .dev_attr       = &capability_dsp_dev_attr,
 381         .class          = &omap2xxx_timer_hwmod_class,
 382 };
 383
 384 /* timer8 */
 385
 386 struct omap_hwmod omap2xxx_timer8_hwmod = {
 387         .name           = "timer8",
 388         .mpu_irqs       = omap2_timer8_mpu_irqs,
 389         .main_clk       = "gpt8_fck",
 390         .prcm           = {
 391                 .omap2 = {
 392                         .prcm_reg_id = 1,
 393                         .module_bit = OMAP24XX_EN_GPT8_SHIFT,
 394                         .module_offs = CORE_MOD,
 395                         .idlest_reg_id = 1,
 396                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
 397                 },
 398         },
 399         .dev_attr       = &capability_dsp_dev_attr,
 400         .class          = &omap2xxx_timer_hwmod_class,
 401 };
 402
 403 /* timer9 */
 404
 405 struct omap_hwmod omap2xxx_timer9_hwmod = {
 406         .name           = "timer9",
 407         .mpu_irqs       = omap2_timer9_mpu_irqs,
 408         .main_clk       = "gpt9_fck",
 409         .prcm           = {
 410                 .omap2 = {
 411                         .prcm_reg_id = 1,
 412                         .module_bit = OMAP24XX_EN_GPT9_SHIFT,
 413                         .module_offs = CORE_MOD,
 414                         .idlest_reg_id = 1,
 415                         .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
 416                 },
 417         },
 418         .dev_attr       = &capability_pwm_dev_attr,
 419         .class          = &omap2xxx_timer_hwmod_class,
 420 };
 421
 422 /* timer10 */
 423
 424 struct omap_hwmod omap2xxx_timer10_hwmod = {
 425         .name           = "timer10",
 426         .mpu_irqs       = omap2_timer10_mpu_irqs,
 427         .main_clk       = "gpt10_fck",
 428         .prcm           = {
 429                 .omap2 = {
 430                         .prcm_reg_id = 1,
 431                         .module_bit = OMAP24XX_EN_GPT10_SHIFT,
 432                         .module_offs = CORE_MOD,
 433                         .idlest_reg_id = 1,
 434                         .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
 435                 },
 436         },
 437         .dev_attr       = &capability_pwm_dev_attr,
 438         .class          = &omap2xxx_timer_hwmod_class,
 439 };
 440
 441 /* timer11 */
 442
 443 struct omap_hwmod omap2xxx_timer11_hwmod = {
 444         .name           = "timer11",
 445         .mpu_irqs       = omap2_timer11_mpu_irqs,
 446         .main_clk       = "gpt11_fck",
 447         .prcm           = {
 448                 .omap2 = {
 449                         .prcm_reg_id = 1,
 450                         .module_bit = OMAP24XX_EN_GPT11_SHIFT,
 451                         .module_offs = CORE_MOD,
 452                         .idlest_reg_id = 1,
 453                         .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
 454                 },
 455         },
 456         .dev_attr       = &capability_pwm_dev_attr,
 457         .class          = &omap2xxx_timer_hwmod_class,
 458 };
 459
 460 /* timer12 */
 461
 462 struct omap_hwmod omap2xxx_timer12_hwmod = {
 463         .name           = "timer12",
 464         .mpu_irqs       = omap2xxx_timer12_mpu_irqs,
 465         .main_clk       = "gpt12_fck",
 466         .prcm           = {
 467                 .omap2 = {
 468                         .prcm_reg_id = 1,
 469                         .module_bit = OMAP24XX_EN_GPT12_SHIFT,
 470                         .module_offs = CORE_MOD,
 471                         .idlest_reg_id = 1,
 472                         .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
 473                 },
 474         },
 475         .dev_attr       = &capability_pwm_dev_attr,
 476         .class          = &omap2xxx_timer_hwmod_class,
 477 };
 478
 479 /* wd_timer2 */
 480 struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
 481         .name           = "wd_timer2",
 482         .class          = &omap2xxx_wd_timer_hwmod_class,
 483         .main_clk       = "mpu_wdt_fck",
 484         .prcm           = {
 485                 .omap2 = {
 486                         .prcm_reg_id = 1,
 487                         .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
 488                         .module_offs = WKUP_MOD,
 489                         .idlest_reg_id = 1,
 490                         .idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
 491                 },
 492         },
 493 };
 494
 495 /* UART1 */
 496
 497 struct omap_hwmod omap2xxx_uart1_hwmod = {
 498         .name           = "uart1",
 499         .mpu_irqs       = omap2_uart1_mpu_irqs,
 500         .sdma_reqs      = omap2_uart1_sdma_reqs,
 501         .main_clk       = "uart1_fck",
 502         .prcm           = {
 503                 .omap2 = {
 504                         .module_offs = CORE_MOD,
 505                         .prcm_reg_id = 1,
 506                         .module_bit = OMAP24XX_EN_UART1_SHIFT,
 507                         .idlest_reg_id = 1,
 508                         .idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
 509                 },
 510         },
 511         .class          = &omap2_uart_class,
 512 };
 513
 514 /* UART2 */
 515
 516 struct omap_hwmod omap2xxx_uart2_hwmod = {
 517         .name           = "uart2",
 518         .mpu_irqs       = omap2_uart2_mpu_irqs,
 519         .sdma_reqs      = omap2_uart2_sdma_reqs,
 520         .main_clk       = "uart2_fck",
 521         .prcm           = {
 522                 .omap2 = {
 523                         .module_offs = CORE_MOD,
 524                         .prcm_reg_id = 1,
 525                         .module_bit = OMAP24XX_EN_UART2_SHIFT,
 526                         .idlest_reg_id = 1,
 527                         .idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
 528                 },
 529         },
 530         .class          = &omap2_uart_class,
 531 };
 532
 533 /* UART3 */
 534
 535 struct omap_hwmod omap2xxx_uart3_hwmod = {
 536         .name           = "uart3",
 537         .mpu_irqs       = omap2_uart3_mpu_irqs,
 538         .sdma_reqs      = omap2_uart3_sdma_reqs,
 539         .main_clk       = "uart3_fck",
 540         .prcm           = {
 541                 .omap2 = {
 542                         .module_offs = CORE_MOD,
 543                         .prcm_reg_id = 2,
 544                         .module_bit = OMAP24XX_EN_UART3_SHIFT,
 545                         .idlest_reg_id = 2,
 546                         .idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
 547                 },
 548         },
 549         .class          = &omap2_uart_class,
 550 };
 551
 552 /* dss */
 553
 554 static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 555         /*
 556          * The DSS HW needs all DSS clocks enabled during reset. The dss_core
 557          * driver does not use these clocks.
 558          */
 559         { .role = "tv_clk", .clk = "dss_54m_fck" },
 560         { .role = "sys_clk", .clk = "dss2_fck" },
 561 };
 562
 563 struct omap_hwmod omap2xxx_dss_core_hwmod = {
 564         .name           = "dss_core",
 565         .class          = &omap2_dss_hwmod_class,
 566         .main_clk       = "dss1_fck", /* instead of dss_fck */
 567         .sdma_reqs      = omap2xxx_dss_sdma_chs,
 568         .prcm           = {
 569                 .omap2 = {
 570                         .prcm_reg_id = 1,
 571                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 572                         .module_offs = CORE_MOD,
 573                         .idlest_reg_id = 1,
 574                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 575                 },
 576         },
 577         .opt_clks       = dss_opt_clks,
 578         .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
 579         .flags          = HWMOD_NO_IDLEST | HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 580 };
 581
 582 struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
 583         .name           = "dss_dispc",
 584         .class          = &omap2_dispc_hwmod_class,
 585         .mpu_irqs       = omap2_dispc_irqs,
 586         .main_clk       = "dss1_fck",
 587         .prcm           = {
 588                 .omap2 = {
 589                         .prcm_reg_id = 1,
 590                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 591                         .module_offs = CORE_MOD,
 592                         .idlest_reg_id = 1,
 593                         .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
 594                 },
 595         },
 596         .flags          = HWMOD_NO_IDLEST,
 597         .dev_attr       = &omap2_3_dss_dispc_dev_attr
 598 };
 599
 600 static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 601         { .role = "ick", .clk = "dss_ick" },
 602 };
 603
 604 struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
 605         .name           = "dss_rfbi",
 606         .class          = &omap2_rfbi_hwmod_class,
 607         .main_clk       = "dss1_fck",
 608         .prcm           = {
 609                 .omap2 = {
 610                         .prcm_reg_id = 1,
 611                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 612                         .module_offs = CORE_MOD,
 613                 },
 614         },
 615         .opt_clks       = dss_rfbi_opt_clks,
 616         .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
 617         .flags          = HWMOD_NO_IDLEST,
 618 };
 619
 620 struct omap_hwmod omap2xxx_dss_venc_hwmod = {
 621         .name           = "dss_venc",
 622         .class          = &omap2_venc_hwmod_class,
 623         .main_clk       = "dss_54m_fck",
 624         .prcm           = {
 625                 .omap2 = {
 626                         .prcm_reg_id = 1,
 627                         .module_bit = OMAP24XX_EN_DSS1_SHIFT,
 628                         .module_offs = CORE_MOD,
 629                 },
 630         },
 631         .flags          = HWMOD_NO_IDLEST,
 632 };
 633
 634 /* gpio dev_attr */
 635 struct omap_gpio_dev_attr omap2xxx_gpio_dev_attr = {
 636         .bank_width = 32,
 637         .dbck_flag = false,
 638 };
 639
 640 /* gpio1 */
 641 struct omap_hwmod omap2xxx_gpio1_hwmod = {
 642         .name           = "gpio1",
 643         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 644         .mpu_irqs       = omap2_gpio1_irqs,
 645         .main_clk       = "gpios_fck",
 646         .prcm           = {
 647                 .omap2 = {
 648                         .prcm_reg_id = 1,
 649                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 650                         .module_offs = WKUP_MOD,
 651                         .idlest_reg_id = 1,
 652                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 653                 },
 654         },
 655         .class          = &omap2xxx_gpio_hwmod_class,
 656         .dev_attr       = &omap2xxx_gpio_dev_attr,
 657 };
 658
 659 /* gpio2 */
 660 struct omap_hwmod omap2xxx_gpio2_hwmod = {
 661         .name           = "gpio2",
 662         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 663         .mpu_irqs       = omap2_gpio2_irqs,
 664         .main_clk       = "gpios_fck",
 665         .prcm           = {
 666                 .omap2 = {
 667                         .prcm_reg_id = 1,
 668                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 669                         .module_offs = WKUP_MOD,
 670                         .idlest_reg_id = 1,
 671                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 672                 },
 673         },
 674         .class          = &omap2xxx_gpio_hwmod_class,
 675         .dev_attr       = &omap2xxx_gpio_dev_attr,
 676 };
 677
 678 /* gpio3 */
 679 struct omap_hwmod omap2xxx_gpio3_hwmod = {
 680         .name           = "gpio3",
 681         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 682         .mpu_irqs       = omap2_gpio3_irqs,
 683         .main_clk       = "gpios_fck",
 684         .prcm           = {
 685                 .omap2 = {
 686                         .prcm_reg_id = 1,
 687                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 688                         .module_offs = WKUP_MOD,
 689                         .idlest_reg_id = 1,
 690                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 691                 },
 692         },
 693         .class          = &omap2xxx_gpio_hwmod_class,
 694         .dev_attr       = &omap2xxx_gpio_dev_attr,
 695 };
 696
 697 /* gpio4 */
 698 struct omap_hwmod omap2xxx_gpio4_hwmod = {
 699         .name           = "gpio4",
 700         .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 701         .mpu_irqs       = omap2_gpio4_irqs,
 702         .main_clk       = "gpios_fck",
 703         .prcm           = {
 704                 .omap2 = {
 705                         .prcm_reg_id = 1,
 706                         .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
 707                         .module_offs = WKUP_MOD,
 708                         .idlest_reg_id = 1,
 709                         .idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
 710                 },
 711         },
 712         .class          = &omap2xxx_gpio_hwmod_class,
 713         .dev_attr       = &omap2xxx_gpio_dev_attr,
 714 };
 715
 716 /* mcspi1 */
 717 static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
 718         .num_chipselect = 4,
 719 };
 720
 721 struct omap_hwmod omap2xxx_mcspi1_hwmod = {
 722         .name           = "mcspi1",
 723         .mpu_irqs       = omap2_mcspi1_mpu_irqs,
 724         .sdma_reqs      = omap2_mcspi1_sdma_reqs,
 725         .main_clk       = "mcspi1_fck",
 726         .prcm           = {
 727                 .omap2 = {
 728                         .module_offs = CORE_MOD,
 729                         .prcm_reg_id = 1,
 730                         .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
 731                         .idlest_reg_id = 1,
 732                         .idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
 733                 },
 734         },
 735         .class          = &omap2xxx_mcspi_class,
 736         .dev_attr       = &omap_mcspi1_dev_attr,
 737 };
 738
 739 /* mcspi2 */
 740 static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
 741         .num_chipselect = 2,
 742 };
 743
 744 struct omap_hwmod omap2xxx_mcspi2_hwmod = {
 745         .name           = "mcspi2",
 746         .mpu_irqs       = omap2_mcspi2_mpu_irqs,
 747         .sdma_reqs      = omap2_mcspi2_sdma_reqs,
 748         .main_clk       = "mcspi2_fck",
 749         .prcm           = {
 750                 .omap2 = {
 751                         .module_offs = CORE_MOD,
 752                         .prcm_reg_id = 1,
 753                         .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
 754                         .idlest_reg_id = 1,
 755                         .idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
 756                 },
 757         },
 758         .class          = &omap2xxx_mcspi_class,
 759         .dev_attr       = &omap_mcspi2_dev_attr,
 760 };
 761
 762 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
 763         .name   = "counter",
 764 };
 765
 766 struct omap_hwmod omap2xxx_counter_32k_hwmod = {
 767         .name           = "counter_32k",
 768         .main_clk       = "func_32k_ck",
 769         .prcm           = {
 770                 .omap2  = {
 771                         .module_offs = WKUP_MOD,
 772                         .prcm_reg_id = 1,
 773                         .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 774                         .idlest_reg_id = 1,
 775                         .idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
 776                 },
 777         },
 778         .class          = &omap2xxx_counter_hwmod_class,
 779 };
 780
 781 /* gpmc */
 782 static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
 783         { .irq = 20 },
 784         { .irq = -1 }
 785 };
 786
 787 struct omap_hwmod omap2xxx_gpmc_hwmod = {
 788         .name           = "gpmc",
 789         .class          = &omap2xxx_gpmc_hwmod_class,
 790         .mpu_irqs       = omap2xxx_gpmc_irqs,
 791         .main_clk       = "gpmc_fck",
 792         /*
 793          * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
 794          * block.  It is not being added due to any known bugs with
 795          * resetting the GPMC IP block, but rather because any timings
 796          * set by the bootloader are not being correctly programmed by
 797          * the kernel from the board file or DT data.
 798          * HWMOD_INIT_NO_RESET should be removed ASAP.
 799          */
 800         .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
 801                            HWMOD_NO_IDLEST),
 802         .prcm           = {
 803                 .omap2  = {
 804                         .prcm_reg_id = 3,
 805                         .module_bit = OMAP24XX_EN_GPMC_MASK,
 806                         .module_offs = CORE_MOD,
 807                 },
 808         },
 809 };
 810
 811 /* RNG */
 812
 813 static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
 814         .rev_offs       = 0x3c,
 815         .sysc_offs      = 0x40,
 816         .syss_offs      = 0x44,
 817         .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
 818                            SYSS_HAS_RESET_STATUS),
 819         .sysc_fields    = &omap_hwmod_sysc_type1,
 820 };
 821
 822 static struct omap_hwmod_class omap2_rng_hwmod_class = {
 823         .name           = "rng",
 824         .sysc           = &omap2_rng_sysc,
 825 };
 826
 827 static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
 828         { .irq = 52 },
 829         { .irq = -1 }
 830 };
 831
 832 struct omap_hwmod omap2xxx_rng_hwmod = {
 833         .name           = "rng",
 834         .mpu_irqs       = omap2_rng_mpu_irqs,
 835         .main_clk       = "l4_ck",
 836         .prcm           = {
 837                 .omap2 = {
 838                         .module_offs = CORE_MOD,
 839                         .prcm_reg_id = 4,
 840                         .module_bit = OMAP24XX_EN_RNG_SHIFT,
 841                         .idlest_reg_id = 4,
 842                         .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
 843                 },
 844         },
 845         /*
 846          * XXX The first read from the SYSSTATUS register of the RNG
 847          * after the SYSCONFIG SOFTRESET bit is set triggers an
 848          * imprecise external abort.  It's unclear why this happens.
 849          * Until this is analyzed, skip the IP block reset.
 850          */
 851         .flags          = HWMOD_INIT_NO_RESET,
 852         .class          = &omap2_rng_hwmod_class,
 853 };