2 * 8259 interrupt controller emulation
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2007 Intel Corporation
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com>
29 #include <linux/slab.h>
30 #include <linux/bitops.h>
33 #include <linux/kvm_host.h>
36 static void pic_lock(struct kvm_pic
*s
)
39 raw_spin_lock(&s
->lock
);
42 static void pic_unlock(struct kvm_pic
*s
)
45 bool wakeup
= s
->wakeup_needed
;
46 struct kvm_vcpu
*vcpu
;
48 s
->wakeup_needed
= false;
50 raw_spin_unlock(&s
->lock
);
53 vcpu
= s
->kvm
->bsp_vcpu
;
59 static void pic_clear_isr(struct kvm_kpic_state
*s
, int irq
)
61 s
->isr
&= ~(1 << irq
);
62 s
->isr_ack
|= (1 << irq
);
63 if (s
!= &s
->pics_state
->pics
[0])
66 * We are dropping lock while calling ack notifiers since ack
67 * notifier callbacks for assigned devices call into PIC recursively.
68 * Other interrupt may be delivered to PIC while lock is dropped but
69 * it should be safe since PIC state is already updated at this stage.
71 pic_unlock(s
->pics_state
);
72 kvm_notify_acked_irq(s
->pics_state
->kvm
, SELECT_PIC(irq
), irq
);
73 pic_lock(s
->pics_state
);
76 void kvm_pic_clear_isr_ack(struct kvm
*kvm
)
78 struct kvm_pic
*s
= pic_irqchip(kvm
);
81 s
->pics
[0].isr_ack
= 0xff;
82 s
->pics
[1].isr_ack
= 0xff;
87 * set irq level. If an edge is detected, then the IRR is set to 1
89 static inline int pic_set_irq1(struct kvm_kpic_state
*s
, int irq
, int level
)
93 if (s
->elcr
& mask
) /* level triggered */
95 ret
= !(s
->irr
& mask
);
100 s
->last_irr
&= ~mask
;
102 else /* edge triggered */
104 if ((s
->last_irr
& mask
) == 0) {
105 ret
= !(s
->irr
& mask
);
110 s
->last_irr
&= ~mask
;
112 return (s
->imr
& mask
) ? -1 : ret
;
116 * return the highest priority found in mask (highest = smallest
117 * number). Return 8 if no irq
119 static inline int get_priority(struct kvm_kpic_state
*s
, int mask
)
125 while ((mask
& (1 << ((priority
+ s
->priority_add
) & 7))) == 0)
131 * return the pic wanted interrupt. return -1 if none
133 static int pic_get_irq(struct kvm_kpic_state
*s
)
135 int mask
, cur_priority
, priority
;
137 mask
= s
->irr
& ~s
->imr
;
138 priority
= get_priority(s
, mask
);
142 * compute current priority. If special fully nested mode on the
143 * master, the IRQ coming from the slave is not taken into account
144 * for the priority computation.
147 if (s
->special_fully_nested_mode
&& s
== &s
->pics_state
->pics
[0])
149 cur_priority
= get_priority(s
, mask
);
150 if (priority
< cur_priority
)
152 * higher priority found: an irq should be generated
154 return (priority
+ s
->priority_add
) & 7;
160 * raise irq to CPU if necessary. must be called every time the active
163 static void pic_update_irq(struct kvm_pic
*s
)
167 irq2
= pic_get_irq(&s
->pics
[1]);
170 * if irq request by slave pic, signal master PIC
172 pic_set_irq1(&s
->pics
[0], 2, 1);
173 pic_set_irq1(&s
->pics
[0], 2, 0);
175 irq
= pic_get_irq(&s
->pics
[0]);
177 s
->irq_request(s
->irq_request_opaque
, 1);
179 s
->irq_request(s
->irq_request_opaque
, 0);
182 void kvm_pic_update_irq(struct kvm_pic
*s
)
189 int kvm_pic_set_irq(void *opaque
, int irq
, int level
)
191 struct kvm_pic
*s
= opaque
;
195 if (irq
>= 0 && irq
< PIC_NUM_PINS
) {
196 ret
= pic_set_irq1(&s
->pics
[irq
>> 3], irq
& 7, level
);
198 trace_kvm_pic_set_irq(irq
>> 3, irq
& 7, s
->pics
[irq
>> 3].elcr
,
199 s
->pics
[irq
>> 3].imr
, ret
== 0);
207 * acknowledge interrupt 'irq'
209 static inline void pic_intack(struct kvm_kpic_state
*s
, int irq
)
213 * We don't clear a level sensitive interrupt here
215 if (!(s
->elcr
& (1 << irq
)))
216 s
->irr
&= ~(1 << irq
);
219 if (s
->rotate_on_auto_eoi
)
220 s
->priority_add
= (irq
+ 1) & 7;
221 pic_clear_isr(s
, irq
);
226 int kvm_pic_read_irq(struct kvm
*kvm
)
228 int irq
, irq2
, intno
;
229 struct kvm_pic
*s
= pic_irqchip(kvm
);
232 irq
= pic_get_irq(&s
->pics
[0]);
234 pic_intack(&s
->pics
[0], irq
);
236 irq2
= pic_get_irq(&s
->pics
[1]);
238 pic_intack(&s
->pics
[1], irq2
);
241 * spurious IRQ on slave controller
244 intno
= s
->pics
[1].irq_base
+ irq2
;
247 intno
= s
->pics
[0].irq_base
+ irq
;
250 * spurious IRQ on host controller
253 intno
= s
->pics
[0].irq_base
+ irq
;
261 void kvm_pic_reset(struct kvm_kpic_state
*s
)
264 struct kvm
*kvm
= s
->pics_state
->irq_request_opaque
;
265 struct kvm_vcpu
*vcpu0
= kvm
->bsp_vcpu
;
266 u8 irr
= s
->irr
, isr
= s
->imr
;
275 s
->read_reg_select
= 0;
280 s
->rotate_on_auto_eoi
= 0;
281 s
->special_fully_nested_mode
= 0;
284 for (irq
= 0; irq
< PIC_NUM_PINS
/2; irq
++) {
285 if (vcpu0
&& kvm_apic_accept_pic_intr(vcpu0
))
286 if (irr
& (1 << irq
) || isr
& (1 << irq
)) {
287 pic_clear_isr(s
, irq
);
292 static void pic_ioport_write(void *opaque
, u32 addr
, u32 val
)
294 struct kvm_kpic_state
*s
= opaque
;
295 int priority
, cmd
, irq
;
300 kvm_pic_reset(s
); /* init */
302 * deassert a pending interrupt
304 s
->pics_state
->irq_request(s
->pics_state
->
305 irq_request_opaque
, 0);
309 printk(KERN_ERR
"single mode not supported");
312 "level sensitive irq not supported");
313 } else if (val
& 0x08) {
317 s
->read_reg_select
= val
& 1;
319 s
->special_mask
= (val
>> 5) & 1;
325 s
->rotate_on_auto_eoi
= cmd
>> 2;
327 case 1: /* end of interrupt */
329 priority
= get_priority(s
, s
->isr
);
331 irq
= (priority
+ s
->priority_add
) & 7;
333 s
->priority_add
= (irq
+ 1) & 7;
334 pic_clear_isr(s
, irq
);
335 pic_update_irq(s
->pics_state
);
340 pic_clear_isr(s
, irq
);
341 pic_update_irq(s
->pics_state
);
344 s
->priority_add
= (val
+ 1) & 7;
345 pic_update_irq(s
->pics_state
);
349 s
->priority_add
= (irq
+ 1) & 7;
350 pic_clear_isr(s
, irq
);
351 pic_update_irq(s
->pics_state
);
354 break; /* no operation */
358 switch (s
->init_state
) {
359 case 0: /* normal mode */
361 pic_update_irq(s
->pics_state
);
364 s
->irq_base
= val
& 0xf8;
374 s
->special_fully_nested_mode
= (val
>> 4) & 1;
375 s
->auto_eoi
= (val
>> 1) & 1;
381 static u32
pic_poll_read(struct kvm_kpic_state
*s
, u32 addr1
)
385 ret
= pic_get_irq(s
);
388 s
->pics_state
->pics
[0].isr
&= ~(1 << 2);
389 s
->pics_state
->pics
[0].irr
&= ~(1 << 2);
391 s
->irr
&= ~(1 << ret
);
392 pic_clear_isr(s
, ret
);
393 if (addr1
>> 7 || ret
!= 2)
394 pic_update_irq(s
->pics_state
);
397 pic_update_irq(s
->pics_state
);
403 static u32
pic_ioport_read(void *opaque
, u32 addr1
)
405 struct kvm_kpic_state
*s
= opaque
;
412 ret
= pic_poll_read(s
, addr1
);
416 if (s
->read_reg_select
)
425 static void elcr_ioport_write(void *opaque
, u32 addr
, u32 val
)
427 struct kvm_kpic_state
*s
= opaque
;
428 s
->elcr
= val
& s
->elcr_mask
;
431 static u32
elcr_ioport_read(void *opaque
, u32 addr1
)
433 struct kvm_kpic_state
*s
= opaque
;
437 static int picdev_in_range(gpa_t addr
)
452 static inline struct kvm_pic
*to_pic(struct kvm_io_device
*dev
)
454 return container_of(dev
, struct kvm_pic
, dev
);
457 static int picdev_write(struct kvm_io_device
*this,
458 gpa_t addr
, int len
, const void *val
)
460 struct kvm_pic
*s
= to_pic(this);
461 unsigned char data
= *(unsigned char *)val
;
462 if (!picdev_in_range(addr
))
466 if (printk_ratelimit())
467 printk(KERN_ERR
"PIC: non byte write\n");
476 pic_ioport_write(&s
->pics
[addr
>> 7], addr
, data
);
480 elcr_ioport_write(&s
->pics
[addr
& 1], addr
, data
);
487 static int picdev_read(struct kvm_io_device
*this,
488 gpa_t addr
, int len
, void *val
)
490 struct kvm_pic
*s
= to_pic(this);
491 unsigned char data
= 0;
492 if (!picdev_in_range(addr
))
496 if (printk_ratelimit())
497 printk(KERN_ERR
"PIC: non byte read\n");
506 data
= pic_ioport_read(&s
->pics
[addr
>> 7], addr
);
510 data
= elcr_ioport_read(&s
->pics
[addr
& 1], addr
);
513 *(unsigned char *)val
= data
;
519 * callback when PIC0 irq status changed
521 static void pic_irq_request(void *opaque
, int level
)
523 struct kvm
*kvm
= opaque
;
524 struct kvm_vcpu
*vcpu
= kvm
->bsp_vcpu
;
525 struct kvm_pic
*s
= pic_irqchip(kvm
);
526 int irq
= pic_get_irq(&s
->pics
[0]);
529 if (vcpu
&& level
&& (s
->pics
[0].isr_ack
& (1 << irq
))) {
530 s
->pics
[0].isr_ack
&= ~(1 << irq
);
531 s
->wakeup_needed
= true;
535 static const struct kvm_io_device_ops picdev_ops
= {
537 .write
= picdev_write
,
540 struct kvm_pic
*kvm_create_pic(struct kvm
*kvm
)
545 s
= kzalloc(sizeof(struct kvm_pic
), GFP_KERNEL
);
548 raw_spin_lock_init(&s
->lock
);
550 s
->pics
[0].elcr_mask
= 0xf8;
551 s
->pics
[1].elcr_mask
= 0xde;
552 s
->irq_request
= pic_irq_request
;
553 s
->irq_request_opaque
= kvm
;
554 s
->pics
[0].pics_state
= s
;
555 s
->pics
[1].pics_state
= s
;
558 * Initialize PIO device
560 kvm_iodevice_init(&s
->dev
, &picdev_ops
);
561 mutex_lock(&kvm
->slots_lock
);
562 ret
= kvm_io_bus_register_dev(kvm
, KVM_PIO_BUS
, &s
->dev
);
563 mutex_unlock(&kvm
->slots_lock
);
572 void kvm_destroy_pic(struct kvm
*kvm
)
574 struct kvm_pic
*vpic
= kvm
->arch
.vpic
;
577 kvm_io_bus_unregister_dev(kvm
, KVM_PIO_BUS
, &vpic
->dev
);
578 kvm
->arch
.vpic
= NULL
;