arch/sh/kernel/cpu/sh4a/setup-sh7785.c

   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16 #include <linux/sh_timer.h>
  17
  18 #include <asm/dmaengine.h>
  19 #include <asm/mmzone.h>
  20
  21 #include <cpu/dma-register.h>
  22
  23 static struct plat_sci_port scif0_platform_data = {
  24         .mapbase        = 0xffea0000,
  25         .flags          = UPF_BOOT_AUTOCONF,
  26         .type           = PORT_SCIF,
  27         .irqs           = { 40, 40, 40, 40 },
  28         .clk            = "scif_fck",
  29 };
  30
  31 static struct platform_device scif0_device = {
  32         .name           = "sh-sci",
  33         .id             = 0,
  34         .dev            = {
  35                 .platform_data  = &scif0_platform_data,
  36         },
  37 };
  38
  39 static struct plat_sci_port scif1_platform_data = {
  40         .mapbase        = 0xffeb0000,
  41         .flags          = UPF_BOOT_AUTOCONF,
  42         .type           = PORT_SCIF,
  43         .irqs           = { 44, 44, 44, 44 },
  44         .clk            = "scif_fck",
  45 };
  46
  47 static struct platform_device scif1_device = {
  48         .name           = "sh-sci",
  49         .id             = 1,
  50         .dev            = {
  51                 .platform_data  = &scif1_platform_data,
  52         },
  53 };
  54
  55 static struct plat_sci_port scif2_platform_data = {
  56         .mapbase        = 0xffec0000,
  57         .flags          = UPF_BOOT_AUTOCONF,
  58         .type           = PORT_SCIF,
  59         .irqs           = { 60, 60, 60, 60 },
  60         .clk            = "scif_fck",
  61 };
  62
  63 static struct platform_device scif2_device = {
  64         .name           = "sh-sci",
  65         .id             = 2,
  66         .dev            = {
  67                 .platform_data  = &scif2_platform_data,
  68         },
  69 };
  70
  71 static struct plat_sci_port scif3_platform_data = {
  72         .mapbase        = 0xffed0000,
  73         .flags          = UPF_BOOT_AUTOCONF,
  74         .type           = PORT_SCIF,
  75         .irqs           = { 61, 61, 61, 61 },
  76         .clk            = "scif_fck",
  77 };
  78
  79 static struct platform_device scif3_device = {
  80         .name           = "sh-sci",
  81         .id             = 3,
  82         .dev            = {
  83                 .platform_data  = &scif3_platform_data,
  84         },
  85 };
  86
  87 static struct plat_sci_port scif4_platform_data = {
  88         .mapbase        = 0xffee0000,
  89         .flags          = UPF_BOOT_AUTOCONF,
  90         .type           = PORT_SCIF,
  91         .irqs           = { 62, 62, 62, 62 },
  92         .clk            = "scif_fck",
  93 };
  94
  95 static struct platform_device scif4_device = {
  96         .name           = "sh-sci",
  97         .id             = 4,
  98         .dev            = {
  99                 .platform_data  = &scif4_platform_data,
 100         },
 101 };
 102
 103 static struct plat_sci_port scif5_platform_data = {
 104         .mapbase        = 0xffef0000,
 105         .flags          = UPF_BOOT_AUTOCONF,
 106         .type           = PORT_SCIF,
 107         .irqs           = { 63, 63, 63, 63 },
 108         .clk            = "scif_fck",
 109 };
 110
 111 static struct platform_device scif5_device = {
 112         .name           = "sh-sci",
 113         .id             = 5,
 114         .dev            = {
 115                 .platform_data  = &scif5_platform_data,
 116         },
 117 };
 118
 119 static struct sh_timer_config tmu0_platform_data = {
 120         .name = "TMU0",
 121         .channel_offset = 0x04,
 122         .timer_bit = 0,
 123         .clk = "tmu012_fck",
 124         .clockevent_rating = 200,
 125 };
 126
 127 static struct resource tmu0_resources[] = {
 128         [0] = {
 129                 .name   = "TMU0",
 130                 .start  = 0xffd80008,
 131                 .end    = 0xffd80013,
 132                 .flags  = IORESOURCE_MEM,
 133         },
 134         [1] = {
 135                 .start  = 28,
 136                 .flags  = IORESOURCE_IRQ,
 137         },
 138 };
 139
 140 static struct platform_device tmu0_device = {
 141         .name           = "sh_tmu",
 142         .id             = 0,
 143         .dev = {
 144                 .platform_data  = &tmu0_platform_data,
 145         },
 146         .resource       = tmu0_resources,
 147         .num_resources  = ARRAY_SIZE(tmu0_resources),
 148 };
 149
 150 static struct sh_timer_config tmu1_platform_data = {
 151         .name = "TMU1",
 152         .channel_offset = 0x10,
 153         .timer_bit = 1,
 154         .clk = "tmu012_fck",
 155         .clocksource_rating = 200,
 156 };
 157
 158 static struct resource tmu1_resources[] = {
 159         [0] = {
 160                 .name   = "TMU1",
 161                 .start  = 0xffd80014,
 162                 .end    = 0xffd8001f,
 163                 .flags  = IORESOURCE_MEM,
 164         },
 165         [1] = {
 166                 .start  = 29,
 167                 .flags  = IORESOURCE_IRQ,
 168         },
 169 };
 170
 171 static struct platform_device tmu1_device = {
 172         .name           = "sh_tmu",
 173         .id             = 1,
 174         .dev = {
 175                 .platform_data  = &tmu1_platform_data,
 176         },
 177         .resource       = tmu1_resources,
 178         .num_resources  = ARRAY_SIZE(tmu1_resources),
 179 };
 180
 181 static struct sh_timer_config tmu2_platform_data = {
 182         .name = "TMU2",
 183         .channel_offset = 0x1c,
 184         .timer_bit = 2,
 185         .clk = "tmu012_fck",
 186 };
 187
 188 static struct resource tmu2_resources[] = {
 189         [0] = {
 190                 .name   = "TMU2",
 191                 .start  = 0xffd80020,
 192                 .end    = 0xffd8002f,
 193                 .flags  = IORESOURCE_MEM,
 194         },
 195         [1] = {
 196                 .start  = 30,
 197                 .flags  = IORESOURCE_IRQ,
 198         },
 199 };
 200
 201 static struct platform_device tmu2_device = {
 202         .name           = "sh_tmu",
 203         .id             = 2,
 204         .dev = {
 205                 .platform_data  = &tmu2_platform_data,
 206         },
 207         .resource       = tmu2_resources,
 208         .num_resources  = ARRAY_SIZE(tmu2_resources),
 209 };
 210
 211 static struct sh_timer_config tmu3_platform_data = {
 212         .name = "TMU3",
 213         .channel_offset = 0x04,
 214         .timer_bit = 0,
 215         .clk = "tmu345_fck",
 216 };
 217
 218 static struct resource tmu3_resources[] = {
 219         [0] = {
 220                 .name   = "TMU3",
 221                 .start  = 0xffdc0008,
 222                 .end    = 0xffdc0013,
 223                 .flags  = IORESOURCE_MEM,
 224         },
 225         [1] = {
 226                 .start  = 96,
 227                 .flags  = IORESOURCE_IRQ,
 228         },
 229 };
 230
 231 static struct platform_device tmu3_device = {
 232         .name           = "sh_tmu",
 233         .id             = 3,
 234         .dev = {
 235                 .platform_data  = &tmu3_platform_data,
 236         },
 237         .resource       = tmu3_resources,
 238         .num_resources  = ARRAY_SIZE(tmu3_resources),
 239 };
 240
 241 static struct sh_timer_config tmu4_platform_data = {
 242         .name = "TMU4",
 243         .channel_offset = 0x10,
 244         .timer_bit = 1,
 245         .clk = "tmu345_fck",
 246 };
 247
 248 static struct resource tmu4_resources[] = {
 249         [0] = {
 250                 .name   = "TMU4",
 251                 .start  = 0xffdc0014,
 252                 .end    = 0xffdc001f,
 253                 .flags  = IORESOURCE_MEM,
 254         },
 255         [1] = {
 256                 .start  = 97,
 257                 .flags  = IORESOURCE_IRQ,
 258         },
 259 };
 260
 261 static struct platform_device tmu4_device = {
 262         .name           = "sh_tmu",
 263         .id             = 4,
 264         .dev = {
 265                 .platform_data  = &tmu4_platform_data,
 266         },
 267         .resource       = tmu4_resources,
 268         .num_resources  = ARRAY_SIZE(tmu4_resources),
 269 };
 270
 271 static struct sh_timer_config tmu5_platform_data = {
 272         .name = "TMU5",
 273         .channel_offset = 0x1c,
 274         .timer_bit = 2,
 275         .clk = "tmu345_fck",
 276 };
 277
 278 static struct resource tmu5_resources[] = {
 279         [0] = {
 280                 .name   = "TMU5",
 281                 .start  = 0xffdc0020,
 282                 .end    = 0xffdc002b,
 283                 .flags  = IORESOURCE_MEM,
 284         },
 285         [1] = {
 286                 .start  = 98,
 287                 .flags  = IORESOURCE_IRQ,
 288         },
 289 };
 290
 291 static struct platform_device tmu5_device = {
 292         .name           = "sh_tmu",
 293         .id             = 5,
 294         .dev = {
 295                 .platform_data  = &tmu5_platform_data,
 296         },
 297         .resource       = tmu5_resources,
 298         .num_resources  = ARRAY_SIZE(tmu5_resources),
 299 };
 300
 301 /* DMA */
 302 static struct sh_dmae_channel sh7785_dmae0_channels[] = {
 303         {
 304                 .offset = 0,
 305                 .dmars = 0,
 306                 .dmars_bit = 0,
 307         }, {
 308                 .offset = 0x10,
 309                 .dmars = 0,
 310                 .dmars_bit = 8,
 311         }, {
 312                 .offset = 0x20,
 313                 .dmars = 4,
 314                 .dmars_bit = 0,
 315         }, {
 316                 .offset = 0x30,
 317                 .dmars = 4,
 318                 .dmars_bit = 8,
 319         }, {
 320                 .offset = 0x50,
 321                 .dmars = 8,
 322                 .dmars_bit = 0,
 323         }, {
 324                 .offset = 0x60,
 325                 .dmars = 8,
 326                 .dmars_bit = 8,
 327         }
 328 };
 329
 330 static struct sh_dmae_channel sh7785_dmae1_channels[] = {
 331         {
 332                 .offset = 0,
 333         }, {
 334                 .offset = 0x10,
 335         }, {
 336                 .offset = 0x20,
 337         }, {
 338                 .offset = 0x30,
 339         }, {
 340                 .offset = 0x50,
 341         }, {
 342                 .offset = 0x60,
 343         }
 344 };
 345
 346 static unsigned int ts_shift[] = TS_SHIFT;
 347
 348 static struct sh_dmae_pdata dma0_platform_data = {
 349         .channel        = sh7785_dmae0_channels,
 350         .channel_num    = ARRAY_SIZE(sh7785_dmae0_channels),
 351         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 352         .ts_low_mask    = CHCR_TS_LOW_MASK,
 353         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 354         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 355         .ts_shift       = ts_shift,
 356         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 357         .dmaor_init     = DMAOR_INIT,
 358 };
 359
 360 static struct sh_dmae_pdata dma1_platform_data = {
 361         .channel        = sh7785_dmae1_channels,
 362         .channel_num    = ARRAY_SIZE(sh7785_dmae1_channels),
 363         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 364         .ts_low_mask    = CHCR_TS_LOW_MASK,
 365         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 366         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 367         .ts_shift       = ts_shift,
 368         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 369         .dmaor_init     = DMAOR_INIT,
 370 };
 371
 372 static struct resource sh7785_dmae0_resources[] = {
 373         [0] = {
 374                 /* Channel registers and DMAOR */
 375                 .start  = 0xfc808020,
 376                 .end    = 0xfc80808f,
 377                 .flags  = IORESOURCE_MEM,
 378         },
 379         [1] = {
 380                 /* DMARSx */
 381                 .start  = 0xfc809000,
 382                 .end    = 0xfc80900b,
 383                 .flags  = IORESOURCE_MEM,
 384         },
 385         {
 386                 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
 387                 .start  = 33,
 388                 .end    = 33,
 389                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 390         },
 391 };
 392
 393 static struct resource sh7785_dmae1_resources[] = {
 394         [0] = {
 395                 /* Channel registers and DMAOR */
 396                 .start  = 0xfcc08020,
 397                 .end    = 0xfcc0808f,
 398                 .flags  = IORESOURCE_MEM,
 399         },
 400         /* DMAC1 has no DMARS */
 401         {
 402                 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
 403                 .start  = 52,
 404                 .end    = 52,
 405                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 406         },
 407 };
 408
 409 static struct platform_device dma0_device = {
 410         .name           = "sh-dma-engine",
 411         .id             = 0,
 412         .resource       = sh7785_dmae0_resources,
 413         .num_resources  = ARRAY_SIZE(sh7785_dmae0_resources),
 414         .dev            = {
 415                 .platform_data  = &dma0_platform_data,
 416         },
 417 };
 418
 419 static struct platform_device dma1_device = {
 420         .name           = "sh-dma-engine",
 421         .id             = 1,
 422         .resource       = sh7785_dmae1_resources,
 423         .num_resources  = ARRAY_SIZE(sh7785_dmae1_resources),
 424         .dev            = {
 425                 .platform_data  = &dma1_platform_data,
 426         },
 427 };
 428
 429 static struct platform_device *sh7785_devices[] __initdata = {
 430         &scif0_device,
 431         &scif1_device,
 432         &scif2_device,
 433         &scif3_device,
 434         &scif4_device,
 435         &scif5_device,
 436         &tmu0_device,
 437         &tmu1_device,
 438         &tmu2_device,
 439         &tmu3_device,
 440         &tmu4_device,
 441         &tmu5_device,
 442         &dma0_device,
 443         &dma1_device,
 444 };
 445
 446 static int __init sh7785_devices_setup(void)
 447 {
 448         return platform_add_devices(sh7785_devices,
 449                                     ARRAY_SIZE(sh7785_devices));
 450 }
 451 arch_initcall(sh7785_devices_setup);
 452
 453 static struct platform_device *sh7785_early_devices[] __initdata = {
 454         &scif0_device,
 455         &scif1_device,
 456         &scif2_device,
 457         &scif3_device,
 458         &scif4_device,
 459         &scif5_device,
 460         &tmu0_device,
 461         &tmu1_device,
 462         &tmu2_device,
 463         &tmu3_device,
 464         &tmu4_device,
 465         &tmu5_device,
 466 };
 467
 468 void __init plat_early_device_setup(void)
 469 {
 470         early_platform_add_devices(sh7785_early_devices,
 471                                    ARRAY_SIZE(sh7785_early_devices));
 472 }
 473
 474 enum {
 475         UNUSED = 0,
 476
 477         /* interrupt sources */
 478
 479         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 480         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 481         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 482         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 483
 484         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 485         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 486         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 487         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 488
 489         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 490         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 491         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
 492         SCIF2, SCIF3, SCIF4, SCIF5,
 493         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 494         SIOF, MMCIF, DU, GDTA,
 495         TMU3, TMU4, TMU5,
 496         SSI0, SSI1,
 497         HAC0, HAC1,
 498         FLCTL, GPIO,
 499
 500         /* interrupt groups */
 501
 502         TMU012, TMU345
 503 };
 504
 505 static struct intc_vect vectors[] __initdata = {
 506         INTC_VECT(WDT, 0x560),
 507         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 508         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 509         INTC_VECT(HUDI, 0x600),
 510         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
 511         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
 512         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
 513         INTC_VECT(DMAC0, 0x6e0),
 514         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 515         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 516         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
 517         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
 518         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
 519         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
 520         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
 521         INTC_VECT(DMAC1, 0x940),
 522         INTC_VECT(HSPI, 0x960),
 523         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 524         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 525         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 526         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 527         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 528         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 529         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 530         INTC_VECT(SIOF, 0xc00),
 531         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 532         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 533         INTC_VECT(DU, 0xd80),
 534         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
 535         INTC_VECT(GDTA, 0xde0),
 536         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 537         INTC_VECT(TMU5, 0xe40),
 538         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 539         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 540         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 541         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 542         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 543         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 544 };
 545
 546 static struct intc_group groups[] __initdata = {
 547         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 548         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 549 };
 550
 551 static struct intc_mask_reg mask_registers[] __initdata = {
 552         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 553           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 554
 555         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 556           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 557             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 558             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 559             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 560             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 561             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 562             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 563             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 564
 565         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 566           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 567             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 568             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 569             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 570 };
 571
 572 static struct intc_prio_reg prio_registers[] __initdata = {
 573         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 574                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 575         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 576                                                  TMU2, TMU2_TICPI } },
 577         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 578         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 579                                                  SCIF2, SCIF3 } },
 580         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 581         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 582         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 583                                                  PCISERR, PCIINTA } },
 584         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 585                                                  PCIINTD, PCIC5 } },
 586         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 587         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 588         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 589 };
 590
 591 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 592                          mask_registers, prio_registers, NULL);
 593
 594 /* Support for external interrupt pins in IRQ mode */
 595
 596 static struct intc_vect vectors_irq0123[] __initdata = {
 597         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 598         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 599 };
 600
 601 static struct intc_vect vectors_irq4567[] __initdata = {
 602         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 603         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 604 };
 605
 606 static struct intc_sense_reg sense_registers[] __initdata = {
 607         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 608                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 609 };
 610
 611 static struct intc_mask_reg ack_registers[] __initdata = {
 612         { 0xffd00024, 0, 32, /* INTREQ */
 613           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 614 };
 615
 616 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
 617                              vectors_irq0123, NULL, mask_registers,
 618                              prio_registers, sense_registers, ack_registers);
 619
 620 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
 621                              vectors_irq4567, NULL, mask_registers,
 622                              prio_registers, sense_registers, ack_registers);
 623
 624 /* External interrupt pins in IRL mode */
 625
 626 static struct intc_vect vectors_irl0123[] __initdata = {
 627         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 628         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 629         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 630         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 631         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 632         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 633         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 634         INTC_VECT(IRL0_HHHL, 0x3c0),
 635 };
 636
 637 static struct intc_vect vectors_irl4567[] __initdata = {
 638         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 639         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 640         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 641         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 642         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 643         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 644         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 645         INTC_VECT(IRL4_HHHL, 0xcc0),
 646 };
 647
 648 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 649                          NULL, mask_registers, NULL, NULL);
 650
 651 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 652                          NULL, mask_registers, NULL, NULL);
 653
 654 #define INTC_ICR0       0xffd00000
 655 #define INTC_INTMSK0    0xffd00044
 656 #define INTC_INTMSK1    0xffd00048
 657 #define INTC_INTMSK2    0xffd40080
 658 #define INTC_INTMSKCLR1 0xffd00068
 659 #define INTC_INTMSKCLR2 0xffd40084
 660
 661 void __init plat_irq_setup(void)
 662 {
 663         /* disable IRQ3-0 + IRQ7-4 */
 664         __raw_writel(0xff000000, INTC_INTMSK0);
 665
 666         /* disable IRL3-0 + IRL7-4 */
 667         __raw_writel(0xc0000000, INTC_INTMSK1);
 668         __raw_writel(0xfffefffe, INTC_INTMSK2);
 669
 670         /* select IRL mode for IRL3-0 + IRL7-4 */
 671         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 672
 673         /* disable holding function, ie enable "SH-4 Mode" */
 674         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 675
 676         register_intc_controller(&intc_desc);
 677 }
 678
 679 void __init plat_irq_setup_pins(int mode)
 680 {
 681         switch (mode) {
 682         case IRQ_MODE_IRQ7654:
 683                 /* select IRQ mode for IRL7-4 */
 684                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 685                 register_intc_controller(&intc_desc_irq4567);
 686                 break;
 687         case IRQ_MODE_IRQ3210:
 688                 /* select IRQ mode for IRL3-0 */
 689                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 690                 register_intc_controller(&intc_desc_irq0123);
 691                 break;
 692         case IRQ_MODE_IRL7654:
 693                 /* enable IRL7-4 but don't provide any masking */
 694                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 695                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 696                 break;
 697         case IRQ_MODE_IRL3210:
 698                 /* enable IRL0-3 but don't provide any masking */
 699                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 700                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 701                 break;
 702         case IRQ_MODE_IRL7654_MASK:
 703                 /* enable IRL7-4 and mask using cpu intc controller */
 704                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 705                 register_intc_controller(&intc_desc_irl4567);
 706                 break;
 707         case IRQ_MODE_IRL3210_MASK:
 708                 /* enable IRL0-3 and mask using cpu intc controller */
 709                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 710                 register_intc_controller(&intc_desc_irl0123);
 711                 break;
 712         default:
 713                 BUG();
 714         }
 715 }
 716
 717 void __init plat_mem_setup(void)
 718 {
 719         /* Register the URAM space as Node 1 */
 720         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 721 }