1 //------------------------------------------------------------------------------
2 // <copyright file="ar6k.h" company="Atheros">
3 // Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
6 // Permission to use, copy, modify, and/or distribute this software for any
7 // purpose with or without fee is hereby granted, provided that the above
8 // copyright notice and this permission notice appear in all copies.
10 // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 // ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 // WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 // ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 // OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 //------------------------------------------------------------------------------
20 //==============================================================================
21 // AR6K device layer that handles register level I/O
23 // Author(s): ="Atheros"
24 //==============================================================================
28 #include "hci_transport_api.h"
29 #include "../htc_debug.h"
31 #define AR6K_MAILBOXES 4
33 /* HTC runs over mailbox 0 */
36 #define AR6K_TARGET_DEBUG_INTR_MASK 0x01
38 #define OTHER_INTS_ENABLED (INT_STATUS_ENABLE_ERROR_MASK | \
39 INT_STATUS_ENABLE_CPU_MASK | \
40 INT_STATUS_ENABLE_COUNTER_MASK)
43 //#define MBOXHW_UNIT_TEST 1
45 #include "athstartpack.h"
46 typedef PREPACK
struct _AR6K_IRQ_PROC_REGISTERS
{
50 u8 counter_int_status
;
52 u8 rx_lookahead_valid
;
56 u32 rx_gmbox_lookahead_alias
[2];
57 } POSTPACK AR6K_IRQ_PROC_REGISTERS
;
59 #define AR6K_IRQ_PROC_REGS_SIZE sizeof(AR6K_IRQ_PROC_REGISTERS)
61 typedef PREPACK
struct _AR6K_IRQ_ENABLE_REGISTERS
{
63 u8 cpu_int_status_enable
;
64 u8 error_status_enable
;
65 u8 counter_int_status_enable
;
66 } POSTPACK AR6K_IRQ_ENABLE_REGISTERS
;
68 PREPACK
struct ar6k_gmbox_ctrl_registers
{
72 #include "athendpack.h"
74 #define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(AR6K_IRQ_ENABLE_REGISTERS)
76 #define AR6K_REG_IO_BUFFER_SIZE 32
77 #define AR6K_MAX_REG_IO_BUFFERS 8
78 #define FROM_DMA_BUFFER true
79 #define TO_DMA_BUFFER false
80 #define AR6K_SCATTER_ENTRIES_PER_REQ 16
81 #define AR6K_MAX_TRANSFER_SIZE_PER_SCATTER 16*1024
82 #define AR6K_SCATTER_REQS 4
83 #define AR6K_LEGACY_MAX_WRITE_LENGTH 2048
85 #ifndef A_CACHE_LINE_PAD
86 #define A_CACHE_LINE_PAD 128
88 #define AR6K_MIN_SCATTER_ENTRIES_PER_REQ 2
89 #define AR6K_MIN_TRANSFER_SIZE_PER_SCATTER 4*1024
91 /* buffers for ASYNC I/O */
92 struct ar6k_async_reg_io_buffer
{
93 HTC_PACKET HtcPacket
; /* we use an HTC packet as a wrapper for our async register-based I/O */
94 u8 _Pad1
[A_CACHE_LINE_PAD
];
95 u8 Buffer
[AR6K_REG_IO_BUFFER_SIZE
]; /* cache-line safe with pads around */
96 u8 _Pad2
[A_CACHE_LINE_PAD
];
99 typedef struct _AR6K_GMBOX_INFO
{
100 void *pProtocolContext
;
101 int (*pMessagePendingCallBack
)(void *pContext
, u8 LookAheadBytes
[], int ValidBytes
);
102 int (*pCreditsPendingCallback
)(void *pContext
, int NumCredits
, bool CreditIRQEnabled
);
103 void (*pTargetFailureCallback
)(void *pContext
, int Status
);
104 void (*pStateDumpCallback
)(void *pContext
);
105 bool CreditCountIRQEnabled
;
110 u8 _Pad1
[A_CACHE_LINE_PAD
];
111 AR6K_IRQ_PROC_REGISTERS IrqProcRegisters
; /* cache-line safe with pads around */
112 u8 _Pad2
[A_CACHE_LINE_PAD
];
113 AR6K_IRQ_ENABLE_REGISTERS IrqEnableRegisters
; /* cache-line safe with pads around */
114 u8 _Pad3
[A_CACHE_LINE_PAD
];
118 HIF_DEVICE_MBOX_INFO MailBoxInfo
;
119 HIF_PENDING_EVENTS_FUNC GetPendingEventsFunc
;
121 HTC_PACKET_QUEUE RegisterIOList
;
122 struct ar6k_async_reg_io_buffer RegIOBuffers
[AR6K_MAX_REG_IO_BUFFERS
];
123 void (*TargetFailureCallback
)(void *Context
);
124 int (*MessagePendingCallback
)(void *Context
,
128 int *pNumPktsFetched
);
129 HIF_DEVICE_IRQ_PROCESSING_MODE HifIRQProcessingMode
;
130 HIF_MASK_UNMASK_RECV_EVENT HifMaskUmaskRecvEvent
;
132 HIF_DEVICE_IRQ_YIELD_PARAMS HifIRQYieldParams
;
134 int CurrentDSRRecvCount
;
135 HIF_DEVICE_SCATTER_SUPPORT_INFO HifScatterInfo
;
136 DL_LIST ScatterReqHead
;
137 bool ScatterIsVirtual
;
138 int MaxRecvBundleSize
;
139 int MaxSendBundleSize
;
140 AR6K_GMBOX_INFO GMboxInfo
;
142 struct ar6k_gmbox_ctrl_registers GMboxControlRegisters
;
143 int RecheckIRQStatusCnt
;
146 #define LOCK_AR6K(p) A_MUTEX_LOCK(&(p)->Lock);
147 #define UNLOCK_AR6K(p) A_MUTEX_UNLOCK(&(p)->Lock);
148 #define REF_IRQ_STATUS_RECHECK(p) (p)->RecheckIRQStatusCnt = 1 /* note: no need to lock this, it only gets set */
150 int DevSetup(struct ar6k_device
*pDev
);
151 void DevCleanup(struct ar6k_device
*pDev
);
152 int DevUnmaskInterrupts(struct ar6k_device
*pDev
);
153 int DevMaskInterrupts(struct ar6k_device
*pDev
);
154 int DevPollMboxMsgRecv(struct ar6k_device
*pDev
,
157 int DevRWCompletionHandler(void *context
, int status
);
158 int DevDsrHandler(void *context
);
159 int DevCheckPendingRecvMsgsAsync(void *context
);
160 void DevAsyncIrqProcessComplete(struct ar6k_device
*pDev
);
161 void DevDumpRegisters(struct ar6k_device
*pDev
,
162 AR6K_IRQ_PROC_REGISTERS
*pIrqProcRegs
,
163 AR6K_IRQ_ENABLE_REGISTERS
*pIrqEnableRegs
);
165 #define DEV_STOP_RECV_ASYNC true
166 #define DEV_STOP_RECV_SYNC false
167 #define DEV_ENABLE_RECV_ASYNC true
168 #define DEV_ENABLE_RECV_SYNC false
169 int DevStopRecv(struct ar6k_device
*pDev
, bool ASyncMode
);
170 int DevEnableRecv(struct ar6k_device
*pDev
, bool ASyncMode
);
171 int DevEnableInterrupts(struct ar6k_device
*pDev
);
172 int DevDisableInterrupts(struct ar6k_device
*pDev
);
173 int DevWaitForPendingRecv(struct ar6k_device
*pDev
,u32 TimeoutInMs
,bool *pbIsRecvPending
);
175 #define DEV_CALC_RECV_PADDED_LEN(pDev, length) (((length) + (pDev)->BlockMask) & (~((pDev)->BlockMask)))
176 #define DEV_CALC_SEND_PADDED_LEN(pDev, length) DEV_CALC_RECV_PADDED_LEN(pDev,length)
177 #define DEV_IS_LEN_BLOCK_ALIGNED(pDev, length) (((length) % (pDev)->BlockSize) == 0)
179 static INLINE
int DevSendPacket(struct ar6k_device
*pDev
, HTC_PACKET
*pPacket
, u32 SendLength
) {
181 bool sync
= (pPacket
->Completion
== NULL
) ? true : false;
184 /* adjust the length to be a multiple of block size if appropriate */
185 paddedLength
= DEV_CALC_SEND_PADDED_LEN(pDev
, SendLength
);
188 if (paddedLength
> pPacket
->BufferLength
) {
190 if (pPacket
->Completion
!= NULL
) {
191 COMPLETE_HTC_PACKET(pPacket
,A_EINVAL
);
198 AR_DEBUG_PRINTF(ATH_DEBUG_SEND
,
199 ("DevSendPacket, Padded Length: %d Mbox:0x%X (mode:%s)\n",
201 pDev
->MailBoxInfo
.MboxAddresses
[HTC_MAILBOX
],
202 sync
? "SYNC" : "ASYNC"));
204 status
= HIFReadWrite(pDev
->HIFDevice
,
205 pDev
->MailBoxInfo
.MboxAddresses
[HTC_MAILBOX
],
207 paddedLength
, /* the padded length */
208 sync
? HIF_WR_SYNC_BLOCK_INC
: HIF_WR_ASYNC_BLOCK_INC
,
209 sync
? NULL
: pPacket
); /* pass the packet as the context to the HIF request */
212 pPacket
->Status
= status
;
214 if (status
== A_PENDING
) {
222 static INLINE
int DevRecvPacket(struct ar6k_device
*pDev
, HTC_PACKET
*pPacket
, u32 RecvLength
) {
225 bool sync
= (pPacket
->Completion
== NULL
) ? true : false;
227 /* adjust the length to be a multiple of block size if appropriate */
228 paddedLength
= DEV_CALC_RECV_PADDED_LEN(pDev
, RecvLength
);
230 if (paddedLength
> pPacket
->BufferLength
) {
232 AR_DEBUG_PRINTF(ATH_DEBUG_ERR
,
233 ("DevRecvPacket, Not enough space for padlen:%d recvlen:%d bufferlen:%d \n",
234 paddedLength
,RecvLength
,pPacket
->BufferLength
));
235 if (pPacket
->Completion
!= NULL
) {
236 COMPLETE_HTC_PACKET(pPacket
,A_EINVAL
);
242 AR_DEBUG_PRINTF(ATH_DEBUG_RECV
,
243 ("DevRecvPacket (0x%lX : hdr:0x%X) Padded Length: %d Mbox:0x%X (mode:%s)\n",
244 (unsigned long)pPacket
, pPacket
->PktInfo
.AsRx
.ExpectedHdr
,
246 pDev
->MailBoxInfo
.MboxAddresses
[HTC_MAILBOX
],
247 sync
? "SYNC" : "ASYNC"));
249 status
= HIFReadWrite(pDev
->HIFDevice
,
250 pDev
->MailBoxInfo
.MboxAddresses
[HTC_MAILBOX
],
253 sync
? HIF_RD_SYNC_BLOCK_FIX
: HIF_RD_ASYNC_BLOCK_FIX
,
254 sync
? NULL
: pPacket
); /* pass the packet as the context to the HIF request */
257 pPacket
->Status
= status
;
263 #define DEV_CHECK_RECV_YIELD(pDev) \
264 ((pDev)->CurrentDSRRecvCount >= (pDev)->HifIRQYieldParams.RecvPacketYieldCount)
266 #define IS_DEV_IRQ_PROC_SYNC_MODE(pDev) (HIF_DEVICE_IRQ_SYNC_ONLY == (pDev)->HifIRQProcessingMode)
267 #define IS_DEV_IRQ_PROCESSING_ASYNC_ALLOWED(pDev) ((pDev)->HifIRQProcessingMode != HIF_DEVICE_IRQ_SYNC_ONLY)
269 /**************************************************/
270 /****** Scatter Function and Definitions
275 int DevCopyScatterListToFromDMABuffer(HIF_SCATTER_REQ
*pReq
, bool FromDMA
);
277 /* copy any READ data back into scatter list */
278 #define DEV_FINISH_SCATTER_OPERATION(pR) \
280 if (!((pR)->CompletionStatus) && \
281 !((pR)->Request & HIF_WRITE) && \
282 ((pR)->ScatterMethod == HIF_SCATTER_DMA_BOUNCE)) { \
283 (pR)->CompletionStatus = \
284 DevCopyScatterListToFromDMABuffer((pR), \
289 /* copy any WRITE data to bounce buffer */
290 static INLINE
int DEV_PREPARE_SCATTER_OPERATION(HIF_SCATTER_REQ
*pReq
) {
291 if ((pReq
->Request
& HIF_WRITE
) && (pReq
->ScatterMethod
== HIF_SCATTER_DMA_BOUNCE
)) {
292 return DevCopyScatterListToFromDMABuffer(pReq
,TO_DMA_BUFFER
);
299 int DevSetupMsgBundling(struct ar6k_device
*pDev
, int MaxMsgsPerTransfer
);
301 int DevCleanupMsgBundling(struct ar6k_device
*pDev
);
303 #define DEV_GET_MAX_MSG_PER_BUNDLE(pDev) (pDev)->HifScatterInfo.MaxScatterEntries
304 #define DEV_GET_MAX_BUNDLE_LENGTH(pDev) (pDev)->HifScatterInfo.MaxTransferSizePerScatterReq
305 #define DEV_ALLOC_SCATTER_REQ(pDev) \
306 (pDev)->HifScatterInfo.pAllocateReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice)
308 #define DEV_FREE_SCATTER_REQ(pDev,pR) \
309 (pDev)->HifScatterInfo.pFreeReqFunc((pDev)->ScatterIsVirtual ? (pDev) : (pDev)->HIFDevice,(pR))
311 #define DEV_GET_MAX_BUNDLE_RECV_LENGTH(pDev) (pDev)->MaxRecvBundleSize
312 #define DEV_GET_MAX_BUNDLE_SEND_LENGTH(pDev) (pDev)->MaxSendBundleSize
314 #define DEV_SCATTER_READ true
315 #define DEV_SCATTER_WRITE false
316 #define DEV_SCATTER_ASYNC true
317 #define DEV_SCATTER_SYNC false
318 int DevSubmitScatterRequest(struct ar6k_device
*pDev
, HIF_SCATTER_REQ
*pScatterReq
, bool Read
, bool Async
);
320 #ifdef MBOXHW_UNIT_TEST
321 int DoMboxHWTest(struct ar6k_device
*pDev
);
324 /* completely virtual */
325 typedef struct _DEV_SCATTER_DMA_VIRTUAL_INFO
{
326 u8
*pVirtDmaBuffer
; /* dma-able buffer - CPU accessible address */
327 u8 DataArea
[1]; /* start of data area */
328 } DEV_SCATTER_DMA_VIRTUAL_INFO
;
332 void DumpAR6KDevState(struct ar6k_device
*pDev
);
334 /**************************************************/
335 /****** GMBOX functions and definitions
340 #ifdef ATH_AR6K_ENABLE_GMBOX
342 void DevCleanupGMbox(struct ar6k_device
*pDev
);
343 int DevSetupGMbox(struct ar6k_device
*pDev
);
344 int DevCheckGMboxInterrupts(struct ar6k_device
*pDev
);
345 void DevNotifyGMboxTargetFailure(struct ar6k_device
*pDev
);
350 #define DevCleanupGMbox(p)
351 #define DevCheckGMboxInterrupts(p) 0
352 #define DevNotifyGMboxTargetFailure(p)
354 static INLINE
int DevSetupGMbox(struct ar6k_device
*pDev
) {
355 pDev
->GMboxEnabled
= false;
361 #ifdef ATH_AR6K_ENABLE_GMBOX
363 /* GMBOX protocol modules must expose each of these internal APIs */
364 HCI_TRANSPORT_HANDLE
GMboxAttachProtocol(struct ar6k_device
*pDev
, HCI_TRANSPORT_CONFIG_INFO
*pInfo
);
365 int GMboxProtocolInstall(struct ar6k_device
*pDev
);
366 void GMboxProtocolUninstall(struct ar6k_device
*pDev
);
368 /* API used by GMBOX protocol modules */
369 struct ar6k_device
*HTCGetAR6KDevice(void *HTCHandle
);
370 #define DEV_GMBOX_SET_PROTOCOL(pDev,recv_callback,credits_pending,failure,statedump,context) \
372 (pDev)->GMboxInfo.pProtocolContext = (context); \
373 (pDev)->GMboxInfo.pMessagePendingCallBack = (recv_callback); \
374 (pDev)->GMboxInfo.pCreditsPendingCallback = (credits_pending); \
375 (pDev)->GMboxInfo.pTargetFailureCallback = (failure); \
376 (pDev)->GMboxInfo.pStateDumpCallback = (statedump); \
379 #define DEV_GMBOX_GET_PROTOCOL(pDev) (pDev)->GMboxInfo.pProtocolContext
381 int DevGMboxWrite(struct ar6k_device
*pDev
, HTC_PACKET
*pPacket
, u32 WriteLength
);
382 int DevGMboxRead(struct ar6k_device
*pDev
, HTC_PACKET
*pPacket
, u32 ReadLength
);
384 #define PROC_IO_ASYNC true
385 #define PROC_IO_SYNC false
386 typedef enum GMBOX_IRQ_ACTION_TYPE
{
387 GMBOX_ACTION_NONE
= 0,
389 GMBOX_ERRORS_IRQ_ENABLE
,
390 GMBOX_RECV_IRQ_ENABLE
,
391 GMBOX_RECV_IRQ_DISABLE
,
392 GMBOX_CREDIT_IRQ_ENABLE
,
393 GMBOX_CREDIT_IRQ_DISABLE
,
394 } GMBOX_IRQ_ACTION_TYPE
;
396 int DevGMboxIRQAction(struct ar6k_device
*pDev
, GMBOX_IRQ_ACTION_TYPE
, bool AsyncMode
);
397 int DevGMboxReadCreditCounter(struct ar6k_device
*pDev
, bool AsyncMode
, int *pCredits
);
398 int DevGMboxReadCreditSize(struct ar6k_device
*pDev
, int *pCreditSize
);
399 int DevGMboxRecvLookAheadPeek(struct ar6k_device
*pDev
, u8
*pLookAheadBuffer
, int *pLookAheadBytes
);
400 int DevGMboxSetTargetInterrupt(struct ar6k_device
*pDev
, int SignalNumber
, int AckTimeoutMS
);