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brcmsmac: use sprom from bcma
[linux-2.6/libata-dev.git] / drivers / net / wireless / brcm80211 / brcmsmac / aiutils.c
blobf0cef235516bfe189de56058c85050e97849433b
1 /*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 *
16 * File contents: support functions for PCI/PCIe
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/delay.h>
22 #include <linux/pci.h>
23
24 #include <defs.h>
25 #include <chipcommon.h>
26 #include <brcmu_utils.h>
27 #include <brcm_hw_ids.h>
28 #include <soc.h>
29 #include "types.h"
30 #include "pub.h"
31 #include "pmu.h"
32 #include "srom.h"
33 #include "nicpci.h"
34 #include "aiutils.h"
35
36 /* slow_clk_ctl */
37 /* slow clock source mask */
38 #define SCC_SS_MASK 0x00000007
39 /* source of slow clock is LPO */
40 #define SCC_SS_LPO 0x00000000
41 /* source of slow clock is crystal */
42 #define SCC_SS_XTAL 0x00000001
43 /* source of slow clock is PCI */
44 #define SCC_SS_PCI 0x00000002
45 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
46 #define SCC_LF 0x00000200
47 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
48 #define SCC_LP 0x00000400
49 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
50 #define SCC_FS 0x00000800
51 /* IgnorePllOffReq, 1/0:
52 * power logic ignores/honors PLL clock disable requests from core
53 */
54 #define SCC_IP 0x00001000
55 /* XtalControlEn, 1/0:
56 * power logic does/doesn't disable crystal when appropriate
57 */
58 #define SCC_XC 0x00002000
59 /* XtalPU (RO), 1/0: crystal running/disabled */
60 #define SCC_XP 0x00004000
61 /* ClockDivider (SlowClk = 1/(4+divisor)) */
62 #define SCC_CD_MASK 0xffff0000
63 #define SCC_CD_SHIFT 16
64
65 /* system_clk_ctl */
66 /* ILPen: Enable Idle Low Power */
67 #define SYCC_IE 0x00000001
68 /* ALPen: Enable Active Low Power */
69 #define SYCC_AE 0x00000002
70 /* ForcePLLOn */
71 #define SYCC_FP 0x00000004
72 /* Force ALP (or HT if ALPen is not set */
73 #define SYCC_AR 0x00000008
74 /* Force HT */
75 #define SYCC_HR 0x00000010
76 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
77 #define SYCC_CD_MASK 0xffff0000
78 #define SYCC_CD_SHIFT 16
79
80 #define CST4329_SPROM_OTP_SEL_MASK 0x00000003
81 /* OTP is powered up, use def. CIS, no SPROM */
82 #define CST4329_DEFCIS_SEL 0
83 /* OTP is powered up, SPROM is present */
84 #define CST4329_SPROM_SEL 1
85 /* OTP is powered up, no SPROM */
86 #define CST4329_OTP_SEL 2
87 /* OTP is powered down, SPROM is present */
88 #define CST4329_OTP_PWRDN 3
89
90 #define CST4329_SPI_SDIO_MODE_MASK 0x00000004
91 #define CST4329_SPI_SDIO_MODE_SHIFT 2
92
93 /* 43224 chip-specific ChipControl register bits */
94 #define CCTRL43224_GPIO_TOGGLE 0x8000
95 /* 12 mA drive strength */
96 #define CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0
97 /* 12 mA drive strength for later 43224s */
98 #define CCTRL_43224B0_12MA_LED_DRIVE 0xF0
99
100 /* 43236 Chip specific ChipStatus register bits */
101 #define CST43236_SFLASH_MASK 0x00000040
102 #define CST43236_OTP_MASK 0x00000080
103 #define CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */
104 #define CST43236_BP_CLK 0x00000200 /* 120/96Mbps */
105 #define CST43236_BOOT_MASK 0x00001800
106 #define CST43236_BOOT_SHIFT 11
107 #define CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */
108 #define CST43236_BOOT_FROM_ROM 1 /* boot from ROM */
109 #define CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */
110 #define CST43236_BOOT_FROM_INVALID 3
111
112 /* 4331 chip-specific ChipControl register bits */
113 /* 0 disable */
114 #define CCTRL4331_BT_COEXIST (1<<0)
115 /* 0 SECI is disabled (JTAG functional) */
116 #define CCTRL4331_SECI (1<<1)
117 /* 0 disable */
118 #define CCTRL4331_EXT_LNA (1<<2)
119 /* sprom/gpio13-15 mux */
120 #define CCTRL4331_SPROM_GPIO13_15 (1<<3)
121 /* 0 ext pa disable, 1 ext pa enabled */
122 #define CCTRL4331_EXTPA_EN (1<<4)
123 /* set drive out GPIO_CLK on sprom_cs pin */
124 #define CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5)
125 /* use sprom_cs pin as PCIE mdio interface */
126 #define CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6)
127 /* aband extpa will be at gpio2/5 and sprom_dout */
128 #define CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7)
129 /* override core control on pipe_AuxClkEnable */
130 #define CCTRL4331_OVR_PIPEAUXCLKEN (1<<8)
131 /* override core control on pipe_AuxPowerDown */
132 #define CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9)
133 /* pcie_auxclkenable */
134 #define CCTRL4331_PCIE_AUXCLKEN (1<<10)
135 /* pcie_pipe_pllpowerdown */
136 #define CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11)
137 /* enable bt_shd0 at gpio4 */
138 #define CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16)
139 /* enable bt_shd1 at gpio5 */
140 #define CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17)
141
142 /* 4331 Chip specific ChipStatus register bits */
143 /* crystal frequency 20/40Mhz */
144 #define CST4331_XTAL_FREQ 0x00000001
145 #define CST4331_SPROM_PRESENT 0x00000002
146 #define CST4331_OTP_PRESENT 0x00000004
147 #define CST4331_LDO_RF 0x00000008
148 #define CST4331_LDO_PAR 0x00000010
149
150 /* 4319 chip-specific ChipStatus register bits */
151 #define CST4319_SPI_CPULESSUSB 0x00000001
152 #define CST4319_SPI_CLK_POL 0x00000002
153 #define CST4319_SPI_CLK_PH 0x00000008
154 /* gpio [7:6], SDIO CIS selection */
155 #define CST4319_SPROM_OTP_SEL_MASK 0x000000c0
156 #define CST4319_SPROM_OTP_SEL_SHIFT 6
157 /* use default CIS, OTP is powered up */
158 #define CST4319_DEFCIS_SEL 0x00000000
159 /* use SPROM, OTP is powered up */
160 #define CST4319_SPROM_SEL 0x00000040
161 /* use OTP, OTP is powered up */
162 #define CST4319_OTP_SEL 0x00000080
163 /* use SPROM, OTP is powered down */
164 #define CST4319_OTP_PWRDN 0x000000c0
165 /* gpio [8], sdio/usb mode */
166 #define CST4319_SDIO_USB_MODE 0x00000100
167 #define CST4319_REMAP_SEL_MASK 0x00000600
168 #define CST4319_ILPDIV_EN 0x00000800
169 #define CST4319_XTAL_PD_POL 0x00001000
170 #define CST4319_LPO_SEL 0x00002000
171 #define CST4319_RES_INIT_MODE 0x0000c000
172 /* PALDO is configured with external PNP */
173 #define CST4319_PALDO_EXTPNP 0x00010000
174 #define CST4319_CBUCK_MODE_MASK 0x00060000
175 #define CST4319_CBUCK_MODE_BURST 0x00020000
176 #define CST4319_CBUCK_MODE_LPBURST 0x00060000
177 #define CST4319_RCAL_VALID 0x01000000
178 #define CST4319_RCAL_VALUE_MASK 0x3e000000
179 #define CST4319_RCAL_VALUE_SHIFT 25
180
181 /* 4336 chip-specific ChipStatus register bits */
182 #define CST4336_SPI_MODE_MASK 0x00000001
183 #define CST4336_SPROM_PRESENT 0x00000002
184 #define CST4336_OTP_PRESENT 0x00000004
185 #define CST4336_ARMREMAP_0 0x00000008
186 #define CST4336_ILPDIV_EN_MASK 0x00000010
187 #define CST4336_ILPDIV_EN_SHIFT 4
188 #define CST4336_XTAL_PD_POL_MASK 0x00000020
189 #define CST4336_XTAL_PD_POL_SHIFT 5
190 #define CST4336_LPO_SEL_MASK 0x00000040
191 #define CST4336_LPO_SEL_SHIFT 6
192 #define CST4336_RES_INIT_MODE_MASK 0x00000180
193 #define CST4336_RES_INIT_MODE_SHIFT 7
194 #define CST4336_CBUCK_MODE_MASK 0x00000600
195 #define CST4336_CBUCK_MODE_SHIFT 9
196
197 /* 4313 chip-specific ChipStatus register bits */
198 #define CST4313_SPROM_PRESENT 1
199 #define CST4313_OTP_PRESENT 2
200 #define CST4313_SPROM_OTP_SEL_MASK 0x00000002
201 #define CST4313_SPROM_OTP_SEL_SHIFT 0
202
203 /* 4313 Chip specific ChipControl register bits */
204 /* 12 mA drive strengh for later 4313 */
205 #define CCTRL_4313_12MA_LED_DRIVE 0x00000007
206
207 /* Manufacturer Ids */
208 #define MFGID_ARM 0x43b
209 #define MFGID_BRCM 0x4bf
210 #define MFGID_MIPS 0x4a7
211
212 /* Enumeration ROM registers */
213 #define ER_EROMENTRY 0x000
214 #define ER_REMAPCONTROL 0xe00
215 #define ER_REMAPSELECT 0xe04
216 #define ER_MASTERSELECT 0xe10
217 #define ER_ITCR 0xf00
218 #define ER_ITIP 0xf04
219
220 /* Erom entries */
221 #define ER_TAG 0xe
222 #define ER_TAG1 0x6
223 #define ER_VALID 1
224 #define ER_CI 0
225 #define ER_MP 2
226 #define ER_ADD 4
227 #define ER_END 0xe
228 #define ER_BAD 0xffffffff
229
230 /* EROM CompIdentA */
231 #define CIA_MFG_MASK 0xfff00000
232 #define CIA_MFG_SHIFT 20
233 #define CIA_CID_MASK 0x000fff00
234 #define CIA_CID_SHIFT 8
235 #define CIA_CCL_MASK 0x000000f0
236 #define CIA_CCL_SHIFT 4
237
238 /* EROM CompIdentB */
239 #define CIB_REV_MASK 0xff000000
240 #define CIB_REV_SHIFT 24
241 #define CIB_NSW_MASK 0x00f80000
242 #define CIB_NSW_SHIFT 19
243 #define CIB_NMW_MASK 0x0007c000
244 #define CIB_NMW_SHIFT 14
245 #define CIB_NSP_MASK 0x00003e00
246 #define CIB_NSP_SHIFT 9
247 #define CIB_NMP_MASK 0x000001f0
248 #define CIB_NMP_SHIFT 4
249
250 /* EROM AddrDesc */
251 #define AD_ADDR_MASK 0xfffff000
252 #define AD_SP_MASK 0x00000f00
253 #define AD_SP_SHIFT 8
254 #define AD_ST_MASK 0x000000c0
255 #define AD_ST_SHIFT 6
256 #define AD_ST_SLAVE 0x00000000
257 #define AD_ST_BRIDGE 0x00000040
258 #define AD_ST_SWRAP 0x00000080
259 #define AD_ST_MWRAP 0x000000c0
260 #define AD_SZ_MASK 0x00000030
261 #define AD_SZ_SHIFT 4
262 #define AD_SZ_4K 0x00000000
263 #define AD_SZ_8K 0x00000010
264 #define AD_SZ_16K 0x00000020
265 #define AD_SZ_SZD 0x00000030
266 #define AD_AG32 0x00000008
267 #define AD_ADDR_ALIGN 0x00000fff
268 #define AD_SZ_BASE 0x00001000 /* 4KB */
269
270 /* EROM SizeDesc */
271 #define SD_SZ_MASK 0xfffff000
272 #define SD_SG32 0x00000008
273 #define SD_SZ_ALIGN 0x00000fff
274
275 /* PCI config space bit 4 for 4306c0 slow clock source */
276 #define PCI_CFG_GPIO_SCS 0x10
277 /* PCI config space GPIO 14 for Xtal power-up */
278 #define PCI_CFG_GPIO_XTAL 0x40
279 /* PCI config space GPIO 15 for PLL power-down */
280 #define PCI_CFG_GPIO_PLL 0x80
281
282 /* power control defines */
283 #define PLL_DELAY 150 /* us pll on delay */
284 #define FREF_DELAY 200 /* us fref change delay */
285 #define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
286
287 /* resetctrl */
288 #define AIRC_RESET 1
289
290 #define NOREV -1 /* Invalid rev */
291
292 /* GPIO Based LED powersave defines */
293 #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
294 #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
295
296 /* When Srom support present, fields in sromcontrol */
297 #define SRC_START 0x80000000
298 #define SRC_BUSY 0x80000000
299 #define SRC_OPCODE 0x60000000
300 #define SRC_OP_READ 0x00000000
301 #define SRC_OP_WRITE 0x20000000
302 #define SRC_OP_WRDIS 0x40000000
303 #define SRC_OP_WREN 0x60000000
304 #define SRC_OTPSEL 0x00000010
305 #define SRC_LOCK 0x00000008
306 #define SRC_SIZE_MASK 0x00000006
307 #define SRC_SIZE_1K 0x00000000
308 #define SRC_SIZE_4K 0x00000002
309 #define SRC_SIZE_16K 0x00000004
310 #define SRC_SIZE_SHIFT 1
311 #define SRC_PRESENT 0x00000001
312
313 /* External PA enable mask */
314 #define GPIO_CTRL_EPA_EN_MASK 0x40
315
316 #define DEFAULT_GPIOTIMERVAL \
317 ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
318
319 #define BADIDX (SI_MAXCORES + 1)
320
321 #define IS_SIM(chippkg) \
322 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
323
324 #define PCI(sih) (ai_get_buscoretype(sih) == PCI_CORE_ID)
325 #define PCIE(sih) (ai_get_buscoretype(sih) == PCIE_CORE_ID)
326
327 #define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
328
329 #ifdef DEBUG
330 #define SI_MSG(fmt, ...) pr_debug(fmt, ##__VA_ARGS__)
331 #else
332 #define SI_MSG(fmt, ...) no_printk(fmt, ##__VA_ARGS__)
333 #endif /* DEBUG */
334
335 #define GOODCOREADDR(x, b) \
336 (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
337 IS_ALIGNED((x), SI_CORE_SIZE))
338
339 struct aidmp {
340 u32 oobselina30; /* 0x000 */
341 u32 oobselina74; /* 0x004 */
342 u32 PAD[6];
343 u32 oobselinb30; /* 0x020 */
344 u32 oobselinb74; /* 0x024 */
345 u32 PAD[6];
346 u32 oobselinc30; /* 0x040 */
347 u32 oobselinc74; /* 0x044 */
348 u32 PAD[6];
349 u32 oobselind30; /* 0x060 */
350 u32 oobselind74; /* 0x064 */
351 u32 PAD[38];
352 u32 oobselouta30; /* 0x100 */
353 u32 oobselouta74; /* 0x104 */
354 u32 PAD[6];
355 u32 oobseloutb30; /* 0x120 */
356 u32 oobseloutb74; /* 0x124 */
357 u32 PAD[6];
358 u32 oobseloutc30; /* 0x140 */
359 u32 oobseloutc74; /* 0x144 */
360 u32 PAD[6];
361 u32 oobseloutd30; /* 0x160 */
362 u32 oobseloutd74; /* 0x164 */
363 u32 PAD[38];
364 u32 oobsynca; /* 0x200 */
365 u32 oobseloutaen; /* 0x204 */
366 u32 PAD[6];
367 u32 oobsyncb; /* 0x220 */
368 u32 oobseloutben; /* 0x224 */
369 u32 PAD[6];
370 u32 oobsyncc; /* 0x240 */
371 u32 oobseloutcen; /* 0x244 */
372 u32 PAD[6];
373 u32 oobsyncd; /* 0x260 */
374 u32 oobseloutden; /* 0x264 */
375 u32 PAD[38];
376 u32 oobaextwidth; /* 0x300 */
377 u32 oobainwidth; /* 0x304 */
378 u32 oobaoutwidth; /* 0x308 */
379 u32 PAD[5];
380 u32 oobbextwidth; /* 0x320 */
381 u32 oobbinwidth; /* 0x324 */
382 u32 oobboutwidth; /* 0x328 */
383 u32 PAD[5];
384 u32 oobcextwidth; /* 0x340 */
385 u32 oobcinwidth; /* 0x344 */
386 u32 oobcoutwidth; /* 0x348 */
387 u32 PAD[5];
388 u32 oobdextwidth; /* 0x360 */
389 u32 oobdinwidth; /* 0x364 */
390 u32 oobdoutwidth; /* 0x368 */
391 u32 PAD[37];
392 u32 ioctrlset; /* 0x400 */
393 u32 ioctrlclear; /* 0x404 */
394 u32 ioctrl; /* 0x408 */
395 u32 PAD[61];
396 u32 iostatus; /* 0x500 */
397 u32 PAD[127];
398 u32 ioctrlwidth; /* 0x700 */
399 u32 iostatuswidth; /* 0x704 */
400 u32 PAD[62];
401 u32 resetctrl; /* 0x800 */
402 u32 resetstatus; /* 0x804 */
403 u32 resetreadid; /* 0x808 */
404 u32 resetwriteid; /* 0x80c */
405 u32 PAD[60];
406 u32 errlogctrl; /* 0x900 */
407 u32 errlogdone; /* 0x904 */
408 u32 errlogstatus; /* 0x908 */
409 u32 errlogaddrlo; /* 0x90c */
410 u32 errlogaddrhi; /* 0x910 */
411 u32 errlogid; /* 0x914 */
412 u32 errloguser; /* 0x918 */
413 u32 errlogflags; /* 0x91c */
414 u32 PAD[56];
415 u32 intstatus; /* 0xa00 */
416 u32 PAD[127];
417 u32 config; /* 0xe00 */
418 u32 PAD[63];
419 u32 itcr; /* 0xf00 */
420 u32 PAD[3];
421 u32 itipooba; /* 0xf10 */
422 u32 itipoobb; /* 0xf14 */
423 u32 itipoobc; /* 0xf18 */
424 u32 itipoobd; /* 0xf1c */
425 u32 PAD[4];
426 u32 itipoobaout; /* 0xf30 */
427 u32 itipoobbout; /* 0xf34 */
428 u32 itipoobcout; /* 0xf38 */
429 u32 itipoobdout; /* 0xf3c */
430 u32 PAD[4];
431 u32 itopooba; /* 0xf50 */
432 u32 itopoobb; /* 0xf54 */
433 u32 itopoobc; /* 0xf58 */
434 u32 itopoobd; /* 0xf5c */
435 u32 PAD[4];
436 u32 itopoobain; /* 0xf70 */
437 u32 itopoobbin; /* 0xf74 */
438 u32 itopoobcin; /* 0xf78 */
439 u32 itopoobdin; /* 0xf7c */
440 u32 PAD[4];
441 u32 itopreset; /* 0xf90 */
442 u32 PAD[15];
443 u32 peripherialid4; /* 0xfd0 */
444 u32 peripherialid5; /* 0xfd4 */
445 u32 peripherialid6; /* 0xfd8 */
446 u32 peripherialid7; /* 0xfdc */
447 u32 peripherialid0; /* 0xfe0 */
448 u32 peripherialid1; /* 0xfe4 */
449 u32 peripherialid2; /* 0xfe8 */
450 u32 peripherialid3; /* 0xfec */
451 u32 componentid0; /* 0xff0 */
452 u32 componentid1; /* 0xff4 */
453 u32 componentid2; /* 0xff8 */
454 u32 componentid3; /* 0xffc */
455 };
456
457 /* return true if PCIE capability exists in the pci config space */
458 static bool ai_ispcie(struct si_info *sii)
459 {
460 u8 cap_ptr;
461
462 cap_ptr =
463 pcicore_find_pci_capability(sii->pcibus, PCI_CAP_ID_EXP, NULL,
464 NULL);
465 if (!cap_ptr)
466 return false;
467
468 return true;
469 }
470
471 static bool ai_buscore_prep(struct si_info *sii)
472 {
473 /* kludge to enable the clock on the 4306 which lacks a slowclock */
474 if (!ai_ispcie(sii))
475 ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
476 return true;
477 }
478
479 static bool
480 ai_buscore_setup(struct si_info *sii, struct bcma_device *cc)
481 {
482 struct bcma_device *pci = NULL;
483 struct bcma_device *pcie = NULL;
484 struct bcma_device *core;
485
486
487 /* no cores found, bail out */
488 if (cc->bus->nr_cores == 0)
489 return false;
490
491 /* get chipcommon rev */
492 sii->pub.ccrev = cc->id.rev;
493
494 /* get chipcommon chipstatus */
495 if (ai_get_ccrev(&sii->pub) >= 11)
496 sii->chipst = bcma_read32(cc, CHIPCREGOFFS(chipstatus));
497
498 /* get chipcommon capabilites */
499 sii->pub.cccaps = bcma_read32(cc, CHIPCREGOFFS(capabilities));
500
501 /* get pmu rev and caps */
502 if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
503 sii->pub.pmucaps = bcma_read32(cc,
504 CHIPCREGOFFS(pmucapabilities));
505 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
506 }
507
508 /* figure out buscore */
509 list_for_each_entry(core, &cc->bus->cores, list) {
510 uint cid, crev;
511
512 cid = core->id.id;
513 crev = core->id.rev;
514
515 if (cid == PCI_CORE_ID) {
516 pci = core;
517 } else if (cid == PCIE_CORE_ID) {
518 pcie = core;
519 }
520 }
521
522 if (pci && pcie) {
523 if (ai_ispcie(sii))
524 pci = NULL;
525 else
526 pcie = NULL;
527 }
528 if (pci) {
529 sii->buscore = pci;
530 } else if (pcie) {
531 sii->buscore = pcie;
532 }
533
534 /* fixup necessary chip/core configurations */
535 if (!sii->pch) {
536 sii->pch = pcicore_init(&sii->pub, sii->icbus->drv_pci.core);
537 if (sii->pch == NULL)
538 return false;
539 }
540 if (ai_pci_fixcfg(&sii->pub))
541 return false;
542
543 return true;
544 }
545
546 /*
547 * get boardtype and boardrev
548 */
549 static __used void ai_nvram_process(struct si_info *sii)
550 {
551 uint w = 0;
552
553 /* do a pci config read to get subsystem id and subvendor id */
554 pci_read_config_dword(sii->pcibus, PCI_SUBSYSTEM_VENDOR_ID, &w);
555
556 sii->pub.boardvendor = w & 0xffff;
557 sii->pub.boardtype = (w >> 16) & 0xffff;
558 }
559
560 static struct si_info *ai_doattach(struct si_info *sii,
561 struct bcma_bus *pbus)
562 {
563 struct si_pub *sih = &sii->pub;
564 u32 w, savewin;
565 struct bcma_device *cc;
566 uint socitype;
567 struct ssb_sprom *sprom = &pbus->sprom;
568
569 savewin = 0;
570
571 sii->icbus = pbus;
572 sii->pcibus = pbus->host_pci;
573
574 /* switch to Chipcommon core */
575 cc = pbus->drv_cc.core;
576
577 /* bus/core/clk setup for register access */
578 if (!ai_buscore_prep(sii))
579 return NULL;
580
581 /*
582 * ChipID recognition.
583 * We assume we can read chipid at offset 0 from the regs arg.
584 * If we add other chiptypes (or if we need to support old sdio
585 * hosts w/o chipcommon), some way of recognizing them needs to
586 * be added here.
587 */
588 w = bcma_read32(cc, CHIPCREGOFFS(chipid));
589 socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
590 /* Might as wll fill in chip id rev & pkg */
591 sih->chip = w & CID_ID_MASK;
592 sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
593 sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
594
595 /* scan for cores */
596 if (socitype != SOCI_AI)
597 return NULL;
598
599 SI_MSG("Found chip type AI (0x%08x)\n", w);
600 if (!ai_buscore_setup(sii, cc))
601 goto exit;
602
603 /* Init nvram from sprom/otp if they exist */
604 if (srom_var_init(&sii->pub))
605 goto exit;
606
607 ai_nvram_process(sii);
608
609 /* === NVRAM, clock is ready === */
610 bcma_write32(cc, CHIPCREGOFFS(gpiopullup), 0);
611 bcma_write32(cc, CHIPCREGOFFS(gpiopulldown), 0);
612
613 /* PMU specific initializations */
614 if (ai_get_cccaps(sih) & CC_CAP_PMU) {
615 si_pmu_init(sih);
616 (void)si_pmu_measure_alpclk(sih);
617 si_pmu_res_init(sih);
618 }
619
620 /* setup the GPIO based LED powersave register */
621 w = (sprom->leddc_on_time << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
622 (sprom->leddc_off_time << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT);
623 if (w == 0)
624 w = DEFAULT_GPIOTIMERVAL;
625 ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
626 ~0, w);
627
628 if (PCIE(sih))
629 pcicore_attach(sii->pch, SI_DOATTACH);
630
631 if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
632 /*
633 * enable 12 mA drive strenth for 43224 and
634 * set chipControl register bit 15
635 */
636 if (ai_get_chiprev(sih) == 0) {
637 SI_MSG("Applying 43224A0 WARs\n");
638 ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol),
639 CCTRL43224_GPIO_TOGGLE,
640 CCTRL43224_GPIO_TOGGLE);
641 si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
642 CCTRL_43224A0_12MA_LED_DRIVE);
643 }
644 if (ai_get_chiprev(sih) >= 1) {
645 SI_MSG("Applying 43224B0+ WARs\n");
646 si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
647 CCTRL_43224B0_12MA_LED_DRIVE);
648 }
649 }
650
651 if (ai_get_chip_id(sih) == BCM4313_CHIP_ID) {
652 /*
653 * enable 12 mA drive strenth for 4313 and
654 * set chipControl register bit 1
655 */
656 SI_MSG("Applying 4313 WARs\n");
657 si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
658 CCTRL_4313_12MA_LED_DRIVE);
659 }
660
661 return sii;
662
663 exit:
664 if (sii->pch)
665 pcicore_deinit(sii->pch);
666 sii->pch = NULL;
667
668 return NULL;
669 }
670
671 /*
672 * Allocate a si handle and do the attach.
673 */
674 struct si_pub *
675 ai_attach(struct bcma_bus *pbus)
676 {
677 struct si_info *sii;
678
679 /* alloc struct si_info */
680 sii = kzalloc(sizeof(struct si_info), GFP_ATOMIC);
681 if (sii == NULL)
682 return NULL;
683
684 if (ai_doattach(sii, pbus) == NULL) {
685 kfree(sii);
686 return NULL;
687 }
688
689 return (struct si_pub *) sii;
690 }
691
692 /* may be called with core in reset */
693 void ai_detach(struct si_pub *sih)
694 {
695 struct si_info *sii;
696
697 struct si_pub *si_local = NULL;
698 memcpy(&si_local, &sih, sizeof(struct si_pub **));
699
700 sii = (struct si_info *)sih;
701
702 if (sii == NULL)
703 return;
704
705 if (sii->pch)
706 pcicore_deinit(sii->pch);
707 sii->pch = NULL;
708
709 srom_free_vars(sih);
710 kfree(sii);
711 }
712
713 /* return index of coreid or BADIDX if not found */
714 struct bcma_device *ai_findcore(struct si_pub *sih, u16 coreid, u16 coreunit)
715 {
716 struct bcma_device *core;
717 struct si_info *sii;
718 uint found;
719
720 sii = (struct si_info *)sih;
721
722 found = 0;
723
724 list_for_each_entry(core, &sii->icbus->cores, list)
725 if (core->id.id == coreid) {
726 if (found == coreunit)
727 return core;
728 found++;
729 }
730
731 return NULL;
732 }
733
734 /*
735 * read/modify chipcommon core register.
736 */
737 uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val)
738 {
739 struct bcma_device *cc;
740 u32 w;
741 struct si_info *sii;
742
743 sii = (struct si_info *)sih;
744 cc = sii->icbus->drv_cc.core;
745
746 /* mask and set */
747 if (mask || val) {
748 bcma_maskset32(cc, regoff, ~mask, val);
749 }
750
751 /* readback */
752 w = bcma_read32(cc, regoff);
753
754 return w;
755 }
756
757 /* return the slow clock source - LPO, XTAL, or PCI */
758 static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc)
759 {
760 struct si_info *sii;
761 u32 val;
762
763 sii = (struct si_info *)sih;
764 if (ai_get_ccrev(&sii->pub) < 6) {
765 pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT,
766 &val);
767 if (val & PCI_CFG_GPIO_SCS)
768 return SCC_SS_PCI;
769 return SCC_SS_XTAL;
770 } else if (ai_get_ccrev(&sii->pub) < 10) {
771 return bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
772 SCC_SS_MASK;
773 } else /* Insta-clock */
774 return SCC_SS_XTAL;
775 }
776
777 /*
778 * return the ILP (slowclock) min or max frequency
779 * precondition: we've established the chip has dynamic clk control
780 */
781 static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq,
782 struct bcma_device *cc)
783 {
784 u32 slowclk;
785 uint div;
786
787 slowclk = ai_slowclk_src(sih, cc);
788 if (ai_get_ccrev(sih) < 6) {
789 if (slowclk == SCC_SS_PCI)
790 return max_freq ? (PCIMAXFREQ / 64)
791 : (PCIMINFREQ / 64);
792 else
793 return max_freq ? (XTALMAXFREQ / 32)
794 : (XTALMINFREQ / 32);
795 } else if (ai_get_ccrev(sih) < 10) {
796 div = 4 *
797 (((bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl)) &
798 SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
799 if (slowclk == SCC_SS_LPO)
800 return max_freq ? LPOMAXFREQ : LPOMINFREQ;
801 else if (slowclk == SCC_SS_XTAL)
802 return max_freq ? (XTALMAXFREQ / div)
803 : (XTALMINFREQ / div);
804 else if (slowclk == SCC_SS_PCI)
805 return max_freq ? (PCIMAXFREQ / div)
806 : (PCIMINFREQ / div);
807 } else {
808 /* Chipc rev 10 is InstaClock */
809 div = bcma_read32(cc, CHIPCREGOFFS(system_clk_ctl));
810 div = 4 * ((div >> SYCC_CD_SHIFT) + 1);
811 return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
812 }
813 return 0;
814 }
815
816 static void
817 ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc)
818 {
819 uint slowmaxfreq, pll_delay, slowclk;
820 uint pll_on_delay, fref_sel_delay;
821
822 pll_delay = PLL_DELAY;
823
824 /*
825 * If the slow clock is not sourced by the xtal then
826 * add the xtal_on_delay since the xtal will also be
827 * powered down by dynamic clk control logic.
828 */
829
830 slowclk = ai_slowclk_src(sih, cc);
831 if (slowclk != SCC_SS_XTAL)
832 pll_delay += XTAL_ON_DELAY;
833
834 /* Starting with 4318 it is ILP that is used for the delays */
835 slowmaxfreq =
836 ai_slowclk_freq(sih,
837 (ai_get_ccrev(sih) >= 10) ? false : true, cc);
838
839 pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
840 fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
841
842 bcma_write32(cc, CHIPCREGOFFS(pll_on_delay), pll_on_delay);
843 bcma_write32(cc, CHIPCREGOFFS(fref_sel_delay), fref_sel_delay);
844 }
845
846 /* initialize power control delay registers */
847 void ai_clkctl_init(struct si_pub *sih)
848 {
849 struct bcma_device *cc;
850
851 if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
852 return;
853
854 cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
855 if (cc == NULL)
856 return;
857
858 /* set all Instaclk chip ILP to 1 MHz */
859 if (ai_get_ccrev(sih) >= 10)
860 bcma_maskset32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_CD_MASK,
861 (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
862
863 ai_clkctl_setdelay(sih, cc);
864 }
865
866 /*
867 * return the value suitable for writing to the
868 * dot11 core FAST_PWRUP_DELAY register
869 */
870 u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih)
871 {
872 struct si_info *sii;
873 struct bcma_device *cc;
874 uint slowminfreq;
875 u16 fpdelay;
876
877 sii = (struct si_info *)sih;
878 if (ai_get_cccaps(sih) & CC_CAP_PMU) {
879 fpdelay = si_pmu_fast_pwrup_delay(sih);
880 return fpdelay;
881 }
882
883 if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
884 return 0;
885
886 fpdelay = 0;
887 cc = ai_findcore(sih, CC_CORE_ID, 0);
888 if (cc) {
889 slowminfreq = ai_slowclk_freq(sih, false, cc);
890 fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2)
891 * 1000000) + (slowminfreq - 1)) / slowminfreq;
892 }
893 return fpdelay;
894 }
895
896 /* turn primary xtal and/or pll off/on */
897 int ai_clkctl_xtal(struct si_pub *sih, uint what, bool on)
898 {
899 struct si_info *sii;
900 u32 in, out, outen;
901
902 sii = (struct si_info *)sih;
903
904 /* pcie core doesn't have any mapping to control the xtal pu */
905 if (PCIE(sih))
906 return -1;
907
908 pci_read_config_dword(sii->pcibus, PCI_GPIO_IN, &in);
909 pci_read_config_dword(sii->pcibus, PCI_GPIO_OUT, &out);
910 pci_read_config_dword(sii->pcibus, PCI_GPIO_OUTEN, &outen);
911
912 /*
913 * Avoid glitching the clock if GPRS is already using it.
914 * We can't actually read the state of the PLLPD so we infer it
915 * by the value of XTAL_PU which *is* readable via gpioin.
916 */
917 if (on && (in & PCI_CFG_GPIO_XTAL))
918 return 0;
919
920 if (what & XTAL)
921 outen |= PCI_CFG_GPIO_XTAL;
922 if (what & PLL)
923 outen |= PCI_CFG_GPIO_PLL;
924
925 if (on) {
926 /* turn primary xtal on */
927 if (what & XTAL) {
928 out |= PCI_CFG_GPIO_XTAL;
929 if (what & PLL)
930 out |= PCI_CFG_GPIO_PLL;
931 pci_write_config_dword(sii->pcibus,
932 PCI_GPIO_OUT, out);
933 pci_write_config_dword(sii->pcibus,
934 PCI_GPIO_OUTEN, outen);
935 udelay(XTAL_ON_DELAY);
936 }
937
938 /* turn pll on */
939 if (what & PLL) {
940 out &= ~PCI_CFG_GPIO_PLL;
941 pci_write_config_dword(sii->pcibus,
942 PCI_GPIO_OUT, out);
943 mdelay(2);
944 }
945 } else {
946 if (what & XTAL)
947 out &= ~PCI_CFG_GPIO_XTAL;
948 if (what & PLL)
949 out |= PCI_CFG_GPIO_PLL;
950 pci_write_config_dword(sii->pcibus,
951 PCI_GPIO_OUT, out);
952 pci_write_config_dword(sii->pcibus,
953 PCI_GPIO_OUTEN, outen);
954 }
955
956 return 0;
957 }
958
959 /* clk control mechanism through chipcommon, no policy checking */
960 static bool _ai_clkctl_cc(struct si_info *sii, uint mode)
961 {
962 struct bcma_device *cc;
963 u32 scc;
964
965 /* chipcommon cores prior to rev6 don't support dynamic clock control */
966 if (ai_get_ccrev(&sii->pub) < 6)
967 return false;
968
969 cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
970
971 if (!(ai_get_cccaps(&sii->pub) & CC_CAP_PWR_CTL) &&
972 (ai_get_ccrev(&sii->pub) < 20))
973 return mode == CLK_FAST;
974
975 switch (mode) {
976 case CLK_FAST: /* FORCEHT, fast (pll) clock */
977 if (ai_get_ccrev(&sii->pub) < 10) {
978 /*
979 * don't forget to force xtal back
980 * on before we clear SCC_DYN_XTAL..
981 */
982 ai_clkctl_xtal(&sii->pub, XTAL, ON);
983 bcma_maskset32(cc, CHIPCREGOFFS(slow_clk_ctl),
984 (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
985 } else if (ai_get_ccrev(&sii->pub) < 20) {
986 bcma_set32(cc, CHIPCREGOFFS(system_clk_ctl), SYCC_HR);
987 } else {
988 bcma_set32(cc, CHIPCREGOFFS(clk_ctl_st), CCS_FORCEHT);
989 }
990
991 /* wait for the PLL */
992 if (ai_get_cccaps(&sii->pub) & CC_CAP_PMU) {
993 u32 htavail = CCS_HTAVAIL;
994 SPINWAIT(((bcma_read32(cc, CHIPCREGOFFS(clk_ctl_st)) &
995 htavail) == 0), PMU_MAX_TRANSITION_DLY);
996 } else {
997 udelay(PLL_DELAY);
998 }
999 break;
1000
1001 case CLK_DYNAMIC: /* enable dynamic clock control */
1002 if (ai_get_ccrev(&sii->pub) < 10) {
1003 scc = bcma_read32(cc, CHIPCREGOFFS(slow_clk_ctl));
1004 scc &= ~(SCC_FS | SCC_IP | SCC_XC);
1005 if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
1006 scc |= SCC_XC;
1007 bcma_write32(cc, CHIPCREGOFFS(slow_clk_ctl), scc);
1008
1009 /*
1010 * for dynamic control, we have to
1011 * release our xtal_pu "force on"
1012 */
1013 if (scc & SCC_XC)
1014 ai_clkctl_xtal(&sii->pub, XTAL, OFF);
1015 } else if (ai_get_ccrev(&sii->pub) < 20) {
1016 /* Instaclock */
1017 bcma_mask32(cc, CHIPCREGOFFS(system_clk_ctl), ~SYCC_HR);
1018 } else {
1019 bcma_mask32(cc, CHIPCREGOFFS(clk_ctl_st), ~CCS_FORCEHT);
1020 }
1021 break;
1022
1023 default:
1024 break;
1025 }
1026
1027 return mode == CLK_FAST;
1028 }
1029
1030 /*
1031 * clock control policy function throught chipcommon
1032 *
1033 * set dynamic clk control mode (forceslow, forcefast, dynamic)
1034 * returns true if we are forcing fast clock
1035 * this is a wrapper over the next internal function
1036 * to allow flexible policy settings for outside caller
1037 */
1038 bool ai_clkctl_cc(struct si_pub *sih, uint mode)
1039 {
1040 struct si_info *sii;
1041
1042 sii = (struct si_info *)sih;
1043
1044 /* chipcommon cores prior to rev6 don't support dynamic clock control */
1045 if (ai_get_ccrev(sih) < 6)
1046 return false;
1047
1048 if (PCI_FORCEHT(sih))
1049 return mode == CLK_FAST;
1050
1051 return _ai_clkctl_cc(sii, mode);
1052 }
1053
1054 void ai_pci_up(struct si_pub *sih)
1055 {
1056 struct si_info *sii;
1057
1058 sii = (struct si_info *)sih;
1059
1060 if (PCI_FORCEHT(sih))
1061 _ai_clkctl_cc(sii, CLK_FAST);
1062
1063 if (PCIE(sih))
1064 pcicore_up(sii->pch, SI_PCIUP);
1065
1066 }
1067
1068 /* Unconfigure and/or apply various WARs when system is going to sleep mode */
1069 void ai_pci_sleep(struct si_pub *sih)
1070 {
1071 struct si_info *sii;
1072
1073 sii = (struct si_info *)sih;
1074
1075 pcicore_sleep(sii->pch);
1076 }
1077
1078 /* Unconfigure and/or apply various WARs when going down */
1079 void ai_pci_down(struct si_pub *sih)
1080 {
1081 struct si_info *sii;
1082
1083 sii = (struct si_info *)sih;
1084
1085 /* release FORCEHT since chip is going to "down" state */
1086 if (PCI_FORCEHT(sih))
1087 _ai_clkctl_cc(sii, CLK_DYNAMIC);
1088
1089 pcicore_down(sii->pch, SI_PCIDOWN);
1090 }
1091
1092 /*
1093 * Configure the pci core for pci client (NIC) action
1094 * coremask is the bitvec of cores by index to be enabled.
1095 */
1096 void ai_pci_setup(struct si_pub *sih, uint coremask)
1097 {
1098 struct si_info *sii;
1099 u32 w;
1100
1101 sii = (struct si_info *)sih;
1102
1103 /*
1104 * Enable sb->pci interrupts. Assume
1105 * PCI rev 2.3 support was added in pci core rev 6 and things changed..
1106 */
1107 if (PCIE(sih) || (PCI(sih) && (ai_get_buscorerev(sih) >= 6))) {
1108 /* pci config write to set this core bit in PCIIntMask */
1109 pci_read_config_dword(sii->pcibus, PCI_INT_MASK, &w);
1110 w |= (coremask << PCI_SBIM_SHIFT);
1111 pci_write_config_dword(sii->pcibus, PCI_INT_MASK, w);
1112 }
1113
1114 if (PCI(sih)) {
1115 pcicore_pci_setup(sii->pch);
1116 }
1117 }
1118
1119 /*
1120 * Fixup SROMless PCI device's configuration.
1121 * The current core may be changed upon return.
1122 */
1123 int ai_pci_fixcfg(struct si_pub *sih)
1124 {
1125 struct si_info *sii = (struct si_info *)sih;
1126
1127 /* Fixup PI in SROM shadow area to enable the correct PCI core access */
1128 /* check 'pi' is correct and fix it if not */
1129 pcicore_fixcfg(sii->pch);
1130 pcicore_hwup(sii->pch);
1131 return 0;
1132 }
1133
1134 /* mask&set gpiocontrol bits */
1135 u32 ai_gpiocontrol(struct si_pub *sih, u32 mask, u32 val, u8 priority)
1136 {
1137 uint regoff;
1138
1139 regoff = offsetof(struct chipcregs, gpiocontrol);
1140 return ai_cc_reg(sih, regoff, mask, val);
1141 }
1142
1143 void ai_chipcontrl_epa4331(struct si_pub *sih, bool on)
1144 {
1145 struct bcma_device *cc;
1146 u32 val;
1147
1148 cc = ai_findcore(sih, CC_CORE_ID, 0);
1149
1150 if (on) {
1151 if (ai_get_chippkg(sih) == 9 || ai_get_chippkg(sih) == 0xb)
1152 /* Ext PA Controls for 4331 12x9 Package */
1153 bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
1154 CCTRL4331_EXTPA_EN |
1155 CCTRL4331_EXTPA_ON_GPIO2_5);
1156 else
1157 /* Ext PA Controls for 4331 12x12 Package */
1158 bcma_set32(cc, CHIPCREGOFFS(chipcontrol),
1159 CCTRL4331_EXTPA_EN);
1160 } else {
1161 val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
1162 bcma_mask32(cc, CHIPCREGOFFS(chipcontrol),
1163 ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5));
1164 }
1165 }
1166
1167 /* Enable BT-COEX & Ex-PA for 4313 */
1168 void ai_epa_4313war(struct si_pub *sih)
1169 {
1170 struct bcma_device *cc;
1171
1172 cc = ai_findcore(sih, CC_CORE_ID, 0);
1173
1174 /* EPA Fix */
1175 bcma_set32(cc, CHIPCREGOFFS(gpiocontrol), GPIO_CTRL_EPA_EN_MASK);
1176 }
1177
1178 /* check if the device is removed */
1179 bool ai_deviceremoved(struct si_pub *sih)
1180 {
1181 u32 w;
1182 struct si_info *sii;
1183
1184 sii = (struct si_info *)sih;
1185
1186 pci_read_config_dword(sii->pcibus, PCI_VENDOR_ID, &w);
1187 if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
1188 return true;
1189
1190 return false;
1191 }
1192
1193 bool ai_is_sprom_available(struct si_pub *sih)
1194 {
1195 struct si_info *sii = (struct si_info *)sih;
1196
1197 if (ai_get_ccrev(sih) >= 31) {
1198 struct bcma_device *cc;
1199 u32 sromctrl;
1200
1201 if ((ai_get_cccaps(sih) & CC_CAP_SROM) == 0)
1202 return false;
1203
1204 cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
1205 sromctrl = bcma_read32(cc, CHIPCREGOFFS(sromcontrol));
1206 return sromctrl & SRC_PRESENT;
1207 }
1208
1209 switch (ai_get_chip_id(sih)) {
1210 case BCM4313_CHIP_ID:
1211 return (sii->chipst & CST4313_SPROM_PRESENT) != 0;
1212 default:
1213 return true;
1214 }
1215 }
1216
1217 bool ai_is_otp_disabled(struct si_pub *sih)
1218 {
1219 struct si_info *sii = (struct si_info *)sih;
1220
1221 switch (ai_get_chip_id(sih)) {
1222 case BCM4313_CHIP_ID:
1223 return (sii->chipst & CST4313_OTP_PRESENT) == 0;
1224 /* These chips always have their OTP on */
1225 case BCM43224_CHIP_ID:
1226 case BCM43225_CHIP_ID:
1227 default:
1228 return false;
1229 }
1230 }
1231
1232 uint ai_get_buscoretype(struct si_pub *sih)
1233 {
1234 struct si_info *sii = (struct si_info *)sih;
1235 return sii->buscore->id.id;
1236 }
1237
1238 uint ai_get_buscorerev(struct si_pub *sih)
1239 {
1240 struct si_info *sii = (struct si_info *)sih;
1241 return sii->buscore->id.rev;
1242 }
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