2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
5 * Right now, I am very wasteful with the buffers. I allocate memory
6 * pages and then divide them into 2K frame buffers. This way I know I
7 * have buffers large enough to hold one frame within one buffer descriptor.
8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which
9 * will be much more memory efficient and will easily handle lots of
12 * Much better multiple PHY support by Magnus Damm.
13 * Copyright (c) 2000 Ericsson Radio Systems AB.
15 * Support for FEC controller of ColdFire processors.
16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com)
18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be)
19 * Copyright (c) 2004-2006 Macq Electronique SA.
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/string.h>
25 #include <linux/ptrace.h>
26 #include <linux/errno.h>
27 #include <linux/ioport.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/delay.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/skbuff.h>
36 #include <linux/spinlock.h>
37 #include <linux/workqueue.h>
38 #include <linux/bitops.h>
40 #include <linux/irq.h>
41 #include <linux/clk.h>
42 #include <linux/platform_device.h>
43 #include <linux/phy.h>
44 #include <linux/fec.h>
46 #include <asm/cacheflush.h>
48 #ifndef CONFIG_ARCH_MXC
49 #include <asm/coldfire.h>
50 #include <asm/mcfsim.h>
55 #ifdef CONFIG_ARCH_MXC
56 #include <mach/hardware.h>
57 #define FEC_ALIGNMENT 0xf
59 #define FEC_ALIGNMENT 0x3
63 * Define the fixed address of the FEC hardware.
65 #if defined(CONFIG_M5272)
67 static unsigned char fec_mac_default
[] = {
68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72 * Some hardware gets it MAC address out of local flash memory.
73 * if this is non-zero then assume it is the address to get MAC from.
75 #if defined(CONFIG_NETtel)
76 #define FEC_FLASHMAC 0xf0006006
77 #elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES)
78 #define FEC_FLASHMAC 0xf0006000
79 #elif defined(CONFIG_CANCam)
80 #define FEC_FLASHMAC 0xf0020000
81 #elif defined (CONFIG_M5272C3)
82 #define FEC_FLASHMAC (0xffe04000 + 4)
83 #elif defined(CONFIG_MOD5272)
84 #define FEC_FLASHMAC 0xffc0406b
86 #define FEC_FLASHMAC 0
88 #endif /* CONFIG_M5272 */
90 /* The number of Tx and Rx buffers. These are allocated from the page
91 * pool. The code may assume these are power of two, so it it best
92 * to keep them that size.
93 * We don't need to allocate pages for the transmitter. We just use
94 * the skbuffer directly.
96 #define FEC_ENET_RX_PAGES 8
97 #define FEC_ENET_RX_FRSIZE 2048
98 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE)
99 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES)
100 #define FEC_ENET_TX_FRSIZE 2048
101 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE)
102 #define TX_RING_SIZE 16 /* Must be power of two */
103 #define TX_RING_MOD_MASK 15 /* for this to work */
105 #if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE)
106 #error "FEC: descriptor ring size constants too large"
109 /* Interrupt events/masks. */
110 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */
111 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */
112 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */
113 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */
114 #define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */
115 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */
116 #define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */
117 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */
118 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */
119 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */
121 /* The FEC stores dest/src/type, data, and checksum for receive packets.
123 #define PKT_MAXBUF_SIZE 1518
124 #define PKT_MINBUF_SIZE 64
125 #define PKT_MAXBLR_SIZE 1520
129 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame
130 * size bits. Other FEC hardware does not, so we need to take that into
131 * account when setting it.
133 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
134 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC)
135 #define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16)
137 #define OPT_FRAME_SIZE 0
140 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and
141 * tx_bd_base always point to the base of the buffer descriptors. The
142 * cur_rx and cur_tx point to the currently available buffer.
143 * The dirty_tx tracks the current buffer that is being sent by the
144 * controller. The cur_tx and dirty_tx are equal under both completely
145 * empty and completely full conditions. The empty/ready indicator in
146 * the buffer descriptor determines the actual condition.
148 struct fec_enet_private
{
149 /* Hardware registers of the FEC device */
152 struct net_device
*netdev
;
156 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
157 unsigned char *tx_bounce
[TX_RING_SIZE
];
158 struct sk_buff
* tx_skbuff
[TX_RING_SIZE
];
159 struct sk_buff
* rx_skbuff
[RX_RING_SIZE
];
163 /* CPM dual port RAM relative addresses */
165 /* Address of Rx and Tx buffers */
166 struct bufdesc
*rx_bd_base
;
167 struct bufdesc
*tx_bd_base
;
168 /* The next free ring entry */
169 struct bufdesc
*cur_rx
, *cur_tx
;
170 /* The ring entries to be free()ed */
171 struct bufdesc
*dirty_tx
;
174 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */
177 struct platform_device
*pdev
;
181 /* Phylib and MDIO interface */
182 struct mii_bus
*mii_bus
;
183 struct phy_device
*phy_dev
;
186 phy_interface_t phy_interface
;
192 static irqreturn_t
fec_enet_interrupt(int irq
, void * dev_id
);
193 static void fec_enet_tx(struct net_device
*dev
);
194 static void fec_enet_rx(struct net_device
*dev
);
195 static int fec_enet_close(struct net_device
*dev
);
196 static void fec_restart(struct net_device
*dev
, int duplex
);
197 static void fec_stop(struct net_device
*dev
);
199 /* FEC MII MMFR bits definition */
200 #define FEC_MMFR_ST (1 << 30)
201 #define FEC_MMFR_OP_READ (2 << 28)
202 #define FEC_MMFR_OP_WRITE (1 << 28)
203 #define FEC_MMFR_PA(v) ((v & 0x1f) << 23)
204 #define FEC_MMFR_RA(v) ((v & 0x1f) << 18)
205 #define FEC_MMFR_TA (2 << 16)
206 #define FEC_MMFR_DATA(v) (v & 0xffff)
208 #define FEC_MII_TIMEOUT 10000
210 /* Transmitter timeout */
211 #define TX_TIMEOUT (2 * HZ)
214 fec_enet_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
216 struct fec_enet_private
*fep
= netdev_priv(dev
);
219 unsigned short status
;
223 /* Link is down or autonegotiation is in progress. */
224 return NETDEV_TX_BUSY
;
227 spin_lock_irqsave(&fep
->hw_lock
, flags
);
228 /* Fill in a Tx ring entry */
231 status
= bdp
->cbd_sc
;
233 if (status
& BD_ENET_TX_READY
) {
234 /* Ooops. All transmit buffers are full. Bail out.
235 * This should not happen, since dev->tbusy should be set.
237 printk("%s: tx queue full!.\n", dev
->name
);
238 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
239 return NETDEV_TX_BUSY
;
242 /* Clear all of the status flags */
243 status
&= ~BD_ENET_TX_STATS
;
245 /* Set buffer length and buffer pointer */
247 bdp
->cbd_datlen
= skb
->len
;
250 * On some FEC implementations data must be aligned on
251 * 4-byte boundaries. Use bounce buffers to copy data
252 * and get it aligned. Ugh.
254 if (((unsigned long) bufaddr
) & FEC_ALIGNMENT
) {
256 index
= bdp
- fep
->tx_bd_base
;
257 memcpy(fep
->tx_bounce
[index
], (void *)skb
->data
, skb
->len
);
258 bufaddr
= fep
->tx_bounce
[index
];
261 /* Save skb pointer */
262 fep
->tx_skbuff
[fep
->skb_cur
] = skb
;
264 dev
->stats
.tx_bytes
+= skb
->len
;
265 fep
->skb_cur
= (fep
->skb_cur
+1) & TX_RING_MOD_MASK
;
267 /* Push the data cache so the CPM does not get stale memory
270 bdp
->cbd_bufaddr
= dma_map_single(&dev
->dev
, bufaddr
,
271 FEC_ENET_TX_FRSIZE
, DMA_TO_DEVICE
);
273 /* Send it on its way. Tell FEC it's ready, interrupt when done,
274 * it's the last BD of the frame, and to put the CRC on the end.
276 status
|= (BD_ENET_TX_READY
| BD_ENET_TX_INTR
277 | BD_ENET_TX_LAST
| BD_ENET_TX_TC
);
278 bdp
->cbd_sc
= status
;
280 /* Trigger transmission start */
281 writel(0, fep
->hwp
+ FEC_X_DES_ACTIVE
);
283 /* If this was the last BD in the ring, start at the beginning again. */
284 if (status
& BD_ENET_TX_WRAP
)
285 bdp
= fep
->tx_bd_base
;
289 if (bdp
== fep
->dirty_tx
) {
291 netif_stop_queue(dev
);
296 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
302 fec_timeout(struct net_device
*dev
)
304 struct fec_enet_private
*fep
= netdev_priv(dev
);
306 dev
->stats
.tx_errors
++;
308 fec_restart(dev
, fep
->full_duplex
);
309 netif_wake_queue(dev
);
313 fec_enet_interrupt(int irq
, void * dev_id
)
315 struct net_device
*dev
= dev_id
;
316 struct fec_enet_private
*fep
= netdev_priv(dev
);
318 irqreturn_t ret
= IRQ_NONE
;
321 int_events
= readl(fep
->hwp
+ FEC_IEVENT
);
322 writel(int_events
, fep
->hwp
+ FEC_IEVENT
);
324 if (int_events
& FEC_ENET_RXF
) {
329 /* Transmit OK, or non-fatal error. Update the buffer
330 * descriptors. FEC handles all errors, we just discover
331 * them as part of the transmit process.
333 if (int_events
& FEC_ENET_TXF
) {
337 } while (int_events
);
344 fec_enet_tx(struct net_device
*dev
)
346 struct fec_enet_private
*fep
;
348 unsigned short status
;
351 fep
= netdev_priv(dev
);
352 spin_lock(&fep
->hw_lock
);
355 while (((status
= bdp
->cbd_sc
) & BD_ENET_TX_READY
) == 0) {
356 if (bdp
== fep
->cur_tx
&& fep
->tx_full
== 0)
359 dma_unmap_single(&dev
->dev
, bdp
->cbd_bufaddr
, FEC_ENET_TX_FRSIZE
, DMA_TO_DEVICE
);
360 bdp
->cbd_bufaddr
= 0;
362 skb
= fep
->tx_skbuff
[fep
->skb_dirty
];
363 /* Check for errors. */
364 if (status
& (BD_ENET_TX_HB
| BD_ENET_TX_LC
|
365 BD_ENET_TX_RL
| BD_ENET_TX_UN
|
367 dev
->stats
.tx_errors
++;
368 if (status
& BD_ENET_TX_HB
) /* No heartbeat */
369 dev
->stats
.tx_heartbeat_errors
++;
370 if (status
& BD_ENET_TX_LC
) /* Late collision */
371 dev
->stats
.tx_window_errors
++;
372 if (status
& BD_ENET_TX_RL
) /* Retrans limit */
373 dev
->stats
.tx_aborted_errors
++;
374 if (status
& BD_ENET_TX_UN
) /* Underrun */
375 dev
->stats
.tx_fifo_errors
++;
376 if (status
& BD_ENET_TX_CSL
) /* Carrier lost */
377 dev
->stats
.tx_carrier_errors
++;
379 dev
->stats
.tx_packets
++;
382 if (status
& BD_ENET_TX_READY
)
383 printk("HEY! Enet xmit interrupt and TX_READY.\n");
385 /* Deferred means some collisions occurred during transmit,
386 * but we eventually sent the packet OK.
388 if (status
& BD_ENET_TX_DEF
)
389 dev
->stats
.collisions
++;
391 /* Free the sk buffer associated with this last transmit */
392 dev_kfree_skb_any(skb
);
393 fep
->tx_skbuff
[fep
->skb_dirty
] = NULL
;
394 fep
->skb_dirty
= (fep
->skb_dirty
+ 1) & TX_RING_MOD_MASK
;
396 /* Update pointer to next buffer descriptor to be transmitted */
397 if (status
& BD_ENET_TX_WRAP
)
398 bdp
= fep
->tx_bd_base
;
402 /* Since we have freed up a buffer, the ring is no longer full
406 if (netif_queue_stopped(dev
))
407 netif_wake_queue(dev
);
411 spin_unlock(&fep
->hw_lock
);
415 /* During a receive, the cur_rx points to the current incoming buffer.
416 * When we update through the ring, if the next incoming buffer has
417 * not been given to the system, we just set the empty indicator,
418 * effectively tossing the packet.
421 fec_enet_rx(struct net_device
*dev
)
423 struct fec_enet_private
*fep
= netdev_priv(dev
);
425 unsigned short status
;
434 spin_lock(&fep
->hw_lock
);
436 /* First, grab all of the stats for the incoming packet.
437 * These get messed up if we get called due to a busy condition.
441 while (!((status
= bdp
->cbd_sc
) & BD_ENET_RX_EMPTY
)) {
443 /* Since we have allocated space to hold a complete frame,
444 * the last indicator should be set.
446 if ((status
& BD_ENET_RX_LAST
) == 0)
447 printk("FEC ENET: rcv is not +last\n");
450 goto rx_processing_done
;
452 /* Check for errors. */
453 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
| BD_ENET_RX_NO
|
454 BD_ENET_RX_CR
| BD_ENET_RX_OV
)) {
455 dev
->stats
.rx_errors
++;
456 if (status
& (BD_ENET_RX_LG
| BD_ENET_RX_SH
)) {
457 /* Frame too long or too short. */
458 dev
->stats
.rx_length_errors
++;
460 if (status
& BD_ENET_RX_NO
) /* Frame alignment */
461 dev
->stats
.rx_frame_errors
++;
462 if (status
& BD_ENET_RX_CR
) /* CRC Error */
463 dev
->stats
.rx_crc_errors
++;
464 if (status
& BD_ENET_RX_OV
) /* FIFO overrun */
465 dev
->stats
.rx_fifo_errors
++;
468 /* Report late collisions as a frame error.
469 * On this error, the BD is closed, but we don't know what we
470 * have in the buffer. So, just drop this frame on the floor.
472 if (status
& BD_ENET_RX_CL
) {
473 dev
->stats
.rx_errors
++;
474 dev
->stats
.rx_frame_errors
++;
475 goto rx_processing_done
;
478 /* Process the incoming frame. */
479 dev
->stats
.rx_packets
++;
480 pkt_len
= bdp
->cbd_datlen
;
481 dev
->stats
.rx_bytes
+= pkt_len
;
482 data
= (__u8
*)__va(bdp
->cbd_bufaddr
);
484 dma_unmap_single(NULL
, bdp
->cbd_bufaddr
, bdp
->cbd_datlen
,
487 /* This does 16 byte alignment, exactly what we need.
488 * The packet length includes FCS, but we don't want to
489 * include that when passing upstream as it messes up
490 * bridging applications.
492 skb
= dev_alloc_skb(pkt_len
- 4 + NET_IP_ALIGN
);
494 if (unlikely(!skb
)) {
495 printk("%s: Memory squeeze, dropping packet.\n",
497 dev
->stats
.rx_dropped
++;
499 skb_reserve(skb
, NET_IP_ALIGN
);
500 skb_put(skb
, pkt_len
- 4); /* Make room */
501 skb_copy_to_linear_data(skb
, data
, pkt_len
- 4);
502 skb
->protocol
= eth_type_trans(skb
, dev
);
506 bdp
->cbd_bufaddr
= dma_map_single(NULL
, data
, bdp
->cbd_datlen
,
509 /* Clear the status flags for this buffer */
510 status
&= ~BD_ENET_RX_STATS
;
512 /* Mark the buffer empty */
513 status
|= BD_ENET_RX_EMPTY
;
514 bdp
->cbd_sc
= status
;
516 /* Update BD pointer to next entry */
517 if (status
& BD_ENET_RX_WRAP
)
518 bdp
= fep
->rx_bd_base
;
521 /* Doing this here will keep the FEC running while we process
522 * incoming frames. On a heavily loaded network, we should be
523 * able to keep up at the expense of system resources.
525 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
529 spin_unlock(&fep
->hw_lock
);
532 /* ------------------------------------------------------------------------- */
534 static void __inline__
fec_get_mac(struct net_device
*dev
)
536 struct fec_enet_private
*fep
= netdev_priv(dev
);
537 unsigned char *iap
, tmpaddr
[ETH_ALEN
];
541 * Get MAC address from FLASH.
542 * If it is all 1's or 0's, use the default.
544 iap
= (unsigned char *)FEC_FLASHMAC
;
545 if ((iap
[0] == 0) && (iap
[1] == 0) && (iap
[2] == 0) &&
546 (iap
[3] == 0) && (iap
[4] == 0) && (iap
[5] == 0))
547 iap
= fec_mac_default
;
548 if ((iap
[0] == 0xff) && (iap
[1] == 0xff) && (iap
[2] == 0xff) &&
549 (iap
[3] == 0xff) && (iap
[4] == 0xff) && (iap
[5] == 0xff))
550 iap
= fec_mac_default
;
552 *((unsigned long *) &tmpaddr
[0]) = readl(fep
->hwp
+ FEC_ADDR_LOW
);
553 *((unsigned short *) &tmpaddr
[4]) = (readl(fep
->hwp
+ FEC_ADDR_HIGH
) >> 16);
557 memcpy(dev
->dev_addr
, iap
, ETH_ALEN
);
559 /* Adjust MAC if using default MAC address */
560 if (iap
== fec_mac_default
)
561 dev
->dev_addr
[ETH_ALEN
-1] = fec_mac_default
[ETH_ALEN
-1] + fep
->index
;
565 /* ------------------------------------------------------------------------- */
570 static void fec_enet_adjust_link(struct net_device
*dev
)
572 struct fec_enet_private
*fep
= netdev_priv(dev
);
573 struct phy_device
*phy_dev
= fep
->phy_dev
;
576 int status_change
= 0;
578 spin_lock_irqsave(&fep
->hw_lock
, flags
);
580 /* Prevent a state halted on mii error */
581 if (fep
->mii_timeout
&& phy_dev
->state
== PHY_HALTED
) {
582 phy_dev
->state
= PHY_RESUMING
;
586 /* Duplex link change */
588 if (fep
->full_duplex
!= phy_dev
->duplex
) {
589 fec_restart(dev
, phy_dev
->duplex
);
594 /* Link on or off change */
595 if (phy_dev
->link
!= fep
->link
) {
596 fep
->link
= phy_dev
->link
;
598 fec_restart(dev
, phy_dev
->duplex
);
605 spin_unlock_irqrestore(&fep
->hw_lock
, flags
);
608 phy_print_status(phy_dev
);
612 * NOTE: a MII transaction is during around 25 us, so polling it...
614 static int fec_enet_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
616 struct fec_enet_private
*fep
= bus
->priv
;
617 int timeout
= FEC_MII_TIMEOUT
;
619 fep
->mii_timeout
= 0;
621 /* clear MII end of transfer bit*/
622 writel(FEC_ENET_MII
, fep
->hwp
+ FEC_IEVENT
);
624 /* start a read op */
625 writel(FEC_MMFR_ST
| FEC_MMFR_OP_READ
|
626 FEC_MMFR_PA(mii_id
) | FEC_MMFR_RA(regnum
) |
627 FEC_MMFR_TA
, fep
->hwp
+ FEC_MII_DATA
);
629 /* wait for end of transfer */
630 while (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_MII
)) {
633 fep
->mii_timeout
= 1;
634 printk(KERN_ERR
"FEC: MDIO read timeout\n");
640 return FEC_MMFR_DATA(readl(fep
->hwp
+ FEC_MII_DATA
));
643 static int fec_enet_mdio_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
646 struct fec_enet_private
*fep
= bus
->priv
;
647 int timeout
= FEC_MII_TIMEOUT
;
649 fep
->mii_timeout
= 0;
651 /* clear MII end of transfer bit*/
652 writel(FEC_ENET_MII
, fep
->hwp
+ FEC_IEVENT
);
654 /* start a read op */
655 writel(FEC_MMFR_ST
| FEC_MMFR_OP_READ
|
656 FEC_MMFR_PA(mii_id
) | FEC_MMFR_RA(regnum
) |
657 FEC_MMFR_TA
| FEC_MMFR_DATA(value
),
658 fep
->hwp
+ FEC_MII_DATA
);
660 /* wait for end of transfer */
661 while (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_MII
)) {
664 fep
->mii_timeout
= 1;
665 printk(KERN_ERR
"FEC: MDIO write timeout\n");
673 static int fec_enet_mdio_reset(struct mii_bus
*bus
)
678 static int fec_enet_mii_probe(struct net_device
*dev
)
680 struct fec_enet_private
*fep
= netdev_priv(dev
);
681 struct phy_device
*phy_dev
= NULL
;
686 /* find the first phy */
687 phy_dev
= phy_find_first(fep
->mii_bus
);
689 printk(KERN_ERR
"%s: no PHY found\n", dev
->name
);
693 /* attach the mac to the phy */
694 ret
= phy_connect_direct(dev
, phy_dev
,
695 &fec_enet_adjust_link
, 0,
696 PHY_INTERFACE_MODE_MII
);
698 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
702 /* mask with MAC supported features */
703 phy_dev
->supported
&= PHY_BASIC_FEATURES
;
704 phy_dev
->advertising
= phy_dev
->supported
;
706 fep
->phy_dev
= phy_dev
;
708 fep
->full_duplex
= 0;
710 printk(KERN_INFO
"%s: Freescale FEC PHY driver [%s] "
711 "(mii_bus:phy_addr=%s, irq=%d)\n", dev
->name
,
712 fep
->phy_dev
->drv
->name
, dev_name(&fep
->phy_dev
->dev
),
718 static int fec_enet_mii_init(struct platform_device
*pdev
)
720 struct net_device
*dev
= platform_get_drvdata(pdev
);
721 struct fec_enet_private
*fep
= netdev_priv(dev
);
724 fep
->mii_timeout
= 0;
727 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed)
729 fep
->phy_speed
= DIV_ROUND_UP(clk_get_rate(fep
->clk
), 5000000) << 1;
730 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
732 fep
->mii_bus
= mdiobus_alloc();
733 if (fep
->mii_bus
== NULL
) {
738 fep
->mii_bus
->name
= "fec_enet_mii_bus";
739 fep
->mii_bus
->read
= fec_enet_mdio_read
;
740 fep
->mii_bus
->write
= fec_enet_mdio_write
;
741 fep
->mii_bus
->reset
= fec_enet_mdio_reset
;
742 snprintf(fep
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%x", pdev
->id
);
743 fep
->mii_bus
->priv
= fep
;
744 fep
->mii_bus
->parent
= &pdev
->dev
;
746 fep
->mii_bus
->irq
= kmalloc(sizeof(int) * PHY_MAX_ADDR
, GFP_KERNEL
);
747 if (!fep
->mii_bus
->irq
) {
749 goto err_out_free_mdiobus
;
752 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
753 fep
->mii_bus
->irq
[i
] = PHY_POLL
;
755 platform_set_drvdata(dev
, fep
->mii_bus
);
757 if (mdiobus_register(fep
->mii_bus
))
758 goto err_out_free_mdio_irq
;
762 err_out_free_mdio_irq
:
763 kfree(fep
->mii_bus
->irq
);
764 err_out_free_mdiobus
:
765 mdiobus_free(fep
->mii_bus
);
770 static void fec_enet_mii_remove(struct fec_enet_private
*fep
)
773 phy_disconnect(fep
->phy_dev
);
774 mdiobus_unregister(fep
->mii_bus
);
775 kfree(fep
->mii_bus
->irq
);
776 mdiobus_free(fep
->mii_bus
);
779 static int fec_enet_get_settings(struct net_device
*dev
,
780 struct ethtool_cmd
*cmd
)
782 struct fec_enet_private
*fep
= netdev_priv(dev
);
783 struct phy_device
*phydev
= fep
->phy_dev
;
788 return phy_ethtool_gset(phydev
, cmd
);
791 static int fec_enet_set_settings(struct net_device
*dev
,
792 struct ethtool_cmd
*cmd
)
794 struct fec_enet_private
*fep
= netdev_priv(dev
);
795 struct phy_device
*phydev
= fep
->phy_dev
;
800 return phy_ethtool_sset(phydev
, cmd
);
803 static void fec_enet_get_drvinfo(struct net_device
*dev
,
804 struct ethtool_drvinfo
*info
)
806 struct fec_enet_private
*fep
= netdev_priv(dev
);
808 strcpy(info
->driver
, fep
->pdev
->dev
.driver
->name
);
809 strcpy(info
->version
, "Revision: 1.0");
810 strcpy(info
->bus_info
, dev_name(&dev
->dev
));
813 static struct ethtool_ops fec_enet_ethtool_ops
= {
814 .get_settings
= fec_enet_get_settings
,
815 .set_settings
= fec_enet_set_settings
,
816 .get_drvinfo
= fec_enet_get_drvinfo
,
817 .get_link
= ethtool_op_get_link
,
820 static int fec_enet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
822 struct fec_enet_private
*fep
= netdev_priv(dev
);
823 struct phy_device
*phydev
= fep
->phy_dev
;
825 if (!netif_running(dev
))
831 return phy_mii_ioctl(phydev
, if_mii(rq
), cmd
);
834 static void fec_enet_free_buffers(struct net_device
*dev
)
836 struct fec_enet_private
*fep
= netdev_priv(dev
);
841 bdp
= fep
->rx_bd_base
;
842 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
843 skb
= fep
->rx_skbuff
[i
];
845 if (bdp
->cbd_bufaddr
)
846 dma_unmap_single(&dev
->dev
, bdp
->cbd_bufaddr
,
847 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
853 bdp
= fep
->tx_bd_base
;
854 for (i
= 0; i
< TX_RING_SIZE
; i
++)
855 kfree(fep
->tx_bounce
[i
]);
858 static int fec_enet_alloc_buffers(struct net_device
*dev
)
860 struct fec_enet_private
*fep
= netdev_priv(dev
);
865 bdp
= fep
->rx_bd_base
;
866 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
867 skb
= dev_alloc_skb(FEC_ENET_RX_FRSIZE
);
869 fec_enet_free_buffers(dev
);
872 fep
->rx_skbuff
[i
] = skb
;
874 bdp
->cbd_bufaddr
= dma_map_single(&dev
->dev
, skb
->data
,
875 FEC_ENET_RX_FRSIZE
, DMA_FROM_DEVICE
);
876 bdp
->cbd_sc
= BD_ENET_RX_EMPTY
;
880 /* Set the last buffer to wrap. */
882 bdp
->cbd_sc
|= BD_SC_WRAP
;
884 bdp
= fep
->tx_bd_base
;
885 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
886 fep
->tx_bounce
[i
] = kmalloc(FEC_ENET_TX_FRSIZE
, GFP_KERNEL
);
889 bdp
->cbd_bufaddr
= 0;
893 /* Set the last buffer to wrap. */
895 bdp
->cbd_sc
|= BD_SC_WRAP
;
901 fec_enet_open(struct net_device
*dev
)
903 struct fec_enet_private
*fep
= netdev_priv(dev
);
906 /* I should reset the ring buffers here, but I don't yet know
907 * a simple way to do that.
910 ret
= fec_enet_alloc_buffers(dev
);
914 /* Probe and connect to PHY when open the interface */
915 ret
= fec_enet_mii_probe(dev
);
917 fec_enet_free_buffers(dev
);
920 phy_start(fep
->phy_dev
);
921 netif_start_queue(dev
);
927 fec_enet_close(struct net_device
*dev
)
929 struct fec_enet_private
*fep
= netdev_priv(dev
);
931 /* Don't know what to do yet. */
933 netif_stop_queue(dev
);
937 phy_disconnect(fep
->phy_dev
);
939 fec_enet_free_buffers(dev
);
944 /* Set or clear the multicast filter for this adaptor.
945 * Skeleton taken from sunlance driver.
946 * The CPM Ethernet implementation allows Multicast as well as individual
947 * MAC address filtering. Some of the drivers check to make sure it is
948 * a group multicast address, and discard those that are not. I guess I
949 * will do the same for now, but just remove the test if you want
950 * individual filtering as well (do the upper net layers want or support
951 * this kind of feature?).
954 #define HASH_BITS 6 /* #bits in hash */
955 #define CRC32_POLY 0xEDB88320
957 static void set_multicast_list(struct net_device
*dev
)
959 struct fec_enet_private
*fep
= netdev_priv(dev
);
960 struct netdev_hw_addr
*ha
;
961 unsigned int i
, bit
, data
, crc
, tmp
;
964 if (dev
->flags
& IFF_PROMISC
) {
965 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
967 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
971 tmp
= readl(fep
->hwp
+ FEC_R_CNTRL
);
973 writel(tmp
, fep
->hwp
+ FEC_R_CNTRL
);
975 if (dev
->flags
& IFF_ALLMULTI
) {
976 /* Catch all multicast addresses, so set the
979 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
980 writel(0xffffffff, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
985 /* Clear filter and add the addresses in hash register
987 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
988 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
990 netdev_for_each_mc_addr(ha
, dev
) {
991 /* Only support group multicast for now */
992 if (!(ha
->addr
[0] & 1))
995 /* calculate crc32 value of mac address */
998 for (i
= 0; i
< dev
->addr_len
; i
++) {
1000 for (bit
= 0; bit
< 8; bit
++, data
>>= 1) {
1002 (((crc
^ data
) & 1) ? CRC32_POLY
: 0);
1006 /* only upper 6 bits (HASH_BITS) are used
1007 * which point to specific bit in he hash registers
1009 hash
= (crc
>> (32 - HASH_BITS
)) & 0x3f;
1012 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1013 tmp
|= 1 << (hash
- 32);
1014 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1016 tmp
= readl(fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1018 writel(tmp
, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1023 /* Set a MAC change in hardware. */
1025 fec_set_mac_address(struct net_device
*dev
, void *p
)
1027 struct fec_enet_private
*fep
= netdev_priv(dev
);
1028 struct sockaddr
*addr
= p
;
1030 if (!is_valid_ether_addr(addr
->sa_data
))
1031 return -EADDRNOTAVAIL
;
1033 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1035 writel(dev
->dev_addr
[3] | (dev
->dev_addr
[2] << 8) |
1036 (dev
->dev_addr
[1] << 16) | (dev
->dev_addr
[0] << 24),
1037 fep
->hwp
+ FEC_ADDR_LOW
);
1038 writel((dev
->dev_addr
[5] << 16) | (dev
->dev_addr
[4] << 24),
1039 fep
->hwp
+ FEC_ADDR_HIGH
);
1043 static const struct net_device_ops fec_netdev_ops
= {
1044 .ndo_open
= fec_enet_open
,
1045 .ndo_stop
= fec_enet_close
,
1046 .ndo_start_xmit
= fec_enet_start_xmit
,
1047 .ndo_set_multicast_list
= set_multicast_list
,
1048 .ndo_change_mtu
= eth_change_mtu
,
1049 .ndo_validate_addr
= eth_validate_addr
,
1050 .ndo_tx_timeout
= fec_timeout
,
1051 .ndo_set_mac_address
= fec_set_mac_address
,
1052 .ndo_do_ioctl
= fec_enet_ioctl
,
1056 * XXX: We need to clean up on failure exits here.
1058 * index is only used in legacy code
1060 static int fec_enet_init(struct net_device
*dev
, int index
)
1062 struct fec_enet_private
*fep
= netdev_priv(dev
);
1063 struct bufdesc
*cbd_base
;
1064 struct bufdesc
*bdp
;
1067 /* Allocate memory for buffer descriptors. */
1068 cbd_base
= dma_alloc_coherent(NULL
, PAGE_SIZE
, &fep
->bd_dma
,
1071 printk("FEC: allocate descriptor memory failed?\n");
1075 spin_lock_init(&fep
->hw_lock
);
1078 fep
->hwp
= (void __iomem
*)dev
->base_addr
;
1081 /* Set the Ethernet address */
1087 l
= readl(fep
->hwp
+ FEC_ADDR_LOW
);
1088 dev
->dev_addr
[0] = (unsigned char)((l
& 0xFF000000) >> 24);
1089 dev
->dev_addr
[1] = (unsigned char)((l
& 0x00FF0000) >> 16);
1090 dev
->dev_addr
[2] = (unsigned char)((l
& 0x0000FF00) >> 8);
1091 dev
->dev_addr
[3] = (unsigned char)((l
& 0x000000FF) >> 0);
1092 l
= readl(fep
->hwp
+ FEC_ADDR_HIGH
);
1093 dev
->dev_addr
[4] = (unsigned char)((l
& 0xFF000000) >> 24);
1094 dev
->dev_addr
[5] = (unsigned char)((l
& 0x00FF0000) >> 16);
1098 /* Set receive and transmit descriptor base. */
1099 fep
->rx_bd_base
= cbd_base
;
1100 fep
->tx_bd_base
= cbd_base
+ RX_RING_SIZE
;
1102 /* The FEC Ethernet specific entries in the device structure */
1103 dev
->watchdog_timeo
= TX_TIMEOUT
;
1104 dev
->netdev_ops
= &fec_netdev_ops
;
1105 dev
->ethtool_ops
= &fec_enet_ethtool_ops
;
1107 /* Initialize the receive buffer descriptors. */
1108 bdp
= fep
->rx_bd_base
;
1109 for (i
= 0; i
< RX_RING_SIZE
; i
++) {
1111 /* Initialize the BD for every fragment in the page. */
1116 /* Set the last buffer to wrap */
1118 bdp
->cbd_sc
|= BD_SC_WRAP
;
1120 /* ...and the same for transmit */
1121 bdp
= fep
->tx_bd_base
;
1122 for (i
= 0; i
< TX_RING_SIZE
; i
++) {
1124 /* Initialize the BD for every fragment in the page. */
1126 bdp
->cbd_bufaddr
= 0;
1130 /* Set the last buffer to wrap */
1132 bdp
->cbd_sc
|= BD_SC_WRAP
;
1134 fec_restart(dev
, 0);
1139 /* This function is called to start or restart the FEC during a link
1140 * change. This only happens when switching between half and full
1144 fec_restart(struct net_device
*dev
, int duplex
)
1146 struct fec_enet_private
*fep
= netdev_priv(dev
);
1149 /* Whack a reset. We should wait for this. */
1150 writel(1, fep
->hwp
+ FEC_ECNTRL
);
1153 /* Clear any outstanding interrupt. */
1154 writel(0xffc00000, fep
->hwp
+ FEC_IEVENT
);
1156 /* Reset all multicast. */
1157 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_HIGH
);
1158 writel(0, fep
->hwp
+ FEC_GRP_HASH_TABLE_LOW
);
1159 #ifndef CONFIG_M5272
1160 writel(0, fep
->hwp
+ FEC_HASH_TABLE_HIGH
);
1161 writel(0, fep
->hwp
+ FEC_HASH_TABLE_LOW
);
1164 /* Set maximum receive buffer size. */
1165 writel(PKT_MAXBLR_SIZE
, fep
->hwp
+ FEC_R_BUFF_SIZE
);
1167 /* Set receive and transmit descriptor base. */
1168 writel(fep
->bd_dma
, fep
->hwp
+ FEC_R_DES_START
);
1169 writel((unsigned long)fep
->bd_dma
+ sizeof(struct bufdesc
) * RX_RING_SIZE
,
1170 fep
->hwp
+ FEC_X_DES_START
);
1172 fep
->dirty_tx
= fep
->cur_tx
= fep
->tx_bd_base
;
1173 fep
->cur_rx
= fep
->rx_bd_base
;
1175 /* Reset SKB transmit buffers. */
1176 fep
->skb_cur
= fep
->skb_dirty
= 0;
1177 for (i
= 0; i
<= TX_RING_MOD_MASK
; i
++) {
1178 if (fep
->tx_skbuff
[i
]) {
1179 dev_kfree_skb_any(fep
->tx_skbuff
[i
]);
1180 fep
->tx_skbuff
[i
] = NULL
;
1184 /* Enable MII mode */
1186 /* MII enable / FD enable */
1187 writel(OPT_FRAME_SIZE
| 0x04, fep
->hwp
+ FEC_R_CNTRL
);
1188 writel(0x04, fep
->hwp
+ FEC_X_CNTRL
);
1190 /* MII enable / No Rcv on Xmit */
1191 writel(OPT_FRAME_SIZE
| 0x06, fep
->hwp
+ FEC_R_CNTRL
);
1192 writel(0x0, fep
->hwp
+ FEC_X_CNTRL
);
1194 fep
->full_duplex
= duplex
;
1197 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1199 #ifdef FEC_MIIGSK_ENR
1200 if (fep
->phy_interface
== PHY_INTERFACE_MODE_RMII
) {
1201 /* disable the gasket and wait */
1202 writel(0, fep
->hwp
+ FEC_MIIGSK_ENR
);
1203 while (readl(fep
->hwp
+ FEC_MIIGSK_ENR
) & 4)
1206 /* configure the gasket: RMII, 50 MHz, no loopback, no echo */
1207 writel(1, fep
->hwp
+ FEC_MIIGSK_CFGR
);
1209 /* re-enable the gasket */
1210 writel(2, fep
->hwp
+ FEC_MIIGSK_ENR
);
1214 /* And last, enable the transmit and receive processing */
1215 writel(2, fep
->hwp
+ FEC_ECNTRL
);
1216 writel(0, fep
->hwp
+ FEC_R_DES_ACTIVE
);
1218 /* Enable interrupts we wish to service */
1219 writel(FEC_ENET_TXF
| FEC_ENET_RXF
, fep
->hwp
+ FEC_IMASK
);
1223 fec_stop(struct net_device
*dev
)
1225 struct fec_enet_private
*fep
= netdev_priv(dev
);
1227 /* We cannot expect a graceful transmit stop without link !!! */
1229 writel(1, fep
->hwp
+ FEC_X_CNTRL
); /* Graceful transmit stop */
1231 if (!(readl(fep
->hwp
+ FEC_IEVENT
) & FEC_ENET_GRA
))
1232 printk("fec_stop : Graceful transmit stop did not complete !\n");
1235 /* Whack a reset. We should wait for this. */
1236 writel(1, fep
->hwp
+ FEC_ECNTRL
);
1239 /* Clear outstanding MII command interrupts. */
1240 writel(FEC_ENET_MII
, fep
->hwp
+ FEC_IEVENT
);
1242 writel(fep
->phy_speed
, fep
->hwp
+ FEC_MII_SPEED
);
1245 static int __devinit
1246 fec_probe(struct platform_device
*pdev
)
1248 struct fec_enet_private
*fep
;
1249 struct fec_platform_data
*pdata
;
1250 struct net_device
*ndev
;
1251 int i
, irq
, ret
= 0;
1254 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1258 r
= request_mem_region(r
->start
, resource_size(r
), pdev
->name
);
1262 /* Init network device */
1263 ndev
= alloc_etherdev(sizeof(struct fec_enet_private
));
1267 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
1269 /* setup board info structure */
1270 fep
= netdev_priv(ndev
);
1271 memset(fep
, 0, sizeof(*fep
));
1273 ndev
->base_addr
= (unsigned long)ioremap(r
->start
, resource_size(r
));
1276 if (!ndev
->base_addr
) {
1278 goto failed_ioremap
;
1281 platform_set_drvdata(pdev
, ndev
);
1283 pdata
= pdev
->dev
.platform_data
;
1285 fep
->phy_interface
= pdata
->phy
;
1287 /* This device has up to three irqs on some platforms */
1288 for (i
= 0; i
< 3; i
++) {
1289 irq
= platform_get_irq(pdev
, i
);
1292 ret
= request_irq(irq
, fec_enet_interrupt
, IRQF_DISABLED
, pdev
->name
, ndev
);
1295 irq
= platform_get_irq(pdev
, i
);
1296 free_irq(irq
, ndev
);
1303 fep
->clk
= clk_get(&pdev
->dev
, "fec_clk");
1304 if (IS_ERR(fep
->clk
)) {
1305 ret
= PTR_ERR(fep
->clk
);
1308 clk_enable(fep
->clk
);
1310 ret
= fec_enet_init(ndev
, 0);
1314 ret
= fec_enet_mii_init(pdev
);
1316 goto failed_mii_init
;
1318 ret
= register_netdev(ndev
);
1320 goto failed_register
;
1325 fec_enet_mii_remove(fep
);
1328 clk_disable(fep
->clk
);
1331 for (i
= 0; i
< 3; i
++) {
1332 irq
= platform_get_irq(pdev
, i
);
1334 free_irq(irq
, ndev
);
1337 iounmap((void __iomem
*)ndev
->base_addr
);
1344 static int __devexit
1345 fec_drv_remove(struct platform_device
*pdev
)
1347 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1348 struct fec_enet_private
*fep
= netdev_priv(ndev
);
1350 platform_set_drvdata(pdev
, NULL
);
1353 fec_enet_mii_remove(fep
);
1354 clk_disable(fep
->clk
);
1356 iounmap((void __iomem
*)ndev
->base_addr
);
1357 unregister_netdev(ndev
);
1364 fec_suspend(struct device
*dev
)
1366 struct net_device
*ndev
= dev_get_drvdata(dev
);
1367 struct fec_enet_private
*fep
;
1370 fep
= netdev_priv(ndev
);
1371 if (netif_running(ndev
))
1372 fec_enet_close(ndev
);
1373 clk_disable(fep
->clk
);
1379 fec_resume(struct device
*dev
)
1381 struct net_device
*ndev
= dev_get_drvdata(dev
);
1382 struct fec_enet_private
*fep
;
1385 fep
= netdev_priv(ndev
);
1386 clk_enable(fep
->clk
);
1387 if (netif_running(ndev
))
1388 fec_enet_open(ndev
);
1393 static const struct dev_pm_ops fec_pm_ops
= {
1394 .suspend
= fec_suspend
,
1395 .resume
= fec_resume
,
1396 .freeze
= fec_suspend
,
1398 .poweroff
= fec_suspend
,
1399 .restore
= fec_resume
,
1403 static struct platform_driver fec_driver
= {
1406 .owner
= THIS_MODULE
,
1412 .remove
= __devexit_p(fec_drv_remove
),
1416 fec_enet_module_init(void)
1418 printk(KERN_INFO
"FEC Ethernet Driver\n");
1420 return platform_driver_register(&fec_driver
);
1424 fec_enet_cleanup(void)
1426 platform_driver_unregister(&fec_driver
);
1429 module_exit(fec_enet_cleanup
);
1430 module_init(fec_enet_module_init
);
1432 MODULE_LICENSE("GPL");