drivers/pci/msi.h

   1 /*
   2  * Copyright (C) 2003-2004 Intel
   3  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   4  */
   5
   6 #ifndef MSI_H
   7 #define MSI_H
   8
   9 #include <asm/msi.h>
  10
  11 /*
  12  * Assume the maximum number of hot plug slots supported by the system is about
  13  * ten. The worstcase is that each of these slots is hot-added with a device,
  14  * which has two MSI/MSI-X capable functions. To avoid any MSI-X driver, which
  15  * attempts to request all available vectors, NR_HP_RESERVED_VECTORS is defined
  16  * as below to ensure at least one message is assigned to each detected MSI/
  17  * MSI-X device function.
  18  */
  19 #define NR_HP_RESERVED_VECTORS  20
  20
  21 extern int vector_irq[NR_VECTORS];
  22 extern void (*interrupt[NR_IRQS])(void);
  23 extern int pci_vector_resources(int last, int nr_released);
  24
  25 /*
  26  * MSI-X Address Register
  27  */
  28 #define PCI_MSIX_FLAGS_QSIZE            0x7FF
  29 #define PCI_MSIX_FLAGS_ENABLE           (1 << 15)
  30 #define PCI_MSIX_FLAGS_BIRMASK          (7 << 0)
  31 #define PCI_MSIX_FLAGS_BITMASK          (1 << 0)
  32
  33 #define PCI_MSIX_ENTRY_SIZE                     16
  34 #define  PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET       0
  35 #define  PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET       4
  36 #define  PCI_MSIX_ENTRY_DATA_OFFSET             8
  37 #define  PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET      12
  38
  39 #define msi_control_reg(base)           (base + PCI_MSI_FLAGS)
  40 #define msi_lower_address_reg(base)     (base + PCI_MSI_ADDRESS_LO)
  41 #define msi_upper_address_reg(base)     (base + PCI_MSI_ADDRESS_HI)
  42 #define msi_data_reg(base, is64bit)     \
  43         ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
  44 #define msi_mask_bits_reg(base, is64bit) \
  45         ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
  46 #define msi_disable(control)            control &= ~PCI_MSI_FLAGS_ENABLE
  47 #define multi_msi_capable(control) \
  48         (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
  49 #define multi_msi_enable(control, num) \
  50         control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
  51 #define is_64bit_address(control)       (control & PCI_MSI_FLAGS_64BIT)
  52 #define is_mask_bit_support(control)    (control & PCI_MSI_FLAGS_MASKBIT)
  53 #define msi_enable(control, num) multi_msi_enable(control, num); \
  54         control |= PCI_MSI_FLAGS_ENABLE
  55
  56 #define msix_table_offset_reg(base)     (base + 0x04)
  57 #define msix_pba_offset_reg(base)       (base + 0x08)
  58 #define msix_enable(control)            control |= PCI_MSIX_FLAGS_ENABLE
  59 #define msix_disable(control)           control &= ~PCI_MSIX_FLAGS_ENABLE
  60 #define msix_table_size(control)        ((control & PCI_MSIX_FLAGS_QSIZE)+1)
  61 #define multi_msix_capable              msix_table_size
  62 #define msix_unmask(address)            (address & ~PCI_MSIX_FLAGS_BITMASK)
  63 #define msix_mask(address)              (address | PCI_MSIX_FLAGS_BITMASK)
  64 #define msix_is_pending(address)        (address & PCI_MSIX_FLAGS_PENDMASK)
  65
  66 /*
  67  * MSI Defined Data Structures
  68  */
  69 #define MSI_ADDRESS_HEADER              0xfee
  70 #define MSI_ADDRESS_HEADER_SHIFT        12
  71 #define MSI_ADDRESS_HEADER_MASK         0xfff000
  72 #define MSI_ADDRESS_DEST_ID_MASK        0xfff0000f
  73 #define MSI_TARGET_CPU_MASK             0xff
  74 #define MSI_DELIVERY_MODE               0
  75 #define MSI_LEVEL_MODE                  1       /* Edge always assert */
  76 #define MSI_TRIGGER_MODE                0       /* MSI is edge sensitive */
  77 #define MSI_PHYSICAL_MODE               0
  78 #define MSI_LOGICAL_MODE                1
  79 #define MSI_REDIRECTION_HINT_MODE       0
  80
  81 struct msg_data {
  82 #if defined(__LITTLE_ENDIAN_BITFIELD)
  83         __u32   vector          :  8;
  84         __u32   delivery_mode   :  3;   /* 000b: FIXED | 001b: lowest prior */
  85         __u32   reserved_1      :  3;
  86         __u32   level           :  1;   /* 0: deassert | 1: assert */
  87         __u32   trigger         :  1;   /* 0: edge | 1: level */
  88         __u32   reserved_2      : 16;
  89 #elif defined(__BIG_ENDIAN_BITFIELD)
  90         __u32   reserved_2      : 16;
  91         __u32   trigger         :  1;   /* 0: edge | 1: level */
  92         __u32   level           :  1;   /* 0: deassert | 1: assert */
  93         __u32   reserved_1      :  3;
  94         __u32   delivery_mode   :  3;   /* 000b: FIXED | 001b: lowest prior */
  95         __u32   vector          :  8;
  96 #else
  97 #error "Bitfield endianness not defined! Check your byteorder.h"
  98 #endif
  99 } __attribute__ ((packed));
 100
 101 struct msg_address {
 102         union {
 103                 struct {
 104 #if defined(__LITTLE_ENDIAN_BITFIELD)
 105                         __u32   reserved_1      :  2;
 106                         __u32   dest_mode       :  1;   /*0:physic | 1:logic */
 107                         __u32   redirection_hint:  1;   /*0: dedicated CPU
 108                                                           1: lowest priority */
 109                         __u32   reserved_2      :  4;
 110                         __u32   dest_id         : 24;   /* Destination ID */
 111 #elif defined(__BIG_ENDIAN_BITFIELD)
 112                         __u32   dest_id         : 24;   /* Destination ID */
 113                         __u32   reserved_2      :  4;
 114                         __u32   redirection_hint:  1;   /*0: dedicated CPU
 115                                                           1: lowest priority */
 116                         __u32   dest_mode       :  1;   /*0:physic | 1:logic */
 117                         __u32   reserved_1      :  2;
 118 #else
 119 #error "Bitfield endianness not defined! Check your byteorder.h"
 120 #endif
 121                 }u;
 122                 __u32  value;
 123         }lo_address;
 124         __u32   hi_address;
 125 } __attribute__ ((packed));
 126
 127 struct msi_desc {
 128         struct {
 129                 __u8    type    : 5;    /* {0: unused, 5h:MSI, 11h:MSI-X} */
 130                 __u8    maskbit : 1;    /* mask-pending bit supported ?   */
 131                 __u8    state   : 1;    /* {0: free, 1: busy}             */
 132                 __u8    reserved: 1;    /* reserved                       */
 133                 __u8    entry_nr;       /* specific enabled entry         */
 134                 __u8    default_vector; /* default pre-assigned vector    */
 135                 __u8    current_cpu;    /* current destination cpu        */
 136         }msi_attrib;
 137
 138         struct {
 139                 __u16   head;
 140                 __u16   tail;
 141         }link;
 142
 143         void __iomem *mask_base;
 144         struct pci_dev *dev;
 145 };
 146
 147 #endif /* MSI_H */